?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
USB: drivers/usb/musb/: disable it on SuperH
[linux-2.6/mini2440.git] / drivers / net / ns83820.c
blobff449619f047e57fd36be41805b33bf6b66ec113
1 #define VERSION "0.23"
2 /* ns83820.c by Benjamin LaHaise with contributions.
3 *
4 * Questions/comments/discussion to linux-ns83820@kvack.org.
5 *
6 * $Revision: 1.34.2.23 $
7 *
8 * Copyright 2001 Benjamin LaHaise.
9 * Copyright 2001, 2002 Red Hat.
10 *
11 * Mmmm, chocolate vanilla mocha...
12 *
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 *
28 *
29 * ChangeLog
30 * =========
31 * 20010414 0.1 - created
32 * 20010622 0.2 - basic rx and tx.
33 * 20010711 0.3 - added duplex and link state detection support.
34 * 20010713 0.4 - zero copy, no hangs.
35 * 0.5 - 64 bit dma support (davem will hate me for this)
36 * - disable jumbo frames to avoid tx hangs
37 * - work around tx deadlocks on my 1.02 card via
38 * fiddling with TXCFG
39 * 20010810 0.6 - use pci dma api for ringbuffers, work on ia64
40 * 20010816 0.7 - misc cleanups
41 * 20010826 0.8 - fix critical zero copy bugs
42 * 0.9 - internal experiment
43 * 20010827 0.10 - fix ia64 unaligned access.
44 * 20010906 0.11 - accept all packets with checksum errors as
45 * otherwise fragments get lost
46 * - fix >> 32 bugs
47 * 0.12 - add statistics counters
48 * - add allmulti/promisc support
49 * 20011009 0.13 - hotplug support, other smaller pci api cleanups
50 * 20011204 0.13a - optical transceiver support added
51 * by Michael Clark <michael@metaparadigm.com>
52 * 20011205 0.13b - call register_netdev earlier in initialization
53 * suppress duplicate link status messages
54 * 20011117 0.14 - ethtool GDRVINFO, GLINK support from jgarzik
55 * 20011204 0.15 get ppc (big endian) working
56 * 20011218 0.16 various cleanups
57 * 20020310 0.17 speedups
58 * 20020610 0.18 - actually use the pci dma api for highmem
59 * - remove pci latency register fiddling
60 * 0.19 - better bist support
61 * - add ihr and reset_phy parameters
62 * - gmii bus probing
63 * - fix missed txok introduced during performance
64 * tuning
65 * 0.20 - fix stupid RFEN thinko. i am such a smurf.
66 * 20040828 0.21 - add hardware vlan accleration
67 * by Neil Horman <nhorman@redhat.com>
68 * 20050406 0.22 - improved DAC ifdefs from Andi Kleen
69 * - removal of dead code from Adrian Bunk
70 * - fix half duplex collision behaviour
71 * Driver Overview
72 * ===============
73 *
74 * This driver was originally written for the National Semiconductor
75 * 83820 chip, a 10/100/1000 Mbps 64 bit PCI ethernet NIC. Hopefully
76 * this code will turn out to be a) clean, b) correct, and c) fast.
77 * With that in mind, I'm aiming to split the code up as much as
78 * reasonably possible. At present there are X major sections that
79 * break down into a) packet receive, b) packet transmit, c) link
80 * management, d) initialization and configuration. Where possible,
81 * these code paths are designed to run in parallel.
82 *
83 * This driver has been tested and found to work with the following
84 * cards (in no particular order):
85 *
86 * Cameo SOHO-GA2000T SOHO-GA2500T
87 * D-Link DGE-500T
88 * PureData PDP8023Z-TG
89 * SMC SMC9452TX SMC9462TX
90 * Netgear GA621
91 *
92 * Special thanks to SMC for providing hardware to test this driver on.
93 *
94 * Reports of success or failure would be greatly appreciated.
95 */
96 //#define dprintk printk
97 #define dprintk(x...) do { } while (0)
98
99 #include <linux/module.h>
100 #include <linux/moduleparam.h>
101 #include <linux/types.h>
102 #include <linux/pci.h>
103 #include <linux/dma-mapping.h>
104 #include <linux/netdevice.h>
105 #include <linux/etherdevice.h>
106 #include <linux/delay.h>
107 #include <linux/workqueue.h>
108 #include <linux/init.h>
109 #include <linux/ip.h> /* for iph */
110 #include <linux/in.h> /* for IPPROTO_... */
111 #include <linux/compiler.h>
112 #include <linux/prefetch.h>
113 #include <linux/ethtool.h>
114 #include <linux/timer.h>
115 #include <linux/if_vlan.h>
116 #include <linux/rtnetlink.h>
117 #include <linux/jiffies.h>
118
119 #include <asm/io.h>
120 #include <asm/uaccess.h>
121 #include <asm/system.h>
122
123 #define DRV_NAME "ns83820"
124
125 /* Global parameters. See module_param near the bottom. */
126 static int ihr = 2;
127 static int reset_phy = 0;
128 static int lnksts = 0; /* CFG_LNKSTS bit polarity */
129
130 /* Dprintk is used for more interesting debug events */
131 #undef Dprintk
132 #define Dprintk dprintk
133
134 /* tunables */
135 #define RX_BUF_SIZE 1500 /* 8192 */
136 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
137 #define NS83820_VLAN_ACCEL_SUPPORT
138 #endif
139
140 /* Must not exceed ~65000. */
141 #define NR_RX_DESC 64
142 #define NR_TX_DESC 128
143
144 /* not tunable */
145 #define REAL_RX_BUF_SIZE (RX_BUF_SIZE + 14) /* rx/tx mac addr + type */
146
147 #define MIN_TX_DESC_FREE 8
148
149 /* register defines */
150 #define CFGCS 0x04
151
152 #define CR_TXE 0x00000001
153 #define CR_TXD 0x00000002
154 /* Ramit : Here's a tip, don't do a RXD immediately followed by an RXE
155 * The Receive engine skips one descriptor and moves
156 * onto the next one!! */
157 #define CR_RXE 0x00000004
158 #define CR_RXD 0x00000008
159 #define CR_TXR 0x00000010
160 #define CR_RXR 0x00000020
161 #define CR_SWI 0x00000080
162 #define CR_RST 0x00000100
163
164 #define PTSCR_EEBIST_FAIL 0x00000001
165 #define PTSCR_EEBIST_EN 0x00000002
166 #define PTSCR_EELOAD_EN 0x00000004
167 #define PTSCR_RBIST_FAIL 0x000001b8
168 #define PTSCR_RBIST_DONE 0x00000200
169 #define PTSCR_RBIST_EN 0x00000400
170 #define PTSCR_RBIST_RST 0x00002000
171
172 #define MEAR_EEDI 0x00000001
173 #define MEAR_EEDO 0x00000002
174 #define MEAR_EECLK 0x00000004
175 #define MEAR_EESEL 0x00000008
176 #define MEAR_MDIO 0x00000010
177 #define MEAR_MDDIR 0x00000020
178 #define MEAR_MDC 0x00000040
179
180 #define ISR_TXDESC3 0x40000000
181 #define ISR_TXDESC2 0x20000000
182 #define ISR_TXDESC1 0x10000000
183 #define ISR_TXDESC0 0x08000000
184 #define ISR_RXDESC3 0x04000000
185 #define ISR_RXDESC2 0x02000000
186 #define ISR_RXDESC1 0x01000000
187 #define ISR_RXDESC0 0x00800000
188 #define ISR_TXRCMP 0x00400000
189 #define ISR_RXRCMP 0x00200000
190 #define ISR_DPERR 0x00100000
191 #define ISR_SSERR 0x00080000
192 #define ISR_RMABT 0x00040000
193 #define ISR_RTABT 0x00020000
194 #define ISR_RXSOVR 0x00010000
195 #define ISR_HIBINT 0x00008000
196 #define ISR_PHY 0x00004000
197 #define ISR_PME 0x00002000
198 #define ISR_SWI 0x00001000
199 #define ISR_MIB 0x00000800
200 #define ISR_TXURN 0x00000400
201 #define ISR_TXIDLE 0x00000200
202 #define ISR_TXERR 0x00000100
203 #define ISR_TXDESC 0x00000080
204 #define ISR_TXOK 0x00000040
205 #define ISR_RXORN 0x00000020
206 #define ISR_RXIDLE 0x00000010
207 #define ISR_RXEARLY 0x00000008
208 #define ISR_RXERR 0x00000004
209 #define ISR_RXDESC 0x00000002
210 #define ISR_RXOK 0x00000001
211
212 #define TXCFG_CSI 0x80000000
213 #define TXCFG_HBI 0x40000000
214 #define TXCFG_MLB 0x20000000
215 #define TXCFG_ATP 0x10000000
216 #define TXCFG_ECRETRY 0x00800000
217 #define TXCFG_BRST_DIS 0x00080000
218 #define TXCFG_MXDMA1024 0x00000000
219 #define TXCFG_MXDMA512 0x00700000
220 #define TXCFG_MXDMA256 0x00600000
221 #define TXCFG_MXDMA128 0x00500000
222 #define TXCFG_MXDMA64 0x00400000
223 #define TXCFG_MXDMA32 0x00300000
224 #define TXCFG_MXDMA16 0x00200000
225 #define TXCFG_MXDMA8 0x00100000
226
227 #define CFG_LNKSTS 0x80000000
228 #define CFG_SPDSTS 0x60000000
229 #define CFG_SPDSTS1 0x40000000
230 #define CFG_SPDSTS0 0x20000000
231 #define CFG_DUPSTS 0x10000000
232 #define CFG_TBI_EN 0x01000000
233 #define CFG_MODE_1000 0x00400000
234 /* Ramit : Dont' ever use AUTO_1000, it never works and is buggy.
235 * Read the Phy response and then configure the MAC accordingly */
236 #define CFG_AUTO_1000 0x00200000
237 #define CFG_PINT_CTL 0x001c0000
238 #define CFG_PINT_DUPSTS 0x00100000
239 #define CFG_PINT_LNKSTS 0x00080000
240 #define CFG_PINT_SPDSTS 0x00040000
241 #define CFG_TMRTEST 0x00020000
242 #define CFG_MRM_DIS 0x00010000
243 #define CFG_MWI_DIS 0x00008000
244 #define CFG_T64ADDR 0x00004000
245 #define CFG_PCI64_DET 0x00002000
246 #define CFG_DATA64_EN 0x00001000
247 #define CFG_M64ADDR 0x00000800
248 #define CFG_PHY_RST 0x00000400
249 #define CFG_PHY_DIS 0x00000200
250 #define CFG_EXTSTS_EN 0x00000100
251 #define CFG_REQALG 0x00000080
252 #define CFG_SB 0x00000040
253 #define CFG_POW 0x00000020
254 #define CFG_EXD 0x00000010
255 #define CFG_PESEL 0x00000008
256 #define CFG_BROM_DIS 0x00000004
257 #define CFG_EXT_125 0x00000002
258 #define CFG_BEM 0x00000001
259
260 #define EXTSTS_UDPPKT 0x00200000
261 #define EXTSTS_TCPPKT 0x00080000
262 #define EXTSTS_IPPKT 0x00020000
263 #define EXTSTS_VPKT 0x00010000
264 #define EXTSTS_VTG_MASK 0x0000ffff
265
266 #define SPDSTS_POLARITY (CFG_SPDSTS1 | CFG_SPDSTS0 | CFG_DUPSTS | (lnksts ? CFG_LNKSTS : 0))
267
268 #define MIBC_MIBS 0x00000008
269 #define MIBC_ACLR 0x00000004
270 #define MIBC_FRZ 0x00000002
271 #define MIBC_WRN 0x00000001
272
273 #define PCR_PSEN (1 << 31)
274 #define PCR_PS_MCAST (1 << 30)
275 #define PCR_PS_DA (1 << 29)
276 #define PCR_STHI_8 (3 << 23)
277 #define PCR_STLO_4 (1 << 23)
278 #define PCR_FFHI_8K (3 << 21)
279 #define PCR_FFLO_4K (1 << 21)
280 #define PCR_PAUSE_CNT 0xFFFE
281
282 #define RXCFG_AEP 0x80000000
283 #define RXCFG_ARP 0x40000000
284 #define RXCFG_STRIPCRC 0x20000000
285 #define RXCFG_RX_FD 0x10000000
286 #define RXCFG_ALP 0x08000000
287 #define RXCFG_AIRL 0x04000000
288 #define RXCFG_MXDMA512 0x00700000
289 #define RXCFG_DRTH 0x0000003e
290 #define RXCFG_DRTH0 0x00000002
291
292 #define RFCR_RFEN 0x80000000
293 #define RFCR_AAB 0x40000000
294 #define RFCR_AAM 0x20000000
295 #define RFCR_AAU 0x10000000
296 #define RFCR_APM 0x08000000
297 #define RFCR_APAT 0x07800000
298 #define RFCR_APAT3 0x04000000
299 #define RFCR_APAT2 0x02000000
300 #define RFCR_APAT1 0x01000000
301 #define RFCR_APAT0 0x00800000
302 #define RFCR_AARP 0x00400000
303 #define RFCR_MHEN 0x00200000
304 #define RFCR_UHEN 0x00100000
305 #define RFCR_ULM 0x00080000
306
307 #define VRCR_RUDPE 0x00000080
308 #define VRCR_RTCPE 0x00000040
309 #define VRCR_RIPE 0x00000020
310 #define VRCR_IPEN 0x00000010
311 #define VRCR_DUTF 0x00000008
312 #define VRCR_DVTF 0x00000004
313 #define VRCR_VTREN 0x00000002
314 #define VRCR_VTDEN 0x00000001
315
316 #define VTCR_PPCHK 0x00000008
317 #define VTCR_GCHK 0x00000004
318 #define VTCR_VPPTI 0x00000002
319 #define VTCR_VGTI 0x00000001
320
321 #define CR 0x00
322 #define CFG 0x04
323 #define MEAR 0x08
324 #define PTSCR 0x0c
325 #define ISR 0x10
326 #define IMR 0x14
327 #define IER 0x18
328 #define IHR 0x1c
329 #define TXDP 0x20
330 #define TXDP_HI 0x24
331 #define TXCFG 0x28
332 #define GPIOR 0x2c
333 #define RXDP 0x30
334 #define RXDP_HI 0x34
335 #define RXCFG 0x38
336 #define PQCR 0x3c
337 #define WCSR 0x40
338 #define PCR 0x44
339 #define RFCR 0x48
340 #define RFDR 0x4c
341
342 #define SRR 0x58
343
344 #define VRCR 0xbc
345 #define VTCR 0xc0
346 #define VDR 0xc4
347 #define CCSR 0xcc
348
349 #define TBICR 0xe0
350 #define TBISR 0xe4
351 #define TANAR 0xe8
352 #define TANLPAR 0xec
353 #define TANER 0xf0
354 #define TESR 0xf4
355
356 #define TBICR_MR_AN_ENABLE 0x00001000
357 #define TBICR_MR_RESTART_AN 0x00000200
358
359 #define TBISR_MR_LINK_STATUS 0x00000020
360 #define TBISR_MR_AN_COMPLETE 0x00000004
361
362 #define TANAR_PS2 0x00000100
363 #define TANAR_PS1 0x00000080
364 #define TANAR_HALF_DUP 0x00000040
365 #define TANAR_FULL_DUP 0x00000020
366
367 #define GPIOR_GP5_OE 0x00000200
368 #define GPIOR_GP4_OE 0x00000100
369 #define GPIOR_GP3_OE 0x00000080
370 #define GPIOR_GP2_OE 0x00000040
371 #define GPIOR_GP1_OE 0x00000020
372 #define GPIOR_GP3_OUT 0x00000004
373 #define GPIOR_GP1_OUT 0x00000001
374
375 #define LINK_AUTONEGOTIATE 0x01
376 #define LINK_DOWN 0x02
377 #define LINK_UP 0x04
378
379 #define HW_ADDR_LEN sizeof(dma_addr_t)
380 #define desc_addr_set(desc, addr) \
381 do { \
382 ((desc)[0] = cpu_to_le32(addr)); \
383 if (HW_ADDR_LEN == 8) \
384 (desc)[1] = cpu_to_le32(((u64)addr) >> 32); \
385 } while(0)
386 #define desc_addr_get(desc) \
387 (le32_to_cpu((desc)[0]) | \
388 (HW_ADDR_LEN == 8 ? ((dma_addr_t)le32_to_cpu((desc)[1]))<<32 : 0))
389
390 #define DESC_LINK 0
391 #define DESC_BUFPTR (DESC_LINK + HW_ADDR_LEN/4)
392 #define DESC_CMDSTS (DESC_BUFPTR + HW_ADDR_LEN/4)
393 #define DESC_EXTSTS (DESC_CMDSTS + 4/4)
394
395 #define CMDSTS_OWN 0x80000000
396 #define CMDSTS_MORE 0x40000000
397 #define CMDSTS_INTR 0x20000000
398 #define CMDSTS_ERR 0x10000000
399 #define CMDSTS_OK 0x08000000
400 #define CMDSTS_RUNT 0x00200000
401 #define CMDSTS_LEN_MASK 0x0000ffff
402
403 #define CMDSTS_DEST_MASK 0x01800000
404 #define CMDSTS_DEST_SELF 0x00800000
405 #define CMDSTS_DEST_MULTI 0x01000000
406
407 #define DESC_SIZE 8 /* Should be cache line sized */
408
409 struct rx_info {
410 spinlock_t lock;
411 int up;
412 long idle;
413
414 struct sk_buff *skbs[NR_RX_DESC];
415
416 __le32 *next_rx_desc;
417 u16 next_rx, next_empty;
418
419 __le32 *descs;
420 dma_addr_t phy_descs;
421 };
422
423
424 struct ns83820 {
425 struct net_device_stats stats;
426 u8 __iomem *base;
427
428 struct pci_dev *pci_dev;
429 struct net_device *ndev;
430
431 #ifdef NS83820_VLAN_ACCEL_SUPPORT
432 struct vlan_group *vlgrp;
433 #endif
434
435 struct rx_info rx_info;
436 struct tasklet_struct rx_tasklet;
437
438 unsigned ihr;
439 struct work_struct tq_refill;
440
441 /* protects everything below. irqsave when using. */
442 spinlock_t misc_lock;
443
444 u32 CFG_cache;
445
446 u32 MEAR_cache;
447 u32 IMR_cache;
448
449 unsigned linkstate;
450
451 spinlock_t tx_lock;
452
453 u16 tx_done_idx;
454 u16 tx_idx;
455 volatile u16 tx_free_idx; /* idx of free desc chain */
456 u16 tx_intr_idx;
457
458 atomic_t nr_tx_skbs;
459 struct sk_buff *tx_skbs[NR_TX_DESC];
460
461 char pad[16] __attribute__((aligned(16)));
462 __le32 *tx_descs;
463 dma_addr_t tx_phy_descs;
464
465 struct timer_list tx_watchdog;
466 };
467
468 static inline struct ns83820 *PRIV(struct net_device *dev)
469 {
470 return netdev_priv(dev);
471 }
472
473 #define __kick_rx(dev) writel(CR_RXE, dev->base + CR)
474
475 static inline void kick_rx(struct net_device *ndev)
476 {
477 struct ns83820 *dev = PRIV(ndev);
478 dprintk("kick_rx: maybe kicking\n");
479 if (test_and_clear_bit(0, &dev->rx_info.idle)) {
480 dprintk("actually kicking\n");
481 writel(dev->rx_info.phy_descs +
482 (4 * DESC_SIZE * dev->rx_info.next_rx),
483 dev->base + RXDP);
484 if (dev->rx_info.next_rx == dev->rx_info.next_empty)
485 printk(KERN_DEBUG "%s: uh-oh: next_rx == next_empty???\n",
486 ndev->name);
487 __kick_rx(dev);
488 }
489 }
490
491 //free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC
492 #define start_tx_okay(dev) \
493 (((NR_TX_DESC-2 + dev->tx_done_idx - dev->tx_free_idx) % NR_TX_DESC) > MIN_TX_DESC_FREE)
494
495
496 #ifdef NS83820_VLAN_ACCEL_SUPPORT
497 static void ns83820_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
498 {
499 struct ns83820 *dev = PRIV(ndev);
500
501 spin_lock_irq(&dev->misc_lock);
502 spin_lock(&dev->tx_lock);
503
504 dev->vlgrp = grp;
505
506 spin_unlock(&dev->tx_lock);
507 spin_unlock_irq(&dev->misc_lock);
508 }
509 #endif
510
511 /* Packet Receiver
512 *
513 * The hardware supports linked lists of receive descriptors for
514 * which ownership is transfered back and forth by means of an
515 * ownership bit. While the hardware does support the use of a
516 * ring for receive descriptors, we only make use of a chain in
517 * an attempt to reduce bus traffic under heavy load scenarios.
518 * This will also make bugs a bit more obvious. The current code
519 * only makes use of a single rx chain; I hope to implement
520 * priority based rx for version 1.0. Goal: even under overload
521 * conditions, still route realtime traffic with as low jitter as
522 * possible.
523 */
524 static inline void build_rx_desc(struct ns83820 *dev, __le32 *desc, dma_addr_t link, dma_addr_t buf, u32 cmdsts, u32 extsts)
525 {
526 desc_addr_set(desc + DESC_LINK, link);
527 desc_addr_set(desc + DESC_BUFPTR, buf);
528 desc[DESC_EXTSTS] = cpu_to_le32(extsts);
529 mb();
530 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
531 }
532
533 #define nr_rx_empty(dev) ((NR_RX_DESC-2 + dev->rx_info.next_rx - dev->rx_info.next_empty) % NR_RX_DESC)
534 static inline int ns83820_add_rx_skb(struct ns83820 *dev, struct sk_buff *skb)
535 {
536 unsigned next_empty;
537 u32 cmdsts;
538 __le32 *sg;
539 dma_addr_t buf;
540
541 next_empty = dev->rx_info.next_empty;
542
543 /* don't overrun last rx marker */
544 if (unlikely(nr_rx_empty(dev) <= 2)) {
545 kfree_skb(skb);
546 return 1;
547 }
548
549 #if 0
550 dprintk("next_empty[%d] nr_used[%d] next_rx[%d]\n",
551 dev->rx_info.next_empty,
552 dev->rx_info.nr_used,
553 dev->rx_info.next_rx
554 );
555 #endif
556
557 sg = dev->rx_info.descs + (next_empty * DESC_SIZE);
558 BUG_ON(NULL != dev->rx_info.skbs[next_empty]);
559 dev->rx_info.skbs[next_empty] = skb;
560
561 dev->rx_info.next_empty = (next_empty + 1) % NR_RX_DESC;
562 cmdsts = REAL_RX_BUF_SIZE | CMDSTS_INTR;
563 buf = pci_map_single(dev->pci_dev, skb->data,
564 REAL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
565 build_rx_desc(dev, sg, 0, buf, cmdsts, 0);
566 /* update link of previous rx */
567 if (likely(next_empty != dev->rx_info.next_rx))
568 dev->rx_info.descs[((NR_RX_DESC + next_empty - 1) % NR_RX_DESC) * DESC_SIZE] = cpu_to_le32(dev->rx_info.phy_descs + (next_empty * DESC_SIZE * 4));
569
570 return 0;
571 }
572
573 static inline int rx_refill(struct net_device *ndev, gfp_t gfp)
574 {
575 struct ns83820 *dev = PRIV(ndev);
576 unsigned i;
577 unsigned long flags = 0;
578
579 if (unlikely(nr_rx_empty(dev) <= 2))
580 return 0;
581
582 dprintk("rx_refill(%p)\n", ndev);
583 if (gfp == GFP_ATOMIC)
584 spin_lock_irqsave(&dev->rx_info.lock, flags);
585 for (i=0; i<NR_RX_DESC; i++) {
586 struct sk_buff *skb;
587 long res;
588
589 /* extra 16 bytes for alignment */
590 skb = __netdev_alloc_skb(ndev, REAL_RX_BUF_SIZE+16, gfp);
591 if (unlikely(!skb))
592 break;
593
594 skb_reserve(skb, skb->data - PTR_ALIGN(skb->data, 16));
595 if (gfp != GFP_ATOMIC)
596 spin_lock_irqsave(&dev->rx_info.lock, flags);
597 res = ns83820_add_rx_skb(dev, skb);
598 if (gfp != GFP_ATOMIC)
599 spin_unlock_irqrestore(&dev->rx_info.lock, flags);
600 if (res) {
601 i = 1;
602 break;
603 }
604 }
605 if (gfp == GFP_ATOMIC)
606 spin_unlock_irqrestore(&dev->rx_info.lock, flags);
607
608 return i ? 0 : -ENOMEM;
609 }
610
611 static void rx_refill_atomic(struct net_device *ndev)
612 {
613 rx_refill(ndev, GFP_ATOMIC);
614 }
615
616 /* REFILL */
617 static inline void queue_refill(struct work_struct *work)
618 {
619 struct ns83820 *dev = container_of(work, struct ns83820, tq_refill);
620 struct net_device *ndev = dev->ndev;
621
622 rx_refill(ndev, GFP_KERNEL);
623 if (dev->rx_info.up)
624 kick_rx(ndev);
625 }
626
627 static inline void clear_rx_desc(struct ns83820 *dev, unsigned i)
628 {
629 build_rx_desc(dev, dev->rx_info.descs + (DESC_SIZE * i), 0, 0, CMDSTS_OWN, 0);
630 }
631
632 static void phy_intr(struct net_device *ndev)
633 {
634 struct ns83820 *dev = PRIV(ndev);
635 static const char *speeds[] = { "10", "100", "1000", "1000(?)", "1000F" };
636 u32 cfg, new_cfg;
637 u32 tbisr, tanar, tanlpar;
638 int speed, fullduplex, newlinkstate;
639
640 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
641
642 if (dev->CFG_cache & CFG_TBI_EN) {
643 /* we have an optical transceiver */
644 tbisr = readl(dev->base + TBISR);
645 tanar = readl(dev->base + TANAR);
646 tanlpar = readl(dev->base + TANLPAR);
647 dprintk("phy_intr: tbisr=%08x, tanar=%08x, tanlpar=%08x\n",
648 tbisr, tanar, tanlpar);
649
650 if ( (fullduplex = (tanlpar & TANAR_FULL_DUP)
651 && (tanar & TANAR_FULL_DUP)) ) {
652
653 /* both of us are full duplex */
654 writel(readl(dev->base + TXCFG)
655 | TXCFG_CSI | TXCFG_HBI | TXCFG_ATP,
656 dev->base + TXCFG);
657 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
658 dev->base + RXCFG);
659 /* Light up full duplex LED */
660 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT,
661 dev->base + GPIOR);
662
663 } else if(((tanlpar & TANAR_HALF_DUP)
664 && (tanar & TANAR_HALF_DUP))
665 || ((tanlpar & TANAR_FULL_DUP)
666 && (tanar & TANAR_HALF_DUP))
667 || ((tanlpar & TANAR_HALF_DUP)
668 && (tanar & TANAR_FULL_DUP))) {
669
670 /* one or both of us are half duplex */
671 writel((readl(dev->base + TXCFG)
672 & ~(TXCFG_CSI | TXCFG_HBI)) | TXCFG_ATP,
673 dev->base + TXCFG);
674 writel(readl(dev->base + RXCFG) & ~RXCFG_RX_FD,
675 dev->base + RXCFG);
676 /* Turn off full duplex LED */
677 writel(readl(dev->base + GPIOR) & ~GPIOR_GP1_OUT,
678 dev->base + GPIOR);
679 }
680
681 speed = 4; /* 1000F */
682
683 } else {
684 /* we have a copper transceiver */
685 new_cfg = dev->CFG_cache & ~(CFG_SB | CFG_MODE_1000 | CFG_SPDSTS);
686
687 if (cfg & CFG_SPDSTS1)
688 new_cfg |= CFG_MODE_1000;
689 else
690 new_cfg &= ~CFG_MODE_1000;
691
692 speed = ((cfg / CFG_SPDSTS0) & 3);
693 fullduplex = (cfg & CFG_DUPSTS);
694
695 if (fullduplex) {
696 new_cfg |= CFG_SB;
697 writel(readl(dev->base + TXCFG)
698 | TXCFG_CSI | TXCFG_HBI,
699 dev->base + TXCFG);
700 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
701 dev->base + RXCFG);
702 } else {
703 writel(readl(dev->base + TXCFG)
704 & ~(TXCFG_CSI | TXCFG_HBI),
705 dev->base + TXCFG);
706 writel(readl(dev->base + RXCFG) & ~(RXCFG_RX_FD),
707 dev->base + RXCFG);
708 }
709
710 if ((cfg & CFG_LNKSTS) &&
711 ((new_cfg ^ dev->CFG_cache) != 0)) {
712 writel(new_cfg, dev->base + CFG);
713 dev->CFG_cache = new_cfg;
714 }
715
716 dev->CFG_cache &= ~CFG_SPDSTS;
717 dev->CFG_cache |= cfg & CFG_SPDSTS;
718 }
719
720 newlinkstate = (cfg & CFG_LNKSTS) ? LINK_UP : LINK_DOWN;
721
722 if (newlinkstate & LINK_UP
723 && dev->linkstate != newlinkstate) {
724 netif_start_queue(ndev);
725 netif_wake_queue(ndev);
726 printk(KERN_INFO "%s: link now %s mbps, %s duplex and up.\n",
727 ndev->name,
728 speeds[speed],
729 fullduplex ? "full" : "half");
730 } else if (newlinkstate & LINK_DOWN
731 && dev->linkstate != newlinkstate) {
732 netif_stop_queue(ndev);
733 printk(KERN_INFO "%s: link now down.\n", ndev->name);
734 }
735
736 dev->linkstate = newlinkstate;
737 }
738
739 static int ns83820_setup_rx(struct net_device *ndev)
740 {
741 struct ns83820 *dev = PRIV(ndev);
742 unsigned i;
743 int ret;
744
745 dprintk("ns83820_setup_rx(%p)\n", ndev);
746
747 dev->rx_info.idle = 1;
748 dev->rx_info.next_rx = 0;
749 dev->rx_info.next_rx_desc = dev->rx_info.descs;
750 dev->rx_info.next_empty = 0;
751
752 for (i=0; i<NR_RX_DESC; i++)
753 clear_rx_desc(dev, i);
754
755 writel(0, dev->base + RXDP_HI);
756 writel(dev->rx_info.phy_descs, dev->base + RXDP);
757
758 ret = rx_refill(ndev, GFP_KERNEL);
759 if (!ret) {
760 dprintk("starting receiver\n");
761 /* prevent the interrupt handler from stomping on us */
762 spin_lock_irq(&dev->rx_info.lock);
763
764 writel(0x0001, dev->base + CCSR);
765 writel(0, dev->base + RFCR);
766 writel(0x7fc00000, dev->base + RFCR);
767 writel(0xffc00000, dev->base + RFCR);
768
769 dev->rx_info.up = 1;
770
771 phy_intr(ndev);
772
773 /* Okay, let it rip */
774 spin_lock_irq(&dev->misc_lock);
775 dev->IMR_cache |= ISR_PHY;
776 dev->IMR_cache |= ISR_RXRCMP;
777 //dev->IMR_cache |= ISR_RXERR;
778 //dev->IMR_cache |= ISR_RXOK;
779 dev->IMR_cache |= ISR_RXORN;
780 dev->IMR_cache |= ISR_RXSOVR;
781 dev->IMR_cache |= ISR_RXDESC;
782 dev->IMR_cache |= ISR_RXIDLE;
783 dev->IMR_cache |= ISR_TXDESC;
784 dev->IMR_cache |= ISR_TXIDLE;
785
786 writel(dev->IMR_cache, dev->base + IMR);
787 writel(1, dev->base + IER);
788 spin_unlock(&dev->misc_lock);
789
790 kick_rx(ndev);
791
792 spin_unlock_irq(&dev->rx_info.lock);
793 }
794 return ret;
795 }
796
797 static void ns83820_cleanup_rx(struct ns83820 *dev)
798 {
799 unsigned i;
800 unsigned long flags;
801
802 dprintk("ns83820_cleanup_rx(%p)\n", dev);
803
804 /* disable receive interrupts */
805 spin_lock_irqsave(&dev->misc_lock, flags);
806 dev->IMR_cache &= ~(ISR_RXOK | ISR_RXDESC | ISR_RXERR | ISR_RXEARLY | ISR_RXIDLE);
807 writel(dev->IMR_cache, dev->base + IMR);
808 spin_unlock_irqrestore(&dev->misc_lock, flags);
809
810 /* synchronize with the interrupt handler and kill it */
811 dev->rx_info.up = 0;
812 synchronize_irq(dev->pci_dev->irq);
813
814 /* touch the pci bus... */
815 readl(dev->base + IMR);
816
817 /* assumes the transmitter is already disabled and reset */
818 writel(0, dev->base + RXDP_HI);
819 writel(0, dev->base + RXDP);
820
821 for (i=0; i<NR_RX_DESC; i++) {
822 struct sk_buff *skb = dev->rx_info.skbs[i];
823 dev->rx_info.skbs[i] = NULL;
824 clear_rx_desc(dev, i);
825 if (skb)
826 kfree_skb(skb);
827 }
828 }
829
830 static void ns83820_rx_kick(struct net_device *ndev)
831 {
832 struct ns83820 *dev = PRIV(ndev);
833 /*if (nr_rx_empty(dev) >= NR_RX_DESC/4)*/ {
834 if (dev->rx_info.up) {
835 rx_refill_atomic(ndev);
836 kick_rx(ndev);
837 }
838 }
839
840 if (dev->rx_info.up && nr_rx_empty(dev) > NR_RX_DESC*3/4)
841 schedule_work(&dev->tq_refill);
842 else
843 kick_rx(ndev);
844 if (dev->rx_info.idle)
845 printk(KERN_DEBUG "%s: BAD\n", ndev->name);
846 }
847
848 /* rx_irq
849 *
850 */
851 static void rx_irq(struct net_device *ndev)
852 {
853 struct ns83820 *dev = PRIV(ndev);
854 struct rx_info *info = &dev->rx_info;
855 unsigned next_rx;
856 int rx_rc, len;
857 u32 cmdsts;
858 __le32 *desc;
859 unsigned long flags;
860 int nr = 0;
861
862 dprintk("rx_irq(%p)\n", ndev);
863 dprintk("rxdp: %08x, descs: %08lx next_rx[%d]: %p next_empty[%d]: %p\n",
864 readl(dev->base + RXDP),
865 (long)(dev->rx_info.phy_descs),
866 (int)dev->rx_info.next_rx,
867 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_rx)),
868 (int)dev->rx_info.next_empty,
869 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_empty))
870 );
871
872 spin_lock_irqsave(&info->lock, flags);
873 if (!info->up)
874 goto out;
875
876 dprintk("walking descs\n");
877 next_rx = info->next_rx;
878 desc = info->next_rx_desc;
879 while ((CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) &&
880 (cmdsts != CMDSTS_OWN)) {
881 struct sk_buff *skb;
882 u32 extsts = le32_to_cpu(desc[DESC_EXTSTS]);
883 dma_addr_t bufptr = desc_addr_get(desc + DESC_BUFPTR);
884
885 dprintk("cmdsts: %08x\n", cmdsts);
886 dprintk("link: %08x\n", cpu_to_le32(desc[DESC_LINK]));
887 dprintk("extsts: %08x\n", extsts);
888
889 skb = info->skbs[next_rx];
890 info->skbs[next_rx] = NULL;
891 info->next_rx = (next_rx + 1) % NR_RX_DESC;
892
893 mb();
894 clear_rx_desc(dev, next_rx);
895
896 pci_unmap_single(dev->pci_dev, bufptr,
897 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
898 len = cmdsts & CMDSTS_LEN_MASK;
899 #ifdef NS83820_VLAN_ACCEL_SUPPORT
900 /* NH: As was mentioned below, this chip is kinda
901 * brain dead about vlan tag stripping. Frames
902 * that are 64 bytes with a vlan header appended
903 * like arp frames, or pings, are flagged as Runts
904 * when the tag is stripped and hardware. This
905 * also means that the OK bit in the descriptor
906 * is cleared when the frame comes in so we have
907 * to do a specific length check here to make sure
908 * the frame would have been ok, had we not stripped
909 * the tag.
910 */
911 if (likely((CMDSTS_OK & cmdsts) ||
912 ((cmdsts & CMDSTS_RUNT) && len >= 56))) {
913 #else
914 if (likely(CMDSTS_OK & cmdsts)) {
915 #endif
916 skb_put(skb, len);
917 if (unlikely(!skb))
918 goto netdev_mangle_me_harder_failed;
919 if (cmdsts & CMDSTS_DEST_MULTI)
920 dev->stats.multicast ++;
921 dev->stats.rx_packets ++;
922 dev->stats.rx_bytes += len;
923 if ((extsts & 0x002a0000) && !(extsts & 0x00540000)) {
924 skb->ip_summed = CHECKSUM_UNNECESSARY;
925 } else {
926 skb->ip_summed = CHECKSUM_NONE;
927 }
928 skb->protocol = eth_type_trans(skb, ndev);
929 #ifdef NS83820_VLAN_ACCEL_SUPPORT
930 if(extsts & EXTSTS_VPKT) {
931 unsigned short tag;
932 tag = ntohs(extsts & EXTSTS_VTG_MASK);
933 rx_rc = vlan_hwaccel_rx(skb,dev->vlgrp,tag);
934 } else {
935 rx_rc = netif_rx(skb);
936 }
937 #else
938 rx_rc = netif_rx(skb);
939 #endif
940 if (NET_RX_DROP == rx_rc) {
941 netdev_mangle_me_harder_failed:
942 dev->stats.rx_dropped ++;
943 }
944 } else {
945 kfree_skb(skb);
946 }
947
948 nr++;
949 next_rx = info->next_rx;
950 desc = info->descs + (DESC_SIZE * next_rx);
951 }
952 info->next_rx = next_rx;
953 info->next_rx_desc = info->descs + (DESC_SIZE * next_rx);
954
955 out:
956 if (0 && !nr) {
957 Dprintk("dazed: cmdsts_f: %08x\n", cmdsts);
958 }
959
960 spin_unlock_irqrestore(&info->lock, flags);
961 }
962
963 static void rx_action(unsigned long _dev)
964 {
965 struct net_device *ndev = (void *)_dev;
966 struct ns83820 *dev = PRIV(ndev);
967 rx_irq(ndev);
968 writel(ihr, dev->base + IHR);
969
970 spin_lock_irq(&dev->misc_lock);
971 dev->IMR_cache |= ISR_RXDESC;
972 writel(dev->IMR_cache, dev->base + IMR);
973 spin_unlock_irq(&dev->misc_lock);
974
975 rx_irq(ndev);
976 ns83820_rx_kick(ndev);
977 }
978
979 /* Packet Transmit code
980 */
981 static inline void kick_tx(struct ns83820 *dev)
982 {
983 dprintk("kick_tx(%p): tx_idx=%d free_idx=%d\n",
984 dev, dev->tx_idx, dev->tx_free_idx);
985 writel(CR_TXE, dev->base + CR);
986 }
987
988 /* No spinlock needed on the transmit irq path as the interrupt handler is
989 * serialized.
990 */
991 static void do_tx_done(struct net_device *ndev)
992 {
993 struct ns83820 *dev = PRIV(ndev);
994 u32 cmdsts, tx_done_idx;
995 __le32 *desc;
996
997 dprintk("do_tx_done(%p)\n", ndev);
998 tx_done_idx = dev->tx_done_idx;
999 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1000
1001 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1002 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1003 while ((tx_done_idx != dev->tx_free_idx) &&
1004 !(CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) ) {
1005 struct sk_buff *skb;
1006 unsigned len;
1007 dma_addr_t addr;
1008
1009 if (cmdsts & CMDSTS_ERR)
1010 dev->stats.tx_errors ++;
1011 if (cmdsts & CMDSTS_OK)
1012 dev->stats.tx_packets ++;
1013 if (cmdsts & CMDSTS_OK)
1014 dev->stats.tx_bytes += cmdsts & 0xffff;
1015
1016 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1017 tx_done_idx, dev->tx_free_idx, cmdsts);
1018 skb = dev->tx_skbs[tx_done_idx];
1019 dev->tx_skbs[tx_done_idx] = NULL;
1020 dprintk("done(%p)\n", skb);
1021
1022 len = cmdsts & CMDSTS_LEN_MASK;
1023 addr = desc_addr_get(desc + DESC_BUFPTR);
1024 if (skb) {
1025 pci_unmap_single(dev->pci_dev,
1026 addr,
1027 len,
1028 PCI_DMA_TODEVICE);
1029 dev_kfree_skb_irq(skb);
1030 atomic_dec(&dev->nr_tx_skbs);
1031 } else
1032 pci_unmap_page(dev->pci_dev,
1033 addr,
1034 len,
1035 PCI_DMA_TODEVICE);
1036
1037 tx_done_idx = (tx_done_idx + 1) % NR_TX_DESC;
1038 dev->tx_done_idx = tx_done_idx;
1039 desc[DESC_CMDSTS] = cpu_to_le32(0);
1040 mb();
1041 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1042 }
1043
1044 /* Allow network stack to resume queueing packets after we've
1045 * finished transmitting at least 1/4 of the packets in the queue.
1046 */
1047 if (netif_queue_stopped(ndev) && start_tx_okay(dev)) {
1048 dprintk("start_queue(%p)\n", ndev);
1049 netif_start_queue(ndev);
1050 netif_wake_queue(ndev);
1051 }
1052 }
1053
1054 static void ns83820_cleanup_tx(struct ns83820 *dev)
1055 {
1056 unsigned i;
1057
1058 for (i=0; i<NR_TX_DESC; i++) {
1059 struct sk_buff *skb = dev->tx_skbs[i];
1060 dev->tx_skbs[i] = NULL;
1061 if (skb) {
1062 __le32 *desc = dev->tx_descs + (i * DESC_SIZE);
1063 pci_unmap_single(dev->pci_dev,
1064 desc_addr_get(desc + DESC_BUFPTR),
1065 le32_to_cpu(desc[DESC_CMDSTS]) & CMDSTS_LEN_MASK,
1066 PCI_DMA_TODEVICE);
1067 dev_kfree_skb_irq(skb);
1068 atomic_dec(&dev->nr_tx_skbs);
1069 }
1070 }
1071
1072 memset(dev->tx_descs, 0, NR_TX_DESC * DESC_SIZE * 4);
1073 }
1074
1075 /* transmit routine. This code relies on the network layer serializing
1076 * its calls in, but will run happily in parallel with the interrupt
1077 * handler. This code currently has provisions for fragmenting tx buffers
1078 * while trying to track down a bug in either the zero copy code or
1079 * the tx fifo (hence the MAX_FRAG_LEN).
1080 */
1081 static int ns83820_hard_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1082 {
1083 struct ns83820 *dev = PRIV(ndev);
1084 u32 free_idx, cmdsts, extsts;
1085 int nr_free, nr_frags;
1086 unsigned tx_done_idx, last_idx;
1087 dma_addr_t buf;
1088 unsigned len;
1089 skb_frag_t *frag;
1090 int stopped = 0;
1091 int do_intr = 0;
1092 volatile __le32 *first_desc;
1093
1094 dprintk("ns83820_hard_start_xmit\n");
1095
1096 nr_frags = skb_shinfo(skb)->nr_frags;
1097 again:
1098 if (unlikely(dev->CFG_cache & CFG_LNKSTS)) {
1099 netif_stop_queue(ndev);
1100 if (unlikely(dev->CFG_cache & CFG_LNKSTS))
1101 return 1;
1102 netif_start_queue(ndev);
1103 }
1104
1105 last_idx = free_idx = dev->tx_free_idx;
1106 tx_done_idx = dev->tx_done_idx;
1107 nr_free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC;
1108 nr_free -= 1;
1109 if (nr_free <= nr_frags) {
1110 dprintk("stop_queue - not enough(%p)\n", ndev);
1111 netif_stop_queue(ndev);
1112
1113 /* Check again: we may have raced with a tx done irq */
1114 if (dev->tx_done_idx != tx_done_idx) {
1115 dprintk("restart queue(%p)\n", ndev);
1116 netif_start_queue(ndev);
1117 goto again;
1118 }
1119 return 1;
1120 }
1121
1122 if (free_idx == dev->tx_intr_idx) {
1123 do_intr = 1;
1124 dev->tx_intr_idx = (dev->tx_intr_idx + NR_TX_DESC/4) % NR_TX_DESC;
1125 }
1126
1127 nr_free -= nr_frags;
1128 if (nr_free < MIN_TX_DESC_FREE) {
1129 dprintk("stop_queue - last entry(%p)\n", ndev);
1130 netif_stop_queue(ndev);
1131 stopped = 1;
1132 }
1133
1134 frag = skb_shinfo(skb)->frags;
1135 if (!nr_frags)
1136 frag = NULL;
1137 extsts = 0;
1138 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1139 extsts |= EXTSTS_IPPKT;
1140 if (IPPROTO_TCP == ip_hdr(skb)->protocol)
1141 extsts |= EXTSTS_TCPPKT;
1142 else if (IPPROTO_UDP == ip_hdr(skb)->protocol)
1143 extsts |= EXTSTS_UDPPKT;
1144 }
1145
1146 #ifdef NS83820_VLAN_ACCEL_SUPPORT
1147 if(vlan_tx_tag_present(skb)) {
1148 /* fetch the vlan tag info out of the
1149 * ancilliary data if the vlan code
1150 * is using hw vlan acceleration
1151 */
1152 short tag = vlan_tx_tag_get(skb);
1153 extsts |= (EXTSTS_VPKT | htons(tag));
1154 }
1155 #endif
1156
1157 len = skb->len;
1158 if (nr_frags)
1159 len -= skb->data_len;
1160 buf = pci_map_single(dev->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
1161
1162 first_desc = dev->tx_descs + (free_idx * DESC_SIZE);
1163
1164 for (;;) {
1165 volatile __le32 *desc = dev->tx_descs + (free_idx * DESC_SIZE);
1166
1167 dprintk("frag[%3u]: %4u @ 0x%08Lx\n", free_idx, len,
1168 (unsigned long long)buf);
1169 last_idx = free_idx;
1170 free_idx = (free_idx + 1) % NR_TX_DESC;
1171 desc[DESC_LINK] = cpu_to_le32(dev->tx_phy_descs + (free_idx * DESC_SIZE * 4));
1172 desc_addr_set(desc + DESC_BUFPTR, buf);
1173 desc[DESC_EXTSTS] = cpu_to_le32(extsts);
1174
1175 cmdsts = ((nr_frags) ? CMDSTS_MORE : do_intr ? CMDSTS_INTR : 0);
1176 cmdsts |= (desc == first_desc) ? 0 : CMDSTS_OWN;
1177 cmdsts |= len;
1178 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
1179
1180 if (!nr_frags)
1181 break;
1182
1183 buf = pci_map_page(dev->pci_dev, frag->page,
1184 frag->page_offset,
1185 frag->size, PCI_DMA_TODEVICE);
1186 dprintk("frag: buf=%08Lx page=%08lx offset=%08lx\n",
1187 (long long)buf, (long) page_to_pfn(frag->page),
1188 frag->page_offset);
1189 len = frag->size;
1190 frag++;
1191 nr_frags--;
1192 }
1193 dprintk("done pkt\n");
1194
1195 spin_lock_irq(&dev->tx_lock);
1196 dev->tx_skbs[last_idx] = skb;
1197 first_desc[DESC_CMDSTS] |= cpu_to_le32(CMDSTS_OWN);
1198 dev->tx_free_idx = free_idx;
1199 atomic_inc(&dev->nr_tx_skbs);
1200 spin_unlock_irq(&dev->tx_lock);
1201
1202 kick_tx(dev);
1203
1204 /* Check again: we may have raced with a tx done irq */
1205 if (stopped && (dev->tx_done_idx != tx_done_idx) && start_tx_okay(dev))
1206 netif_start_queue(ndev);
1207
1208 /* set the transmit start time to catch transmit timeouts */
1209 ndev->trans_start = jiffies;
1210 return 0;
1211 }
1212
1213 static void ns83820_update_stats(struct ns83820 *dev)
1214 {
1215 u8 __iomem *base = dev->base;
1216
1217 /* the DP83820 will freeze counters, so we need to read all of them */
1218 dev->stats.rx_errors += readl(base + 0x60) & 0xffff;
1219 dev->stats.rx_crc_errors += readl(base + 0x64) & 0xffff;
1220 dev->stats.rx_missed_errors += readl(base + 0x68) & 0xffff;
1221 dev->stats.rx_frame_errors += readl(base + 0x6c) & 0xffff;
1222 /*dev->stats.rx_symbol_errors +=*/ readl(base + 0x70);
1223 dev->stats.rx_length_errors += readl(base + 0x74) & 0xffff;
1224 dev->stats.rx_length_errors += readl(base + 0x78) & 0xffff;
1225 /*dev->stats.rx_badopcode_errors += */ readl(base + 0x7c);
1226 /*dev->stats.rx_pause_count += */ readl(base + 0x80);
1227 /*dev->stats.tx_pause_count += */ readl(base + 0x84);
1228 dev->stats.tx_carrier_errors += readl(base + 0x88) & 0xff;
1229 }
1230
1231 static struct net_device_stats *ns83820_get_stats(struct net_device *ndev)
1232 {
1233 struct ns83820 *dev = PRIV(ndev);
1234
1235 /* somewhat overkill */
1236 spin_lock_irq(&dev->misc_lock);
1237 ns83820_update_stats(dev);
1238 spin_unlock_irq(&dev->misc_lock);
1239
1240 return &dev->stats;
1241 }
1242
1243 /* Let ethtool retrieve info */
1244 static int ns83820_get_settings(struct net_device *ndev,
1245 struct ethtool_cmd *cmd)
1246 {
1247 struct ns83820 *dev = PRIV(ndev);
1248 u32 cfg, tanar, tbicr;
1249 int have_optical = 0;
1250 int fullduplex = 0;
1251
1252 /*
1253 * Here's the list of available ethtool commands from other drivers:
1254 * cmd->advertising =
1255 * cmd->speed =
1256 * cmd->duplex =
1257 * cmd->port = 0;
1258 * cmd->phy_address =
1259 * cmd->transceiver = 0;
1260 * cmd->autoneg =
1261 * cmd->maxtxpkt = 0;
1262 * cmd->maxrxpkt = 0;
1263 */
1264
1265 /* read current configuration */
1266 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1267 tanar = readl(dev->base + TANAR);
1268 tbicr = readl(dev->base + TBICR);
1269
1270 if (dev->CFG_cache & CFG_TBI_EN) {
1271 /* we have an optical interface */
1272 have_optical = 1;
1273 fullduplex = (cfg & CFG_DUPSTS) ? 1 : 0;
1274
1275 } else {
1276 /* We have copper */
1277 fullduplex = (cfg & CFG_DUPSTS) ? 1 : 0;
1278 }
1279
1280 cmd->supported = SUPPORTED_Autoneg;
1281
1282 /* we have optical interface */
1283 if (dev->CFG_cache & CFG_TBI_EN) {
1284 cmd->supported |= SUPPORTED_1000baseT_Half |
1285 SUPPORTED_1000baseT_Full |
1286 SUPPORTED_FIBRE;
1287 cmd->port = PORT_FIBRE;
1288 } /* TODO: else copper related support */
1289
1290 cmd->duplex = fullduplex ? DUPLEX_FULL : DUPLEX_HALF;
1291 switch (cfg / CFG_SPDSTS0 & 3) {
1292 case 2:
1293 cmd->speed = SPEED_1000;
1294 break;
1295 case 1:
1296 cmd->speed = SPEED_100;
1297 break;
1298 default:
1299 cmd->speed = SPEED_10;
1300 break;
1301 }
1302 cmd->autoneg = (tbicr & TBICR_MR_AN_ENABLE) ? 1: 0;
1303 return 0;
1304 }
1305
1306 /* Let ethool change settings*/
1307 static int ns83820_set_settings(struct net_device *ndev,
1308 struct ethtool_cmd *cmd)
1309 {
1310 struct ns83820 *dev = PRIV(ndev);
1311 u32 cfg, tanar;
1312 int have_optical = 0;
1313 int fullduplex = 0;
1314
1315 /* read current configuration */
1316 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1317 tanar = readl(dev->base + TANAR);
1318
1319 if (dev->CFG_cache & CFG_TBI_EN) {
1320 /* we have optical */
1321 have_optical = 1;
1322 fullduplex = (tanar & TANAR_FULL_DUP);
1323
1324 } else {
1325 /* we have copper */
1326 fullduplex = cfg & CFG_DUPSTS;
1327 }
1328
1329 spin_lock_irq(&dev->misc_lock);
1330 spin_lock(&dev->tx_lock);
1331
1332 /* Set duplex */
1333 if (cmd->duplex != fullduplex) {
1334 if (have_optical) {
1335 /*set full duplex*/
1336 if (cmd->duplex == DUPLEX_FULL) {
1337 /* force full duplex */
1338 writel(readl(dev->base + TXCFG)
1339 | TXCFG_CSI | TXCFG_HBI | TXCFG_ATP,
1340 dev->base + TXCFG);
1341 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
1342 dev->base + RXCFG);
1343 /* Light up full duplex LED */
1344 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT,
1345 dev->base + GPIOR);
1346 } else {
1347 /*TODO: set half duplex */
1348 }
1349
1350 } else {
1351 /*we have copper*/
1352 /* TODO: Set duplex for copper cards */
1353 }
1354 printk(KERN_INFO "%s: Duplex set via ethtool\n",
1355 ndev->name);
1356 }
1357
1358 /* Set autonegotiation */
1359 if (1) {
1360 if (cmd->autoneg == AUTONEG_ENABLE) {
1361 /* restart auto negotiation */
1362 writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN,
1363 dev->base + TBICR);
1364 writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
1365 dev->linkstate = LINK_AUTONEGOTIATE;
1366
1367 printk(KERN_INFO "%s: autoneg enabled via ethtool\n",
1368 ndev->name);
1369 } else {
1370 /* disable auto negotiation */
1371 writel(0x00000000, dev->base + TBICR);
1372 }
1373
1374 printk(KERN_INFO "%s: autoneg %s via ethtool\n", ndev->name,
1375 cmd->autoneg ? "ENABLED" : "DISABLED");
1376 }
1377
1378 phy_intr(ndev);
1379 spin_unlock(&dev->tx_lock);
1380 spin_unlock_irq(&dev->misc_lock);
1381
1382 return 0;
1383 }
1384 /* end ethtool get/set support -df */
1385
1386 static void ns83820_get_drvinfo(struct net_device *ndev, struct ethtool_drvinfo *info)
1387 {
1388 struct ns83820 *dev = PRIV(ndev);
1389 strcpy(info->driver, "ns83820");
1390 strcpy(info->version, VERSION);
1391 strcpy(info->bus_info, pci_name(dev->pci_dev));
1392 }
1393
1394 static u32 ns83820_get_link(struct net_device *ndev)
1395 {
1396 struct ns83820 *dev = PRIV(ndev);
1397 u32 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1398 return cfg & CFG_LNKSTS ? 1 : 0;
1399 }
1400
1401 static const struct ethtool_ops ops = {
1402 .get_settings = ns83820_get_settings,
1403 .set_settings = ns83820_set_settings,
1404 .get_drvinfo = ns83820_get_drvinfo,
1405 .get_link = ns83820_get_link
1406 };
1407
1408 /* this function is called in irq context from the ISR */
1409 static void ns83820_mib_isr(struct ns83820 *dev)
1410 {
1411 unsigned long flags;
1412 spin_lock_irqsave(&dev->misc_lock, flags);
1413 ns83820_update_stats(dev);
1414 spin_unlock_irqrestore(&dev->misc_lock, flags);
1415 }
1416
1417 static void ns83820_do_isr(struct net_device *ndev, u32 isr);
1418 static irqreturn_t ns83820_irq(int foo, void *data)
1419 {
1420 struct net_device *ndev = data;
1421 struct ns83820 *dev = PRIV(ndev);
1422 u32 isr;
1423 dprintk("ns83820_irq(%p)\n", ndev);
1424
1425 dev->ihr = 0;
1426
1427 isr = readl(dev->base + ISR);
1428 dprintk("irq: %08x\n", isr);
1429 ns83820_do_isr(ndev, isr);
1430 return IRQ_HANDLED;
1431 }
1432
1433 static void ns83820_do_isr(struct net_device *ndev, u32 isr)
1434 {
1435 struct ns83820 *dev = PRIV(ndev);
1436 unsigned long flags;
1437
1438 #ifdef DEBUG
1439 if (isr & ~(ISR_PHY | ISR_RXDESC | ISR_RXEARLY | ISR_RXOK | ISR_RXERR | ISR_TXIDLE | ISR_TXOK | ISR_TXDESC))
1440 Dprintk("odd isr? 0x%08x\n", isr);
1441 #endif
1442
1443 if (ISR_RXIDLE & isr) {
1444 dev->rx_info.idle = 1;
1445 Dprintk("oh dear, we are idle\n");
1446 ns83820_rx_kick(ndev);
1447 }
1448
1449 if ((ISR_RXDESC | ISR_RXOK) & isr) {
1450 prefetch(dev->rx_info.next_rx_desc);
1451
1452 spin_lock_irqsave(&dev->misc_lock, flags);
1453 dev->IMR_cache &= ~(ISR_RXDESC | ISR_RXOK);
1454 writel(dev->IMR_cache, dev->base + IMR);
1455 spin_unlock_irqrestore(&dev->misc_lock, flags);
1456
1457 tasklet_schedule(&dev->rx_tasklet);
1458 //rx_irq(ndev);
1459 //writel(4, dev->base + IHR);
1460 }
1461
1462 if ((ISR_RXIDLE | ISR_RXORN | ISR_RXDESC | ISR_RXOK | ISR_RXERR) & isr)
1463 ns83820_rx_kick(ndev);
1464
1465 if (unlikely(ISR_RXSOVR & isr)) {
1466 //printk("overrun: rxsovr\n");
1467 dev->stats.rx_fifo_errors ++;
1468 }
1469
1470 if (unlikely(ISR_RXORN & isr)) {
1471 //printk("overrun: rxorn\n");
1472 dev->stats.rx_fifo_errors ++;
1473 }
1474
1475 if ((ISR_RXRCMP & isr) && dev->rx_info.up)
1476 writel(CR_RXE, dev->base + CR);
1477
1478 if (ISR_TXIDLE & isr) {
1479 u32 txdp;
1480 txdp = readl(dev->base + TXDP);
1481 dprintk("txdp: %08x\n", txdp);
1482 txdp -= dev->tx_phy_descs;
1483 dev->tx_idx = txdp / (DESC_SIZE * 4);
1484 if (dev->tx_idx >= NR_TX_DESC) {
1485 printk(KERN_ALERT "%s: BUG -- txdp out of range\n", ndev->name);
1486 dev->tx_idx = 0;
1487 }
1488 /* The may have been a race between a pci originated read
1489 * and the descriptor update from the cpu. Just in case,
1490 * kick the transmitter if the hardware thinks it is on a
1491 * different descriptor than we are.
1492 */
1493 if (dev->tx_idx != dev->tx_free_idx)
1494 kick_tx(dev);
1495 }
1496
1497 /* Defer tx ring processing until more than a minimum amount of
1498 * work has accumulated
1499 */
1500 if ((ISR_TXDESC | ISR_TXIDLE | ISR_TXOK | ISR_TXERR) & isr) {
1501 spin_lock_irqsave(&dev->tx_lock, flags);
1502 do_tx_done(ndev);
1503 spin_unlock_irqrestore(&dev->tx_lock, flags);
1504
1505 /* Disable TxOk if there are no outstanding tx packets.
1506 */
1507 if ((dev->tx_done_idx == dev->tx_free_idx) &&
1508 (dev->IMR_cache & ISR_TXOK)) {
1509 spin_lock_irqsave(&dev->misc_lock, flags);
1510 dev->IMR_cache &= ~ISR_TXOK;
1511 writel(dev->IMR_cache, dev->base + IMR);
1512 spin_unlock_irqrestore(&dev->misc_lock, flags);
1513 }
1514 }
1515
1516 /* The TxIdle interrupt can come in before the transmit has
1517 * completed. Normally we reap packets off of the combination
1518 * of TxDesc and TxIdle and leave TxOk disabled (since it
1519 * occurs on every packet), but when no further irqs of this
1520 * nature are expected, we must enable TxOk.
1521 */
1522 if ((ISR_TXIDLE & isr) && (dev->tx_done_idx != dev->tx_free_idx)) {
1523 spin_lock_irqsave(&dev->misc_lock, flags);
1524 dev->IMR_cache |= ISR_TXOK;
1525 writel(dev->IMR_cache, dev->base + IMR);
1526 spin_unlock_irqrestore(&dev->misc_lock, flags);
1527 }
1528
1529 /* MIB interrupt: one of the statistics counters is about to overflow */
1530 if (unlikely(ISR_MIB & isr))
1531 ns83820_mib_isr(dev);
1532
1533 /* PHY: Link up/down/negotiation state change */
1534 if (unlikely(ISR_PHY & isr))
1535 phy_intr(ndev);
1536
1537 #if 0 /* Still working on the interrupt mitigation strategy */
1538 if (dev->ihr)
1539 writel(dev->ihr, dev->base + IHR);
1540 #endif
1541 }
1542
1543 static void ns83820_do_reset(struct ns83820 *dev, u32 which)
1544 {
1545 Dprintk("resetting chip...\n");
1546 writel(which, dev->base + CR);
1547 do {
1548 schedule();
1549 } while (readl(dev->base + CR) & which);
1550 Dprintk("okay!\n");
1551 }
1552
1553 static int ns83820_stop(struct net_device *ndev)
1554 {
1555 struct ns83820 *dev = PRIV(ndev);
1556
1557 /* FIXME: protect against interrupt handler? */
1558 del_timer_sync(&dev->tx_watchdog);
1559
1560 /* disable interrupts */
1561 writel(0, dev->base + IMR);
1562 writel(0, dev->base + IER);
1563 readl(dev->base + IER);
1564
1565 dev->rx_info.up = 0;
1566 synchronize_irq(dev->pci_dev->irq);
1567
1568 ns83820_do_reset(dev, CR_RST);
1569
1570 synchronize_irq(dev->pci_dev->irq);
1571
1572 spin_lock_irq(&dev->misc_lock);
1573 dev->IMR_cache &= ~(ISR_TXURN | ISR_TXIDLE | ISR_TXERR | ISR_TXDESC | ISR_TXOK);
1574 spin_unlock_irq(&dev->misc_lock);
1575
1576 ns83820_cleanup_rx(dev);
1577 ns83820_cleanup_tx(dev);
1578
1579 return 0;
1580 }
1581
1582 static void ns83820_tx_timeout(struct net_device *ndev)
1583 {
1584 struct ns83820 *dev = PRIV(ndev);
1585 u32 tx_done_idx;
1586 __le32 *desc;
1587 unsigned long flags;
1588
1589 spin_lock_irqsave(&dev->tx_lock, flags);
1590
1591 tx_done_idx = dev->tx_done_idx;
1592 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1593
1594 printk(KERN_INFO "%s: tx_timeout: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1595 ndev->name,
1596 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1597
1598 #if defined(DEBUG)
1599 {
1600 u32 isr;
1601 isr = readl(dev->base + ISR);
1602 printk("irq: %08x imr: %08x\n", isr, dev->IMR_cache);
1603 ns83820_do_isr(ndev, isr);
1604 }
1605 #endif
1606
1607 do_tx_done(ndev);
1608
1609 tx_done_idx = dev->tx_done_idx;
1610 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1611
1612 printk(KERN_INFO "%s: after: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1613 ndev->name,
1614 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1615
1616 spin_unlock_irqrestore(&dev->tx_lock, flags);
1617 }
1618
1619 static void ns83820_tx_watch(unsigned long data)
1620 {
1621 struct net_device *ndev = (void *)data;
1622 struct ns83820 *dev = PRIV(ndev);
1623
1624 #if defined(DEBUG)
1625 printk("ns83820_tx_watch: %u %u %d\n",
1626 dev->tx_done_idx, dev->tx_free_idx, atomic_read(&dev->nr_tx_skbs)
1627 );
1628 #endif
1629
1630 if (time_after(jiffies, ndev->trans_start + 1*HZ) &&
1631 dev->tx_done_idx != dev->tx_free_idx) {
1632 printk(KERN_DEBUG "%s: ns83820_tx_watch: %u %u %d\n",
1633 ndev->name,
1634 dev->tx_done_idx, dev->tx_free_idx,
1635 atomic_read(&dev->nr_tx_skbs));
1636 ns83820_tx_timeout(ndev);
1637 }
1638
1639 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1640 }
1641
1642 static int ns83820_open(struct net_device *ndev)
1643 {
1644 struct ns83820 *dev = PRIV(ndev);
1645 unsigned i;
1646 u32 desc;
1647 int ret;
1648
1649 dprintk("ns83820_open\n");
1650
1651 writel(0, dev->base + PQCR);
1652
1653 ret = ns83820_setup_rx(ndev);
1654 if (ret)
1655 goto failed;
1656
1657 memset(dev->tx_descs, 0, 4 * NR_TX_DESC * DESC_SIZE);
1658 for (i=0; i<NR_TX_DESC; i++) {
1659 dev->tx_descs[(i * DESC_SIZE) + DESC_LINK]
1660 = cpu_to_le32(
1661 dev->tx_phy_descs
1662 + ((i+1) % NR_TX_DESC) * DESC_SIZE * 4);
1663 }
1664
1665 dev->tx_idx = 0;
1666 dev->tx_done_idx = 0;
1667 desc = dev->tx_phy_descs;
1668 writel(0, dev->base + TXDP_HI);
1669 writel(desc, dev->base + TXDP);
1670
1671 init_timer(&dev->tx_watchdog);
1672 dev->tx_watchdog.data = (unsigned long)ndev;
1673 dev->tx_watchdog.function = ns83820_tx_watch;
1674 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1675
1676 netif_start_queue(ndev); /* FIXME: wait for phy to come up */
1677
1678 return 0;
1679
1680 failed:
1681 ns83820_stop(ndev);
1682 return ret;
1683 }
1684
1685 static void ns83820_getmac(struct ns83820 *dev, u8 *mac)
1686 {
1687 unsigned i;
1688 for (i=0; i<3; i++) {
1689 u32 data;
1690
1691 /* Read from the perfect match memory: this is loaded by
1692 * the chip from the EEPROM via the EELOAD self test.
1693 */
1694 writel(i*2, dev->base + RFCR);
1695 data = readl(dev->base + RFDR);
1696
1697 *mac++ = data;
1698 *mac++ = data >> 8;
1699 }
1700 }
1701
1702 static int ns83820_change_mtu(struct net_device *ndev, int new_mtu)
1703 {
1704 if (new_mtu > RX_BUF_SIZE)
1705 return -EINVAL;
1706 ndev->mtu = new_mtu;
1707 return 0;
1708 }
1709
1710 static void ns83820_set_multicast(struct net_device *ndev)
1711 {
1712 struct ns83820 *dev = PRIV(ndev);
1713 u8 __iomem *rfcr = dev->base + RFCR;
1714 u32 and_mask = 0xffffffff;
1715 u32 or_mask = 0;
1716 u32 val;
1717
1718 if (ndev->flags & IFF_PROMISC)
1719 or_mask |= RFCR_AAU | RFCR_AAM;
1720 else
1721 and_mask &= ~(RFCR_AAU | RFCR_AAM);
1722
1723 if (ndev->flags & IFF_ALLMULTI || ndev->mc_count)
1724 or_mask |= RFCR_AAM;
1725 else
1726 and_mask &= ~RFCR_AAM;
1727
1728 spin_lock_irq(&dev->misc_lock);
1729 val = (readl(rfcr) & and_mask) | or_mask;
1730 /* Ramit : RFCR Write Fix doc says RFEN must be 0 modify other bits */
1731 writel(val & ~RFCR_RFEN, rfcr);
1732 writel(val, rfcr);
1733 spin_unlock_irq(&dev->misc_lock);
1734 }
1735
1736 static void ns83820_run_bist(struct net_device *ndev, const char *name, u32 enable, u32 done, u32 fail)
1737 {
1738 struct ns83820 *dev = PRIV(ndev);
1739 int timed_out = 0;
1740 unsigned long start;
1741 u32 status;
1742 int loops = 0;
1743
1744 dprintk("%s: start %s\n", ndev->name, name);
1745
1746 start = jiffies;
1747
1748 writel(enable, dev->base + PTSCR);
1749 for (;;) {
1750 loops++;
1751 status = readl(dev->base + PTSCR);
1752 if (!(status & enable))
1753 break;
1754 if (status & done)
1755 break;
1756 if (status & fail)
1757 break;
1758 if (time_after_eq(jiffies, start + HZ)) {
1759 timed_out = 1;
1760 break;
1761 }
1762 schedule_timeout_uninterruptible(1);
1763 }
1764
1765 if (status & fail)
1766 printk(KERN_INFO "%s: %s failed! (0x%08x & 0x%08x)\n",
1767 ndev->name, name, status, fail);
1768 else if (timed_out)
1769 printk(KERN_INFO "%s: run_bist %s timed out! (%08x)\n",
1770 ndev->name, name, status);
1771
1772 dprintk("%s: done %s in %d loops\n", ndev->name, name, loops);
1773 }
1774
1775 #ifdef PHY_CODE_IS_FINISHED
1776 static void ns83820_mii_write_bit(struct ns83820 *dev, int bit)
1777 {
1778 /* drive MDC low */
1779 dev->MEAR_cache &= ~MEAR_MDC;
1780 writel(dev->MEAR_cache, dev->base + MEAR);
1781 readl(dev->base + MEAR);
1782
1783 /* enable output, set bit */
1784 dev->MEAR_cache |= MEAR_MDDIR;
1785 if (bit)
1786 dev->MEAR_cache |= MEAR_MDIO;
1787 else
1788 dev->MEAR_cache &= ~MEAR_MDIO;
1789
1790 /* set the output bit */
1791 writel(dev->MEAR_cache, dev->base + MEAR);
1792 readl(dev->base + MEAR);
1793
1794 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */
1795 udelay(1);
1796
1797 /* drive MDC high causing the data bit to be latched */
1798 dev->MEAR_cache |= MEAR_MDC;
1799 writel(dev->MEAR_cache, dev->base + MEAR);
1800 readl(dev->base + MEAR);
1801
1802 /* Wait again... */
1803 udelay(1);
1804 }
1805
1806 static int ns83820_mii_read_bit(struct ns83820 *dev)
1807 {
1808 int bit;
1809
1810 /* drive MDC low, disable output */
1811 dev->MEAR_cache &= ~MEAR_MDC;
1812 dev->MEAR_cache &= ~MEAR_MDDIR;
1813 writel(dev->MEAR_cache, dev->base + MEAR);
1814 readl(dev->base + MEAR);
1815
1816 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */
1817 udelay(1);
1818
1819 /* drive MDC high causing the data bit to be latched */
1820 bit = (readl(dev->base + MEAR) & MEAR_MDIO) ? 1 : 0;
1821 dev->MEAR_cache |= MEAR_MDC;
1822 writel(dev->MEAR_cache, dev->base + MEAR);
1823
1824 /* Wait again... */
1825 udelay(1);
1826
1827 return bit;
1828 }
1829
1830 static unsigned ns83820_mii_read_reg(struct ns83820 *dev, unsigned phy, unsigned reg)
1831 {
1832 unsigned data = 0;
1833 int i;
1834
1835 /* read some garbage so that we eventually sync up */
1836 for (i=0; i<64; i++)
1837 ns83820_mii_read_bit(dev);
1838
1839 ns83820_mii_write_bit(dev, 0); /* start */
1840 ns83820_mii_write_bit(dev, 1);
1841 ns83820_mii_write_bit(dev, 1); /* opcode read */
1842 ns83820_mii_write_bit(dev, 0);
1843
1844 /* write out the phy address: 5 bits, msb first */
1845 for (i=0; i<5; i++)
1846 ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1847
1848 /* write out the register address, 5 bits, msb first */
1849 for (i=0; i<5; i++)
1850 ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1851
1852 ns83820_mii_read_bit(dev); /* turn around cycles */
1853 ns83820_mii_read_bit(dev);
1854
1855 /* read in the register data, 16 bits msb first */
1856 for (i=0; i<16; i++) {
1857 data <<= 1;
1858 data |= ns83820_mii_read_bit(dev);
1859 }
1860
1861 return data;
1862 }
1863
1864 static unsigned ns83820_mii_write_reg(struct ns83820 *dev, unsigned phy, unsigned reg, unsigned data)
1865 {
1866 int i;
1867
1868 /* read some garbage so that we eventually sync up */
1869 for (i=0; i<64; i++)
1870 ns83820_mii_read_bit(dev);
1871
1872 ns83820_mii_write_bit(dev, 0); /* start */
1873 ns83820_mii_write_bit(dev, 1);
1874 ns83820_mii_write_bit(dev, 0); /* opcode read */
1875 ns83820_mii_write_bit(dev, 1);
1876
1877 /* write out the phy address: 5 bits, msb first */
1878 for (i=0; i<5; i++)
1879 ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1880
1881 /* write out the register address, 5 bits, msb first */
1882 for (i=0; i<5; i++)
1883 ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1884
1885 ns83820_mii_read_bit(dev); /* turn around cycles */
1886 ns83820_mii_read_bit(dev);
1887
1888 /* read in the register data, 16 bits msb first */
1889 for (i=0; i<16; i++)
1890 ns83820_mii_write_bit(dev, (data >> (15 - i)) & 1);
1891
1892 return data;
1893 }
1894
1895 static void ns83820_probe_phy(struct net_device *ndev)
1896 {
1897 struct ns83820 *dev = PRIV(ndev);
1898 static int first;
1899 int i;
1900 #define MII_PHYIDR1 0x02
1901 #define MII_PHYIDR2 0x03
1902
1903 #if 0
1904 if (!first) {
1905 unsigned tmp;
1906 ns83820_mii_read_reg(dev, 1, 0x09);
1907 ns83820_mii_write_reg(dev, 1, 0x10, 0x0d3e);
1908
1909 tmp = ns83820_mii_read_reg(dev, 1, 0x00);
1910 ns83820_mii_write_reg(dev, 1, 0x00, tmp | 0x8000);
1911 udelay(1300);
1912 ns83820_mii_read_reg(dev, 1, 0x09);
1913 }
1914 #endif
1915 first = 1;
1916
1917 for (i=1; i<2; i++) {
1918 int j;
1919 unsigned a, b;
1920 a = ns83820_mii_read_reg(dev, i, MII_PHYIDR1);
1921 b = ns83820_mii_read_reg(dev, i, MII_PHYIDR2);
1922
1923 //printk("%s: phy %d: 0x%04x 0x%04x\n",
1924 // ndev->name, i, a, b);
1925
1926 for (j=0; j<0x16; j+=4) {
1927 dprintk("%s: [0x%02x] %04x %04x %04x %04x\n",
1928 ndev->name, j,
1929 ns83820_mii_read_reg(dev, i, 0 + j),
1930 ns83820_mii_read_reg(dev, i, 1 + j),
1931 ns83820_mii_read_reg(dev, i, 2 + j),
1932 ns83820_mii_read_reg(dev, i, 3 + j)
1933 );
1934 }
1935 }
1936 {
1937 unsigned a, b;
1938 /* read firmware version: memory addr is 0x8402 and 0x8403 */
1939 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1940 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1941 a = ns83820_mii_read_reg(dev, 1, 0x1d);
1942
1943 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1944 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1945 b = ns83820_mii_read_reg(dev, 1, 0x1d);
1946 dprintk("version: 0x%04x 0x%04x\n", a, b);
1947 }
1948 }
1949 #endif
1950
1951 static int __devinit ns83820_init_one(struct pci_dev *pci_dev, const struct pci_device_id *id)
1952 {
1953 struct net_device *ndev;
1954 struct ns83820 *dev;
1955 long addr;
1956 int err;
1957 int using_dac = 0;
1958 DECLARE_MAC_BUF(mac);
1959
1960 /* See if we can set the dma mask early on; failure is fatal. */
1961 if (sizeof(dma_addr_t) == 8 &&
1962 !pci_set_dma_mask(pci_dev, DMA_64BIT_MASK)) {
1963 using_dac = 1;
1964 } else if (!pci_set_dma_mask(pci_dev, DMA_32BIT_MASK)) {
1965 using_dac = 0;
1966 } else {
1967 dev_warn(&pci_dev->dev, "pci_set_dma_mask failed!\n");
1968 return -ENODEV;
1969 }
1970
1971 ndev = alloc_etherdev(sizeof(struct ns83820));
1972 dev = PRIV(ndev);
1973
1974 err = -ENOMEM;
1975 if (!dev)
1976 goto out;
1977
1978 dev->ndev = ndev;
1979
1980 spin_lock_init(&dev->rx_info.lock);
1981 spin_lock_init(&dev->tx_lock);
1982 spin_lock_init(&dev->misc_lock);
1983 dev->pci_dev = pci_dev;
1984
1985 SET_NETDEV_DEV(ndev, &pci_dev->dev);
1986
1987 INIT_WORK(&dev->tq_refill, queue_refill);
1988 tasklet_init(&dev->rx_tasklet, rx_action, (unsigned long)ndev);
1989
1990 err = pci_enable_device(pci_dev);
1991 if (err) {
1992 dev_info(&pci_dev->dev, "pci_enable_dev failed: %d\n", err);
1993 goto out_free;
1994 }
1995
1996 pci_set_master(pci_dev);
1997 addr = pci_resource_start(pci_dev, 1);
1998 dev->base = ioremap_nocache(addr, PAGE_SIZE);
1999 dev->tx_descs = pci_alloc_consistent(pci_dev,
2000 4 * DESC_SIZE * NR_TX_DESC, &dev->tx_phy_descs);
2001 dev->rx_info.descs = pci_alloc_consistent(pci_dev,
2002 4 * DESC_SIZE * NR_RX_DESC, &dev->rx_info.phy_descs);
2003 err = -ENOMEM;
2004 if (!dev->base || !dev->tx_descs || !dev->rx_info.descs)
2005 goto out_disable;
2006
2007 dprintk("%p: %08lx %p: %08lx\n",
2008 dev->tx_descs, (long)dev->tx_phy_descs,
2009 dev->rx_info.descs, (long)dev->rx_info.phy_descs);
2010
2011 /* disable interrupts */
2012 writel(0, dev->base + IMR);
2013 writel(0, dev->base + IER);
2014 readl(dev->base + IER);
2015
2016 dev->IMR_cache = 0;
2017
2018 err = request_irq(pci_dev->irq, ns83820_irq, IRQF_SHARED,
2019 DRV_NAME, ndev);
2020 if (err) {
2021 dev_info(&pci_dev->dev, "unable to register irq %d, err %d\n",
2022 pci_dev->irq, err);
2023 goto out_disable;
2024 }
2025
2026 /*
2027 * FIXME: we are holding rtnl_lock() over obscenely long area only
2028 * because some of the setup code uses dev->name. It's Wrong(tm) -
2029 * we should be using driver-specific names for all that stuff.
2030 * For now that will do, but we really need to come back and kill
2031 * most of the dev_alloc_name() users later.
2032 */
2033 rtnl_lock();
2034 err = dev_alloc_name(ndev, ndev->name);
2035 if (err < 0) {
2036 dev_info(&pci_dev->dev, "unable to get netdev name: %d\n", err);
2037 goto out_free_irq;
2038 }
2039
2040 printk("%s: ns83820.c: 0x22c: %08x, subsystem: %04x:%04x\n",
2041 ndev->name, le32_to_cpu(readl(dev->base + 0x22c)),
2042 pci_dev->subsystem_vendor, pci_dev->subsystem_device);
2043
2044 ndev->open = ns83820_open;
2045 ndev->stop = ns83820_stop;
2046 ndev->hard_start_xmit = ns83820_hard_start_xmit;
2047 ndev->get_stats = ns83820_get_stats;
2048 ndev->change_mtu = ns83820_change_mtu;
2049 ndev->set_multicast_list = ns83820_set_multicast;
2050 SET_ETHTOOL_OPS(ndev, &ops);
2051 ndev->tx_timeout = ns83820_tx_timeout;
2052 ndev->watchdog_timeo = 5 * HZ;
2053 pci_set_drvdata(pci_dev, ndev);
2054
2055 ns83820_do_reset(dev, CR_RST);
2056
2057 /* Must reset the ram bist before running it */
2058 writel(PTSCR_RBIST_RST, dev->base + PTSCR);
2059 ns83820_run_bist(ndev, "sram bist", PTSCR_RBIST_EN,
2060 PTSCR_RBIST_DONE, PTSCR_RBIST_FAIL);
2061 ns83820_run_bist(ndev, "eeprom bist", PTSCR_EEBIST_EN, 0,
2062 PTSCR_EEBIST_FAIL);
2063 ns83820_run_bist(ndev, "eeprom load", PTSCR_EELOAD_EN, 0, 0);
2064
2065 /* I love config registers */
2066 dev->CFG_cache = readl(dev->base + CFG);
2067
2068 if ((dev->CFG_cache & CFG_PCI64_DET)) {
2069 printk(KERN_INFO "%s: detected 64 bit PCI data bus.\n",
2070 ndev->name);
2071 /*dev->CFG_cache |= CFG_DATA64_EN;*/
2072 if (!(dev->CFG_cache & CFG_DATA64_EN))
2073 printk(KERN_INFO "%s: EEPROM did not enable 64 bit bus. Disabled.\n",
2074 ndev->name);
2075 } else
2076 dev->CFG_cache &= ~(CFG_DATA64_EN);
2077
2078 dev->CFG_cache &= (CFG_TBI_EN | CFG_MRM_DIS | CFG_MWI_DIS |
2079 CFG_T64ADDR | CFG_DATA64_EN | CFG_EXT_125 |
2080 CFG_M64ADDR);
2081 dev->CFG_cache |= CFG_PINT_DUPSTS | CFG_PINT_LNKSTS | CFG_PINT_SPDSTS |
2082 CFG_EXTSTS_EN | CFG_EXD | CFG_PESEL;
2083 dev->CFG_cache |= CFG_REQALG;
2084 dev->CFG_cache |= CFG_POW;
2085 dev->CFG_cache |= CFG_TMRTEST;
2086
2087 /* When compiled with 64 bit addressing, we must always enable
2088 * the 64 bit descriptor format.
2089 */
2090 if (sizeof(dma_addr_t) == 8)
2091 dev->CFG_cache |= CFG_M64ADDR;
2092 if (using_dac)
2093 dev->CFG_cache |= CFG_T64ADDR;
2094
2095 /* Big endian mode does not seem to do what the docs suggest */
2096 dev->CFG_cache &= ~CFG_BEM;
2097
2098 /* setup optical transceiver if we have one */
2099 if (dev->CFG_cache & CFG_TBI_EN) {
2100 printk(KERN_INFO "%s: enabling optical transceiver\n",
2101 ndev->name);
2102 writel(readl(dev->base + GPIOR) | 0x3e8, dev->base + GPIOR);
2103
2104 /* setup auto negotiation feature advertisement */
2105 writel(readl(dev->base + TANAR)
2106 | TANAR_HALF_DUP | TANAR_FULL_DUP,
2107 dev->base + TANAR);
2108
2109 /* start auto negotiation */
2110 writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN,
2111 dev->base + TBICR);
2112 writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
2113 dev->linkstate = LINK_AUTONEGOTIATE;
2114
2115 dev->CFG_cache |= CFG_MODE_1000;
2116 }
2117
2118 writel(dev->CFG_cache, dev->base + CFG);
2119 dprintk("CFG: %08x\n", dev->CFG_cache);
2120
2121 if (reset_phy) {
2122 printk(KERN_INFO "%s: resetting phy\n", ndev->name);
2123 writel(dev->CFG_cache | CFG_PHY_RST, dev->base + CFG);
2124 msleep(10);
2125 writel(dev->CFG_cache, dev->base + CFG);
2126 }
2127
2128 #if 0 /* Huh? This sets the PCI latency register. Should be done via
2129 * the PCI layer. FIXME.
2130 */
2131 if (readl(dev->base + SRR))
2132 writel(readl(dev->base+0x20c) | 0xfe00, dev->base + 0x20c);
2133 #endif
2134
2135 /* Note! The DMA burst size interacts with packet
2136 * transmission, such that the largest packet that
2137 * can be transmitted is 8192 - FLTH - burst size.
2138 * If only the transmit fifo was larger...
2139 */
2140 /* Ramit : 1024 DMA is not a good idea, it ends up banging
2141 * some DELL and COMPAQ SMP systems */
2142 writel(TXCFG_CSI | TXCFG_HBI | TXCFG_ATP | TXCFG_MXDMA512
2143 | ((1600 / 32) * 0x100),
2144 dev->base + TXCFG);
2145
2146 /* Flush the interrupt holdoff timer */
2147 writel(0x000, dev->base + IHR);
2148 writel(0x100, dev->base + IHR);
2149 writel(0x000, dev->base + IHR);
2150
2151 /* Set Rx to full duplex, don't accept runt, errored, long or length
2152 * range errored packets. Use 512 byte DMA.
2153 */
2154 /* Ramit : 1024 DMA is not a good idea, it ends up banging
2155 * some DELL and COMPAQ SMP systems
2156 * Turn on ALP, only we are accpeting Jumbo Packets */
2157 writel(RXCFG_AEP | RXCFG_ARP | RXCFG_AIRL | RXCFG_RX_FD
2158 | RXCFG_STRIPCRC
2159 //| RXCFG_ALP
2160 | (RXCFG_MXDMA512) | 0, dev->base + RXCFG);
2161
2162 /* Disable priority queueing */
2163 writel(0, dev->base + PQCR);
2164
2165 /* Enable IP checksum validation and detetion of VLAN headers.
2166 * Note: do not set the reject options as at least the 0x102
2167 * revision of the chip does not properly accept IP fragments
2168 * at least for UDP.
2169 */
2170 /* Ramit : Be sure to turn on RXCFG_ARP if VLAN's are enabled, since
2171 * the MAC it calculates the packetsize AFTER stripping the VLAN
2172 * header, and if a VLAN Tagged packet of 64 bytes is received (like
2173 * a ping with a VLAN header) then the card, strips the 4 byte VLAN
2174 * tag and then checks the packet size, so if RXCFG_ARP is not enabled,
2175 * it discrards it!. These guys......
2176 * also turn on tag stripping if hardware acceleration is enabled
2177 */
2178 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2179 #define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN|VRCR_VTREN)
2180 #else
2181 #define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN)
2182 #endif
2183 writel(VRCR_INIT_VALUE, dev->base + VRCR);
2184
2185 /* Enable per-packet TCP/UDP/IP checksumming
2186 * and per packet vlan tag insertion if
2187 * vlan hardware acceleration is enabled
2188 */
2189 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2190 #define VTCR_INIT_VALUE (VTCR_PPCHK|VTCR_VPPTI)
2191 #else
2192 #define VTCR_INIT_VALUE VTCR_PPCHK
2193 #endif
2194 writel(VTCR_INIT_VALUE, dev->base + VTCR);
2195
2196 /* Ramit : Enable async and sync pause frames */
2197 /* writel(0, dev->base + PCR); */
2198 writel((PCR_PS_MCAST | PCR_PS_DA | PCR_PSEN | PCR_FFLO_4K |
2199 PCR_FFHI_8K | PCR_STLO_4 | PCR_STHI_8 | PCR_PAUSE_CNT),
2200 dev->base + PCR);
2201
2202 /* Disable Wake On Lan */
2203 writel(0, dev->base + WCSR);
2204
2205 ns83820_getmac(dev, ndev->dev_addr);
2206
2207 /* Yes, we support dumb IP checksum on transmit */
2208 ndev->features |= NETIF_F_SG;
2209 ndev->features |= NETIF_F_IP_CSUM;
2210
2211 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2212 /* We also support hardware vlan acceleration */
2213 ndev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2214 ndev->vlan_rx_register = ns83820_vlan_rx_register;
2215 #endif
2216
2217 if (using_dac) {
2218 printk(KERN_INFO "%s: using 64 bit addressing.\n",
2219 ndev->name);
2220 ndev->features |= NETIF_F_HIGHDMA;
2221 }
2222
2223 printk(KERN_INFO "%s: ns83820 v" VERSION ": DP83820 v%u.%u: %s io=0x%08lx irq=%d f=%s\n",
2224 ndev->name,
2225 (unsigned)readl(dev->base + SRR) >> 8,
2226 (unsigned)readl(dev->base + SRR) & 0xff,
2227 print_mac(mac, ndev->dev_addr),
2228 addr, pci_dev->irq,
2229 (ndev->features & NETIF_F_HIGHDMA) ? "h,sg" : "sg"
2230 );
2231
2232 #ifdef PHY_CODE_IS_FINISHED
2233 ns83820_probe_phy(ndev);
2234 #endif
2235
2236 err = register_netdevice(ndev);
2237 if (err) {
2238 printk(KERN_INFO "ns83820: unable to register netdev: %d\n", err);
2239 goto out_cleanup;
2240 }
2241 rtnl_unlock();
2242
2243 return 0;
2244
2245 out_cleanup:
2246 writel(0, dev->base + IMR); /* paranoia */
2247 writel(0, dev->base + IER);
2248 readl(dev->base + IER);
2249 out_free_irq:
2250 rtnl_unlock();
2251 free_irq(pci_dev->irq, ndev);
2252 out_disable:
2253 if (dev->base)
2254 iounmap(dev->base);
2255 pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_TX_DESC, dev->tx_descs, dev->tx_phy_descs);
2256 pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_RX_DESC, dev->rx_info.descs, dev->rx_info.phy_descs);
2257 pci_disable_device(pci_dev);
2258 out_free:
2259 free_netdev(ndev);
2260 pci_set_drvdata(pci_dev, NULL);
2261 out:
2262 return err;
2263 }
2264
2265 static void __devexit ns83820_remove_one(struct pci_dev *pci_dev)
2266 {
2267 struct net_device *ndev = pci_get_drvdata(pci_dev);
2268 struct ns83820 *dev = PRIV(ndev); /* ok even if NULL */
2269
2270 if (!ndev) /* paranoia */
2271 return;
2272
2273 writel(0, dev->base + IMR); /* paranoia */
2274 writel(0, dev->base + IER);
2275 readl(dev->base + IER);
2276
2277 unregister_netdev(ndev);
2278 free_irq(dev->pci_dev->irq, ndev);
2279 iounmap(dev->base);
2280 pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_TX_DESC,
2281 dev->tx_descs, dev->tx_phy_descs);
2282 pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_RX_DESC,
2283 dev->rx_info.descs, dev->rx_info.phy_descs);
2284 pci_disable_device(dev->pci_dev);
2285 free_netdev(ndev);
2286 pci_set_drvdata(pci_dev, NULL);
2287 }
2288
2289 static struct pci_device_id ns83820_pci_tbl[] = {
2290 { 0x100b, 0x0022, PCI_ANY_ID, PCI_ANY_ID, 0, .driver_data = 0, },
2291 { 0, },
2292 };
2293
2294 static struct pci_driver driver = {
2295 .name = "ns83820",
2296 .id_table = ns83820_pci_tbl,
2297 .probe = ns83820_init_one,
2298 .remove = __devexit_p(ns83820_remove_one),
2299 #if 0 /* FIXME: implement */
2300 .suspend = ,
2301 .resume = ,
2302 #endif
2303 };
2304
2305
2306 static int __init ns83820_init(void)
2307 {
2308 printk(KERN_INFO "ns83820.c: National Semiconductor DP83820 10/100/1000 driver.\n");
2309 return pci_register_driver(&driver);
2310 }
2311
2312 static void __exit ns83820_exit(void)
2313 {
2314 pci_unregister_driver(&driver);
2315 }
2316
2317 MODULE_AUTHOR("Benjamin LaHaise <bcrl@kvack.org>");
2318 MODULE_DESCRIPTION("National Semiconductor DP83820 10/100/1000 driver");
2319 MODULE_LICENSE("GPL");
2320
2321 MODULE_DEVICE_TABLE(pci, ns83820_pci_tbl);
2322
2323 module_param(lnksts, int, 0);
2324 MODULE_PARM_DESC(lnksts, "Polarity of LNKSTS bit");
2325
2326 module_param(ihr, int, 0);
2327 MODULE_PARM_DESC(ihr, "Time in 100 us increments to delay interrupts (range 0-127)");
2328
2329 module_param(reset_phy, int, 0);
2330 MODULE_PARM_DESC(reset_phy, "Set to 1 to reset the PHY on startup");
2331
2332 module_init(ns83820_init);
2333 module_exit(ns83820_exit);
Support for the Chinese Samsung S3C2440 based development boards