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e1000: gather hardware bit tweaks.
[linux-2.6/mini2440.git] / drivers / net / e1000 / e1000_hw.c
blobdceaf5bd5f5b48a7af20a0bc689427627cfbc2d7
1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /* e1000_hw.c
30 * Shared functions for accessing and configuring the MAC
31 */
32
33
34 #include "e1000_hw.h"
35
36 static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
37 static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
38 static int32_t e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data);
39 static int32_t e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data);
40 static int32_t e1000_get_software_semaphore(struct e1000_hw *hw);
41 static void e1000_release_software_semaphore(struct e1000_hw *hw);
42
43 static uint8_t e1000_arc_subsystem_valid(struct e1000_hw *hw);
44 static int32_t e1000_check_downshift(struct e1000_hw *hw);
45 static int32_t e1000_check_polarity(struct e1000_hw *hw, e1000_rev_polarity *polarity);
46 static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
47 static void e1000_clear_vfta(struct e1000_hw *hw);
48 static int32_t e1000_commit_shadow_ram(struct e1000_hw *hw);
49 static int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw, boolean_t link_up);
50 static int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw);
51 static int32_t e1000_detect_gig_phy(struct e1000_hw *hw);
52 static int32_t e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank);
53 static int32_t e1000_get_auto_rd_done(struct e1000_hw *hw);
54 static int32_t e1000_get_cable_length(struct e1000_hw *hw, uint16_t *min_length, uint16_t *max_length);
55 static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
56 static int32_t e1000_get_phy_cfg_done(struct e1000_hw *hw);
57 static int32_t e1000_get_software_flag(struct e1000_hw *hw);
58 static int32_t e1000_ich8_cycle_init(struct e1000_hw *hw);
59 static int32_t e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout);
60 static int32_t e1000_id_led_init(struct e1000_hw *hw);
61 static int32_t e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, uint32_t cnf_base_addr, uint32_t cnf_size);
62 static int32_t e1000_init_lcd_from_nvm(struct e1000_hw *hw);
63 static void e1000_init_rx_addrs(struct e1000_hw *hw);
64 static void e1000_initialize_hardware_bits(struct e1000_hw *hw);
65 static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw);
66 static int32_t e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw);
67 static int32_t e1000_mng_enable_host_if(struct e1000_hw *hw);
68 static int32_t e1000_mng_host_if_write(struct e1000_hw *hw, uint8_t *buffer, uint16_t length, uint16_t offset, uint8_t *sum);
69 static int32_t e1000_mng_write_cmd_header(struct e1000_hw* hw, struct e1000_host_mng_command_header* hdr);
70 static int32_t e1000_mng_write_commit(struct e1000_hw *hw);
71 static int32_t e1000_phy_ife_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
72 static int32_t e1000_phy_igp_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
73 static int32_t e1000_read_eeprom_eerd(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
74 static int32_t e1000_write_eeprom_eewr(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
75 static int32_t e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd);
76 static int32_t e1000_phy_m88_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
77 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
78 static int32_t e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t *data);
79 static int32_t e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte);
80 static int32_t e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte);
81 static int32_t e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data);
82 static int32_t e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t *data);
83 static int32_t e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t data);
84 static int32_t e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
85 static int32_t e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
86 static void e1000_release_software_flag(struct e1000_hw *hw);
87 static int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active);
88 static int32_t e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active);
89 static int32_t e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop);
90 static void e1000_set_pci_express_master_disable(struct e1000_hw *hw);
91 static int32_t e1000_wait_autoneg(struct e1000_hw *hw);
92 static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value);
93 static int32_t e1000_set_phy_type(struct e1000_hw *hw);
94 static void e1000_phy_init_script(struct e1000_hw *hw);
95 static int32_t e1000_setup_copper_link(struct e1000_hw *hw);
96 static int32_t e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
97 static int32_t e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
98 static int32_t e1000_phy_force_speed_duplex(struct e1000_hw *hw);
99 static int32_t e1000_config_mac_to_phy(struct e1000_hw *hw);
100 static void e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
101 static void e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
102 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data,
103 uint16_t count);
104 static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw);
105 static int32_t e1000_phy_reset_dsp(struct e1000_hw *hw);
106 static int32_t e1000_write_eeprom_spi(struct e1000_hw *hw, uint16_t offset,
107 uint16_t words, uint16_t *data);
108 static int32_t e1000_write_eeprom_microwire(struct e1000_hw *hw,
109 uint16_t offset, uint16_t words,
110 uint16_t *data);
111 static int32_t e1000_spi_eeprom_ready(struct e1000_hw *hw);
112 static void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
113 static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
114 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data,
115 uint16_t count);
116 static int32_t e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
117 uint16_t phy_data);
118 static int32_t e1000_read_phy_reg_ex(struct e1000_hw *hw,uint32_t reg_addr,
119 uint16_t *phy_data);
120 static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count);
121 static int32_t e1000_acquire_eeprom(struct e1000_hw *hw);
122 static void e1000_release_eeprom(struct e1000_hw *hw);
123 static void e1000_standby_eeprom(struct e1000_hw *hw);
124 static int32_t e1000_set_vco_speed(struct e1000_hw *hw);
125 static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw);
126 static int32_t e1000_set_phy_mode(struct e1000_hw *hw);
127 static int32_t e1000_host_if_read_cookie(struct e1000_hw *hw, uint8_t *buffer);
128 static uint8_t e1000_calculate_mng_checksum(char *buffer, uint32_t length);
129 static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw,
130 uint16_t duplex);
131 static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw);
132
133 /* IGP cable length table */
134 static const
135 uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
136 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
137 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
138 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
139 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
140 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
141 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
142 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
143 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
144
145 static const
146 uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =
147 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
148 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
149 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
150 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
151 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
152 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
153 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
154 104, 109, 114, 118, 121, 124};
155
156 /******************************************************************************
157 * Set the phy type member in the hw struct.
158 *
159 * hw - Struct containing variables accessed by shared code
160 *****************************************************************************/
161 static int32_t
162 e1000_set_phy_type(struct e1000_hw *hw)
163 {
164 DEBUGFUNC("e1000_set_phy_type");
165
166 if (hw->mac_type == e1000_undefined)
167 return -E1000_ERR_PHY_TYPE;
168
169 switch (hw->phy_id) {
170 case M88E1000_E_PHY_ID:
171 case M88E1000_I_PHY_ID:
172 case M88E1011_I_PHY_ID:
173 case M88E1111_I_PHY_ID:
174 hw->phy_type = e1000_phy_m88;
175 break;
176 case IGP01E1000_I_PHY_ID:
177 if (hw->mac_type == e1000_82541 ||
178 hw->mac_type == e1000_82541_rev_2 ||
179 hw->mac_type == e1000_82547 ||
180 hw->mac_type == e1000_82547_rev_2) {
181 hw->phy_type = e1000_phy_igp;
182 break;
183 }
184 case IGP03E1000_E_PHY_ID:
185 hw->phy_type = e1000_phy_igp_3;
186 break;
187 case IFE_E_PHY_ID:
188 case IFE_PLUS_E_PHY_ID:
189 case IFE_C_E_PHY_ID:
190 hw->phy_type = e1000_phy_ife;
191 break;
192 case GG82563_E_PHY_ID:
193 if (hw->mac_type == e1000_80003es2lan) {
194 hw->phy_type = e1000_phy_gg82563;
195 break;
196 }
197 /* Fall Through */
198 default:
199 /* Should never have loaded on this device */
200 hw->phy_type = e1000_phy_undefined;
201 return -E1000_ERR_PHY_TYPE;
202 }
203
204 return E1000_SUCCESS;
205 }
206
207 /******************************************************************************
208 * IGP phy init script - initializes the GbE PHY
209 *
210 * hw - Struct containing variables accessed by shared code
211 *****************************************************************************/
212 static void
213 e1000_phy_init_script(struct e1000_hw *hw)
214 {
215 uint32_t ret_val;
216 uint16_t phy_saved_data;
217
218 DEBUGFUNC("e1000_phy_init_script");
219
220 if (hw->phy_init_script) {
221 msleep(20);
222
223 /* Save off the current value of register 0x2F5B to be restored at
224 * the end of this routine. */
225 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
226
227 /* Disabled the PHY transmitter */
228 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
229
230 msleep(20);
231
232 e1000_write_phy_reg(hw,0x0000,0x0140);
233
234 msleep(5);
235
236 switch (hw->mac_type) {
237 case e1000_82541:
238 case e1000_82547:
239 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
240
241 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
242
243 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
244
245 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
246
247 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
248
249 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
250
251 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
252
253 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
254
255 e1000_write_phy_reg(hw, 0x2010, 0x0008);
256 break;
257
258 case e1000_82541_rev_2:
259 case e1000_82547_rev_2:
260 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
261 break;
262 default:
263 break;
264 }
265
266 e1000_write_phy_reg(hw, 0x0000, 0x3300);
267
268 msleep(20);
269
270 /* Now enable the transmitter */
271 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
272
273 if (hw->mac_type == e1000_82547) {
274 uint16_t fused, fine, coarse;
275
276 /* Move to analog registers page */
277 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
278
279 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
280 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
281
282 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
283 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
284
285 if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
286 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
287 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
288 } else if (coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
289 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
290
291 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
292 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
293 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
294
295 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
296 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
297 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
298 }
299 }
300 }
301 }
302
303 /******************************************************************************
304 * Set the mac type member in the hw struct.
305 *
306 * hw - Struct containing variables accessed by shared code
307 *****************************************************************************/
308 int32_t
309 e1000_set_mac_type(struct e1000_hw *hw)
310 {
311 DEBUGFUNC("e1000_set_mac_type");
312
313 switch (hw->device_id) {
314 case E1000_DEV_ID_82542:
315 switch (hw->revision_id) {
316 case E1000_82542_2_0_REV_ID:
317 hw->mac_type = e1000_82542_rev2_0;
318 break;
319 case E1000_82542_2_1_REV_ID:
320 hw->mac_type = e1000_82542_rev2_1;
321 break;
322 default:
323 /* Invalid 82542 revision ID */
324 return -E1000_ERR_MAC_TYPE;
325 }
326 break;
327 case E1000_DEV_ID_82543GC_FIBER:
328 case E1000_DEV_ID_82543GC_COPPER:
329 hw->mac_type = e1000_82543;
330 break;
331 case E1000_DEV_ID_82544EI_COPPER:
332 case E1000_DEV_ID_82544EI_FIBER:
333 case E1000_DEV_ID_82544GC_COPPER:
334 case E1000_DEV_ID_82544GC_LOM:
335 hw->mac_type = e1000_82544;
336 break;
337 case E1000_DEV_ID_82540EM:
338 case E1000_DEV_ID_82540EM_LOM:
339 case E1000_DEV_ID_82540EP:
340 case E1000_DEV_ID_82540EP_LOM:
341 case E1000_DEV_ID_82540EP_LP:
342 hw->mac_type = e1000_82540;
343 break;
344 case E1000_DEV_ID_82545EM_COPPER:
345 case E1000_DEV_ID_82545EM_FIBER:
346 hw->mac_type = e1000_82545;
347 break;
348 case E1000_DEV_ID_82545GM_COPPER:
349 case E1000_DEV_ID_82545GM_FIBER:
350 case E1000_DEV_ID_82545GM_SERDES:
351 hw->mac_type = e1000_82545_rev_3;
352 break;
353 case E1000_DEV_ID_82546EB_COPPER:
354 case E1000_DEV_ID_82546EB_FIBER:
355 case E1000_DEV_ID_82546EB_QUAD_COPPER:
356 hw->mac_type = e1000_82546;
357 break;
358 case E1000_DEV_ID_82546GB_COPPER:
359 case E1000_DEV_ID_82546GB_FIBER:
360 case E1000_DEV_ID_82546GB_SERDES:
361 case E1000_DEV_ID_82546GB_PCIE:
362 case E1000_DEV_ID_82546GB_QUAD_COPPER:
363 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
364 hw->mac_type = e1000_82546_rev_3;
365 break;
366 case E1000_DEV_ID_82541EI:
367 case E1000_DEV_ID_82541EI_MOBILE:
368 case E1000_DEV_ID_82541ER_LOM:
369 hw->mac_type = e1000_82541;
370 break;
371 case E1000_DEV_ID_82541ER:
372 case E1000_DEV_ID_82541GI:
373 case E1000_DEV_ID_82541GI_LF:
374 case E1000_DEV_ID_82541GI_MOBILE:
375 hw->mac_type = e1000_82541_rev_2;
376 break;
377 case E1000_DEV_ID_82547EI:
378 case E1000_DEV_ID_82547EI_MOBILE:
379 hw->mac_type = e1000_82547;
380 break;
381 case E1000_DEV_ID_82547GI:
382 hw->mac_type = e1000_82547_rev_2;
383 break;
384 case E1000_DEV_ID_82571EB_COPPER:
385 case E1000_DEV_ID_82571EB_FIBER:
386 case E1000_DEV_ID_82571EB_SERDES:
387 case E1000_DEV_ID_82571EB_QUAD_COPPER:
388 hw->mac_type = e1000_82571;
389 break;
390 case E1000_DEV_ID_82572EI_COPPER:
391 case E1000_DEV_ID_82572EI_FIBER:
392 case E1000_DEV_ID_82572EI_SERDES:
393 case E1000_DEV_ID_82572EI:
394 hw->mac_type = e1000_82572;
395 break;
396 case E1000_DEV_ID_82573E:
397 case E1000_DEV_ID_82573E_IAMT:
398 case E1000_DEV_ID_82573L:
399 hw->mac_type = e1000_82573;
400 break;
401 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
402 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
403 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
404 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
405 hw->mac_type = e1000_80003es2lan;
406 break;
407 case E1000_DEV_ID_ICH8_IGP_M_AMT:
408 case E1000_DEV_ID_ICH8_IGP_AMT:
409 case E1000_DEV_ID_ICH8_IGP_C:
410 case E1000_DEV_ID_ICH8_IFE:
411 case E1000_DEV_ID_ICH8_IGP_M:
412 hw->mac_type = e1000_ich8lan;
413 break;
414 default:
415 /* Should never have loaded on this device */
416 return -E1000_ERR_MAC_TYPE;
417 }
418
419 switch (hw->mac_type) {
420 case e1000_ich8lan:
421 hw->swfwhw_semaphore_present = TRUE;
422 hw->asf_firmware_present = TRUE;
423 break;
424 case e1000_80003es2lan:
425 hw->swfw_sync_present = TRUE;
426 /* fall through */
427 case e1000_82571:
428 case e1000_82572:
429 case e1000_82573:
430 hw->eeprom_semaphore_present = TRUE;
431 /* fall through */
432 case e1000_82541:
433 case e1000_82547:
434 case e1000_82541_rev_2:
435 case e1000_82547_rev_2:
436 hw->asf_firmware_present = TRUE;
437 break;
438 default:
439 break;
440 }
441
442 return E1000_SUCCESS;
443 }
444
445 /*****************************************************************************
446 * Set media type and TBI compatibility.
447 *
448 * hw - Struct containing variables accessed by shared code
449 * **************************************************************************/
450 void
451 e1000_set_media_type(struct e1000_hw *hw)
452 {
453 uint32_t status;
454
455 DEBUGFUNC("e1000_set_media_type");
456
457 if (hw->mac_type != e1000_82543) {
458 /* tbi_compatibility is only valid on 82543 */
459 hw->tbi_compatibility_en = FALSE;
460 }
461
462 switch (hw->device_id) {
463 case E1000_DEV_ID_82545GM_SERDES:
464 case E1000_DEV_ID_82546GB_SERDES:
465 case E1000_DEV_ID_82571EB_SERDES:
466 case E1000_DEV_ID_82572EI_SERDES:
467 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
468 hw->media_type = e1000_media_type_internal_serdes;
469 break;
470 default:
471 switch (hw->mac_type) {
472 case e1000_82542_rev2_0:
473 case e1000_82542_rev2_1:
474 hw->media_type = e1000_media_type_fiber;
475 break;
476 case e1000_ich8lan:
477 case e1000_82573:
478 /* The STATUS_TBIMODE bit is reserved or reused for the this
479 * device.
480 */
481 hw->media_type = e1000_media_type_copper;
482 break;
483 default:
484 status = E1000_READ_REG(hw, STATUS);
485 if (status & E1000_STATUS_TBIMODE) {
486 hw->media_type = e1000_media_type_fiber;
487 /* tbi_compatibility not valid on fiber */
488 hw->tbi_compatibility_en = FALSE;
489 } else {
490 hw->media_type = e1000_media_type_copper;
491 }
492 break;
493 }
494 }
495 }
496
497 /******************************************************************************
498 * Reset the transmit and receive units; mask and clear all interrupts.
499 *
500 * hw - Struct containing variables accessed by shared code
501 *****************************************************************************/
502 int32_t
503 e1000_reset_hw(struct e1000_hw *hw)
504 {
505 uint32_t ctrl;
506 uint32_t ctrl_ext;
507 uint32_t icr;
508 uint32_t manc;
509 uint32_t led_ctrl;
510 uint32_t timeout;
511 uint32_t extcnf_ctrl;
512 int32_t ret_val;
513
514 DEBUGFUNC("e1000_reset_hw");
515
516 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
517 if (hw->mac_type == e1000_82542_rev2_0) {
518 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
519 e1000_pci_clear_mwi(hw);
520 }
521
522 if (hw->bus_type == e1000_bus_type_pci_express) {
523 /* Prevent the PCI-E bus from sticking if there is no TLP connection
524 * on the last TLP read/write transaction when MAC is reset.
525 */
526 if (e1000_disable_pciex_master(hw) != E1000_SUCCESS) {
527 DEBUGOUT("PCI-E Master disable polling has failed.\n");
528 }
529 }
530
531 /* Clear interrupt mask to stop board from generating interrupts */
532 DEBUGOUT("Masking off all interrupts\n");
533 E1000_WRITE_REG(hw, IMC, 0xffffffff);
534
535 /* Disable the Transmit and Receive units. Then delay to allow
536 * any pending transactions to complete before we hit the MAC with
537 * the global reset.
538 */
539 E1000_WRITE_REG(hw, RCTL, 0);
540 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
541 E1000_WRITE_FLUSH(hw);
542
543 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
544 hw->tbi_compatibility_on = FALSE;
545
546 /* Delay to allow any outstanding PCI transactions to complete before
547 * resetting the device
548 */
549 msleep(10);
550
551 ctrl = E1000_READ_REG(hw, CTRL);
552
553 /* Must reset the PHY before resetting the MAC */
554 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
555 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
556 msleep(5);
557 }
558
559 /* Must acquire the MDIO ownership before MAC reset.
560 * Ownership defaults to firmware after a reset. */
561 if (hw->mac_type == e1000_82573) {
562 timeout = 10;
563
564 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
565 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
566
567 do {
568 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
569 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
570
571 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
572 break;
573 else
574 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
575
576 msleep(2);
577 timeout--;
578 } while (timeout);
579 }
580
581 /* Workaround for ICH8 bit corruption issue in FIFO memory */
582 if (hw->mac_type == e1000_ich8lan) {
583 /* Set Tx and Rx buffer allocation to 8k apiece. */
584 E1000_WRITE_REG(hw, PBA, E1000_PBA_8K);
585 /* Set Packet Buffer Size to 16k. */
586 E1000_WRITE_REG(hw, PBS, E1000_PBS_16K);
587 }
588
589 /* Issue a global reset to the MAC. This will reset the chip's
590 * transmit, receive, DMA, and link units. It will not effect
591 * the current PCI configuration. The global reset bit is self-
592 * clearing, and should clear within a microsecond.
593 */
594 DEBUGOUT("Issuing a global reset to MAC\n");
595
596 switch (hw->mac_type) {
597 case e1000_82544:
598 case e1000_82540:
599 case e1000_82545:
600 case e1000_82546:
601 case e1000_82541:
602 case e1000_82541_rev_2:
603 /* These controllers can't ack the 64-bit write when issuing the
604 * reset, so use IO-mapping as a workaround to issue the reset */
605 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
606 break;
607 case e1000_82545_rev_3:
608 case e1000_82546_rev_3:
609 /* Reset is performed on a shadow of the control register */
610 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
611 break;
612 case e1000_ich8lan:
613 if (!hw->phy_reset_disable &&
614 e1000_check_phy_reset_block(hw) == E1000_SUCCESS) {
615 /* e1000_ich8lan PHY HW reset requires MAC CORE reset
616 * at the same time to make sure the interface between
617 * MAC and the external PHY is reset.
618 */
619 ctrl |= E1000_CTRL_PHY_RST;
620 }
621
622 e1000_get_software_flag(hw);
623 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
624 msleep(5);
625 break;
626 default:
627 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
628 break;
629 }
630
631 /* After MAC reset, force reload of EEPROM to restore power-on settings to
632 * device. Later controllers reload the EEPROM automatically, so just wait
633 * for reload to complete.
634 */
635 switch (hw->mac_type) {
636 case e1000_82542_rev2_0:
637 case e1000_82542_rev2_1:
638 case e1000_82543:
639 case e1000_82544:
640 /* Wait for reset to complete */
641 udelay(10);
642 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
643 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
644 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
645 E1000_WRITE_FLUSH(hw);
646 /* Wait for EEPROM reload */
647 msleep(2);
648 break;
649 case e1000_82541:
650 case e1000_82541_rev_2:
651 case e1000_82547:
652 case e1000_82547_rev_2:
653 /* Wait for EEPROM reload */
654 msleep(20);
655 break;
656 case e1000_82573:
657 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
658 udelay(10);
659 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
660 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
661 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
662 E1000_WRITE_FLUSH(hw);
663 }
664 /* fall through */
665 case e1000_82571:
666 case e1000_82572:
667 case e1000_ich8lan:
668 case e1000_80003es2lan:
669 ret_val = e1000_get_auto_rd_done(hw);
670 if (ret_val)
671 /* We don't want to continue accessing MAC registers. */
672 return ret_val;
673 break;
674 default:
675 /* Wait for EEPROM reload (it happens automatically) */
676 msleep(5);
677 break;
678 }
679
680 /* Disable HW ARPs on ASF enabled adapters */
681 if (hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) {
682 manc = E1000_READ_REG(hw, MANC);
683 manc &= ~(E1000_MANC_ARP_EN);
684 E1000_WRITE_REG(hw, MANC, manc);
685 }
686
687 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
688 e1000_phy_init_script(hw);
689
690 /* Configure activity LED after PHY reset */
691 led_ctrl = E1000_READ_REG(hw, LEDCTL);
692 led_ctrl &= IGP_ACTIVITY_LED_MASK;
693 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
694 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
695 }
696
697 /* Clear interrupt mask to stop board from generating interrupts */
698 DEBUGOUT("Masking off all interrupts\n");
699 E1000_WRITE_REG(hw, IMC, 0xffffffff);
700
701 /* Clear any pending interrupt events. */
702 icr = E1000_READ_REG(hw, ICR);
703
704 /* If MWI was previously enabled, reenable it. */
705 if (hw->mac_type == e1000_82542_rev2_0) {
706 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
707 e1000_pci_set_mwi(hw);
708 }
709
710 if (hw->mac_type == e1000_ich8lan) {
711 uint32_t kab = E1000_READ_REG(hw, KABGTXD);
712 kab |= E1000_KABGTXD_BGSQLBIAS;
713 E1000_WRITE_REG(hw, KABGTXD, kab);
714 }
715
716 return E1000_SUCCESS;
717 }
718
719 /******************************************************************************
720 *
721 * Initialize a number of hardware-dependent bits
722 *
723 * hw: Struct containing variables accessed by shared code
724 *
725 * This function contains hardware limitation workarounds for PCI-E adapters
726 *
727 *****************************************************************************/
728 static void
729 e1000_initialize_hardware_bits(struct e1000_hw *hw)
730 {
731 if ((hw->mac_type >= e1000_82571) && (!hw->initialize_hw_bits_disable)) {
732 /* Settings common to all PCI-express silicon */
733 uint32_t reg_ctrl, reg_ctrl_ext;
734 uint32_t reg_tarc0, reg_tarc1;
735 uint32_t reg_tctl;
736 uint32_t reg_txdctl, reg_txdctl1;
737
738 /* link autonegotiation/sync workarounds */
739 reg_tarc0 = E1000_READ_REG(hw, TARC0);
740 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
741
742 /* Enable not-done TX descriptor counting */
743 reg_txdctl = E1000_READ_REG(hw, TXDCTL);
744 reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
745 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
746 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
747 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
748 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
749
750 switch (hw->mac_type) {
751 case e1000_82571:
752 case e1000_82572:
753 /* Clear PHY TX compatible mode bits */
754 reg_tarc1 = E1000_READ_REG(hw, TARC1);
755 reg_tarc1 &= ~((1 << 30)|(1 << 29));
756
757 /* link autonegotiation/sync workarounds */
758 reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
759
760 /* TX ring control fixes */
761 reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
762
763 /* Multiple read bit is reversed polarity */
764 reg_tctl = E1000_READ_REG(hw, TCTL);
765 if (reg_tctl & E1000_TCTL_MULR)
766 reg_tarc1 &= ~(1 << 28);
767 else
768 reg_tarc1 |= (1 << 28);
769
770 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
771 break;
772 case e1000_82573:
773 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
774 reg_ctrl_ext &= ~(1 << 23);
775 reg_ctrl_ext |= (1 << 22);
776
777 /* TX byte count fix */
778 reg_ctrl = E1000_READ_REG(hw, CTRL);
779 reg_ctrl &= ~(1 << 29);
780
781 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
782 E1000_WRITE_REG(hw, CTRL, reg_ctrl);
783 break;
784 case e1000_80003es2lan:
785 /* improve small packet performace for fiber/serdes */
786 if ((hw->media_type == e1000_media_type_fiber) ||
787 (hw->media_type == e1000_media_type_internal_serdes)) {
788 reg_tarc0 &= ~(1 << 20);
789 }
790
791 /* Multiple read bit is reversed polarity */
792 reg_tctl = E1000_READ_REG(hw, TCTL);
793 reg_tarc1 = E1000_READ_REG(hw, TARC1);
794 if (reg_tctl & E1000_TCTL_MULR)
795 reg_tarc1 &= ~(1 << 28);
796 else
797 reg_tarc1 |= (1 << 28);
798
799 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
800 break;
801 case e1000_ich8lan:
802 /* Reduce concurrent DMA requests to 3 from 4 */
803 if ((hw->revision_id < 3) ||
804 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
805 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
806 reg_tarc0 |= ((1 << 29)|(1 << 28));
807
808 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
809 reg_ctrl_ext |= (1 << 22);
810 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
811
812 /* workaround TX hang with TSO=on */
813 reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
814
815 /* Multiple read bit is reversed polarity */
816 reg_tctl = E1000_READ_REG(hw, TCTL);
817 reg_tarc1 = E1000_READ_REG(hw, TARC1);
818 if (reg_tctl & E1000_TCTL_MULR)
819 reg_tarc1 &= ~(1 << 28);
820 else
821 reg_tarc1 |= (1 << 28);
822
823 /* workaround TX hang with TSO=on */
824 reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
825
826 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
827 break;
828 default:
829 break;
830 }
831
832 E1000_WRITE_REG(hw, TARC0, reg_tarc0);
833 }
834 }
835
836 /******************************************************************************
837 * Performs basic configuration of the adapter.
838 *
839 * hw - Struct containing variables accessed by shared code
840 *
841 * Assumes that the controller has previously been reset and is in a
842 * post-reset uninitialized state. Initializes the receive address registers,
843 * multicast table, and VLAN filter table. Calls routines to setup link
844 * configuration and flow control settings. Clears all on-chip counters. Leaves
845 * the transmit and receive units disabled and uninitialized.
846 *****************************************************************************/
847 int32_t
848 e1000_init_hw(struct e1000_hw *hw)
849 {
850 uint32_t ctrl;
851 uint32_t i;
852 int32_t ret_val;
853 uint16_t pcix_cmd_word;
854 uint16_t pcix_stat_hi_word;
855 uint16_t cmd_mmrbc;
856 uint16_t stat_mmrbc;
857 uint32_t mta_size;
858 uint32_t reg_data;
859 uint32_t ctrl_ext;
860
861 DEBUGFUNC("e1000_init_hw");
862
863 /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
864 if ((hw->mac_type == e1000_ich8lan) &&
865 ((hw->revision_id < 3) ||
866 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
867 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
868 reg_data = E1000_READ_REG(hw, STATUS);
869 reg_data &= ~0x80000000;
870 E1000_WRITE_REG(hw, STATUS, reg_data);
871 }
872
873 /* Initialize Identification LED */
874 ret_val = e1000_id_led_init(hw);
875 if (ret_val) {
876 DEBUGOUT("Error Initializing Identification LED\n");
877 return ret_val;
878 }
879
880 /* Set the media type and TBI compatibility */
881 e1000_set_media_type(hw);
882
883 /* Must be called after e1000_set_media_type because media_type is used */
884 e1000_initialize_hardware_bits(hw);
885
886 /* Disabling VLAN filtering. */
887 DEBUGOUT("Initializing the IEEE VLAN\n");
888 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
889 if (hw->mac_type != e1000_ich8lan) {
890 if (hw->mac_type < e1000_82545_rev_3)
891 E1000_WRITE_REG(hw, VET, 0);
892 e1000_clear_vfta(hw);
893 }
894
895 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
896 if (hw->mac_type == e1000_82542_rev2_0) {
897 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
898 e1000_pci_clear_mwi(hw);
899 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
900 E1000_WRITE_FLUSH(hw);
901 msleep(5);
902 }
903
904 /* Setup the receive address. This involves initializing all of the Receive
905 * Address Registers (RARs 0 - 15).
906 */
907 e1000_init_rx_addrs(hw);
908
909 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
910 if (hw->mac_type == e1000_82542_rev2_0) {
911 E1000_WRITE_REG(hw, RCTL, 0);
912 E1000_WRITE_FLUSH(hw);
913 msleep(1);
914 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
915 e1000_pci_set_mwi(hw);
916 }
917
918 /* Zero out the Multicast HASH table */
919 DEBUGOUT("Zeroing the MTA\n");
920 mta_size = E1000_MC_TBL_SIZE;
921 if (hw->mac_type == e1000_ich8lan)
922 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
923 for (i = 0; i < mta_size; i++) {
924 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
925 /* use write flush to prevent Memory Write Block (MWB) from
926 * occuring when accessing our register space */
927 E1000_WRITE_FLUSH(hw);
928 }
929
930 /* Set the PCI priority bit correctly in the CTRL register. This
931 * determines if the adapter gives priority to receives, or if it
932 * gives equal priority to transmits and receives. Valid only on
933 * 82542 and 82543 silicon.
934 */
935 if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
936 ctrl = E1000_READ_REG(hw, CTRL);
937 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
938 }
939
940 switch (hw->mac_type) {
941 case e1000_82545_rev_3:
942 case e1000_82546_rev_3:
943 break;
944 default:
945 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
946 if (hw->bus_type == e1000_bus_type_pcix) {
947 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
948 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI,
949 &pcix_stat_hi_word);
950 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
951 PCIX_COMMAND_MMRBC_SHIFT;
952 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
953 PCIX_STATUS_HI_MMRBC_SHIFT;
954 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
955 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
956 if (cmd_mmrbc > stat_mmrbc) {
957 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
958 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
959 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER,
960 &pcix_cmd_word);
961 }
962 }
963 break;
964 }
965
966 /* More time needed for PHY to initialize */
967 if (hw->mac_type == e1000_ich8lan)
968 msleep(15);
969
970 /* Call a subroutine to configure the link and setup flow control. */
971 ret_val = e1000_setup_link(hw);
972
973 /* Set the transmit descriptor write-back policy */
974 if (hw->mac_type > e1000_82544) {
975 ctrl = E1000_READ_REG(hw, TXDCTL);
976 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
977 E1000_WRITE_REG(hw, TXDCTL, ctrl);
978 }
979
980 if (hw->mac_type == e1000_82573) {
981 e1000_enable_tx_pkt_filtering(hw);
982 }
983
984 switch (hw->mac_type) {
985 default:
986 break;
987 case e1000_80003es2lan:
988 /* Enable retransmit on late collisions */
989 reg_data = E1000_READ_REG(hw, TCTL);
990 reg_data |= E1000_TCTL_RTLC;
991 E1000_WRITE_REG(hw, TCTL, reg_data);
992
993 /* Configure Gigabit Carry Extend Padding */
994 reg_data = E1000_READ_REG(hw, TCTL_EXT);
995 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
996 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
997 E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
998
999 /* Configure Transmit Inter-Packet Gap */
1000 reg_data = E1000_READ_REG(hw, TIPG);
1001 reg_data &= ~E1000_TIPG_IPGT_MASK;
1002 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1003 E1000_WRITE_REG(hw, TIPG, reg_data);
1004
1005 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
1006 reg_data &= ~0x00100000;
1007 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
1008 /* Fall through */
1009 case e1000_82571:
1010 case e1000_82572:
1011 case e1000_ich8lan:
1012 ctrl = E1000_READ_REG(hw, TXDCTL1);
1013 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
1014 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
1015 break;
1016 }
1017
1018
1019 if (hw->mac_type == e1000_82573) {
1020 uint32_t gcr = E1000_READ_REG(hw, GCR);
1021 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1022 E1000_WRITE_REG(hw, GCR, gcr);
1023 }
1024
1025 /* Clear all of the statistics registers (clear on read). It is
1026 * important that we do this after we have tried to establish link
1027 * because the symbol error count will increment wildly if there
1028 * is no link.
1029 */
1030 e1000_clear_hw_cntrs(hw);
1031
1032 /* ICH8 No-snoop bits are opposite polarity.
1033 * Set to snoop by default after reset. */
1034 if (hw->mac_type == e1000_ich8lan)
1035 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
1036
1037 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
1038 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
1039 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1040 /* Relaxed ordering must be disabled to avoid a parity
1041 * error crash in a PCI slot. */
1042 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
1043 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1044 }
1045
1046 return ret_val;
1047 }
1048
1049 /******************************************************************************
1050 * Adjust SERDES output amplitude based on EEPROM setting.
1051 *
1052 * hw - Struct containing variables accessed by shared code.
1053 *****************************************************************************/
1054 static int32_t
1055 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
1056 {
1057 uint16_t eeprom_data;
1058 int32_t ret_val;
1059
1060 DEBUGFUNC("e1000_adjust_serdes_amplitude");
1061
1062 if (hw->media_type != e1000_media_type_internal_serdes)
1063 return E1000_SUCCESS;
1064
1065 switch (hw->mac_type) {
1066 case e1000_82545_rev_3:
1067 case e1000_82546_rev_3:
1068 break;
1069 default:
1070 return E1000_SUCCESS;
1071 }
1072
1073 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data);
1074 if (ret_val) {
1075 return ret_val;
1076 }
1077
1078 if (eeprom_data != EEPROM_RESERVED_WORD) {
1079 /* Adjust SERDES output amplitude only. */
1080 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
1081 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
1082 if (ret_val)
1083 return ret_val;
1084 }
1085
1086 return E1000_SUCCESS;
1087 }
1088
1089 /******************************************************************************
1090 * Configures flow control and link settings.
1091 *
1092 * hw - Struct containing variables accessed by shared code
1093 *
1094 * Determines which flow control settings to use. Calls the apropriate media-
1095 * specific link configuration function. Configures the flow control settings.
1096 * Assuming the adapter has a valid link partner, a valid link should be
1097 * established. Assumes the hardware has previously been reset and the
1098 * transmitter and receiver are not enabled.
1099 *****************************************************************************/
1100 int32_t
1101 e1000_setup_link(struct e1000_hw *hw)
1102 {
1103 uint32_t ctrl_ext;
1104 int32_t ret_val;
1105 uint16_t eeprom_data;
1106
1107 DEBUGFUNC("e1000_setup_link");
1108
1109 /* In the case of the phy reset being blocked, we already have a link.
1110 * We do not have to set it up again. */
1111 if (e1000_check_phy_reset_block(hw))
1112 return E1000_SUCCESS;
1113
1114 /* Read and store word 0x0F of the EEPROM. This word contains bits
1115 * that determine the hardware's default PAUSE (flow control) mode,
1116 * a bit that determines whether the HW defaults to enabling or
1117 * disabling auto-negotiation, and the direction of the
1118 * SW defined pins. If there is no SW over-ride of the flow
1119 * control setting, then the variable hw->fc will
1120 * be initialized based on a value in the EEPROM.
1121 */
1122 if (hw->fc == E1000_FC_DEFAULT) {
1123 switch (hw->mac_type) {
1124 case e1000_ich8lan:
1125 case e1000_82573:
1126 hw->fc = E1000_FC_FULL;
1127 break;
1128 default:
1129 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
1130 1, &eeprom_data);
1131 if (ret_val) {
1132 DEBUGOUT("EEPROM Read Error\n");
1133 return -E1000_ERR_EEPROM;
1134 }
1135 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
1136 hw->fc = E1000_FC_NONE;
1137 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
1138 EEPROM_WORD0F_ASM_DIR)
1139 hw->fc = E1000_FC_TX_PAUSE;
1140 else
1141 hw->fc = E1000_FC_FULL;
1142 break;
1143 }
1144 }
1145
1146 /* We want to save off the original Flow Control configuration just
1147 * in case we get disconnected and then reconnected into a different
1148 * hub or switch with different Flow Control capabilities.
1149 */
1150 if (hw->mac_type == e1000_82542_rev2_0)
1151 hw->fc &= (~E1000_FC_TX_PAUSE);
1152
1153 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
1154 hw->fc &= (~E1000_FC_RX_PAUSE);
1155
1156 hw->original_fc = hw->fc;
1157
1158 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
1159
1160 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
1161 * polarity value for the SW controlled pins, and setup the
1162 * Extended Device Control reg with that info.
1163 * This is needed because one of the SW controlled pins is used for
1164 * signal detection. So this should be done before e1000_setup_pcs_link()
1165 * or e1000_phy_setup() is called.
1166 */
1167 if (hw->mac_type == e1000_82543) {
1168 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
1169 1, &eeprom_data);
1170 if (ret_val) {
1171 DEBUGOUT("EEPROM Read Error\n");
1172 return -E1000_ERR_EEPROM;
1173 }
1174 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
1175 SWDPIO__EXT_SHIFT);
1176 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1177 }
1178
1179 /* Call the necessary subroutine to configure the link. */
1180 ret_val = (hw->media_type == e1000_media_type_copper) ?
1181 e1000_setup_copper_link(hw) :
1182 e1000_setup_fiber_serdes_link(hw);
1183
1184 /* Initialize the flow control address, type, and PAUSE timer
1185 * registers to their default values. This is done even if flow
1186 * control is disabled, because it does not hurt anything to
1187 * initialize these registers.
1188 */
1189 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
1190
1191 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
1192 if (hw->mac_type != e1000_ich8lan) {
1193 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1194 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1195 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1196 }
1197
1198 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
1199
1200 /* Set the flow control receive threshold registers. Normally,
1201 * these registers will be set to a default threshold that may be
1202 * adjusted later by the driver's runtime code. However, if the
1203 * ability to transmit pause frames in not enabled, then these
1204 * registers will be set to 0.
1205 */
1206 if (!(hw->fc & E1000_FC_TX_PAUSE)) {
1207 E1000_WRITE_REG(hw, FCRTL, 0);
1208 E1000_WRITE_REG(hw, FCRTH, 0);
1209 } else {
1210 /* We need to set up the Receive Threshold high and low water marks
1211 * as well as (optionally) enabling the transmission of XON frames.
1212 */
1213 if (hw->fc_send_xon) {
1214 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
1215 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1216 } else {
1217 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
1218 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1219 }
1220 }
1221 return ret_val;
1222 }
1223
1224 /******************************************************************************
1225 * Sets up link for a fiber based or serdes based adapter
1226 *
1227 * hw - Struct containing variables accessed by shared code
1228 *
1229 * Manipulates Physical Coding Sublayer functions in order to configure
1230 * link. Assumes the hardware has been previously reset and the transmitter
1231 * and receiver are not enabled.
1232 *****************************************************************************/
1233 static int32_t
1234 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1235 {
1236 uint32_t ctrl;
1237 uint32_t status;
1238 uint32_t txcw = 0;
1239 uint32_t i;
1240 uint32_t signal = 0;
1241 int32_t ret_val;
1242
1243 DEBUGFUNC("e1000_setup_fiber_serdes_link");
1244
1245 /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists
1246 * until explicitly turned off or a power cycle is performed. A read to
1247 * the register does not indicate its status. Therefore, we ensure
1248 * loopback mode is disabled during initialization.
1249 */
1250 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572)
1251 E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK);
1252
1253 /* On adapters with a MAC newer than 82544, SWDP 1 will be
1254 * set when the optics detect a signal. On older adapters, it will be
1255 * cleared when there is a signal. This applies to fiber media only.
1256 * If we're on serdes media, adjust the output amplitude to value
1257 * set in the EEPROM.
1258 */
1259 ctrl = E1000_READ_REG(hw, CTRL);
1260 if (hw->media_type == e1000_media_type_fiber)
1261 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
1262
1263 ret_val = e1000_adjust_serdes_amplitude(hw);
1264 if (ret_val)
1265 return ret_val;
1266
1267 /* Take the link out of reset */
1268 ctrl &= ~(E1000_CTRL_LRST);
1269
1270 /* Adjust VCO speed to improve BER performance */
1271 ret_val = e1000_set_vco_speed(hw);
1272 if (ret_val)
1273 return ret_val;
1274
1275 e1000_config_collision_dist(hw);
1276
1277 /* Check for a software override of the flow control settings, and setup
1278 * the device accordingly. If auto-negotiation is enabled, then software
1279 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
1280 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
1281 * auto-negotiation is disabled, then software will have to manually
1282 * configure the two flow control enable bits in the CTRL register.
1283 *
1284 * The possible values of the "fc" parameter are:
1285 * 0: Flow control is completely disabled
1286 * 1: Rx flow control is enabled (we can receive pause frames, but
1287 * not send pause frames).
1288 * 2: Tx flow control is enabled (we can send pause frames but we do
1289 * not support receiving pause frames).
1290 * 3: Both Rx and TX flow control (symmetric) are enabled.
1291 */
1292 switch (hw->fc) {
1293 case E1000_FC_NONE:
1294 /* Flow control is completely disabled by a software over-ride. */
1295 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1296 break;
1297 case E1000_FC_RX_PAUSE:
1298 /* RX Flow control is enabled and TX Flow control is disabled by a
1299 * software over-ride. Since there really isn't a way to advertise
1300 * that we are capable of RX Pause ONLY, we will advertise that we
1301 * support both symmetric and asymmetric RX PAUSE. Later, we will
1302 * disable the adapter's ability to send PAUSE frames.
1303 */
1304 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1305 break;
1306 case E1000_FC_TX_PAUSE:
1307 /* TX Flow control is enabled, and RX Flow control is disabled, by a
1308 * software over-ride.
1309 */
1310 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1311 break;
1312 case E1000_FC_FULL:
1313 /* Flow control (both RX and TX) is enabled by a software over-ride. */
1314 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1315 break;
1316 default:
1317 DEBUGOUT("Flow control param set incorrectly\n");
1318 return -E1000_ERR_CONFIG;
1319 break;
1320 }
1321
1322 /* Since auto-negotiation is enabled, take the link out of reset (the link
1323 * will be in reset, because we previously reset the chip). This will
1324 * restart auto-negotiation. If auto-neogtiation is successful then the
1325 * link-up status bit will be set and the flow control enable bits (RFCE
1326 * and TFCE) will be set according to their negotiated value.
1327 */
1328 DEBUGOUT("Auto-negotiation enabled\n");
1329
1330 E1000_WRITE_REG(hw, TXCW, txcw);
1331 E1000_WRITE_REG(hw, CTRL, ctrl);
1332 E1000_WRITE_FLUSH(hw);
1333
1334 hw->txcw = txcw;
1335 msleep(1);
1336
1337 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
1338 * indication in the Device Status Register. Time-out if a link isn't
1339 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
1340 * less than 500 milliseconds even if the other end is doing it in SW).
1341 * For internal serdes, we just assume a signal is present, then poll.
1342 */
1343 if (hw->media_type == e1000_media_type_internal_serdes ||
1344 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
1345 DEBUGOUT("Looking for Link\n");
1346 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
1347 msleep(10);
1348 status = E1000_READ_REG(hw, STATUS);
1349 if (status & E1000_STATUS_LU) break;
1350 }
1351 if (i == (LINK_UP_TIMEOUT / 10)) {
1352 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1353 hw->autoneg_failed = 1;
1354 /* AutoNeg failed to achieve a link, so we'll call
1355 * e1000_check_for_link. This routine will force the link up if
1356 * we detect a signal. This will allow us to communicate with
1357 * non-autonegotiating link partners.
1358 */
1359 ret_val = e1000_check_for_link(hw);
1360 if (ret_val) {
1361 DEBUGOUT("Error while checking for link\n");
1362 return ret_val;
1363 }
1364 hw->autoneg_failed = 0;
1365 } else {
1366 hw->autoneg_failed = 0;
1367 DEBUGOUT("Valid Link Found\n");
1368 }
1369 } else {
1370 DEBUGOUT("No Signal Detected\n");
1371 }
1372 return E1000_SUCCESS;
1373 }
1374
1375 /******************************************************************************
1376 * Make sure we have a valid PHY and change PHY mode before link setup.
1377 *
1378 * hw - Struct containing variables accessed by shared code
1379 ******************************************************************************/
1380 static int32_t
1381 e1000_copper_link_preconfig(struct e1000_hw *hw)
1382 {
1383 uint32_t ctrl;
1384 int32_t ret_val;
1385 uint16_t phy_data;
1386
1387 DEBUGFUNC("e1000_copper_link_preconfig");
1388
1389 ctrl = E1000_READ_REG(hw, CTRL);
1390 /* With 82543, we need to force speed and duplex on the MAC equal to what
1391 * the PHY speed and duplex configuration is. In addition, we need to
1392 * perform a hardware reset on the PHY to take it out of reset.
1393 */
1394 if (hw->mac_type > e1000_82543) {
1395 ctrl |= E1000_CTRL_SLU;
1396 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1397 E1000_WRITE_REG(hw, CTRL, ctrl);
1398 } else {
1399 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1400 E1000_WRITE_REG(hw, CTRL, ctrl);
1401 ret_val = e1000_phy_hw_reset(hw);
1402 if (ret_val)
1403 return ret_val;
1404 }
1405
1406 /* Make sure we have a valid PHY */
1407 ret_val = e1000_detect_gig_phy(hw);
1408 if (ret_val) {
1409 DEBUGOUT("Error, did not detect valid phy.\n");
1410 return ret_val;
1411 }
1412 DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
1413
1414 /* Set PHY to class A mode (if necessary) */
1415 ret_val = e1000_set_phy_mode(hw);
1416 if (ret_val)
1417 return ret_val;
1418
1419 if ((hw->mac_type == e1000_82545_rev_3) ||
1420 (hw->mac_type == e1000_82546_rev_3)) {
1421 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1422 phy_data |= 0x00000008;
1423 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1424 }
1425
1426 if (hw->mac_type <= e1000_82543 ||
1427 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1428 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
1429 hw->phy_reset_disable = FALSE;
1430
1431 return E1000_SUCCESS;
1432 }
1433
1434
1435 /********************************************************************
1436 * Copper link setup for e1000_phy_igp series.
1437 *
1438 * hw - Struct containing variables accessed by shared code
1439 *********************************************************************/
1440 static int32_t
1441 e1000_copper_link_igp_setup(struct e1000_hw *hw)
1442 {
1443 uint32_t led_ctrl;
1444 int32_t ret_val;
1445 uint16_t phy_data;
1446
1447 DEBUGFUNC("e1000_copper_link_igp_setup");
1448
1449 if (hw->phy_reset_disable)
1450 return E1000_SUCCESS;
1451
1452 ret_val = e1000_phy_reset(hw);
1453 if (ret_val) {
1454 DEBUGOUT("Error Resetting the PHY\n");
1455 return ret_val;
1456 }
1457
1458 /* Wait 15ms for MAC to configure PHY from eeprom settings */
1459 msleep(15);
1460 if (hw->mac_type != e1000_ich8lan) {
1461 /* Configure activity LED after PHY reset */
1462 led_ctrl = E1000_READ_REG(hw, LEDCTL);
1463 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1464 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1465 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
1466 }
1467
1468 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
1469 if (hw->phy_type == e1000_phy_igp) {
1470 /* disable lplu d3 during driver init */
1471 ret_val = e1000_set_d3_lplu_state(hw, FALSE);
1472 if (ret_val) {
1473 DEBUGOUT("Error Disabling LPLU D3\n");
1474 return ret_val;
1475 }
1476 }
1477
1478 /* disable lplu d0 during driver init */
1479 ret_val = e1000_set_d0_lplu_state(hw, FALSE);
1480 if (ret_val) {
1481 DEBUGOUT("Error Disabling LPLU D0\n");
1482 return ret_val;
1483 }
1484 /* Configure mdi-mdix settings */
1485 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1486 if (ret_val)
1487 return ret_val;
1488
1489 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1490 hw->dsp_config_state = e1000_dsp_config_disabled;
1491 /* Force MDI for earlier revs of the IGP PHY */
1492 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX);
1493 hw->mdix = 1;
1494
1495 } else {
1496 hw->dsp_config_state = e1000_dsp_config_enabled;
1497 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1498
1499 switch (hw->mdix) {
1500 case 1:
1501 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1502 break;
1503 case 2:
1504 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1505 break;
1506 case 0:
1507 default:
1508 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1509 break;
1510 }
1511 }
1512 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1513 if (ret_val)
1514 return ret_val;
1515
1516 /* set auto-master slave resolution settings */
1517 if (hw->autoneg) {
1518 e1000_ms_type phy_ms_setting = hw->master_slave;
1519
1520 if (hw->ffe_config_state == e1000_ffe_config_active)
1521 hw->ffe_config_state = e1000_ffe_config_enabled;
1522
1523 if (hw->dsp_config_state == e1000_dsp_config_activated)
1524 hw->dsp_config_state = e1000_dsp_config_enabled;
1525
1526 /* when autonegotiation advertisment is only 1000Mbps then we
1527 * should disable SmartSpeed and enable Auto MasterSlave
1528 * resolution as hardware default. */
1529 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1530 /* Disable SmartSpeed */
1531 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1532 &phy_data);
1533 if (ret_val)
1534 return ret_val;
1535 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1536 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1537 phy_data);
1538 if (ret_val)
1539 return ret_val;
1540 /* Set auto Master/Slave resolution process */
1541 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1542 if (ret_val)
1543 return ret_val;
1544 phy_data &= ~CR_1000T_MS_ENABLE;
1545 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1546 if (ret_val)
1547 return ret_val;
1548 }
1549
1550 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1551 if (ret_val)
1552 return ret_val;
1553
1554 /* load defaults for future use */
1555 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1556 ((phy_data & CR_1000T_MS_VALUE) ?
1557 e1000_ms_force_master :
1558 e1000_ms_force_slave) :
1559 e1000_ms_auto;
1560
1561 switch (phy_ms_setting) {
1562 case e1000_ms_force_master:
1563 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1564 break;
1565 case e1000_ms_force_slave:
1566 phy_data |= CR_1000T_MS_ENABLE;
1567 phy_data &= ~(CR_1000T_MS_VALUE);
1568 break;
1569 case e1000_ms_auto:
1570 phy_data &= ~CR_1000T_MS_ENABLE;
1571 default:
1572 break;
1573 }
1574 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1575 if (ret_val)
1576 return ret_val;
1577 }
1578
1579 return E1000_SUCCESS;
1580 }
1581
1582 /********************************************************************
1583 * Copper link setup for e1000_phy_gg82563 series.
1584 *
1585 * hw - Struct containing variables accessed by shared code
1586 *********************************************************************/
1587 static int32_t
1588 e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1589 {
1590 int32_t ret_val;
1591 uint16_t phy_data;
1592 uint32_t reg_data;
1593
1594 DEBUGFUNC("e1000_copper_link_ggp_setup");
1595
1596 if (!hw->phy_reset_disable) {
1597
1598 /* Enable CRS on TX for half-duplex operation. */
1599 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1600 &phy_data);
1601 if (ret_val)
1602 return ret_val;
1603
1604 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
1605 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
1606 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
1607
1608 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1609 phy_data);
1610 if (ret_val)
1611 return ret_val;
1612
1613 /* Options:
1614 * MDI/MDI-X = 0 (default)
1615 * 0 - Auto for all speeds
1616 * 1 - MDI mode
1617 * 2 - MDI-X mode
1618 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1619 */
1620 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data);
1621 if (ret_val)
1622 return ret_val;
1623
1624 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
1625
1626 switch (hw->mdix) {
1627 case 1:
1628 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
1629 break;
1630 case 2:
1631 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
1632 break;
1633 case 0:
1634 default:
1635 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1636 break;
1637 }
1638
1639 /* Options:
1640 * disable_polarity_correction = 0 (default)
1641 * Automatic Correction for Reversed Cable Polarity
1642 * 0 - Disabled
1643 * 1 - Enabled
1644 */
1645 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1646 if (hw->disable_polarity_correction == 1)
1647 phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1648 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
1649
1650 if (ret_val)
1651 return ret_val;
1652
1653 /* SW Reset the PHY so all changes take effect */
1654 ret_val = e1000_phy_reset(hw);
1655 if (ret_val) {
1656 DEBUGOUT("Error Resetting the PHY\n");
1657 return ret_val;
1658 }
1659 } /* phy_reset_disable */
1660
1661 if (hw->mac_type == e1000_80003es2lan) {
1662 /* Bypass RX and TX FIFO's */
1663 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
1664 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS |
1665 E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
1666 if (ret_val)
1667 return ret_val;
1668
1669 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data);
1670 if (ret_val)
1671 return ret_val;
1672
1673 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1674 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data);
1675
1676 if (ret_val)
1677 return ret_val;
1678
1679 reg_data = E1000_READ_REG(hw, CTRL_EXT);
1680 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1681 E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
1682
1683 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1684 &phy_data);
1685 if (ret_val)
1686 return ret_val;
1687
1688 /* Do not init these registers when the HW is in IAMT mode, since the
1689 * firmware will have already initialized them. We only initialize
1690 * them if the HW is not in IAMT mode.
1691 */
1692 if (e1000_check_mng_mode(hw) == FALSE) {
1693 /* Enable Electrical Idle on the PHY */
1694 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1695 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1696 phy_data);
1697 if (ret_val)
1698 return ret_val;
1699
1700 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1701 &phy_data);
1702 if (ret_val)
1703 return ret_val;
1704
1705 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1706 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1707 phy_data);
1708
1709 if (ret_val)
1710 return ret_val;
1711 }
1712
1713 /* Workaround: Disable padding in Kumeran interface in the MAC
1714 * and in the PHY to avoid CRC errors.
1715 */
1716 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
1717 &phy_data);
1718 if (ret_val)
1719 return ret_val;
1720 phy_data |= GG82563_ICR_DIS_PADDING;
1721 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
1722 phy_data);
1723 if (ret_val)
1724 return ret_val;
1725 }
1726
1727 return E1000_SUCCESS;
1728 }
1729
1730 /********************************************************************
1731 * Copper link setup for e1000_phy_m88 series.
1732 *
1733 * hw - Struct containing variables accessed by shared code
1734 *********************************************************************/
1735 static int32_t
1736 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1737 {
1738 int32_t ret_val;
1739 uint16_t phy_data;
1740
1741 DEBUGFUNC("e1000_copper_link_mgp_setup");
1742
1743 if (hw->phy_reset_disable)
1744 return E1000_SUCCESS;
1745
1746 /* Enable CRS on TX. This must be set for half-duplex operation. */
1747 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1748 if (ret_val)
1749 return ret_val;
1750
1751 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1752
1753 /* Options:
1754 * MDI/MDI-X = 0 (default)
1755 * 0 - Auto for all speeds
1756 * 1 - MDI mode
1757 * 2 - MDI-X mode
1758 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1759 */
1760 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1761
1762 switch (hw->mdix) {
1763 case 1:
1764 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1765 break;
1766 case 2:
1767 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1768 break;
1769 case 3:
1770 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1771 break;
1772 case 0:
1773 default:
1774 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1775 break;
1776 }
1777
1778 /* Options:
1779 * disable_polarity_correction = 0 (default)
1780 * Automatic Correction for Reversed Cable Polarity
1781 * 0 - Disabled
1782 * 1 - Enabled
1783 */
1784 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1785 if (hw->disable_polarity_correction == 1)
1786 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1787 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1788 if (ret_val)
1789 return ret_val;
1790
1791 if (hw->phy_revision < M88E1011_I_REV_4) {
1792 /* Force TX_CLK in the Extended PHY Specific Control Register
1793 * to 25MHz clock.
1794 */
1795 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1796 if (ret_val)
1797 return ret_val;
1798
1799 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1800
1801 if ((hw->phy_revision == E1000_REVISION_2) &&
1802 (hw->phy_id == M88E1111_I_PHY_ID)) {
1803 /* Vidalia Phy, set the downshift counter to 5x */
1804 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
1805 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1806 ret_val = e1000_write_phy_reg(hw,
1807 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1808 if (ret_val)
1809 return ret_val;
1810 } else {
1811 /* Configure Master and Slave downshift values */
1812 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1813 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1814 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1815 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1816 ret_val = e1000_write_phy_reg(hw,
1817 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1818 if (ret_val)
1819 return ret_val;
1820 }
1821 }
1822
1823 /* SW Reset the PHY so all changes take effect */
1824 ret_val = e1000_phy_reset(hw);
1825 if (ret_val) {
1826 DEBUGOUT("Error Resetting the PHY\n");
1827 return ret_val;
1828 }
1829
1830 return E1000_SUCCESS;
1831 }
1832
1833 /********************************************************************
1834 * Setup auto-negotiation and flow control advertisements,
1835 * and then perform auto-negotiation.
1836 *
1837 * hw - Struct containing variables accessed by shared code
1838 *********************************************************************/
1839 static int32_t
1840 e1000_copper_link_autoneg(struct e1000_hw *hw)
1841 {
1842 int32_t ret_val;
1843 uint16_t phy_data;
1844
1845 DEBUGFUNC("e1000_copper_link_autoneg");
1846
1847 /* Perform some bounds checking on the hw->autoneg_advertised
1848 * parameter. If this variable is zero, then set it to the default.
1849 */
1850 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1851
1852 /* If autoneg_advertised is zero, we assume it was not defaulted
1853 * by the calling code so we set to advertise full capability.
1854 */
1855 if (hw->autoneg_advertised == 0)
1856 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1857
1858 /* IFE phy only supports 10/100 */
1859 if (hw->phy_type == e1000_phy_ife)
1860 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
1861
1862 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1863 ret_val = e1000_phy_setup_autoneg(hw);
1864 if (ret_val) {
1865 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1866 return ret_val;
1867 }
1868 DEBUGOUT("Restarting Auto-Neg\n");
1869
1870 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1871 * the Auto Neg Restart bit in the PHY control register.
1872 */
1873 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1874 if (ret_val)
1875 return ret_val;
1876
1877 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1878 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
1879 if (ret_val)
1880 return ret_val;
1881
1882 /* Does the user want to wait for Auto-Neg to complete here, or
1883 * check at a later time (for example, callback routine).
1884 */
1885 if (hw->wait_autoneg_complete) {
1886 ret_val = e1000_wait_autoneg(hw);
1887 if (ret_val) {
1888 DEBUGOUT("Error while waiting for autoneg to complete\n");
1889 return ret_val;
1890 }
1891 }
1892
1893 hw->get_link_status = TRUE;
1894
1895 return E1000_SUCCESS;
1896 }
1897
1898 /******************************************************************************
1899 * Config the MAC and the PHY after link is up.
1900 * 1) Set up the MAC to the current PHY speed/duplex
1901 * if we are on 82543. If we
1902 * are on newer silicon, we only need to configure
1903 * collision distance in the Transmit Control Register.
1904 * 2) Set up flow control on the MAC to that established with
1905 * the link partner.
1906 * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
1907 *
1908 * hw - Struct containing variables accessed by shared code
1909 ******************************************************************************/
1910 static int32_t
1911 e1000_copper_link_postconfig(struct e1000_hw *hw)
1912 {
1913 int32_t ret_val;
1914 DEBUGFUNC("e1000_copper_link_postconfig");
1915
1916 if (hw->mac_type >= e1000_82544) {
1917 e1000_config_collision_dist(hw);
1918 } else {
1919 ret_val = e1000_config_mac_to_phy(hw);
1920 if (ret_val) {
1921 DEBUGOUT("Error configuring MAC to PHY settings\n");
1922 return ret_val;
1923 }
1924 }
1925 ret_val = e1000_config_fc_after_link_up(hw);
1926 if (ret_val) {
1927 DEBUGOUT("Error Configuring Flow Control\n");
1928 return ret_val;
1929 }
1930
1931 /* Config DSP to improve Giga link quality */
1932 if (hw->phy_type == e1000_phy_igp) {
1933 ret_val = e1000_config_dsp_after_link_change(hw, TRUE);
1934 if (ret_val) {
1935 DEBUGOUT("Error Configuring DSP after link up\n");
1936 return ret_val;
1937 }
1938 }
1939
1940 return E1000_SUCCESS;
1941 }
1942
1943 /******************************************************************************
1944 * Detects which PHY is present and setup the speed and duplex
1945 *
1946 * hw - Struct containing variables accessed by shared code
1947 ******************************************************************************/
1948 static int32_t
1949 e1000_setup_copper_link(struct e1000_hw *hw)
1950 {
1951 int32_t ret_val;
1952 uint16_t i;
1953 uint16_t phy_data;
1954 uint16_t reg_data;
1955
1956 DEBUGFUNC("e1000_setup_copper_link");
1957
1958 switch (hw->mac_type) {
1959 case e1000_80003es2lan:
1960 case e1000_ich8lan:
1961 /* Set the mac to wait the maximum time between each
1962 * iteration and increase the max iterations when
1963 * polling the phy; this fixes erroneous timeouts at 10Mbps. */
1964 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
1965 if (ret_val)
1966 return ret_val;
1967 ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
1968 if (ret_val)
1969 return ret_val;
1970 reg_data |= 0x3F;
1971 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
1972 if (ret_val)
1973 return ret_val;
1974 default:
1975 break;
1976 }
1977
1978 /* Check if it is a valid PHY and set PHY mode if necessary. */
1979 ret_val = e1000_copper_link_preconfig(hw);
1980 if (ret_val)
1981 return ret_val;
1982
1983 switch (hw->mac_type) {
1984 case e1000_80003es2lan:
1985 /* Kumeran registers are written-only */
1986 reg_data = E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
1987 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
1988 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL,
1989 reg_data);
1990 if (ret_val)
1991 return ret_val;
1992 break;
1993 default:
1994 break;
1995 }
1996
1997 if (hw->phy_type == e1000_phy_igp ||
1998 hw->phy_type == e1000_phy_igp_3 ||
1999 hw->phy_type == e1000_phy_igp_2) {
2000 ret_val = e1000_copper_link_igp_setup(hw);
2001 if (ret_val)
2002 return ret_val;
2003 } else if (hw->phy_type == e1000_phy_m88) {
2004 ret_val = e1000_copper_link_mgp_setup(hw);
2005 if (ret_val)
2006 return ret_val;
2007 } else if (hw->phy_type == e1000_phy_gg82563) {
2008 ret_val = e1000_copper_link_ggp_setup(hw);
2009 if (ret_val)
2010 return ret_val;
2011 }
2012
2013 if (hw->autoneg) {
2014 /* Setup autoneg and flow control advertisement
2015 * and perform autonegotiation */
2016 ret_val = e1000_copper_link_autoneg(hw);
2017 if (ret_val)
2018 return ret_val;
2019 } else {
2020 /* PHY will be set to 10H, 10F, 100H,or 100F
2021 * depending on value from forced_speed_duplex. */
2022 DEBUGOUT("Forcing speed and duplex\n");
2023 ret_val = e1000_phy_force_speed_duplex(hw);
2024 if (ret_val) {
2025 DEBUGOUT("Error Forcing Speed and Duplex\n");
2026 return ret_val;
2027 }
2028 }
2029
2030 /* Check link status. Wait up to 100 microseconds for link to become
2031 * valid.
2032 */
2033 for (i = 0; i < 10; i++) {
2034 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2035 if (ret_val)
2036 return ret_val;
2037 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2038 if (ret_val)
2039 return ret_val;
2040
2041 if (phy_data & MII_SR_LINK_STATUS) {
2042 /* Config the MAC and PHY after link is up */
2043 ret_val = e1000_copper_link_postconfig(hw);
2044 if (ret_val)
2045 return ret_val;
2046
2047 DEBUGOUT("Valid link established!!!\n");
2048 return E1000_SUCCESS;
2049 }
2050 udelay(10);
2051 }
2052
2053 DEBUGOUT("Unable to establish link!!!\n");
2054 return E1000_SUCCESS;
2055 }
2056
2057 /******************************************************************************
2058 * Configure the MAC-to-PHY interface for 10/100Mbps
2059 *
2060 * hw - Struct containing variables accessed by shared code
2061 ******************************************************************************/
2062 static int32_t
2063 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
2064 {
2065 int32_t ret_val = E1000_SUCCESS;
2066 uint32_t tipg;
2067 uint16_t reg_data;
2068
2069 DEBUGFUNC("e1000_configure_kmrn_for_10_100");
2070
2071 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
2072 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
2073 reg_data);
2074 if (ret_val)
2075 return ret_val;
2076
2077 /* Configure Transmit Inter-Packet Gap */
2078 tipg = E1000_READ_REG(hw, TIPG);
2079 tipg &= ~E1000_TIPG_IPGT_MASK;
2080 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
2081 E1000_WRITE_REG(hw, TIPG, tipg);
2082
2083 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
2084
2085 if (ret_val)
2086 return ret_val;
2087
2088 if (duplex == HALF_DUPLEX)
2089 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
2090 else
2091 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2092
2093 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
2094
2095 return ret_val;
2096 }
2097
2098 static int32_t
2099 e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
2100 {
2101 int32_t ret_val = E1000_SUCCESS;
2102 uint16_t reg_data;
2103 uint32_t tipg;
2104
2105 DEBUGFUNC("e1000_configure_kmrn_for_1000");
2106
2107 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
2108 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
2109 reg_data);
2110 if (ret_val)
2111 return ret_val;
2112
2113 /* Configure Transmit Inter-Packet Gap */
2114 tipg = E1000_READ_REG(hw, TIPG);
2115 tipg &= ~E1000_TIPG_IPGT_MASK;
2116 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
2117 E1000_WRITE_REG(hw, TIPG, tipg);
2118
2119 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
2120
2121 if (ret_val)
2122 return ret_val;
2123
2124 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2125 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
2126
2127 return ret_val;
2128 }
2129
2130 /******************************************************************************
2131 * Configures PHY autoneg and flow control advertisement settings
2132 *
2133 * hw - Struct containing variables accessed by shared code
2134 ******************************************************************************/
2135 int32_t
2136 e1000_phy_setup_autoneg(struct e1000_hw *hw)
2137 {
2138 int32_t ret_val;
2139 uint16_t mii_autoneg_adv_reg;
2140 uint16_t mii_1000t_ctrl_reg;
2141
2142 DEBUGFUNC("e1000_phy_setup_autoneg");
2143
2144 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
2145 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
2146 if (ret_val)
2147 return ret_val;
2148
2149 if (hw->phy_type != e1000_phy_ife) {
2150 /* Read the MII 1000Base-T Control Register (Address 9). */
2151 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
2152 if (ret_val)
2153 return ret_val;
2154 } else
2155 mii_1000t_ctrl_reg=0;
2156
2157 /* Need to parse both autoneg_advertised and fc and set up
2158 * the appropriate PHY registers. First we will parse for
2159 * autoneg_advertised software override. Since we can advertise
2160 * a plethora of combinations, we need to check each bit
2161 * individually.
2162 */
2163
2164 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
2165 * Advertisement Register (Address 4) and the 1000 mb speed bits in
2166 * the 1000Base-T Control Register (Address 9).
2167 */
2168 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
2169 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
2170
2171 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
2172
2173 /* Do we want to advertise 10 Mb Half Duplex? */
2174 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
2175 DEBUGOUT("Advertise 10mb Half duplex\n");
2176 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
2177 }
2178
2179 /* Do we want to advertise 10 Mb Full Duplex? */
2180 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
2181 DEBUGOUT("Advertise 10mb Full duplex\n");
2182 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
2183 }
2184
2185 /* Do we want to advertise 100 Mb Half Duplex? */
2186 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
2187 DEBUGOUT("Advertise 100mb Half duplex\n");
2188 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
2189 }
2190
2191 /* Do we want to advertise 100 Mb Full Duplex? */
2192 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
2193 DEBUGOUT("Advertise 100mb Full duplex\n");
2194 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
2195 }
2196
2197 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
2198 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
2199 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
2200 }
2201
2202 /* Do we want to advertise 1000 Mb Full Duplex? */
2203 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
2204 DEBUGOUT("Advertise 1000mb Full duplex\n");
2205 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
2206 if (hw->phy_type == e1000_phy_ife) {
2207 DEBUGOUT("e1000_phy_ife is a 10/100 PHY. Gigabit speed is not supported.\n");
2208 }
2209 }
2210
2211 /* Check for a software override of the flow control settings, and
2212 * setup the PHY advertisement registers accordingly. If
2213 * auto-negotiation is enabled, then software will have to set the
2214 * "PAUSE" bits to the correct value in the Auto-Negotiation
2215 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
2216 *
2217 * The possible values of the "fc" parameter are:
2218 * 0: Flow control is completely disabled
2219 * 1: Rx flow control is enabled (we can receive pause frames
2220 * but not send pause frames).
2221 * 2: Tx flow control is enabled (we can send pause frames
2222 * but we do not support receiving pause frames).
2223 * 3: Both Rx and TX flow control (symmetric) are enabled.
2224 * other: No software override. The flow control configuration
2225 * in the EEPROM is used.
2226 */
2227 switch (hw->fc) {
2228 case E1000_FC_NONE: /* 0 */
2229 /* Flow control (RX & TX) is completely disabled by a
2230 * software over-ride.
2231 */
2232 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2233 break;
2234 case E1000_FC_RX_PAUSE: /* 1 */
2235 /* RX Flow control is enabled, and TX Flow control is
2236 * disabled, by a software over-ride.
2237 */
2238 /* Since there really isn't a way to advertise that we are
2239 * capable of RX Pause ONLY, we will advertise that we
2240 * support both symmetric and asymmetric RX PAUSE. Later
2241 * (in e1000_config_fc_after_link_up) we will disable the
2242 *hw's ability to send PAUSE frames.
2243 */
2244 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2245 break;
2246 case E1000_FC_TX_PAUSE: /* 2 */
2247 /* TX Flow control is enabled, and RX Flow control is
2248 * disabled, by a software over-ride.
2249 */
2250 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
2251 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
2252 break;
2253 case E1000_FC_FULL: /* 3 */
2254 /* Flow control (both RX and TX) is enabled by a software
2255 * over-ride.
2256 */
2257 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2258 break;
2259 default:
2260 DEBUGOUT("Flow control param set incorrectly\n");
2261 return -E1000_ERR_CONFIG;
2262 }
2263
2264 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
2265 if (ret_val)
2266 return ret_val;
2267
2268 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
2269
2270 if (hw->phy_type != e1000_phy_ife) {
2271 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
2272 if (ret_val)
2273 return ret_val;
2274 }
2275
2276 return E1000_SUCCESS;
2277 }
2278
2279 /******************************************************************************
2280 * Force PHY speed and duplex settings to hw->forced_speed_duplex
2281 *
2282 * hw - Struct containing variables accessed by shared code
2283 ******************************************************************************/
2284 static int32_t
2285 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2286 {
2287 uint32_t ctrl;
2288 int32_t ret_val;
2289 uint16_t mii_ctrl_reg;
2290 uint16_t mii_status_reg;
2291 uint16_t phy_data;
2292 uint16_t i;
2293
2294 DEBUGFUNC("e1000_phy_force_speed_duplex");
2295
2296 /* Turn off Flow control if we are forcing speed and duplex. */
2297 hw->fc = E1000_FC_NONE;
2298
2299 DEBUGOUT1("hw->fc = %d\n", hw->fc);
2300
2301 /* Read the Device Control Register. */
2302 ctrl = E1000_READ_REG(hw, CTRL);
2303
2304 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
2305 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2306 ctrl &= ~(DEVICE_SPEED_MASK);
2307
2308 /* Clear the Auto Speed Detect Enable bit. */
2309 ctrl &= ~E1000_CTRL_ASDE;
2310
2311 /* Read the MII Control Register. */
2312 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
2313 if (ret_val)
2314 return ret_val;
2315
2316 /* We need to disable autoneg in order to force link and duplex. */
2317
2318 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
2319
2320 /* Are we forcing Full or Half Duplex? */
2321 if (hw->forced_speed_duplex == e1000_100_full ||
2322 hw->forced_speed_duplex == e1000_10_full) {
2323 /* We want to force full duplex so we SET the full duplex bits in the
2324 * Device and MII Control Registers.
2325 */
2326 ctrl |= E1000_CTRL_FD;
2327 mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
2328 DEBUGOUT("Full Duplex\n");
2329 } else {
2330 /* We want to force half duplex so we CLEAR the full duplex bits in
2331 * the Device and MII Control Registers.
2332 */
2333 ctrl &= ~E1000_CTRL_FD;
2334 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
2335 DEBUGOUT("Half Duplex\n");
2336 }
2337
2338 /* Are we forcing 100Mbps??? */
2339 if (hw->forced_speed_duplex == e1000_100_full ||
2340 hw->forced_speed_duplex == e1000_100_half) {
2341 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
2342 ctrl |= E1000_CTRL_SPD_100;
2343 mii_ctrl_reg |= MII_CR_SPEED_100;
2344 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
2345 DEBUGOUT("Forcing 100mb ");
2346 } else {
2347 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
2348 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2349 mii_ctrl_reg |= MII_CR_SPEED_10;
2350 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
2351 DEBUGOUT("Forcing 10mb ");
2352 }
2353
2354 e1000_config_collision_dist(hw);
2355
2356 /* Write the configured values back to the Device Control Reg. */
2357 E1000_WRITE_REG(hw, CTRL, ctrl);
2358
2359 if ((hw->phy_type == e1000_phy_m88) ||
2360 (hw->phy_type == e1000_phy_gg82563)) {
2361 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2362 if (ret_val)
2363 return ret_val;
2364
2365 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
2366 * forced whenever speed are duplex are forced.
2367 */
2368 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
2369 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2370 if (ret_val)
2371 return ret_val;
2372
2373 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
2374
2375 /* Need to reset the PHY or these changes will be ignored */
2376 mii_ctrl_reg |= MII_CR_RESET;
2377 /* Disable MDI-X support for 10/100 */
2378 } else if (hw->phy_type == e1000_phy_ife) {
2379 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
2380 if (ret_val)
2381 return ret_val;
2382
2383 phy_data &= ~IFE_PMC_AUTO_MDIX;
2384 phy_data &= ~IFE_PMC_FORCE_MDIX;
2385
2386 ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data);
2387 if (ret_val)
2388 return ret_val;
2389 } else {
2390 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
2391 * forced whenever speed or duplex are forced.
2392 */
2393 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2394 if (ret_val)
2395 return ret_val;
2396
2397 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2398 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2399
2400 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2401 if (ret_val)
2402 return ret_val;
2403 }
2404
2405 /* Write back the modified PHY MII control register. */
2406 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
2407 if (ret_val)
2408 return ret_val;
2409
2410 udelay(1);
2411
2412 /* The wait_autoneg_complete flag may be a little misleading here.
2413 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
2414 * But we do want to delay for a period while forcing only so we
2415 * don't generate false No Link messages. So we will wait here
2416 * only if the user has set wait_autoneg_complete to 1, which is
2417 * the default.
2418 */
2419 if (hw->wait_autoneg_complete) {
2420 /* We will wait for autoneg to complete. */
2421 DEBUGOUT("Waiting for forced speed/duplex link.\n");
2422 mii_status_reg = 0;
2423
2424 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2425 for (i = PHY_FORCE_TIME; i > 0; i--) {
2426 /* Read the MII Status Register and wait for Auto-Neg Complete bit
2427 * to be set.
2428 */
2429 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2430 if (ret_val)
2431 return ret_val;
2432
2433 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2434 if (ret_val)
2435 return ret_val;
2436
2437 if (mii_status_reg & MII_SR_LINK_STATUS) break;
2438 msleep(100);
2439 }
2440 if ((i == 0) &&
2441 ((hw->phy_type == e1000_phy_m88) ||
2442 (hw->phy_type == e1000_phy_gg82563))) {
2443 /* We didn't get link. Reset the DSP and wait again for link. */
2444 ret_val = e1000_phy_reset_dsp(hw);
2445 if (ret_val) {
2446 DEBUGOUT("Error Resetting PHY DSP\n");
2447 return ret_val;
2448 }
2449 }
2450 /* This loop will early-out if the link condition has been met. */
2451 for (i = PHY_FORCE_TIME; i > 0; i--) {
2452 if (mii_status_reg & MII_SR_LINK_STATUS) break;
2453 msleep(100);
2454 /* Read the MII Status Register and wait for Auto-Neg Complete bit
2455 * to be set.
2456 */
2457 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2458 if (ret_val)
2459 return ret_val;
2460
2461 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2462 if (ret_val)
2463 return ret_val;
2464 }
2465 }
2466
2467 if (hw->phy_type == e1000_phy_m88) {
2468 /* Because we reset the PHY above, we need to re-force TX_CLK in the
2469 * Extended PHY Specific Control Register to 25MHz clock. This value
2470 * defaults back to a 2.5MHz clock when the PHY is reset.
2471 */
2472 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
2473 if (ret_val)
2474 return ret_val;
2475
2476 phy_data |= M88E1000_EPSCR_TX_CLK_25;
2477 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2478 if (ret_val)
2479 return ret_val;
2480
2481 /* In addition, because of the s/w reset above, we need to enable CRS on
2482 * TX. This must be set for both full and half duplex operation.
2483 */
2484 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2485 if (ret_val)
2486 return ret_val;
2487
2488 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2489 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2490 if (ret_val)
2491 return ret_val;
2492
2493 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2494 (!hw->autoneg) && (hw->forced_speed_duplex == e1000_10_full ||
2495 hw->forced_speed_duplex == e1000_10_half)) {
2496 ret_val = e1000_polarity_reversal_workaround(hw);
2497 if (ret_val)
2498 return ret_val;
2499 }
2500 } else if (hw->phy_type == e1000_phy_gg82563) {
2501 /* The TX_CLK of the Extended PHY Specific Control Register defaults
2502 * to 2.5MHz on a reset. We need to re-force it back to 25MHz, if
2503 * we're not in a forced 10/duplex configuration. */
2504 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2505 if (ret_val)
2506 return ret_val;
2507
2508 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
2509 if ((hw->forced_speed_duplex == e1000_10_full) ||
2510 (hw->forced_speed_duplex == e1000_10_half))
2511 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ;
2512 else
2513 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ;
2514
2515 /* Also due to the reset, we need to enable CRS on Tx. */
2516 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2517
2518 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2519 if (ret_val)
2520 return ret_val;
2521 }
2522 return E1000_SUCCESS;
2523 }
2524
2525 /******************************************************************************
2526 * Sets the collision distance in the Transmit Control register
2527 *
2528 * hw - Struct containing variables accessed by shared code
2529 *
2530 * Link should have been established previously. Reads the speed and duplex
2531 * information from the Device Status register.
2532 ******************************************************************************/
2533 void
2534 e1000_config_collision_dist(struct e1000_hw *hw)
2535 {
2536 uint32_t tctl, coll_dist;
2537
2538 DEBUGFUNC("e1000_config_collision_dist");
2539
2540 if (hw->mac_type < e1000_82543)
2541 coll_dist = E1000_COLLISION_DISTANCE_82542;
2542 else
2543 coll_dist = E1000_COLLISION_DISTANCE;
2544
2545 tctl = E1000_READ_REG(hw, TCTL);
2546
2547 tctl &= ~E1000_TCTL_COLD;
2548 tctl |= coll_dist << E1000_COLD_SHIFT;
2549
2550 E1000_WRITE_REG(hw, TCTL, tctl);
2551 E1000_WRITE_FLUSH(hw);
2552 }
2553
2554 /******************************************************************************
2555 * Sets MAC speed and duplex settings to reflect the those in the PHY
2556 *
2557 * hw - Struct containing variables accessed by shared code
2558 * mii_reg - data to write to the MII control register
2559 *
2560 * The contents of the PHY register containing the needed information need to
2561 * be passed in.
2562 ******************************************************************************/
2563 static int32_t
2564 e1000_config_mac_to_phy(struct e1000_hw *hw)
2565 {
2566 uint32_t ctrl;
2567 int32_t ret_val;
2568 uint16_t phy_data;
2569
2570 DEBUGFUNC("e1000_config_mac_to_phy");
2571
2572 /* 82544 or newer MAC, Auto Speed Detection takes care of
2573 * MAC speed/duplex configuration.*/
2574 if (hw->mac_type >= e1000_82544)
2575 return E1000_SUCCESS;
2576
2577 /* Read the Device Control Register and set the bits to Force Speed
2578 * and Duplex.
2579 */
2580 ctrl = E1000_READ_REG(hw, CTRL);
2581 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2582 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
2583
2584 /* Set up duplex in the Device Control and Transmit Control
2585 * registers depending on negotiated values.
2586 */
2587 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2588 if (ret_val)
2589 return ret_val;
2590
2591 if (phy_data & M88E1000_PSSR_DPLX)
2592 ctrl |= E1000_CTRL_FD;
2593 else
2594 ctrl &= ~E1000_CTRL_FD;
2595
2596 e1000_config_collision_dist(hw);
2597
2598 /* Set up speed in the Device Control register depending on
2599 * negotiated values.
2600 */
2601 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
2602 ctrl |= E1000_CTRL_SPD_1000;
2603 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
2604 ctrl |= E1000_CTRL_SPD_100;
2605
2606 /* Write the configured values back to the Device Control Reg. */
2607 E1000_WRITE_REG(hw, CTRL, ctrl);
2608 return E1000_SUCCESS;
2609 }
2610
2611 /******************************************************************************
2612 * Forces the MAC's flow control settings.
2613 *
2614 * hw - Struct containing variables accessed by shared code
2615 *
2616 * Sets the TFCE and RFCE bits in the device control register to reflect
2617 * the adapter settings. TFCE and RFCE need to be explicitly set by
2618 * software when a Copper PHY is used because autonegotiation is managed
2619 * by the PHY rather than the MAC. Software must also configure these
2620 * bits when link is forced on a fiber connection.
2621 *****************************************************************************/
2622 int32_t
2623 e1000_force_mac_fc(struct e1000_hw *hw)
2624 {
2625 uint32_t ctrl;
2626
2627 DEBUGFUNC("e1000_force_mac_fc");
2628
2629 /* Get the current configuration of the Device Control Register */
2630 ctrl = E1000_READ_REG(hw, CTRL);
2631
2632 /* Because we didn't get link via the internal auto-negotiation
2633 * mechanism (we either forced link or we got link via PHY
2634 * auto-neg), we have to manually enable/disable transmit an
2635 * receive flow control.
2636 *
2637 * The "Case" statement below enables/disable flow control
2638 * according to the "hw->fc" parameter.
2639 *
2640 * The possible values of the "fc" parameter are:
2641 * 0: Flow control is completely disabled
2642 * 1: Rx flow control is enabled (we can receive pause
2643 * frames but not send pause frames).
2644 * 2: Tx flow control is enabled (we can send pause frames
2645 * frames but we do not receive pause frames).
2646 * 3: Both Rx and TX flow control (symmetric) is enabled.
2647 * other: No other values should be possible at this point.
2648 */
2649
2650 switch (hw->fc) {
2651 case E1000_FC_NONE:
2652 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
2653 break;
2654 case E1000_FC_RX_PAUSE:
2655 ctrl &= (~E1000_CTRL_TFCE);
2656 ctrl |= E1000_CTRL_RFCE;
2657 break;
2658 case E1000_FC_TX_PAUSE:
2659 ctrl &= (~E1000_CTRL_RFCE);
2660 ctrl |= E1000_CTRL_TFCE;
2661 break;
2662 case E1000_FC_FULL:
2663 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
2664 break;
2665 default:
2666 DEBUGOUT("Flow control param set incorrectly\n");
2667 return -E1000_ERR_CONFIG;
2668 }
2669
2670 /* Disable TX Flow Control for 82542 (rev 2.0) */
2671 if (hw->mac_type == e1000_82542_rev2_0)
2672 ctrl &= (~E1000_CTRL_TFCE);
2673
2674 E1000_WRITE_REG(hw, CTRL, ctrl);
2675 return E1000_SUCCESS;
2676 }
2677
2678 /******************************************************************************
2679 * Configures flow control settings after link is established
2680 *
2681 * hw - Struct containing variables accessed by shared code
2682 *
2683 * Should be called immediately after a valid link has been established.
2684 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
2685 * and autonegotiation is enabled, the MAC flow control settings will be set
2686 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
2687 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
2688 *****************************************************************************/
2689 static int32_t
2690 e1000_config_fc_after_link_up(struct e1000_hw *hw)
2691 {
2692 int32_t ret_val;
2693 uint16_t mii_status_reg;
2694 uint16_t mii_nway_adv_reg;
2695 uint16_t mii_nway_lp_ability_reg;
2696 uint16_t speed;
2697 uint16_t duplex;
2698
2699 DEBUGFUNC("e1000_config_fc_after_link_up");
2700
2701 /* Check for the case where we have fiber media and auto-neg failed
2702 * so we had to force link. In this case, we need to force the
2703 * configuration of the MAC to match the "fc" parameter.
2704 */
2705 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
2706 ((hw->media_type == e1000_media_type_internal_serdes) &&
2707 (hw->autoneg_failed)) ||
2708 ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) {
2709 ret_val = e1000_force_mac_fc(hw);
2710 if (ret_val) {
2711 DEBUGOUT("Error forcing flow control settings\n");
2712 return ret_val;
2713 }
2714 }
2715
2716 /* Check for the case where we have copper media and auto-neg is
2717 * enabled. In this case, we need to check and see if Auto-Neg
2718 * has completed, and if so, how the PHY and link partner has
2719 * flow control configured.
2720 */
2721 if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
2722 /* Read the MII Status Register and check to see if AutoNeg
2723 * has completed. We read this twice because this reg has
2724 * some "sticky" (latched) bits.
2725 */
2726 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2727 if (ret_val)
2728 return ret_val;
2729 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2730 if (ret_val)
2731 return ret_val;
2732
2733 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
2734 /* The AutoNeg process has completed, so we now need to
2735 * read both the Auto Negotiation Advertisement Register
2736 * (Address 4) and the Auto_Negotiation Base Page Ability
2737 * Register (Address 5) to determine how flow control was
2738 * negotiated.
2739 */
2740 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
2741 &mii_nway_adv_reg);
2742 if (ret_val)
2743 return ret_val;
2744 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2745 &mii_nway_lp_ability_reg);
2746 if (ret_val)
2747 return ret_val;
2748
2749 /* Two bits in the Auto Negotiation Advertisement Register
2750 * (Address 4) and two bits in the Auto Negotiation Base
2751 * Page Ability Register (Address 5) determine flow control
2752 * for both the PHY and the link partner. The following
2753 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
2754 * 1999, describes these PAUSE resolution bits and how flow
2755 * control is determined based upon these settings.
2756 * NOTE: DC = Don't Care
2757 *
2758 * LOCAL DEVICE | LINK PARTNER
2759 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
2760 *-------|---------|-------|---------|--------------------
2761 * 0 | 0 | DC | DC | E1000_FC_NONE
2762 * 0 | 1 | 0 | DC | E1000_FC_NONE
2763 * 0 | 1 | 1 | 0 | E1000_FC_NONE
2764 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
2765 * 1 | 0 | 0 | DC | E1000_FC_NONE
2766 * 1 | DC | 1 | DC | E1000_FC_FULL
2767 * 1 | 1 | 0 | 0 | E1000_FC_NONE
2768 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
2769 *
2770 */
2771 /* Are both PAUSE bits set to 1? If so, this implies
2772 * Symmetric Flow Control is enabled at both ends. The
2773 * ASM_DIR bits are irrelevant per the spec.
2774 *
2775 * For Symmetric Flow Control:
2776 *
2777 * LOCAL DEVICE | LINK PARTNER
2778 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2779 *-------|---------|-------|---------|--------------------
2780 * 1 | DC | 1 | DC | E1000_FC_FULL
2781 *
2782 */
2783 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2784 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
2785 /* Now we need to check if the user selected RX ONLY
2786 * of pause frames. In this case, we had to advertise
2787 * FULL flow control because we could not advertise RX
2788 * ONLY. Hence, we must now check to see if we need to
2789 * turn OFF the TRANSMISSION of PAUSE frames.
2790 */
2791 if (hw->original_fc == E1000_FC_FULL) {
2792 hw->fc = E1000_FC_FULL;
2793 DEBUGOUT("Flow Control = FULL.\n");
2794 } else {
2795 hw->fc = E1000_FC_RX_PAUSE;
2796 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2797 }
2798 }
2799 /* For receiving PAUSE frames ONLY.
2800 *
2801 * LOCAL DEVICE | LINK PARTNER
2802 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2803 *-------|---------|-------|---------|--------------------
2804 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
2805 *
2806 */
2807 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2808 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2809 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2810 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2811 hw->fc = E1000_FC_TX_PAUSE;
2812 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2813 }
2814 /* For transmitting PAUSE frames ONLY.
2815 *
2816 * LOCAL DEVICE | LINK PARTNER
2817 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2818 *-------|---------|-------|---------|--------------------
2819 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
2820 *
2821 */
2822 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2823 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2824 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2825 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2826 hw->fc = E1000_FC_RX_PAUSE;
2827 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2828 }
2829 /* Per the IEEE spec, at this point flow control should be
2830 * disabled. However, we want to consider that we could
2831 * be connected to a legacy switch that doesn't advertise
2832 * desired flow control, but can be forced on the link
2833 * partner. So if we advertised no flow control, that is
2834 * what we will resolve to. If we advertised some kind of
2835 * receive capability (Rx Pause Only or Full Flow Control)
2836 * and the link partner advertised none, we will configure
2837 * ourselves to enable Rx Flow Control only. We can do
2838 * this safely for two reasons: If the link partner really
2839 * didn't want flow control enabled, and we enable Rx, no
2840 * harm done since we won't be receiving any PAUSE frames
2841 * anyway. If the intent on the link partner was to have
2842 * flow control enabled, then by us enabling RX only, we
2843 * can at least receive pause frames and process them.
2844 * This is a good idea because in most cases, since we are
2845 * predominantly a server NIC, more times than not we will
2846 * be asked to delay transmission of packets than asking
2847 * our link partner to pause transmission of frames.
2848 */
2849 else if ((hw->original_fc == E1000_FC_NONE ||
2850 hw->original_fc == E1000_FC_TX_PAUSE) ||
2851 hw->fc_strict_ieee) {
2852 hw->fc = E1000_FC_NONE;
2853 DEBUGOUT("Flow Control = NONE.\n");
2854 } else {
2855 hw->fc = E1000_FC_RX_PAUSE;
2856 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2857 }
2858
2859 /* Now we need to do one last check... If we auto-
2860 * negotiated to HALF DUPLEX, flow control should not be
2861 * enabled per IEEE 802.3 spec.
2862 */
2863 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
2864 if (ret_val) {
2865 DEBUGOUT("Error getting link speed and duplex\n");
2866 return ret_val;
2867 }
2868
2869 if (duplex == HALF_DUPLEX)
2870 hw->fc = E1000_FC_NONE;
2871
2872 /* Now we call a subroutine to actually force the MAC
2873 * controller to use the correct flow control settings.
2874 */
2875 ret_val = e1000_force_mac_fc(hw);
2876 if (ret_val) {
2877 DEBUGOUT("Error forcing flow control settings\n");
2878 return ret_val;
2879 }
2880 } else {
2881 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
2882 }
2883 }
2884 return E1000_SUCCESS;
2885 }
2886
2887 /******************************************************************************
2888 * Checks to see if the link status of the hardware has changed.
2889 *
2890 * hw - Struct containing variables accessed by shared code
2891 *
2892 * Called by any function that needs to check the link status of the adapter.
2893 *****************************************************************************/
2894 int32_t
2895 e1000_check_for_link(struct e1000_hw *hw)
2896 {
2897 uint32_t rxcw = 0;
2898 uint32_t ctrl;
2899 uint32_t status;
2900 uint32_t rctl;
2901 uint32_t icr;
2902 uint32_t signal = 0;
2903 int32_t ret_val;
2904 uint16_t phy_data;
2905
2906 DEBUGFUNC("e1000_check_for_link");
2907
2908 ctrl = E1000_READ_REG(hw, CTRL);
2909 status = E1000_READ_REG(hw, STATUS);
2910
2911 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
2912 * set when the optics detect a signal. On older adapters, it will be
2913 * cleared when there is a signal. This applies to fiber media only.
2914 */
2915 if ((hw->media_type == e1000_media_type_fiber) ||
2916 (hw->media_type == e1000_media_type_internal_serdes)) {
2917 rxcw = E1000_READ_REG(hw, RXCW);
2918
2919 if (hw->media_type == e1000_media_type_fiber) {
2920 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
2921 if (status & E1000_STATUS_LU)
2922 hw->get_link_status = FALSE;
2923 }
2924 }
2925
2926 /* If we have a copper PHY then we only want to go out to the PHY
2927 * registers to see if Auto-Neg has completed and/or if our link
2928 * status has changed. The get_link_status flag will be set if we
2929 * receive a Link Status Change interrupt or we have Rx Sequence
2930 * Errors.
2931 */
2932 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
2933 /* First we want to see if the MII Status Register reports
2934 * link. If so, then we want to get the current speed/duplex
2935 * of the PHY.
2936 * Read the register twice since the link bit is sticky.
2937 */
2938 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2939 if (ret_val)
2940 return ret_val;
2941 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2942 if (ret_val)
2943 return ret_val;
2944
2945 if (phy_data & MII_SR_LINK_STATUS) {
2946 hw->get_link_status = FALSE;
2947 /* Check if there was DownShift, must be checked immediately after
2948 * link-up */
2949 e1000_check_downshift(hw);
2950
2951 /* If we are on 82544 or 82543 silicon and speed/duplex
2952 * are forced to 10H or 10F, then we will implement the polarity
2953 * reversal workaround. We disable interrupts first, and upon
2954 * returning, place the devices interrupt state to its previous
2955 * value except for the link status change interrupt which will
2956 * happen due to the execution of this workaround.
2957 */
2958
2959 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2960 (!hw->autoneg) &&
2961 (hw->forced_speed_duplex == e1000_10_full ||
2962 hw->forced_speed_duplex == e1000_10_half)) {
2963 E1000_WRITE_REG(hw, IMC, 0xffffffff);
2964 ret_val = e1000_polarity_reversal_workaround(hw);
2965 icr = E1000_READ_REG(hw, ICR);
2966 E1000_WRITE_REG(hw, ICS, (icr & ~E1000_ICS_LSC));
2967 E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK);
2968 }
2969
2970 } else {
2971 /* No link detected */
2972 e1000_config_dsp_after_link_change(hw, FALSE);
2973 return 0;
2974 }
2975
2976 /* If we are forcing speed/duplex, then we simply return since
2977 * we have already determined whether we have link or not.
2978 */
2979 if (!hw->autoneg) return -E1000_ERR_CONFIG;
2980
2981 /* optimize the dsp settings for the igp phy */
2982 e1000_config_dsp_after_link_change(hw, TRUE);
2983
2984 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
2985 * have Si on board that is 82544 or newer, Auto
2986 * Speed Detection takes care of MAC speed/duplex
2987 * configuration. So we only need to configure Collision
2988 * Distance in the MAC. Otherwise, we need to force
2989 * speed/duplex on the MAC to the current PHY speed/duplex
2990 * settings.
2991 */
2992 if (hw->mac_type >= e1000_82544)
2993 e1000_config_collision_dist(hw);
2994 else {
2995 ret_val = e1000_config_mac_to_phy(hw);
2996 if (ret_val) {
2997 DEBUGOUT("Error configuring MAC to PHY settings\n");
2998 return ret_val;
2999 }
3000 }
3001
3002 /* Configure Flow Control now that Auto-Neg has completed. First, we
3003 * need to restore the desired flow control settings because we may
3004 * have had to re-autoneg with a different link partner.
3005 */
3006 ret_val = e1000_config_fc_after_link_up(hw);
3007 if (ret_val) {
3008 DEBUGOUT("Error configuring flow control\n");
3009 return ret_val;
3010 }
3011
3012 /* At this point we know that we are on copper and we have
3013 * auto-negotiated link. These are conditions for checking the link
3014 * partner capability register. We use the link speed to determine if
3015 * TBI compatibility needs to be turned on or off. If the link is not
3016 * at gigabit speed, then TBI compatibility is not needed. If we are
3017 * at gigabit speed, we turn on TBI compatibility.
3018 */
3019 if (hw->tbi_compatibility_en) {
3020 uint16_t speed, duplex;
3021 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
3022 if (ret_val) {
3023 DEBUGOUT("Error getting link speed and duplex\n");
3024 return ret_val;
3025 }
3026 if (speed != SPEED_1000) {
3027 /* If link speed is not set to gigabit speed, we do not need
3028 * to enable TBI compatibility.
3029 */
3030 if (hw->tbi_compatibility_on) {
3031 /* If we previously were in the mode, turn it off. */
3032 rctl = E1000_READ_REG(hw, RCTL);
3033 rctl &= ~E1000_RCTL_SBP;
3034 E1000_WRITE_REG(hw, RCTL, rctl);
3035 hw->tbi_compatibility_on = FALSE;
3036 }
3037 } else {
3038 /* If TBI compatibility is was previously off, turn it on. For
3039 * compatibility with a TBI link partner, we will store bad
3040 * packets. Some frames have an additional byte on the end and
3041 * will look like CRC errors to to the hardware.
3042 */
3043 if (!hw->tbi_compatibility_on) {
3044 hw->tbi_compatibility_on = TRUE;
3045 rctl = E1000_READ_REG(hw, RCTL);
3046 rctl |= E1000_RCTL_SBP;
3047 E1000_WRITE_REG(hw, RCTL, rctl);
3048 }
3049 }
3050 }
3051 }
3052 /* If we don't have link (auto-negotiation failed or link partner cannot
3053 * auto-negotiate), the cable is plugged in (we have signal), and our
3054 * link partner is not trying to auto-negotiate with us (we are receiving
3055 * idles or data), we need to force link up. We also need to give
3056 * auto-negotiation time to complete, in case the cable was just plugged
3057 * in. The autoneg_failed flag does this.
3058 */
3059 else if ((((hw->media_type == e1000_media_type_fiber) &&
3060 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
3061 (hw->media_type == e1000_media_type_internal_serdes)) &&
3062 (!(status & E1000_STATUS_LU)) &&
3063 (!(rxcw & E1000_RXCW_C))) {
3064 if (hw->autoneg_failed == 0) {
3065 hw->autoneg_failed = 1;
3066 return 0;
3067 }
3068 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
3069
3070 /* Disable auto-negotiation in the TXCW register */
3071 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
3072
3073 /* Force link-up and also force full-duplex. */
3074 ctrl = E1000_READ_REG(hw, CTRL);
3075 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
3076 E1000_WRITE_REG(hw, CTRL, ctrl);
3077
3078 /* Configure Flow Control after forcing link up. */
3079 ret_val = e1000_config_fc_after_link_up(hw);
3080 if (ret_val) {
3081 DEBUGOUT("Error configuring flow control\n");
3082 return ret_val;
3083 }
3084 }
3085 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
3086 * auto-negotiation in the TXCW register and disable forced link in the
3087 * Device Control register in an attempt to auto-negotiate with our link
3088 * partner.
3089 */
3090 else if (((hw->media_type == e1000_media_type_fiber) ||
3091 (hw->media_type == e1000_media_type_internal_serdes)) &&
3092 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
3093 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
3094 E1000_WRITE_REG(hw, TXCW, hw->txcw);
3095 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
3096
3097 hw->serdes_link_down = FALSE;
3098 }
3099 /* If we force link for non-auto-negotiation switch, check link status
3100 * based on MAC synchronization for internal serdes media type.
3101 */
3102 else if ((hw->media_type == e1000_media_type_internal_serdes) &&
3103 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
3104 /* SYNCH bit and IV bit are sticky. */
3105 udelay(10);
3106 if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
3107 if (!(rxcw & E1000_RXCW_IV)) {
3108 hw->serdes_link_down = FALSE;
3109 DEBUGOUT("SERDES: Link is up.\n");
3110 }
3111 } else {
3112 hw->serdes_link_down = TRUE;
3113 DEBUGOUT("SERDES: Link is down.\n");
3114 }
3115 }
3116 if ((hw->media_type == e1000_media_type_internal_serdes) &&
3117 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
3118 hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS));
3119 }
3120 return E1000_SUCCESS;
3121 }
3122
3123 /******************************************************************************
3124 * Detects the current speed and duplex settings of the hardware.
3125 *
3126 * hw - Struct containing variables accessed by shared code
3127 * speed - Speed of the connection
3128 * duplex - Duplex setting of the connection
3129 *****************************************************************************/
3130 int32_t
3131 e1000_get_speed_and_duplex(struct e1000_hw *hw,
3132 uint16_t *speed,
3133 uint16_t *duplex)
3134 {
3135 uint32_t status;
3136 int32_t ret_val;
3137 uint16_t phy_data;
3138
3139 DEBUGFUNC("e1000_get_speed_and_duplex");
3140
3141 if (hw->mac_type >= e1000_82543) {
3142 status = E1000_READ_REG(hw, STATUS);
3143 if (status & E1000_STATUS_SPEED_1000) {
3144 *speed = SPEED_1000;
3145 DEBUGOUT("1000 Mbs, ");
3146 } else if (status & E1000_STATUS_SPEED_100) {
3147 *speed = SPEED_100;
3148 DEBUGOUT("100 Mbs, ");
3149 } else {
3150 *speed = SPEED_10;
3151 DEBUGOUT("10 Mbs, ");
3152 }
3153
3154 if (status & E1000_STATUS_FD) {
3155 *duplex = FULL_DUPLEX;
3156 DEBUGOUT("Full Duplex\n");
3157 } else {
3158 *duplex = HALF_DUPLEX;
3159 DEBUGOUT(" Half Duplex\n");
3160 }
3161 } else {
3162 DEBUGOUT("1000 Mbs, Full Duplex\n");
3163 *speed = SPEED_1000;
3164 *duplex = FULL_DUPLEX;
3165 }
3166
3167 /* IGP01 PHY may advertise full duplex operation after speed downgrade even
3168 * if it is operating at half duplex. Here we set the duplex settings to
3169 * match the duplex in the link partner's capabilities.
3170 */
3171 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
3172 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
3173 if (ret_val)
3174 return ret_val;
3175
3176 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
3177 *duplex = HALF_DUPLEX;
3178 else {
3179 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
3180 if (ret_val)
3181 return ret_val;
3182 if ((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
3183 (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
3184 *duplex = HALF_DUPLEX;
3185 }
3186 }
3187
3188 if ((hw->mac_type == e1000_80003es2lan) &&
3189 (hw->media_type == e1000_media_type_copper)) {
3190 if (*speed == SPEED_1000)
3191 ret_val = e1000_configure_kmrn_for_1000(hw);
3192 else
3193 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
3194 if (ret_val)
3195 return ret_val;
3196 }
3197
3198 if ((hw->phy_type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
3199 ret_val = e1000_kumeran_lock_loss_workaround(hw);
3200 if (ret_val)
3201 return ret_val;
3202 }
3203
3204 return E1000_SUCCESS;
3205 }
3206
3207 /******************************************************************************
3208 * Blocks until autoneg completes or times out (~4.5 seconds)
3209 *
3210 * hw - Struct containing variables accessed by shared code
3211 ******************************************************************************/
3212 static int32_t
3213 e1000_wait_autoneg(struct e1000_hw *hw)
3214 {
3215 int32_t ret_val;
3216 uint16_t i;
3217 uint16_t phy_data;
3218
3219 DEBUGFUNC("e1000_wait_autoneg");
3220 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
3221
3222 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
3223 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
3224 /* Read the MII Status Register and wait for Auto-Neg
3225 * Complete bit to be set.
3226 */
3227 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3228 if (ret_val)
3229 return ret_val;
3230 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3231 if (ret_val)
3232 return ret_val;
3233 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
3234 return E1000_SUCCESS;
3235 }
3236 msleep(100);
3237 }
3238 return E1000_SUCCESS;
3239 }
3240
3241 /******************************************************************************
3242 * Raises the Management Data Clock
3243 *
3244 * hw - Struct containing variables accessed by shared code
3245 * ctrl - Device control register's current value
3246 ******************************************************************************/
3247 static void
3248 e1000_raise_mdi_clk(struct e1000_hw *hw,
3249 uint32_t *ctrl)
3250 {
3251 /* Raise the clock input to the Management Data Clock (by setting the MDC
3252 * bit), and then delay 10 microseconds.
3253 */
3254 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
3255 E1000_WRITE_FLUSH(hw);
3256 udelay(10);
3257 }
3258
3259 /******************************************************************************
3260 * Lowers the Management Data Clock
3261 *
3262 * hw - Struct containing variables accessed by shared code
3263 * ctrl - Device control register's current value
3264 ******************************************************************************/
3265 static void
3266 e1000_lower_mdi_clk(struct e1000_hw *hw,
3267 uint32_t *ctrl)
3268 {
3269 /* Lower the clock input to the Management Data Clock (by clearing the MDC
3270 * bit), and then delay 10 microseconds.
3271 */
3272 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
3273 E1000_WRITE_FLUSH(hw);
3274 udelay(10);
3275 }
3276
3277 /******************************************************************************
3278 * Shifts data bits out to the PHY
3279 *
3280 * hw - Struct containing variables accessed by shared code
3281 * data - Data to send out to the PHY
3282 * count - Number of bits to shift out
3283 *
3284 * Bits are shifted out in MSB to LSB order.
3285 ******************************************************************************/
3286 static void
3287 e1000_shift_out_mdi_bits(struct e1000_hw *hw,
3288 uint32_t data,
3289 uint16_t count)
3290 {
3291 uint32_t ctrl;
3292 uint32_t mask;
3293
3294 /* We need to shift "count" number of bits out to the PHY. So, the value
3295 * in the "data" parameter will be shifted out to the PHY one bit at a
3296 * time. In order to do this, "data" must be broken down into bits.
3297 */
3298 mask = 0x01;
3299 mask <<= (count - 1);
3300
3301 ctrl = E1000_READ_REG(hw, CTRL);
3302
3303 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
3304 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
3305
3306 while (mask) {
3307 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
3308 * then raising and lowering the Management Data Clock. A "0" is
3309 * shifted out to the PHY by setting the MDIO bit to "0" and then
3310 * raising and lowering the clock.
3311 */
3312 if (data & mask)
3313 ctrl |= E1000_CTRL_MDIO;
3314 else
3315 ctrl &= ~E1000_CTRL_MDIO;
3316
3317 E1000_WRITE_REG(hw, CTRL, ctrl);
3318 E1000_WRITE_FLUSH(hw);
3319
3320 udelay(10);
3321
3322 e1000_raise_mdi_clk(hw, &ctrl);
3323 e1000_lower_mdi_clk(hw, &ctrl);
3324
3325 mask = mask >> 1;
3326 }
3327 }
3328
3329 /******************************************************************************
3330 * Shifts data bits in from the PHY
3331 *
3332 * hw - Struct containing variables accessed by shared code
3333 *
3334 * Bits are shifted in in MSB to LSB order.
3335 ******************************************************************************/
3336 static uint16_t
3337 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
3338 {
3339 uint32_t ctrl;
3340 uint16_t data = 0;
3341 uint8_t i;
3342
3343 /* In order to read a register from the PHY, we need to shift in a total
3344 * of 18 bits from the PHY. The first two bit (turnaround) times are used
3345 * to avoid contention on the MDIO pin when a read operation is performed.
3346 * These two bits are ignored by us and thrown away. Bits are "shifted in"
3347 * by raising the input to the Management Data Clock (setting the MDC bit),
3348 * and then reading the value of the MDIO bit.
3349 */
3350 ctrl = E1000_READ_REG(hw, CTRL);
3351
3352 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
3353 ctrl &= ~E1000_CTRL_MDIO_DIR;
3354 ctrl &= ~E1000_CTRL_MDIO;
3355
3356 E1000_WRITE_REG(hw, CTRL, ctrl);
3357 E1000_WRITE_FLUSH(hw);
3358
3359 /* Raise and Lower the clock before reading in the data. This accounts for
3360 * the turnaround bits. The first clock occurred when we clocked out the
3361 * last bit of the Register Address.
3362 */
3363 e1000_raise_mdi_clk(hw, &ctrl);
3364 e1000_lower_mdi_clk(hw, &ctrl);
3365
3366 for (data = 0, i = 0; i < 16; i++) {
3367 data = data << 1;
3368 e1000_raise_mdi_clk(hw, &ctrl);
3369 ctrl = E1000_READ_REG(hw, CTRL);
3370 /* Check to see if we shifted in a "1". */
3371 if (ctrl & E1000_CTRL_MDIO)
3372 data |= 1;
3373 e1000_lower_mdi_clk(hw, &ctrl);
3374 }
3375
3376 e1000_raise_mdi_clk(hw, &ctrl);
3377 e1000_lower_mdi_clk(hw, &ctrl);
3378
3379 return data;
3380 }
3381
3382 static int32_t
3383 e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
3384 {
3385 uint32_t swfw_sync = 0;
3386 uint32_t swmask = mask;
3387 uint32_t fwmask = mask << 16;
3388 int32_t timeout = 200;
3389
3390 DEBUGFUNC("e1000_swfw_sync_acquire");
3391
3392 if (hw->swfwhw_semaphore_present)
3393 return e1000_get_software_flag(hw);
3394
3395 if (!hw->swfw_sync_present)
3396 return e1000_get_hw_eeprom_semaphore(hw);
3397
3398 while (timeout) {
3399 if (e1000_get_hw_eeprom_semaphore(hw))
3400 return -E1000_ERR_SWFW_SYNC;
3401
3402 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
3403 if (!(swfw_sync & (fwmask | swmask))) {
3404 break;
3405 }
3406
3407 /* firmware currently using resource (fwmask) */
3408 /* or other software thread currently using resource (swmask) */
3409 e1000_put_hw_eeprom_semaphore(hw);
3410 mdelay(5);
3411 timeout--;
3412 }
3413
3414 if (!timeout) {
3415 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
3416 return -E1000_ERR_SWFW_SYNC;
3417 }
3418
3419 swfw_sync |= swmask;
3420 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
3421
3422 e1000_put_hw_eeprom_semaphore(hw);
3423 return E1000_SUCCESS;
3424 }
3425
3426 static void
3427 e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
3428 {
3429 uint32_t swfw_sync;
3430 uint32_t swmask = mask;
3431
3432 DEBUGFUNC("e1000_swfw_sync_release");
3433
3434 if (hw->swfwhw_semaphore_present) {
3435 e1000_release_software_flag(hw);
3436 return;
3437 }
3438
3439 if (!hw->swfw_sync_present) {
3440 e1000_put_hw_eeprom_semaphore(hw);
3441 return;
3442 }
3443
3444 /* if (e1000_get_hw_eeprom_semaphore(hw))
3445 * return -E1000_ERR_SWFW_SYNC; */
3446 while (e1000_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS);
3447 /* empty */
3448
3449 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
3450 swfw_sync &= ~swmask;
3451 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
3452
3453 e1000_put_hw_eeprom_semaphore(hw);
3454 }
3455
3456 /*****************************************************************************
3457 * Reads the value from a PHY register, if the value is on a specific non zero
3458 * page, sets the page first.
3459 * hw - Struct containing variables accessed by shared code
3460 * reg_addr - address of the PHY register to read
3461 ******************************************************************************/
3462 int32_t
3463 e1000_read_phy_reg(struct e1000_hw *hw,
3464 uint32_t reg_addr,
3465 uint16_t *phy_data)
3466 {
3467 uint32_t ret_val;
3468 uint16_t swfw;
3469
3470 DEBUGFUNC("e1000_read_phy_reg");
3471
3472 if ((hw->mac_type == e1000_80003es2lan) &&
3473 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3474 swfw = E1000_SWFW_PHY1_SM;
3475 } else {
3476 swfw = E1000_SWFW_PHY0_SM;
3477 }
3478 if (e1000_swfw_sync_acquire(hw, swfw))
3479 return -E1000_ERR_SWFW_SYNC;
3480
3481 if ((hw->phy_type == e1000_phy_igp ||
3482 hw->phy_type == e1000_phy_igp_3 ||
3483 hw->phy_type == e1000_phy_igp_2) &&
3484 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3485 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3486 (uint16_t)reg_addr);
3487 if (ret_val) {
3488 e1000_swfw_sync_release(hw, swfw);
3489 return ret_val;
3490 }
3491 } else if (hw->phy_type == e1000_phy_gg82563) {
3492 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
3493 (hw->mac_type == e1000_80003es2lan)) {
3494 /* Select Configuration Page */
3495 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3496 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3497 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3498 } else {
3499 /* Use Alternative Page Select register to access
3500 * registers 30 and 31
3501 */
3502 ret_val = e1000_write_phy_reg_ex(hw,
3503 GG82563_PHY_PAGE_SELECT_ALT,
3504 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3505 }
3506
3507 if (ret_val) {
3508 e1000_swfw_sync_release(hw, swfw);
3509 return ret_val;
3510 }
3511 }
3512 }
3513
3514 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
3515 phy_data);
3516
3517 e1000_swfw_sync_release(hw, swfw);
3518 return ret_val;
3519 }
3520
3521 static int32_t
3522 e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
3523 uint16_t *phy_data)
3524 {
3525 uint32_t i;
3526 uint32_t mdic = 0;
3527 const uint32_t phy_addr = 1;
3528
3529 DEBUGFUNC("e1000_read_phy_reg_ex");
3530
3531 if (reg_addr > MAX_PHY_REG_ADDRESS) {
3532 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3533 return -E1000_ERR_PARAM;
3534 }
3535
3536 if (hw->mac_type > e1000_82543) {
3537 /* Set up Op-code, Phy Address, and register address in the MDI
3538 * Control register. The MAC will take care of interfacing with the
3539 * PHY to retrieve the desired data.
3540 */
3541 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
3542 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3543 (E1000_MDIC_OP_READ));
3544
3545 E1000_WRITE_REG(hw, MDIC, mdic);
3546
3547 /* Poll the ready bit to see if the MDI read completed */
3548 for (i = 0; i < 64; i++) {
3549 udelay(50);
3550 mdic = E1000_READ_REG(hw, MDIC);
3551 if (mdic & E1000_MDIC_READY) break;
3552 }
3553 if (!(mdic & E1000_MDIC_READY)) {
3554 DEBUGOUT("MDI Read did not complete\n");
3555 return -E1000_ERR_PHY;
3556 }
3557 if (mdic & E1000_MDIC_ERROR) {
3558 DEBUGOUT("MDI Error\n");
3559 return -E1000_ERR_PHY;
3560 }
3561 *phy_data = (uint16_t) mdic;
3562 } else {
3563 /* We must first send a preamble through the MDIO pin to signal the
3564 * beginning of an MII instruction. This is done by sending 32
3565 * consecutive "1" bits.
3566 */
3567 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3568
3569 /* Now combine the next few fields that are required for a read
3570 * operation. We use this method instead of calling the
3571 * e1000_shift_out_mdi_bits routine five different times. The format of
3572 * a MII read instruction consists of a shift out of 14 bits and is
3573 * defined as follows:
3574 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
3575 * followed by a shift in of 18 bits. This first two bits shifted in
3576 * are TurnAround bits used to avoid contention on the MDIO pin when a
3577 * READ operation is performed. These two bits are thrown away
3578 * followed by a shift in of 16 bits which contains the desired data.
3579 */
3580 mdic = ((reg_addr) | (phy_addr << 5) |
3581 (PHY_OP_READ << 10) | (PHY_SOF << 12));
3582
3583 e1000_shift_out_mdi_bits(hw, mdic, 14);
3584
3585 /* Now that we've shifted out the read command to the MII, we need to
3586 * "shift in" the 16-bit value (18 total bits) of the requested PHY
3587 * register address.
3588 */
3589 *phy_data = e1000_shift_in_mdi_bits(hw);
3590 }
3591 return E1000_SUCCESS;
3592 }
3593
3594 /******************************************************************************
3595 * Writes a value to a PHY register
3596 *
3597 * hw - Struct containing variables accessed by shared code
3598 * reg_addr - address of the PHY register to write
3599 * data - data to write to the PHY
3600 ******************************************************************************/
3601 int32_t
3602 e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
3603 uint16_t phy_data)
3604 {
3605 uint32_t ret_val;
3606 uint16_t swfw;
3607
3608 DEBUGFUNC("e1000_write_phy_reg");
3609
3610 if ((hw->mac_type == e1000_80003es2lan) &&
3611 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3612 swfw = E1000_SWFW_PHY1_SM;
3613 } else {
3614 swfw = E1000_SWFW_PHY0_SM;
3615 }
3616 if (e1000_swfw_sync_acquire(hw, swfw))
3617 return -E1000_ERR_SWFW_SYNC;
3618
3619 if ((hw->phy_type == e1000_phy_igp ||
3620 hw->phy_type == e1000_phy_igp_3 ||
3621 hw->phy_type == e1000_phy_igp_2) &&
3622 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3623 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3624 (uint16_t)reg_addr);
3625 if (ret_val) {
3626 e1000_swfw_sync_release(hw, swfw);
3627 return ret_val;
3628 }
3629 } else if (hw->phy_type == e1000_phy_gg82563) {
3630 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
3631 (hw->mac_type == e1000_80003es2lan)) {
3632 /* Select Configuration Page */
3633 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3634 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3635 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3636 } else {
3637 /* Use Alternative Page Select register to access
3638 * registers 30 and 31
3639 */
3640 ret_val = e1000_write_phy_reg_ex(hw,
3641 GG82563_PHY_PAGE_SELECT_ALT,
3642 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3643 }
3644
3645 if (ret_val) {
3646 e1000_swfw_sync_release(hw, swfw);
3647 return ret_val;
3648 }
3649 }
3650 }
3651
3652 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
3653 phy_data);
3654
3655 e1000_swfw_sync_release(hw, swfw);
3656 return ret_val;
3657 }
3658
3659 static int32_t
3660 e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
3661 uint16_t phy_data)
3662 {
3663 uint32_t i;
3664 uint32_t mdic = 0;
3665 const uint32_t phy_addr = 1;
3666
3667 DEBUGFUNC("e1000_write_phy_reg_ex");
3668
3669 if (reg_addr > MAX_PHY_REG_ADDRESS) {
3670 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3671 return -E1000_ERR_PARAM;
3672 }
3673
3674 if (hw->mac_type > e1000_82543) {
3675 /* Set up Op-code, Phy Address, register address, and data intended
3676 * for the PHY register in the MDI Control register. The MAC will take
3677 * care of interfacing with the PHY to send the desired data.
3678 */
3679 mdic = (((uint32_t) phy_data) |
3680 (reg_addr << E1000_MDIC_REG_SHIFT) |
3681 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3682 (E1000_MDIC_OP_WRITE));
3683
3684 E1000_WRITE_REG(hw, MDIC, mdic);
3685
3686 /* Poll the ready bit to see if the MDI read completed */
3687 for (i = 0; i < 641; i++) {
3688 udelay(5);
3689 mdic = E1000_READ_REG(hw, MDIC);
3690 if (mdic & E1000_MDIC_READY) break;
3691 }
3692 if (!(mdic & E1000_MDIC_READY)) {
3693 DEBUGOUT("MDI Write did not complete\n");
3694 return -E1000_ERR_PHY;
3695 }
3696 } else {
3697 /* We'll need to use the SW defined pins to shift the write command
3698 * out to the PHY. We first send a preamble to the PHY to signal the
3699 * beginning of the MII instruction. This is done by sending 32
3700 * consecutive "1" bits.
3701 */
3702 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3703
3704 /* Now combine the remaining required fields that will indicate a
3705 * write operation. We use this method instead of calling the
3706 * e1000_shift_out_mdi_bits routine for each field in the command. The
3707 * format of a MII write instruction is as follows:
3708 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
3709 */
3710 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
3711 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
3712 mdic <<= 16;
3713 mdic |= (uint32_t) phy_data;
3714
3715 e1000_shift_out_mdi_bits(hw, mdic, 32);
3716 }
3717
3718 return E1000_SUCCESS;
3719 }
3720
3721 static int32_t
3722 e1000_read_kmrn_reg(struct e1000_hw *hw,
3723 uint32_t reg_addr,
3724 uint16_t *data)
3725 {
3726 uint32_t reg_val;
3727 uint16_t swfw;
3728 DEBUGFUNC("e1000_read_kmrn_reg");
3729
3730 if ((hw->mac_type == e1000_80003es2lan) &&
3731 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3732 swfw = E1000_SWFW_PHY1_SM;
3733 } else {
3734 swfw = E1000_SWFW_PHY0_SM;
3735 }
3736 if (e1000_swfw_sync_acquire(hw, swfw))
3737 return -E1000_ERR_SWFW_SYNC;
3738
3739 /* Write register address */
3740 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3741 E1000_KUMCTRLSTA_OFFSET) |
3742 E1000_KUMCTRLSTA_REN;
3743 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
3744 udelay(2);
3745
3746 /* Read the data returned */
3747 reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
3748 *data = (uint16_t)reg_val;
3749
3750 e1000_swfw_sync_release(hw, swfw);
3751 return E1000_SUCCESS;
3752 }
3753
3754 static int32_t
3755 e1000_write_kmrn_reg(struct e1000_hw *hw,
3756 uint32_t reg_addr,
3757 uint16_t data)
3758 {
3759 uint32_t reg_val;
3760 uint16_t swfw;
3761 DEBUGFUNC("e1000_write_kmrn_reg");
3762
3763 if ((hw->mac_type == e1000_80003es2lan) &&
3764 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3765 swfw = E1000_SWFW_PHY1_SM;
3766 } else {
3767 swfw = E1000_SWFW_PHY0_SM;
3768 }
3769 if (e1000_swfw_sync_acquire(hw, swfw))
3770 return -E1000_ERR_SWFW_SYNC;
3771
3772 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3773 E1000_KUMCTRLSTA_OFFSET) | data;
3774 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
3775 udelay(2);
3776
3777 e1000_swfw_sync_release(hw, swfw);
3778 return E1000_SUCCESS;
3779 }
3780
3781 /******************************************************************************
3782 * Returns the PHY to the power-on reset state
3783 *
3784 * hw - Struct containing variables accessed by shared code
3785 ******************************************************************************/
3786 int32_t
3787 e1000_phy_hw_reset(struct e1000_hw *hw)
3788 {
3789 uint32_t ctrl, ctrl_ext;
3790 uint32_t led_ctrl;
3791 int32_t ret_val;
3792 uint16_t swfw;
3793
3794 DEBUGFUNC("e1000_phy_hw_reset");
3795
3796 /* In the case of the phy reset being blocked, it's not an error, we
3797 * simply return success without performing the reset. */
3798 ret_val = e1000_check_phy_reset_block(hw);
3799 if (ret_val)
3800 return E1000_SUCCESS;
3801
3802 DEBUGOUT("Resetting Phy...\n");
3803
3804 if (hw->mac_type > e1000_82543) {
3805 if ((hw->mac_type == e1000_80003es2lan) &&
3806 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3807 swfw = E1000_SWFW_PHY1_SM;
3808 } else {
3809 swfw = E1000_SWFW_PHY0_SM;
3810 }
3811 if (e1000_swfw_sync_acquire(hw, swfw)) {
3812 e1000_release_software_semaphore(hw);
3813 return -E1000_ERR_SWFW_SYNC;
3814 }
3815 /* Read the device control register and assert the E1000_CTRL_PHY_RST
3816 * bit. Then, take it out of reset.
3817 * For pre-e1000_82571 hardware, we delay for 10ms between the assert
3818 * and deassert. For e1000_82571 hardware and later, we instead delay
3819 * for 50us between and 10ms after the deassertion.
3820 */
3821 ctrl = E1000_READ_REG(hw, CTRL);
3822 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
3823 E1000_WRITE_FLUSH(hw);
3824
3825 if (hw->mac_type < e1000_82571)
3826 msleep(10);
3827 else
3828 udelay(100);
3829
3830 E1000_WRITE_REG(hw, CTRL, ctrl);
3831 E1000_WRITE_FLUSH(hw);
3832
3833 if (hw->mac_type >= e1000_82571)
3834 mdelay(10);
3835
3836 e1000_swfw_sync_release(hw, swfw);
3837 } else {
3838 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
3839 * bit to put the PHY into reset. Then, take it out of reset.
3840 */
3841 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
3842 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
3843 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
3844 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3845 E1000_WRITE_FLUSH(hw);
3846 msleep(10);
3847 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
3848 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3849 E1000_WRITE_FLUSH(hw);
3850 }
3851 udelay(150);
3852
3853 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
3854 /* Configure activity LED after PHY reset */
3855 led_ctrl = E1000_READ_REG(hw, LEDCTL);
3856 led_ctrl &= IGP_ACTIVITY_LED_MASK;
3857 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
3858 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
3859 }
3860
3861 /* Wait for FW to finish PHY configuration. */
3862 ret_val = e1000_get_phy_cfg_done(hw);
3863 if (ret_val != E1000_SUCCESS)
3864 return ret_val;
3865 e1000_release_software_semaphore(hw);
3866
3867 if ((hw->mac_type == e1000_ich8lan) && (hw->phy_type == e1000_phy_igp_3))
3868 ret_val = e1000_init_lcd_from_nvm(hw);
3869
3870 return ret_val;
3871 }
3872
3873 /******************************************************************************
3874 * Resets the PHY
3875 *
3876 * hw - Struct containing variables accessed by shared code
3877 *
3878 * Sets bit 15 of the MII Control regiser
3879 ******************************************************************************/
3880 int32_t
3881 e1000_phy_reset(struct e1000_hw *hw)
3882 {
3883 int32_t ret_val;
3884 uint16_t phy_data;
3885
3886 DEBUGFUNC("e1000_phy_reset");
3887
3888 /* In the case of the phy reset being blocked, it's not an error, we
3889 * simply return success without performing the reset. */
3890 ret_val = e1000_check_phy_reset_block(hw);
3891 if (ret_val)
3892 return E1000_SUCCESS;
3893
3894 switch (hw->mac_type) {
3895 case e1000_82541_rev_2:
3896 case e1000_82571:
3897 case e1000_82572:
3898 case e1000_ich8lan:
3899 ret_val = e1000_phy_hw_reset(hw);
3900 if (ret_val)
3901 return ret_val;
3902 break;
3903 default:
3904 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
3905 if (ret_val)
3906 return ret_val;
3907
3908 phy_data |= MII_CR_RESET;
3909 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
3910 if (ret_val)
3911 return ret_val;
3912
3913 udelay(1);
3914 break;
3915 }
3916
3917 if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
3918 e1000_phy_init_script(hw);
3919
3920 return E1000_SUCCESS;
3921 }
3922
3923 /******************************************************************************
3924 * Work-around for 82566 power-down: on D3 entry-
3925 * 1) disable gigabit link
3926 * 2) write VR power-down enable
3927 * 3) read it back
3928 * if successful continue, else issue LCD reset and repeat
3929 *
3930 * hw - struct containing variables accessed by shared code
3931 ******************************************************************************/
3932 void
3933 e1000_phy_powerdown_workaround(struct e1000_hw *hw)
3934 {
3935 int32_t reg;
3936 uint16_t phy_data;
3937 int32_t retry = 0;
3938
3939 DEBUGFUNC("e1000_phy_powerdown_workaround");
3940
3941 if (hw->phy_type != e1000_phy_igp_3)
3942 return;
3943
3944 do {
3945 /* Disable link */
3946 reg = E1000_READ_REG(hw, PHY_CTRL);
3947 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
3948 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3949
3950 /* Write VR power-down enable */
3951 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3952 e1000_write_phy_reg(hw, IGP3_VR_CTRL, phy_data |
3953 IGP3_VR_CTRL_MODE_SHUT);
3954
3955 /* Read it back and test */
3956 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3957 if ((phy_data & IGP3_VR_CTRL_MODE_SHUT) || retry)
3958 break;
3959
3960 /* Issue PHY reset and repeat at most one more time */
3961 reg = E1000_READ_REG(hw, CTRL);
3962 E1000_WRITE_REG(hw, CTRL, reg | E1000_CTRL_PHY_RST);
3963 retry++;
3964 } while (retry);
3965
3966 return;
3967
3968 }
3969
3970 /******************************************************************************
3971 * Work-around for 82566 Kumeran PCS lock loss:
3972 * On link status change (i.e. PCI reset, speed change) and link is up and
3973 * speed is gigabit-
3974 * 0) if workaround is optionally disabled do nothing
3975 * 1) wait 1ms for Kumeran link to come up
3976 * 2) check Kumeran Diagnostic register PCS lock loss bit
3977 * 3) if not set the link is locked (all is good), otherwise...
3978 * 4) reset the PHY
3979 * 5) repeat up to 10 times
3980 * Note: this is only called for IGP3 copper when speed is 1gb.
3981 *
3982 * hw - struct containing variables accessed by shared code
3983 ******************************************************************************/
3984 static int32_t
3985 e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw)
3986 {
3987 int32_t ret_val;
3988 int32_t reg;
3989 int32_t cnt;
3990 uint16_t phy_data;
3991
3992 if (hw->kmrn_lock_loss_workaround_disabled)
3993 return E1000_SUCCESS;
3994
3995 /* Make sure link is up before proceeding. If not just return.
3996 * Attempting this while link is negotiating fouled up link
3997 * stability */
3998 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3999 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4000
4001 if (phy_data & MII_SR_LINK_STATUS) {
4002 for (cnt = 0; cnt < 10; cnt++) {
4003 /* read once to clear */
4004 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
4005 if (ret_val)
4006 return ret_val;
4007 /* and again to get new status */
4008 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
4009 if (ret_val)
4010 return ret_val;
4011
4012 /* check for PCS lock */
4013 if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
4014 return E1000_SUCCESS;
4015
4016 /* Issue PHY reset */
4017 e1000_phy_hw_reset(hw);
4018 mdelay(5);
4019 }
4020 /* Disable GigE link negotiation */
4021 reg = E1000_READ_REG(hw, PHY_CTRL);
4022 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
4023 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4024
4025 /* unable to acquire PCS lock */
4026 return E1000_ERR_PHY;
4027 }
4028
4029 return E1000_SUCCESS;
4030 }
4031
4032 /******************************************************************************
4033 * Probes the expected PHY address for known PHY IDs
4034 *
4035 * hw - Struct containing variables accessed by shared code
4036 ******************************************************************************/
4037 static int32_t
4038 e1000_detect_gig_phy(struct e1000_hw *hw)
4039 {
4040 int32_t phy_init_status, ret_val;
4041 uint16_t phy_id_high, phy_id_low;
4042 boolean_t match = FALSE;
4043
4044 DEBUGFUNC("e1000_detect_gig_phy");
4045
4046 /* The 82571 firmware may still be configuring the PHY. In this
4047 * case, we cannot access the PHY until the configuration is done. So
4048 * we explicitly set the PHY values. */
4049 if (hw->mac_type == e1000_82571 ||
4050 hw->mac_type == e1000_82572) {
4051 hw->phy_id = IGP01E1000_I_PHY_ID;
4052 hw->phy_type = e1000_phy_igp_2;
4053 return E1000_SUCCESS;
4054 }
4055
4056 /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a work-
4057 * around that forces PHY page 0 to be set or the reads fail. The rest of
4058 * the code in this routine uses e1000_read_phy_reg to read the PHY ID.
4059 * So for ESB-2 we need to have this set so our reads won't fail. If the
4060 * attached PHY is not a e1000_phy_gg82563, the routines below will figure
4061 * this out as well. */
4062 if (hw->mac_type == e1000_80003es2lan)
4063 hw->phy_type = e1000_phy_gg82563;
4064
4065 /* Read the PHY ID Registers to identify which PHY is onboard. */
4066 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
4067 if (ret_val)
4068 return ret_val;
4069
4070 hw->phy_id = (uint32_t) (phy_id_high << 16);
4071 udelay(20);
4072 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
4073 if (ret_val)
4074 return ret_val;
4075
4076 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
4077 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
4078
4079 switch (hw->mac_type) {
4080 case e1000_82543:
4081 if (hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
4082 break;
4083 case e1000_82544:
4084 if (hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
4085 break;
4086 case e1000_82540:
4087 case e1000_82545:
4088 case e1000_82545_rev_3:
4089 case e1000_82546:
4090 case e1000_82546_rev_3:
4091 if (hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
4092 break;
4093 case e1000_82541:
4094 case e1000_82541_rev_2:
4095 case e1000_82547:
4096 case e1000_82547_rev_2:
4097 if (hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
4098 break;
4099 case e1000_82573:
4100 if (hw->phy_id == M88E1111_I_PHY_ID) match = TRUE;
4101 break;
4102 case e1000_80003es2lan:
4103 if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE;
4104 break;
4105 case e1000_ich8lan:
4106 if (hw->phy_id == IGP03E1000_E_PHY_ID) match = TRUE;
4107 if (hw->phy_id == IFE_E_PHY_ID) match = TRUE;
4108 if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = TRUE;
4109 if (hw->phy_id == IFE_C_E_PHY_ID) match = TRUE;
4110 break;
4111 default:
4112 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
4113 return -E1000_ERR_CONFIG;
4114 }
4115 phy_init_status = e1000_set_phy_type(hw);
4116
4117 if ((match) && (phy_init_status == E1000_SUCCESS)) {
4118 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
4119 return E1000_SUCCESS;
4120 }
4121 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
4122 return -E1000_ERR_PHY;
4123 }
4124
4125 /******************************************************************************
4126 * Resets the PHY's DSP
4127 *
4128 * hw - Struct containing variables accessed by shared code
4129 ******************************************************************************/
4130 static int32_t
4131 e1000_phy_reset_dsp(struct e1000_hw *hw)
4132 {
4133 int32_t ret_val;
4134 DEBUGFUNC("e1000_phy_reset_dsp");
4135
4136 do {
4137 if (hw->phy_type != e1000_phy_gg82563) {
4138 ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
4139 if (ret_val) break;
4140 }
4141 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
4142 if (ret_val) break;
4143 ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
4144 if (ret_val) break;
4145 ret_val = E1000_SUCCESS;
4146 } while (0);
4147
4148 return ret_val;
4149 }
4150
4151 /******************************************************************************
4152 * Get PHY information from various PHY registers for igp PHY only.
4153 *
4154 * hw - Struct containing variables accessed by shared code
4155 * phy_info - PHY information structure
4156 ******************************************************************************/
4157 static int32_t
4158 e1000_phy_igp_get_info(struct e1000_hw *hw,
4159 struct e1000_phy_info *phy_info)
4160 {
4161 int32_t ret_val;
4162 uint16_t phy_data, min_length, max_length, average;
4163 e1000_rev_polarity polarity;
4164
4165 DEBUGFUNC("e1000_phy_igp_get_info");
4166
4167 /* The downshift status is checked only once, after link is established,
4168 * and it stored in the hw->speed_downgraded parameter. */
4169 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4170
4171 /* IGP01E1000 does not need to support it. */
4172 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
4173
4174 /* IGP01E1000 always correct polarity reversal */
4175 phy_info->polarity_correction = e1000_polarity_reversal_enabled;
4176
4177 /* Check polarity status */
4178 ret_val = e1000_check_polarity(hw, &polarity);
4179 if (ret_val)
4180 return ret_val;
4181
4182 phy_info->cable_polarity = polarity;
4183
4184 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
4185 if (ret_val)
4186 return ret_val;
4187
4188 phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & IGP01E1000_PSSR_MDIX) >>
4189 IGP01E1000_PSSR_MDIX_SHIFT);
4190
4191 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
4192 IGP01E1000_PSSR_SPEED_1000MBPS) {
4193 /* Local/Remote Receiver Information are only valid at 1000 Mbps */
4194 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
4195 if (ret_val)
4196 return ret_val;
4197
4198 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
4199 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
4200 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4201 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
4202 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
4203 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4204
4205 /* Get cable length */
4206 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
4207 if (ret_val)
4208 return ret_val;
4209
4210 /* Translate to old method */
4211 average = (max_length + min_length) / 2;
4212
4213 if (average <= e1000_igp_cable_length_50)
4214 phy_info->cable_length = e1000_cable_length_50;
4215 else if (average <= e1000_igp_cable_length_80)
4216 phy_info->cable_length = e1000_cable_length_50_80;
4217 else if (average <= e1000_igp_cable_length_110)
4218 phy_info->cable_length = e1000_cable_length_80_110;
4219 else if (average <= e1000_igp_cable_length_140)
4220 phy_info->cable_length = e1000_cable_length_110_140;
4221 else
4222 phy_info->cable_length = e1000_cable_length_140;
4223 }
4224
4225 return E1000_SUCCESS;
4226 }
4227
4228 /******************************************************************************
4229 * Get PHY information from various PHY registers for ife PHY only.
4230 *
4231 * hw - Struct containing variables accessed by shared code
4232 * phy_info - PHY information structure
4233 ******************************************************************************/
4234 static int32_t
4235 e1000_phy_ife_get_info(struct e1000_hw *hw,
4236 struct e1000_phy_info *phy_info)
4237 {
4238 int32_t ret_val;
4239 uint16_t phy_data;
4240 e1000_rev_polarity polarity;
4241
4242 DEBUGFUNC("e1000_phy_ife_get_info");
4243
4244 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4245 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
4246
4247 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
4248 if (ret_val)
4249 return ret_val;
4250 phy_info->polarity_correction =
4251 ((phy_data & IFE_PSC_AUTO_POLARITY_DISABLE) >>
4252 IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT) ?
4253 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
4254
4255 if (phy_info->polarity_correction == e1000_polarity_reversal_enabled) {
4256 ret_val = e1000_check_polarity(hw, &polarity);
4257 if (ret_val)
4258 return ret_val;
4259 } else {
4260 /* Polarity is forced. */
4261 polarity = ((phy_data & IFE_PSC_FORCE_POLARITY) >>
4262 IFE_PSC_FORCE_POLARITY_SHIFT) ?
4263 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
4264 }
4265 phy_info->cable_polarity = polarity;
4266
4267 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
4268 if (ret_val)
4269 return ret_val;
4270
4271 phy_info->mdix_mode = (e1000_auto_x_mode)
4272 ((phy_data & (IFE_PMC_AUTO_MDIX | IFE_PMC_FORCE_MDIX)) >>
4273 IFE_PMC_MDIX_MODE_SHIFT);
4274
4275 return E1000_SUCCESS;
4276 }
4277
4278 /******************************************************************************
4279 * Get PHY information from various PHY registers fot m88 PHY only.
4280 *
4281 * hw - Struct containing variables accessed by shared code
4282 * phy_info - PHY information structure
4283 ******************************************************************************/
4284 static int32_t
4285 e1000_phy_m88_get_info(struct e1000_hw *hw,
4286 struct e1000_phy_info *phy_info)
4287 {
4288 int32_t ret_val;
4289 uint16_t phy_data;
4290 e1000_rev_polarity polarity;
4291
4292 DEBUGFUNC("e1000_phy_m88_get_info");
4293
4294 /* The downshift status is checked only once, after link is established,
4295 * and it stored in the hw->speed_downgraded parameter. */
4296 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4297
4298 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
4299 if (ret_val)
4300 return ret_val;
4301
4302 phy_info->extended_10bt_distance =
4303 ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
4304 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ?
4305 e1000_10bt_ext_dist_enable_lower : e1000_10bt_ext_dist_enable_normal;
4306
4307 phy_info->polarity_correction =
4308 ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
4309 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ?
4310 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
4311
4312 /* Check polarity status */
4313 ret_val = e1000_check_polarity(hw, &polarity);
4314 if (ret_val)
4315 return ret_val;
4316 phy_info->cable_polarity = polarity;
4317
4318 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
4319 if (ret_val)
4320 return ret_val;
4321
4322 phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & M88E1000_PSSR_MDIX) >>
4323 M88E1000_PSSR_MDIX_SHIFT);
4324
4325 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
4326 /* Cable Length Estimation and Local/Remote Receiver Information
4327 * are only valid at 1000 Mbps.
4328 */
4329 if (hw->phy_type != e1000_phy_gg82563) {
4330 phy_info->cable_length = (e1000_cable_length)((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
4331 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
4332 } else {
4333 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
4334 &phy_data);
4335 if (ret_val)
4336 return ret_val;
4337
4338 phy_info->cable_length = (e1000_cable_length)(phy_data & GG82563_DSPD_CABLE_LENGTH);
4339 }
4340
4341 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
4342 if (ret_val)
4343 return ret_val;
4344
4345 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
4346 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
4347 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4348 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
4349 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
4350 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4351
4352 }
4353
4354 return E1000_SUCCESS;
4355 }
4356
4357 /******************************************************************************
4358 * Get PHY information from various PHY registers
4359 *
4360 * hw - Struct containing variables accessed by shared code
4361 * phy_info - PHY information structure
4362 ******************************************************************************/
4363 int32_t
4364 e1000_phy_get_info(struct e1000_hw *hw,
4365 struct e1000_phy_info *phy_info)
4366 {
4367 int32_t ret_val;
4368 uint16_t phy_data;
4369
4370 DEBUGFUNC("e1000_phy_get_info");
4371
4372 phy_info->cable_length = e1000_cable_length_undefined;
4373 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
4374 phy_info->cable_polarity = e1000_rev_polarity_undefined;
4375 phy_info->downshift = e1000_downshift_undefined;
4376 phy_info->polarity_correction = e1000_polarity_reversal_undefined;
4377 phy_info->mdix_mode = e1000_auto_x_mode_undefined;
4378 phy_info->local_rx = e1000_1000t_rx_status_undefined;
4379 phy_info->remote_rx = e1000_1000t_rx_status_undefined;
4380
4381 if (hw->media_type != e1000_media_type_copper) {
4382 DEBUGOUT("PHY info is only valid for copper media\n");
4383 return -E1000_ERR_CONFIG;
4384 }
4385
4386 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4387 if (ret_val)
4388 return ret_val;
4389
4390 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4391 if (ret_val)
4392 return ret_val;
4393
4394 if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
4395 DEBUGOUT("PHY info is only valid if link is up\n");
4396 return -E1000_ERR_CONFIG;
4397 }
4398
4399 if (hw->phy_type == e1000_phy_igp ||
4400 hw->phy_type == e1000_phy_igp_3 ||
4401 hw->phy_type == e1000_phy_igp_2)
4402 return e1000_phy_igp_get_info(hw, phy_info);
4403 else if (hw->phy_type == e1000_phy_ife)
4404 return e1000_phy_ife_get_info(hw, phy_info);
4405 else
4406 return e1000_phy_m88_get_info(hw, phy_info);
4407 }
4408
4409 int32_t
4410 e1000_validate_mdi_setting(struct e1000_hw *hw)
4411 {
4412 DEBUGFUNC("e1000_validate_mdi_settings");
4413
4414 if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
4415 DEBUGOUT("Invalid MDI setting detected\n");
4416 hw->mdix = 1;
4417 return -E1000_ERR_CONFIG;
4418 }
4419 return E1000_SUCCESS;
4420 }
4421
4422
4423 /******************************************************************************
4424 * Sets up eeprom variables in the hw struct. Must be called after mac_type
4425 * is configured. Additionally, if this is ICH8, the flash controller GbE
4426 * registers must be mapped, or this will crash.
4427 *
4428 * hw - Struct containing variables accessed by shared code
4429 *****************************************************************************/
4430 int32_t
4431 e1000_init_eeprom_params(struct e1000_hw *hw)
4432 {
4433 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4434 uint32_t eecd = E1000_READ_REG(hw, EECD);
4435 int32_t ret_val = E1000_SUCCESS;
4436 uint16_t eeprom_size;
4437
4438 DEBUGFUNC("e1000_init_eeprom_params");
4439
4440 switch (hw->mac_type) {
4441 case e1000_82542_rev2_0:
4442 case e1000_82542_rev2_1:
4443 case e1000_82543:
4444 case e1000_82544:
4445 eeprom->type = e1000_eeprom_microwire;
4446 eeprom->word_size = 64;
4447 eeprom->opcode_bits = 3;
4448 eeprom->address_bits = 6;
4449 eeprom->delay_usec = 50;
4450 eeprom->use_eerd = FALSE;
4451 eeprom->use_eewr = FALSE;
4452 break;
4453 case e1000_82540:
4454 case e1000_82545:
4455 case e1000_82545_rev_3:
4456 case e1000_82546:
4457 case e1000_82546_rev_3:
4458 eeprom->type = e1000_eeprom_microwire;
4459 eeprom->opcode_bits = 3;
4460 eeprom->delay_usec = 50;
4461 if (eecd & E1000_EECD_SIZE) {
4462 eeprom->word_size = 256;
4463 eeprom->address_bits = 8;
4464 } else {
4465 eeprom->word_size = 64;
4466 eeprom->address_bits = 6;
4467 }
4468 eeprom->use_eerd = FALSE;
4469 eeprom->use_eewr = FALSE;
4470 break;
4471 case e1000_82541:
4472 case e1000_82541_rev_2:
4473 case e1000_82547:
4474 case e1000_82547_rev_2:
4475 if (eecd & E1000_EECD_TYPE) {
4476 eeprom->type = e1000_eeprom_spi;
4477 eeprom->opcode_bits = 8;
4478 eeprom->delay_usec = 1;
4479 if (eecd & E1000_EECD_ADDR_BITS) {
4480 eeprom->page_size = 32;
4481 eeprom->address_bits = 16;
4482 } else {
4483 eeprom->page_size = 8;
4484 eeprom->address_bits = 8;
4485 }
4486 } else {
4487 eeprom->type = e1000_eeprom_microwire;
4488 eeprom->opcode_bits = 3;
4489 eeprom->delay_usec = 50;
4490 if (eecd & E1000_EECD_ADDR_BITS) {
4491 eeprom->word_size = 256;
4492 eeprom->address_bits = 8;
4493 } else {
4494 eeprom->word_size = 64;
4495 eeprom->address_bits = 6;
4496 }
4497 }
4498 eeprom->use_eerd = FALSE;
4499 eeprom->use_eewr = FALSE;
4500 break;
4501 case e1000_82571:
4502 case e1000_82572:
4503 eeprom->type = e1000_eeprom_spi;
4504 eeprom->opcode_bits = 8;
4505 eeprom->delay_usec = 1;
4506 if (eecd & E1000_EECD_ADDR_BITS) {
4507 eeprom->page_size = 32;
4508 eeprom->address_bits = 16;
4509 } else {
4510 eeprom->page_size = 8;
4511 eeprom->address_bits = 8;
4512 }
4513 eeprom->use_eerd = FALSE;
4514 eeprom->use_eewr = FALSE;
4515 break;
4516 case e1000_82573:
4517 eeprom->type = e1000_eeprom_spi;
4518 eeprom->opcode_bits = 8;
4519 eeprom->delay_usec = 1;
4520 if (eecd & E1000_EECD_ADDR_BITS) {
4521 eeprom->page_size = 32;
4522 eeprom->address_bits = 16;
4523 } else {
4524 eeprom->page_size = 8;
4525 eeprom->address_bits = 8;
4526 }
4527 eeprom->use_eerd = TRUE;
4528 eeprom->use_eewr = TRUE;
4529 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
4530 eeprom->type = e1000_eeprom_flash;
4531 eeprom->word_size = 2048;
4532
4533 /* Ensure that the Autonomous FLASH update bit is cleared due to
4534 * Flash update issue on parts which use a FLASH for NVM. */
4535 eecd &= ~E1000_EECD_AUPDEN;
4536 E1000_WRITE_REG(hw, EECD, eecd);
4537 }
4538 break;
4539 case e1000_80003es2lan:
4540 eeprom->type = e1000_eeprom_spi;
4541 eeprom->opcode_bits = 8;
4542 eeprom->delay_usec = 1;
4543 if (eecd & E1000_EECD_ADDR_BITS) {
4544 eeprom->page_size = 32;
4545 eeprom->address_bits = 16;
4546 } else {
4547 eeprom->page_size = 8;
4548 eeprom->address_bits = 8;
4549 }
4550 eeprom->use_eerd = TRUE;
4551 eeprom->use_eewr = FALSE;
4552 break;
4553 case e1000_ich8lan:
4554 {
4555 int32_t i = 0;
4556 uint32_t flash_size = E1000_READ_ICH8_REG(hw, ICH8_FLASH_GFPREG);
4557
4558 eeprom->type = e1000_eeprom_ich8;
4559 eeprom->use_eerd = FALSE;
4560 eeprom->use_eewr = FALSE;
4561 eeprom->word_size = E1000_SHADOW_RAM_WORDS;
4562
4563 /* Zero the shadow RAM structure. But don't load it from NVM
4564 * so as to save time for driver init */
4565 if (hw->eeprom_shadow_ram != NULL) {
4566 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4567 hw->eeprom_shadow_ram[i].modified = FALSE;
4568 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
4569 }
4570 }
4571
4572 hw->flash_base_addr = (flash_size & ICH8_GFPREG_BASE_MASK) *
4573 ICH8_FLASH_SECTOR_SIZE;
4574
4575 hw->flash_bank_size = ((flash_size >> 16) & ICH8_GFPREG_BASE_MASK) + 1;
4576 hw->flash_bank_size -= (flash_size & ICH8_GFPREG_BASE_MASK);
4577 hw->flash_bank_size *= ICH8_FLASH_SECTOR_SIZE;
4578 hw->flash_bank_size /= 2 * sizeof(uint16_t);
4579
4580 break;
4581 }
4582 default:
4583 break;
4584 }
4585
4586 if (eeprom->type == e1000_eeprom_spi) {
4587 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
4588 * 32KB (incremented by powers of 2).
4589 */
4590 if (hw->mac_type <= e1000_82547_rev_2) {
4591 /* Set to default value for initial eeprom read. */
4592 eeprom->word_size = 64;
4593 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
4594 if (ret_val)
4595 return ret_val;
4596 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
4597 /* 256B eeprom size was not supported in earlier hardware, so we
4598 * bump eeprom_size up one to ensure that "1" (which maps to 256B)
4599 * is never the result used in the shifting logic below. */
4600 if (eeprom_size)
4601 eeprom_size++;
4602 } else {
4603 eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >>
4604 E1000_EECD_SIZE_EX_SHIFT);
4605 }
4606
4607 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
4608 }
4609 return ret_val;
4610 }
4611
4612 /******************************************************************************
4613 * Raises the EEPROM's clock input.
4614 *
4615 * hw - Struct containing variables accessed by shared code
4616 * eecd - EECD's current value
4617 *****************************************************************************/
4618 static void
4619 e1000_raise_ee_clk(struct e1000_hw *hw,
4620 uint32_t *eecd)
4621 {
4622 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
4623 * wait <delay> microseconds.
4624 */
4625 *eecd = *eecd | E1000_EECD_SK;
4626 E1000_WRITE_REG(hw, EECD, *eecd);
4627 E1000_WRITE_FLUSH(hw);
4628 udelay(hw->eeprom.delay_usec);
4629 }
4630
4631 /******************************************************************************
4632 * Lowers the EEPROM's clock input.
4633 *
4634 * hw - Struct containing variables accessed by shared code
4635 * eecd - EECD's current value
4636 *****************************************************************************/
4637 static void
4638 e1000_lower_ee_clk(struct e1000_hw *hw,
4639 uint32_t *eecd)
4640 {
4641 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
4642 * wait 50 microseconds.
4643 */
4644 *eecd = *eecd & ~E1000_EECD_SK;
4645 E1000_WRITE_REG(hw, EECD, *eecd);
4646 E1000_WRITE_FLUSH(hw);
4647 udelay(hw->eeprom.delay_usec);
4648 }
4649
4650 /******************************************************************************
4651 * Shift data bits out to the EEPROM.
4652 *
4653 * hw - Struct containing variables accessed by shared code
4654 * data - data to send to the EEPROM
4655 * count - number of bits to shift out
4656 *****************************************************************************/
4657 static void
4658 e1000_shift_out_ee_bits(struct e1000_hw *hw,
4659 uint16_t data,
4660 uint16_t count)
4661 {
4662 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4663 uint32_t eecd;
4664 uint32_t mask;
4665
4666 /* We need to shift "count" bits out to the EEPROM. So, value in the
4667 * "data" parameter will be shifted out to the EEPROM one bit at a time.
4668 * In order to do this, "data" must be broken down into bits.
4669 */
4670 mask = 0x01 << (count - 1);
4671 eecd = E1000_READ_REG(hw, EECD);
4672 if (eeprom->type == e1000_eeprom_microwire) {
4673 eecd &= ~E1000_EECD_DO;
4674 } else if (eeprom->type == e1000_eeprom_spi) {
4675 eecd |= E1000_EECD_DO;
4676 }
4677 do {
4678 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
4679 * and then raising and then lowering the clock (the SK bit controls
4680 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
4681 * by setting "DI" to "0" and then raising and then lowering the clock.
4682 */
4683 eecd &= ~E1000_EECD_DI;
4684
4685 if (data & mask)
4686 eecd |= E1000_EECD_DI;
4687
4688 E1000_WRITE_REG(hw, EECD, eecd);
4689 E1000_WRITE_FLUSH(hw);
4690
4691 udelay(eeprom->delay_usec);
4692
4693 e1000_raise_ee_clk(hw, &eecd);
4694 e1000_lower_ee_clk(hw, &eecd);
4695
4696 mask = mask >> 1;
4697
4698 } while (mask);
4699
4700 /* We leave the "DI" bit set to "0" when we leave this routine. */
4701 eecd &= ~E1000_EECD_DI;
4702 E1000_WRITE_REG(hw, EECD, eecd);
4703 }
4704
4705 /******************************************************************************
4706 * Shift data bits in from the EEPROM
4707 *
4708 * hw - Struct containing variables accessed by shared code
4709 *****************************************************************************/
4710 static uint16_t
4711 e1000_shift_in_ee_bits(struct e1000_hw *hw,
4712 uint16_t count)
4713 {
4714 uint32_t eecd;
4715 uint32_t i;
4716 uint16_t data;
4717
4718 /* In order to read a register from the EEPROM, we need to shift 'count'
4719 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
4720 * input to the EEPROM (setting the SK bit), and then reading the value of
4721 * the "DO" bit. During this "shifting in" process the "DI" bit should
4722 * always be clear.
4723 */
4724
4725 eecd = E1000_READ_REG(hw, EECD);
4726
4727 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
4728 data = 0;
4729
4730 for (i = 0; i < count; i++) {
4731 data = data << 1;
4732 e1000_raise_ee_clk(hw, &eecd);
4733
4734 eecd = E1000_READ_REG(hw, EECD);
4735
4736 eecd &= ~(E1000_EECD_DI);
4737 if (eecd & E1000_EECD_DO)
4738 data |= 1;
4739
4740 e1000_lower_ee_clk(hw, &eecd);
4741 }
4742
4743 return data;
4744 }
4745
4746 /******************************************************************************
4747 * Prepares EEPROM for access
4748 *
4749 * hw - Struct containing variables accessed by shared code
4750 *
4751 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
4752 * function should be called before issuing a command to the EEPROM.
4753 *****************************************************************************/
4754 static int32_t
4755 e1000_acquire_eeprom(struct e1000_hw *hw)
4756 {
4757 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4758 uint32_t eecd, i=0;
4759
4760 DEBUGFUNC("e1000_acquire_eeprom");
4761
4762 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
4763 return -E1000_ERR_SWFW_SYNC;
4764 eecd = E1000_READ_REG(hw, EECD);
4765
4766 if (hw->mac_type != e1000_82573) {
4767 /* Request EEPROM Access */
4768 if (hw->mac_type > e1000_82544) {
4769 eecd |= E1000_EECD_REQ;
4770 E1000_WRITE_REG(hw, EECD, eecd);
4771 eecd = E1000_READ_REG(hw, EECD);
4772 while ((!(eecd & E1000_EECD_GNT)) &&
4773 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
4774 i++;
4775 udelay(5);
4776 eecd = E1000_READ_REG(hw, EECD);
4777 }
4778 if (!(eecd & E1000_EECD_GNT)) {
4779 eecd &= ~E1000_EECD_REQ;
4780 E1000_WRITE_REG(hw, EECD, eecd);
4781 DEBUGOUT("Could not acquire EEPROM grant\n");
4782 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
4783 return -E1000_ERR_EEPROM;
4784 }
4785 }
4786 }
4787
4788 /* Setup EEPROM for Read/Write */
4789
4790 if (eeprom->type == e1000_eeprom_microwire) {
4791 /* Clear SK and DI */
4792 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
4793 E1000_WRITE_REG(hw, EECD, eecd);
4794
4795 /* Set CS */
4796 eecd |= E1000_EECD_CS;
4797 E1000_WRITE_REG(hw, EECD, eecd);
4798 } else if (eeprom->type == e1000_eeprom_spi) {
4799 /* Clear SK and CS */
4800 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
4801 E1000_WRITE_REG(hw, EECD, eecd);
4802 udelay(1);
4803 }
4804
4805 return E1000_SUCCESS;
4806 }
4807
4808 /******************************************************************************
4809 * Returns EEPROM to a "standby" state
4810 *
4811 * hw - Struct containing variables accessed by shared code
4812 *****************************************************************************/
4813 static void
4814 e1000_standby_eeprom(struct e1000_hw *hw)
4815 {
4816 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4817 uint32_t eecd;
4818
4819 eecd = E1000_READ_REG(hw, EECD);
4820
4821 if (eeprom->type == e1000_eeprom_microwire) {
4822 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
4823 E1000_WRITE_REG(hw, EECD, eecd);
4824 E1000_WRITE_FLUSH(hw);
4825 udelay(eeprom->delay_usec);
4826
4827 /* Clock high */
4828 eecd |= E1000_EECD_SK;
4829 E1000_WRITE_REG(hw, EECD, eecd);
4830 E1000_WRITE_FLUSH(hw);
4831 udelay(eeprom->delay_usec);
4832
4833 /* Select EEPROM */
4834 eecd |= E1000_EECD_CS;
4835 E1000_WRITE_REG(hw, EECD, eecd);
4836 E1000_WRITE_FLUSH(hw);
4837 udelay(eeprom->delay_usec);
4838
4839 /* Clock low */
4840 eecd &= ~E1000_EECD_SK;
4841 E1000_WRITE_REG(hw, EECD, eecd);
4842 E1000_WRITE_FLUSH(hw);
4843 udelay(eeprom->delay_usec);
4844 } else if (eeprom->type == e1000_eeprom_spi) {
4845 /* Toggle CS to flush commands */
4846 eecd |= E1000_EECD_CS;
4847 E1000_WRITE_REG(hw, EECD, eecd);
4848 E1000_WRITE_FLUSH(hw);
4849 udelay(eeprom->delay_usec);
4850 eecd &= ~E1000_EECD_CS;
4851 E1000_WRITE_REG(hw, EECD, eecd);
4852 E1000_WRITE_FLUSH(hw);
4853 udelay(eeprom->delay_usec);
4854 }
4855 }
4856
4857 /******************************************************************************
4858 * Terminates a command by inverting the EEPROM's chip select pin
4859 *
4860 * hw - Struct containing variables accessed by shared code
4861 *****************************************************************************/
4862 static void
4863 e1000_release_eeprom(struct e1000_hw *hw)
4864 {
4865 uint32_t eecd;
4866
4867 DEBUGFUNC("e1000_release_eeprom");
4868
4869 eecd = E1000_READ_REG(hw, EECD);
4870
4871 if (hw->eeprom.type == e1000_eeprom_spi) {
4872 eecd |= E1000_EECD_CS; /* Pull CS high */
4873 eecd &= ~E1000_EECD_SK; /* Lower SCK */
4874
4875 E1000_WRITE_REG(hw, EECD, eecd);
4876
4877 udelay(hw->eeprom.delay_usec);
4878 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
4879 /* cleanup eeprom */
4880
4881 /* CS on Microwire is active-high */
4882 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
4883
4884 E1000_WRITE_REG(hw, EECD, eecd);
4885
4886 /* Rising edge of clock */
4887 eecd |= E1000_EECD_SK;
4888 E1000_WRITE_REG(hw, EECD, eecd);
4889 E1000_WRITE_FLUSH(hw);
4890 udelay(hw->eeprom.delay_usec);
4891
4892 /* Falling edge of clock */
4893 eecd &= ~E1000_EECD_SK;
4894 E1000_WRITE_REG(hw, EECD, eecd);
4895 E1000_WRITE_FLUSH(hw);
4896 udelay(hw->eeprom.delay_usec);
4897 }
4898
4899 /* Stop requesting EEPROM access */
4900 if (hw->mac_type > e1000_82544) {
4901 eecd &= ~E1000_EECD_REQ;
4902 E1000_WRITE_REG(hw, EECD, eecd);
4903 }
4904
4905 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
4906 }
4907
4908 /******************************************************************************
4909 * Reads a 16 bit word from the EEPROM.
4910 *
4911 * hw - Struct containing variables accessed by shared code
4912 *****************************************************************************/
4913 static int32_t
4914 e1000_spi_eeprom_ready(struct e1000_hw *hw)
4915 {
4916 uint16_t retry_count = 0;
4917 uint8_t spi_stat_reg;
4918
4919 DEBUGFUNC("e1000_spi_eeprom_ready");
4920
4921 /* Read "Status Register" repeatedly until the LSB is cleared. The
4922 * EEPROM will signal that the command has been completed by clearing
4923 * bit 0 of the internal status register. If it's not cleared within
4924 * 5 milliseconds, then error out.
4925 */
4926 retry_count = 0;
4927 do {
4928 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
4929 hw->eeprom.opcode_bits);
4930 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
4931 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
4932 break;
4933
4934 udelay(5);
4935 retry_count += 5;
4936
4937 e1000_standby_eeprom(hw);
4938 } while (retry_count < EEPROM_MAX_RETRY_SPI);
4939
4940 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
4941 * only 0-5mSec on 5V devices)
4942 */
4943 if (retry_count >= EEPROM_MAX_RETRY_SPI) {
4944 DEBUGOUT("SPI EEPROM Status error\n");
4945 return -E1000_ERR_EEPROM;
4946 }
4947
4948 return E1000_SUCCESS;
4949 }
4950
4951 /******************************************************************************
4952 * Reads a 16 bit word from the EEPROM.
4953 *
4954 * hw - Struct containing variables accessed by shared code
4955 * offset - offset of word in the EEPROM to read
4956 * data - word read from the EEPROM
4957 * words - number of words to read
4958 *****************************************************************************/
4959 int32_t
4960 e1000_read_eeprom(struct e1000_hw *hw,
4961 uint16_t offset,
4962 uint16_t words,
4963 uint16_t *data)
4964 {
4965 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4966 uint32_t i = 0;
4967 int32_t ret_val;
4968
4969 DEBUGFUNC("e1000_read_eeprom");
4970
4971 /* A check for invalid values: offset too large, too many words, and not
4972 * enough words.
4973 */
4974 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
4975 (words == 0)) {
4976 DEBUGOUT("\"words\" parameter out of bounds\n");
4977 return -E1000_ERR_EEPROM;
4978 }
4979
4980 /* FLASH reads without acquiring the semaphore are safe */
4981 if (e1000_is_onboard_nvm_eeprom(hw) == TRUE &&
4982 hw->eeprom.use_eerd == FALSE) {
4983 switch (hw->mac_type) {
4984 case e1000_80003es2lan:
4985 break;
4986 default:
4987 /* Prepare the EEPROM for reading */
4988 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
4989 return -E1000_ERR_EEPROM;
4990 break;
4991 }
4992 }
4993
4994 if (eeprom->use_eerd == TRUE) {
4995 ret_val = e1000_read_eeprom_eerd(hw, offset, words, data);
4996 if ((e1000_is_onboard_nvm_eeprom(hw) == TRUE) ||
4997 (hw->mac_type != e1000_82573))
4998 e1000_release_eeprom(hw);
4999 return ret_val;
5000 }
5001
5002 if (eeprom->type == e1000_eeprom_ich8)
5003 return e1000_read_eeprom_ich8(hw, offset, words, data);
5004
5005 if (eeprom->type == e1000_eeprom_spi) {
5006 uint16_t word_in;
5007 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
5008
5009 if (e1000_spi_eeprom_ready(hw)) {
5010 e1000_release_eeprom(hw);
5011 return -E1000_ERR_EEPROM;
5012 }
5013
5014 e1000_standby_eeprom(hw);
5015
5016 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
5017 if ((eeprom->address_bits == 8) && (offset >= 128))
5018 read_opcode |= EEPROM_A8_OPCODE_SPI;
5019
5020 /* Send the READ command (opcode + addr) */
5021 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
5022 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
5023
5024 /* Read the data. The address of the eeprom internally increments with
5025 * each byte (spi) being read, saving on the overhead of eeprom setup
5026 * and tear-down. The address counter will roll over if reading beyond
5027 * the size of the eeprom, thus allowing the entire memory to be read
5028 * starting from any offset. */
5029 for (i = 0; i < words; i++) {
5030 word_in = e1000_shift_in_ee_bits(hw, 16);
5031 data[i] = (word_in >> 8) | (word_in << 8);
5032 }
5033 } else if (eeprom->type == e1000_eeprom_microwire) {
5034 for (i = 0; i < words; i++) {
5035 /* Send the READ command (opcode + addr) */
5036 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
5037 eeprom->opcode_bits);
5038 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
5039 eeprom->address_bits);
5040
5041 /* Read the data. For microwire, each word requires the overhead
5042 * of eeprom setup and tear-down. */
5043 data[i] = e1000_shift_in_ee_bits(hw, 16);
5044 e1000_standby_eeprom(hw);
5045 }
5046 }
5047
5048 /* End this read operation */
5049 e1000_release_eeprom(hw);
5050
5051 return E1000_SUCCESS;
5052 }
5053
5054 /******************************************************************************
5055 * Reads a 16 bit word from the EEPROM using the EERD register.
5056 *
5057 * hw - Struct containing variables accessed by shared code
5058 * offset - offset of word in the EEPROM to read
5059 * data - word read from the EEPROM
5060 * words - number of words to read
5061 *****************************************************************************/
5062 static int32_t
5063 e1000_read_eeprom_eerd(struct e1000_hw *hw,
5064 uint16_t offset,
5065 uint16_t words,
5066 uint16_t *data)
5067 {
5068 uint32_t i, eerd = 0;
5069 int32_t error = 0;
5070
5071 for (i = 0; i < words; i++) {
5072 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
5073 E1000_EEPROM_RW_REG_START;
5074
5075 E1000_WRITE_REG(hw, EERD, eerd);
5076 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
5077
5078 if (error) {
5079 break;
5080 }
5081 data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA);
5082
5083 }
5084
5085 return error;
5086 }
5087
5088 /******************************************************************************
5089 * Writes a 16 bit word from the EEPROM using the EEWR register.
5090 *
5091 * hw - Struct containing variables accessed by shared code
5092 * offset - offset of word in the EEPROM to read
5093 * data - word read from the EEPROM
5094 * words - number of words to read
5095 *****************************************************************************/
5096 static int32_t
5097 e1000_write_eeprom_eewr(struct e1000_hw *hw,
5098 uint16_t offset,
5099 uint16_t words,
5100 uint16_t *data)
5101 {
5102 uint32_t register_value = 0;
5103 uint32_t i = 0;
5104 int32_t error = 0;
5105
5106 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
5107 return -E1000_ERR_SWFW_SYNC;
5108
5109 for (i = 0; i < words; i++) {
5110 register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) |
5111 ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) |
5112 E1000_EEPROM_RW_REG_START;
5113
5114 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
5115 if (error) {
5116 break;
5117 }
5118
5119 E1000_WRITE_REG(hw, EEWR, register_value);
5120
5121 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
5122
5123 if (error) {
5124 break;
5125 }
5126 }
5127
5128 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
5129 return error;
5130 }
5131
5132 /******************************************************************************
5133 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
5134 *
5135 * hw - Struct containing variables accessed by shared code
5136 *****************************************************************************/
5137 static int32_t
5138 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
5139 {
5140 uint32_t attempts = 100000;
5141 uint32_t i, reg = 0;
5142 int32_t done = E1000_ERR_EEPROM;
5143
5144 for (i = 0; i < attempts; i++) {
5145 if (eerd == E1000_EEPROM_POLL_READ)
5146 reg = E1000_READ_REG(hw, EERD);
5147 else
5148 reg = E1000_READ_REG(hw, EEWR);
5149
5150 if (reg & E1000_EEPROM_RW_REG_DONE) {
5151 done = E1000_SUCCESS;
5152 break;
5153 }
5154 udelay(5);
5155 }
5156
5157 return done;
5158 }
5159
5160 /***************************************************************************
5161 * Description: Determines if the onboard NVM is FLASH or EEPROM.
5162 *
5163 * hw - Struct containing variables accessed by shared code
5164 ****************************************************************************/
5165 static boolean_t
5166 e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
5167 {
5168 uint32_t eecd = 0;
5169
5170 DEBUGFUNC("e1000_is_onboard_nvm_eeprom");
5171
5172 if (hw->mac_type == e1000_ich8lan)
5173 return FALSE;
5174
5175 if (hw->mac_type == e1000_82573) {
5176 eecd = E1000_READ_REG(hw, EECD);
5177
5178 /* Isolate bits 15 & 16 */
5179 eecd = ((eecd >> 15) & 0x03);
5180
5181 /* If both bits are set, device is Flash type */
5182 if (eecd == 0x03) {
5183 return FALSE;
5184 }
5185 }
5186 return TRUE;
5187 }
5188
5189 /******************************************************************************
5190 * Verifies that the EEPROM has a valid checksum
5191 *
5192 * hw - Struct containing variables accessed by shared code
5193 *
5194 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
5195 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
5196 * valid.
5197 *****************************************************************************/
5198 int32_t
5199 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
5200 {
5201 uint16_t checksum = 0;
5202 uint16_t i, eeprom_data;
5203
5204 DEBUGFUNC("e1000_validate_eeprom_checksum");
5205
5206 if ((hw->mac_type == e1000_82573) &&
5207 (e1000_is_onboard_nvm_eeprom(hw) == FALSE)) {
5208 /* Check bit 4 of word 10h. If it is 0, firmware is done updating
5209 * 10h-12h. Checksum may need to be fixed. */
5210 e1000_read_eeprom(hw, 0x10, 1, &eeprom_data);
5211 if ((eeprom_data & 0x10) == 0) {
5212 /* Read 0x23 and check bit 15. This bit is a 1 when the checksum
5213 * has already been fixed. If the checksum is still wrong and this
5214 * bit is a 1, we need to return bad checksum. Otherwise, we need
5215 * to set this bit to a 1 and update the checksum. */
5216 e1000_read_eeprom(hw, 0x23, 1, &eeprom_data);
5217 if ((eeprom_data & 0x8000) == 0) {
5218 eeprom_data |= 0x8000;
5219 e1000_write_eeprom(hw, 0x23, 1, &eeprom_data);
5220 e1000_update_eeprom_checksum(hw);
5221 }
5222 }
5223 }
5224
5225 if (hw->mac_type == e1000_ich8lan) {
5226 /* Drivers must allocate the shadow ram structure for the
5227 * EEPROM checksum to be updated. Otherwise, this bit as well
5228 * as the checksum must both be set correctly for this
5229 * validation to pass.
5230 */
5231 e1000_read_eeprom(hw, 0x19, 1, &eeprom_data);
5232 if ((eeprom_data & 0x40) == 0) {
5233 eeprom_data |= 0x40;
5234 e1000_write_eeprom(hw, 0x19, 1, &eeprom_data);
5235 e1000_update_eeprom_checksum(hw);
5236 }
5237 }
5238
5239 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
5240 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
5241 DEBUGOUT("EEPROM Read Error\n");
5242 return -E1000_ERR_EEPROM;
5243 }
5244 checksum += eeprom_data;
5245 }
5246
5247 if (checksum == (uint16_t) EEPROM_SUM)
5248 return E1000_SUCCESS;
5249 else {
5250 DEBUGOUT("EEPROM Checksum Invalid\n");
5251 return -E1000_ERR_EEPROM;
5252 }
5253 }
5254
5255 /******************************************************************************
5256 * Calculates the EEPROM checksum and writes it to the EEPROM
5257 *
5258 * hw - Struct containing variables accessed by shared code
5259 *
5260 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
5261 * Writes the difference to word offset 63 of the EEPROM.
5262 *****************************************************************************/
5263 int32_t
5264 e1000_update_eeprom_checksum(struct e1000_hw *hw)
5265 {
5266 uint32_t ctrl_ext;
5267 uint16_t checksum = 0;
5268 uint16_t i, eeprom_data;
5269
5270 DEBUGFUNC("e1000_update_eeprom_checksum");
5271
5272 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
5273 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
5274 DEBUGOUT("EEPROM Read Error\n");
5275 return -E1000_ERR_EEPROM;
5276 }
5277 checksum += eeprom_data;
5278 }
5279 checksum = (uint16_t) EEPROM_SUM - checksum;
5280 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
5281 DEBUGOUT("EEPROM Write Error\n");
5282 return -E1000_ERR_EEPROM;
5283 } else if (hw->eeprom.type == e1000_eeprom_flash) {
5284 e1000_commit_shadow_ram(hw);
5285 } else if (hw->eeprom.type == e1000_eeprom_ich8) {
5286 e1000_commit_shadow_ram(hw);
5287 /* Reload the EEPROM, or else modifications will not appear
5288 * until after next adapter reset. */
5289 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
5290 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
5291 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
5292 msleep(10);
5293 }
5294 return E1000_SUCCESS;
5295 }
5296
5297 /******************************************************************************
5298 * Parent function for writing words to the different EEPROM types.
5299 *
5300 * hw - Struct containing variables accessed by shared code
5301 * offset - offset within the EEPROM to be written to
5302 * words - number of words to write
5303 * data - 16 bit word to be written to the EEPROM
5304 *
5305 * If e1000_update_eeprom_checksum is not called after this function, the
5306 * EEPROM will most likely contain an invalid checksum.
5307 *****************************************************************************/
5308 int32_t
5309 e1000_write_eeprom(struct e1000_hw *hw,
5310 uint16_t offset,
5311 uint16_t words,
5312 uint16_t *data)
5313 {
5314 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5315 int32_t status = 0;
5316
5317 DEBUGFUNC("e1000_write_eeprom");
5318
5319 /* A check for invalid values: offset too large, too many words, and not
5320 * enough words.
5321 */
5322 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
5323 (words == 0)) {
5324 DEBUGOUT("\"words\" parameter out of bounds\n");
5325 return -E1000_ERR_EEPROM;
5326 }
5327
5328 /* 82573 writes only through eewr */
5329 if (eeprom->use_eewr == TRUE)
5330 return e1000_write_eeprom_eewr(hw, offset, words, data);
5331
5332 if (eeprom->type == e1000_eeprom_ich8)
5333 return e1000_write_eeprom_ich8(hw, offset, words, data);
5334
5335 /* Prepare the EEPROM for writing */
5336 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
5337 return -E1000_ERR_EEPROM;
5338
5339 if (eeprom->type == e1000_eeprom_microwire) {
5340 status = e1000_write_eeprom_microwire(hw, offset, words, data);
5341 } else {
5342 status = e1000_write_eeprom_spi(hw, offset, words, data);
5343 msleep(10);
5344 }
5345
5346 /* Done with writing */
5347 e1000_release_eeprom(hw);
5348
5349 return status;
5350 }
5351
5352 /******************************************************************************
5353 * Writes a 16 bit word to a given offset in an SPI EEPROM.
5354 *
5355 * hw - Struct containing variables accessed by shared code
5356 * offset - offset within the EEPROM to be written to
5357 * words - number of words to write
5358 * data - pointer to array of 8 bit words to be written to the EEPROM
5359 *
5360 *****************************************************************************/
5361 static int32_t
5362 e1000_write_eeprom_spi(struct e1000_hw *hw,
5363 uint16_t offset,
5364 uint16_t words,
5365 uint16_t *data)
5366 {
5367 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5368 uint16_t widx = 0;
5369
5370 DEBUGFUNC("e1000_write_eeprom_spi");
5371
5372 while (widx < words) {
5373 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI;
5374
5375 if (e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
5376
5377 e1000_standby_eeprom(hw);
5378
5379 /* Send the WRITE ENABLE command (8 bit opcode ) */
5380 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
5381 eeprom->opcode_bits);
5382
5383 e1000_standby_eeprom(hw);
5384
5385 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
5386 if ((eeprom->address_bits == 8) && (offset >= 128))
5387 write_opcode |= EEPROM_A8_OPCODE_SPI;
5388
5389 /* Send the Write command (8-bit opcode + addr) */
5390 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
5391
5392 e1000_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2),
5393 eeprom->address_bits);
5394
5395 /* Send the data */
5396
5397 /* Loop to allow for up to whole page write (32 bytes) of eeprom */
5398 while (widx < words) {
5399 uint16_t word_out = data[widx];
5400 word_out = (word_out >> 8) | (word_out << 8);
5401 e1000_shift_out_ee_bits(hw, word_out, 16);
5402 widx++;
5403
5404 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
5405 * operation, while the smaller eeproms are capable of an 8-byte
5406 * PAGE WRITE operation. Break the inner loop to pass new address
5407 */
5408 if ((((offset + widx)*2) % eeprom->page_size) == 0) {
5409 e1000_standby_eeprom(hw);
5410 break;
5411 }
5412 }
5413 }
5414
5415 return E1000_SUCCESS;
5416 }
5417
5418 /******************************************************************************
5419 * Writes a 16 bit word to a given offset in a Microwire EEPROM.
5420 *
5421 * hw - Struct containing variables accessed by shared code
5422 * offset - offset within the EEPROM to be written to
5423 * words - number of words to write
5424 * data - pointer to array of 16 bit words to be written to the EEPROM
5425 *
5426 *****************************************************************************/
5427 static int32_t
5428 e1000_write_eeprom_microwire(struct e1000_hw *hw,
5429 uint16_t offset,
5430 uint16_t words,
5431 uint16_t *data)
5432 {
5433 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5434 uint32_t eecd;
5435 uint16_t words_written = 0;
5436 uint16_t i = 0;
5437
5438 DEBUGFUNC("e1000_write_eeprom_microwire");
5439
5440 /* Send the write enable command to the EEPROM (3-bit opcode plus
5441 * 6/8-bit dummy address beginning with 11). It's less work to include
5442 * the 11 of the dummy address as part of the opcode than it is to shift
5443 * it over the correct number of bits for the address. This puts the
5444 * EEPROM into write/erase mode.
5445 */
5446 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
5447 (uint16_t)(eeprom->opcode_bits + 2));
5448
5449 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
5450
5451 /* Prepare the EEPROM */
5452 e1000_standby_eeprom(hw);
5453
5454 while (words_written < words) {
5455 /* Send the Write command (3-bit opcode + addr) */
5456 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
5457 eeprom->opcode_bits);
5458
5459 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + words_written),
5460 eeprom->address_bits);
5461
5462 /* Send the data */
5463 e1000_shift_out_ee_bits(hw, data[words_written], 16);
5464
5465 /* Toggle the CS line. This in effect tells the EEPROM to execute
5466 * the previous command.
5467 */
5468 e1000_standby_eeprom(hw);
5469
5470 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will
5471 * signal that the command has been completed by raising the DO signal.
5472 * If DO does not go high in 10 milliseconds, then error out.
5473 */
5474 for (i = 0; i < 200; i++) {
5475 eecd = E1000_READ_REG(hw, EECD);
5476 if (eecd & E1000_EECD_DO) break;
5477 udelay(50);
5478 }
5479 if (i == 200) {
5480 DEBUGOUT("EEPROM Write did not complete\n");
5481 return -E1000_ERR_EEPROM;
5482 }
5483
5484 /* Recover from write */
5485 e1000_standby_eeprom(hw);
5486
5487 words_written++;
5488 }
5489
5490 /* Send the write disable command to the EEPROM (3-bit opcode plus
5491 * 6/8-bit dummy address beginning with 10). It's less work to include
5492 * the 10 of the dummy address as part of the opcode than it is to shift
5493 * it over the correct number of bits for the address. This takes the
5494 * EEPROM out of write/erase mode.
5495 */
5496 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
5497 (uint16_t)(eeprom->opcode_bits + 2));
5498
5499 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
5500
5501 return E1000_SUCCESS;
5502 }
5503
5504 /******************************************************************************
5505 * Flushes the cached eeprom to NVM. This is done by saving the modified values
5506 * in the eeprom cache and the non modified values in the currently active bank
5507 * to the new bank.
5508 *
5509 * hw - Struct containing variables accessed by shared code
5510 * offset - offset of word in the EEPROM to read
5511 * data - word read from the EEPROM
5512 * words - number of words to read
5513 *****************************************************************************/
5514 static int32_t
5515 e1000_commit_shadow_ram(struct e1000_hw *hw)
5516 {
5517 uint32_t attempts = 100000;
5518 uint32_t eecd = 0;
5519 uint32_t flop = 0;
5520 uint32_t i = 0;
5521 int32_t error = E1000_SUCCESS;
5522 uint32_t old_bank_offset = 0;
5523 uint32_t new_bank_offset = 0;
5524 uint32_t sector_retries = 0;
5525 uint8_t low_byte = 0;
5526 uint8_t high_byte = 0;
5527 uint8_t temp_byte = 0;
5528 boolean_t sector_write_failed = FALSE;
5529
5530 if (hw->mac_type == e1000_82573) {
5531 /* The flop register will be used to determine if flash type is STM */
5532 flop = E1000_READ_REG(hw, FLOP);
5533 for (i=0; i < attempts; i++) {
5534 eecd = E1000_READ_REG(hw, EECD);
5535 if ((eecd & E1000_EECD_FLUPD) == 0) {
5536 break;
5537 }
5538 udelay(5);
5539 }
5540
5541 if (i == attempts) {
5542 return -E1000_ERR_EEPROM;
5543 }
5544
5545 /* If STM opcode located in bits 15:8 of flop, reset firmware */
5546 if ((flop & 0xFF00) == E1000_STM_OPCODE) {
5547 E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET);
5548 }
5549
5550 /* Perform the flash update */
5551 E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD);
5552
5553 for (i=0; i < attempts; i++) {
5554 eecd = E1000_READ_REG(hw, EECD);
5555 if ((eecd & E1000_EECD_FLUPD) == 0) {
5556 break;
5557 }
5558 udelay(5);
5559 }
5560
5561 if (i == attempts) {
5562 return -E1000_ERR_EEPROM;
5563 }
5564 }
5565
5566 if (hw->mac_type == e1000_ich8lan && hw->eeprom_shadow_ram != NULL) {
5567 /* We're writing to the opposite bank so if we're on bank 1,
5568 * write to bank 0 etc. We also need to erase the segment that
5569 * is going to be written */
5570 if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) {
5571 new_bank_offset = hw->flash_bank_size * 2;
5572 old_bank_offset = 0;
5573 e1000_erase_ich8_4k_segment(hw, 1);
5574 } else {
5575 old_bank_offset = hw->flash_bank_size * 2;
5576 new_bank_offset = 0;
5577 e1000_erase_ich8_4k_segment(hw, 0);
5578 }
5579
5580 do {
5581 sector_write_failed = FALSE;
5582 /* Loop for every byte in the shadow RAM,
5583 * which is in units of words. */
5584 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
5585 /* Determine whether to write the value stored
5586 * in the other NVM bank or a modified value stored
5587 * in the shadow RAM */
5588 if (hw->eeprom_shadow_ram[i].modified == TRUE) {
5589 low_byte = (uint8_t)hw->eeprom_shadow_ram[i].eeprom_word;
5590 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset,
5591 &temp_byte);
5592 udelay(100);
5593 error = e1000_verify_write_ich8_byte(hw,
5594 (i << 1) + new_bank_offset,
5595 low_byte);
5596 if (error != E1000_SUCCESS)
5597 sector_write_failed = TRUE;
5598 high_byte =
5599 (uint8_t)(hw->eeprom_shadow_ram[i].eeprom_word >> 8);
5600 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
5601 &temp_byte);
5602 udelay(100);
5603 } else {
5604 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset,
5605 &low_byte);
5606 udelay(100);
5607 error = e1000_verify_write_ich8_byte(hw,
5608 (i << 1) + new_bank_offset, low_byte);
5609 if (error != E1000_SUCCESS)
5610 sector_write_failed = TRUE;
5611 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
5612 &high_byte);
5613 }
5614
5615 /* If the word is 0x13, then make sure the signature bits
5616 * (15:14) are 11b until the commit has completed.
5617 * This will allow us to write 10b which indicates the
5618 * signature is valid. We want to do this after the write
5619 * has completed so that we don't mark the segment valid
5620 * while the write is still in progress */
5621 if (i == E1000_ICH8_NVM_SIG_WORD)
5622 high_byte = E1000_ICH8_NVM_SIG_MASK | high_byte;
5623
5624 error = e1000_verify_write_ich8_byte(hw,
5625 (i << 1) + new_bank_offset + 1, high_byte);
5626 if (error != E1000_SUCCESS)
5627 sector_write_failed = TRUE;
5628
5629 if (sector_write_failed == FALSE) {
5630 /* Clear the now not used entry in the cache */
5631 hw->eeprom_shadow_ram[i].modified = FALSE;
5632 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
5633 }
5634 }
5635
5636 /* Don't bother writing the segment valid bits if sector
5637 * programming failed. */
5638 if (sector_write_failed == FALSE) {
5639 /* Finally validate the new segment by setting bit 15:14
5640 * to 10b in word 0x13 , this can be done without an
5641 * erase as well since these bits are 11 to start with
5642 * and we need to change bit 14 to 0b */
5643 e1000_read_ich8_byte(hw,
5644 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
5645 &high_byte);
5646 high_byte &= 0xBF;
5647 error = e1000_verify_write_ich8_byte(hw,
5648 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
5649 high_byte);
5650 if (error != E1000_SUCCESS)
5651 sector_write_failed = TRUE;
5652
5653 /* And invalidate the previously valid segment by setting
5654 * its signature word (0x13) high_byte to 0b. This can be
5655 * done without an erase because flash erase sets all bits
5656 * to 1's. We can write 1's to 0's without an erase */
5657 error = e1000_verify_write_ich8_byte(hw,
5658 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + old_bank_offset,
5659 0);
5660 if (error != E1000_SUCCESS)
5661 sector_write_failed = TRUE;
5662 }
5663 } while (++sector_retries < 10 && sector_write_failed == TRUE);
5664 }
5665
5666 return error;
5667 }
5668
5669 /******************************************************************************
5670 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
5671 * second function of dual function devices
5672 *
5673 * hw - Struct containing variables accessed by shared code
5674 *****************************************************************************/
5675 int32_t
5676 e1000_read_mac_addr(struct e1000_hw * hw)
5677 {
5678 uint16_t offset;
5679 uint16_t eeprom_data, i;
5680
5681 DEBUGFUNC("e1000_read_mac_addr");
5682
5683 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
5684 offset = i >> 1;
5685 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
5686 DEBUGOUT("EEPROM Read Error\n");
5687 return -E1000_ERR_EEPROM;
5688 }
5689 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF);
5690 hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8);
5691 }
5692
5693 switch (hw->mac_type) {
5694 default:
5695 break;
5696 case e1000_82546:
5697 case e1000_82546_rev_3:
5698 case e1000_82571:
5699 case e1000_80003es2lan:
5700 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
5701 hw->perm_mac_addr[5] ^= 0x01;
5702 break;
5703 }
5704
5705 for (i = 0; i < NODE_ADDRESS_SIZE; i++)
5706 hw->mac_addr[i] = hw->perm_mac_addr[i];
5707 return E1000_SUCCESS;
5708 }
5709
5710 /******************************************************************************
5711 * Initializes receive address filters.
5712 *
5713 * hw - Struct containing variables accessed by shared code
5714 *
5715 * Places the MAC address in receive address register 0 and clears the rest
5716 * of the receive addresss registers. Clears the multicast table. Assumes
5717 * the receiver is in reset when the routine is called.
5718 *****************************************************************************/
5719 static void
5720 e1000_init_rx_addrs(struct e1000_hw *hw)
5721 {
5722 uint32_t i;
5723 uint32_t rar_num;
5724
5725 DEBUGFUNC("e1000_init_rx_addrs");
5726
5727 /* Setup the receive address. */
5728 DEBUGOUT("Programming MAC Address into RAR[0]\n");
5729
5730 e1000_rar_set(hw, hw->mac_addr, 0);
5731
5732 rar_num = E1000_RAR_ENTRIES;
5733
5734 /* Reserve a spot for the Locally Administered Address to work around
5735 * an 82571 issue in which a reset on one port will reload the MAC on
5736 * the other port. */
5737 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE))
5738 rar_num -= 1;
5739 if (hw->mac_type == e1000_ich8lan)
5740 rar_num = E1000_RAR_ENTRIES_ICH8LAN;
5741
5742 /* Zero out the other 15 receive addresses. */
5743 DEBUGOUT("Clearing RAR[1-15]\n");
5744 for (i = 1; i < rar_num; i++) {
5745 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
5746 E1000_WRITE_FLUSH(hw);
5747 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
5748 E1000_WRITE_FLUSH(hw);
5749 }
5750 }
5751
5752 /******************************************************************************
5753 * Hashes an address to determine its location in the multicast table
5754 *
5755 * hw - Struct containing variables accessed by shared code
5756 * mc_addr - the multicast address to hash
5757 *****************************************************************************/
5758 uint32_t
5759 e1000_hash_mc_addr(struct e1000_hw *hw,
5760 uint8_t *mc_addr)
5761 {
5762 uint32_t hash_value = 0;
5763
5764 /* The portion of the address that is used for the hash table is
5765 * determined by the mc_filter_type setting.
5766 */
5767 switch (hw->mc_filter_type) {
5768 /* [0] [1] [2] [3] [4] [5]
5769 * 01 AA 00 12 34 56
5770 * LSB MSB
5771 */
5772 case 0:
5773 if (hw->mac_type == e1000_ich8lan) {
5774 /* [47:38] i.e. 0x158 for above example address */
5775 hash_value = ((mc_addr[4] >> 6) | (((uint16_t) mc_addr[5]) << 2));
5776 } else {
5777 /* [47:36] i.e. 0x563 for above example address */
5778 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
5779 }
5780 break;
5781 case 1:
5782 if (hw->mac_type == e1000_ich8lan) {
5783 /* [46:37] i.e. 0x2B1 for above example address */
5784 hash_value = ((mc_addr[4] >> 5) | (((uint16_t) mc_addr[5]) << 3));
5785 } else {
5786 /* [46:35] i.e. 0xAC6 for above example address */
5787 hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5));
5788 }
5789 break;
5790 case 2:
5791 if (hw->mac_type == e1000_ich8lan) {
5792 /*[45:36] i.e. 0x163 for above example address */
5793 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
5794 } else {
5795 /* [45:34] i.e. 0x5D8 for above example address */
5796 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
5797 }
5798 break;
5799 case 3:
5800 if (hw->mac_type == e1000_ich8lan) {
5801 /* [43:34] i.e. 0x18D for above example address */
5802 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
5803 } else {
5804 /* [43:32] i.e. 0x634 for above example address */
5805 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8));
5806 }
5807 break;
5808 }
5809
5810 hash_value &= 0xFFF;
5811 if (hw->mac_type == e1000_ich8lan)
5812 hash_value &= 0x3FF;
5813
5814 return hash_value;
5815 }
5816
5817 /******************************************************************************
5818 * Sets the bit in the multicast table corresponding to the hash value.
5819 *
5820 * hw - Struct containing variables accessed by shared code
5821 * hash_value - Multicast address hash value
5822 *****************************************************************************/
5823 void
5824 e1000_mta_set(struct e1000_hw *hw,
5825 uint32_t hash_value)
5826 {
5827 uint32_t hash_bit, hash_reg;
5828 uint32_t mta;
5829 uint32_t temp;
5830
5831 /* The MTA is a register array of 128 32-bit registers.
5832 * It is treated like an array of 4096 bits. We want to set
5833 * bit BitArray[hash_value]. So we figure out what register
5834 * the bit is in, read it, OR in the new bit, then write
5835 * back the new value. The register is determined by the
5836 * upper 7 bits of the hash value and the bit within that
5837 * register are determined by the lower 5 bits of the value.
5838 */
5839 hash_reg = (hash_value >> 5) & 0x7F;
5840 if (hw->mac_type == e1000_ich8lan)
5841 hash_reg &= 0x1F;
5842 hash_bit = hash_value & 0x1F;
5843
5844 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
5845
5846 mta |= (1 << hash_bit);
5847
5848 /* If we are on an 82544 and we are trying to write an odd offset
5849 * in the MTA, save off the previous entry before writing and
5850 * restore the old value after writing.
5851 */
5852 if ((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) {
5853 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
5854 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
5855 E1000_WRITE_FLUSH(hw);
5856 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
5857 E1000_WRITE_FLUSH(hw);
5858 } else {
5859 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
5860 E1000_WRITE_FLUSH(hw);
5861 }
5862 }
5863
5864 /******************************************************************************
5865 * Puts an ethernet address into a receive address register.
5866 *
5867 * hw - Struct containing variables accessed by shared code
5868 * addr - Address to put into receive address register
5869 * index - Receive address register to write
5870 *****************************************************************************/
5871 void
5872 e1000_rar_set(struct e1000_hw *hw,
5873 uint8_t *addr,
5874 uint32_t index)
5875 {
5876 uint32_t rar_low, rar_high;
5877
5878 /* HW expects these in little endian so we reverse the byte order
5879 * from network order (big endian) to little endian
5880 */
5881 rar_low = ((uint32_t) addr[0] |
5882 ((uint32_t) addr[1] << 8) |
5883 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24));
5884 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8));
5885
5886 /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
5887 * unit hang.
5888 *
5889 * Description:
5890 * If there are any Rx frames queued up or otherwise present in the HW
5891 * before RSS is enabled, and then we enable RSS, the HW Rx unit will
5892 * hang. To work around this issue, we have to disable receives and
5893 * flush out all Rx frames before we enable RSS. To do so, we modify we
5894 * redirect all Rx traffic to manageability and then reset the HW.
5895 * This flushes away Rx frames, and (since the redirections to
5896 * manageability persists across resets) keeps new ones from coming in
5897 * while we work. Then, we clear the Address Valid AV bit for all MAC
5898 * addresses and undo the re-direction to manageability.
5899 * Now, frames are coming in again, but the MAC won't accept them, so
5900 * far so good. We now proceed to initialize RSS (if necessary) and
5901 * configure the Rx unit. Last, we re-enable the AV bits and continue
5902 * on our merry way.
5903 */
5904 switch (hw->mac_type) {
5905 case e1000_82571:
5906 case e1000_82572:
5907 case e1000_80003es2lan:
5908 if (hw->leave_av_bit_off == TRUE)
5909 break;
5910 default:
5911 /* Indicate to hardware the Address is Valid. */
5912 rar_high |= E1000_RAH_AV;
5913 break;
5914 }
5915
5916 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
5917 E1000_WRITE_FLUSH(hw);
5918 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
5919 E1000_WRITE_FLUSH(hw);
5920 }
5921
5922 /******************************************************************************
5923 * Writes a value to the specified offset in the VLAN filter table.
5924 *
5925 * hw - Struct containing variables accessed by shared code
5926 * offset - Offset in VLAN filer table to write
5927 * value - Value to write into VLAN filter table
5928 *****************************************************************************/
5929 void
5930 e1000_write_vfta(struct e1000_hw *hw,
5931 uint32_t offset,
5932 uint32_t value)
5933 {
5934 uint32_t temp;
5935
5936 if (hw->mac_type == e1000_ich8lan)
5937 return;
5938
5939 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
5940 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
5941 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
5942 E1000_WRITE_FLUSH(hw);
5943 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
5944 E1000_WRITE_FLUSH(hw);
5945 } else {
5946 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
5947 E1000_WRITE_FLUSH(hw);
5948 }
5949 }
5950
5951 /******************************************************************************
5952 * Clears the VLAN filer table
5953 *
5954 * hw - Struct containing variables accessed by shared code
5955 *****************************************************************************/
5956 static void
5957 e1000_clear_vfta(struct e1000_hw *hw)
5958 {
5959 uint32_t offset;
5960 uint32_t vfta_value = 0;
5961 uint32_t vfta_offset = 0;
5962 uint32_t vfta_bit_in_reg = 0;
5963
5964 if (hw->mac_type == e1000_ich8lan)
5965 return;
5966
5967 if (hw->mac_type == e1000_82573) {
5968 if (hw->mng_cookie.vlan_id != 0) {
5969 /* The VFTA is a 4096b bit-field, each identifying a single VLAN
5970 * ID. The following operations determine which 32b entry
5971 * (i.e. offset) into the array we want to set the VLAN ID
5972 * (i.e. bit) of the manageability unit. */
5973 vfta_offset = (hw->mng_cookie.vlan_id >>
5974 E1000_VFTA_ENTRY_SHIFT) &
5975 E1000_VFTA_ENTRY_MASK;
5976 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
5977 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
5978 }
5979 }
5980 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
5981 /* If the offset we want to clear is the same offset of the
5982 * manageability VLAN ID, then clear all bits except that of the
5983 * manageability unit */
5984 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
5985 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
5986 E1000_WRITE_FLUSH(hw);
5987 }
5988 }
5989
5990 static int32_t
5991 e1000_id_led_init(struct e1000_hw * hw)
5992 {
5993 uint32_t ledctl;
5994 const uint32_t ledctl_mask = 0x000000FF;
5995 const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON;
5996 const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
5997 uint16_t eeprom_data, i, temp;
5998 const uint16_t led_mask = 0x0F;
5999
6000 DEBUGFUNC("e1000_id_led_init");
6001
6002 if (hw->mac_type < e1000_82540) {
6003 /* Nothing to do */
6004 return E1000_SUCCESS;
6005 }
6006
6007 ledctl = E1000_READ_REG(hw, LEDCTL);
6008 hw->ledctl_default = ledctl;
6009 hw->ledctl_mode1 = hw->ledctl_default;
6010 hw->ledctl_mode2 = hw->ledctl_default;
6011
6012 if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
6013 DEBUGOUT("EEPROM Read Error\n");
6014 return -E1000_ERR_EEPROM;
6015 }
6016
6017 if ((hw->mac_type == e1000_82573) &&
6018 (eeprom_data == ID_LED_RESERVED_82573))
6019 eeprom_data = ID_LED_DEFAULT_82573;
6020 else if ((eeprom_data == ID_LED_RESERVED_0000) ||
6021 (eeprom_data == ID_LED_RESERVED_FFFF)) {
6022 if (hw->mac_type == e1000_ich8lan)
6023 eeprom_data = ID_LED_DEFAULT_ICH8LAN;
6024 else
6025 eeprom_data = ID_LED_DEFAULT;
6026 }
6027 for (i = 0; i < 4; i++) {
6028 temp = (eeprom_data >> (i << 2)) & led_mask;
6029 switch (temp) {
6030 case ID_LED_ON1_DEF2:
6031 case ID_LED_ON1_ON2:
6032 case ID_LED_ON1_OFF2:
6033 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
6034 hw->ledctl_mode1 |= ledctl_on << (i << 3);
6035 break;
6036 case ID_LED_OFF1_DEF2:
6037 case ID_LED_OFF1_ON2:
6038 case ID_LED_OFF1_OFF2:
6039 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
6040 hw->ledctl_mode1 |= ledctl_off << (i << 3);
6041 break;
6042 default:
6043 /* Do nothing */
6044 break;
6045 }
6046 switch (temp) {
6047 case ID_LED_DEF1_ON2:
6048 case ID_LED_ON1_ON2:
6049 case ID_LED_OFF1_ON2:
6050 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
6051 hw->ledctl_mode2 |= ledctl_on << (i << 3);
6052 break;
6053 case ID_LED_DEF1_OFF2:
6054 case ID_LED_ON1_OFF2:
6055 case ID_LED_OFF1_OFF2:
6056 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
6057 hw->ledctl_mode2 |= ledctl_off << (i << 3);
6058 break;
6059 default:
6060 /* Do nothing */
6061 break;
6062 }
6063 }
6064 return E1000_SUCCESS;
6065 }
6066
6067 /******************************************************************************
6068 * Prepares SW controlable LED for use and saves the current state of the LED.
6069 *
6070 * hw - Struct containing variables accessed by shared code
6071 *****************************************************************************/
6072 int32_t
6073 e1000_setup_led(struct e1000_hw *hw)
6074 {
6075 uint32_t ledctl;
6076 int32_t ret_val = E1000_SUCCESS;
6077
6078 DEBUGFUNC("e1000_setup_led");
6079
6080 switch (hw->mac_type) {
6081 case e1000_82542_rev2_0:
6082 case e1000_82542_rev2_1:
6083 case e1000_82543:
6084 case e1000_82544:
6085 /* No setup necessary */
6086 break;
6087 case e1000_82541:
6088 case e1000_82547:
6089 case e1000_82541_rev_2:
6090 case e1000_82547_rev_2:
6091 /* Turn off PHY Smart Power Down (if enabled) */
6092 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
6093 &hw->phy_spd_default);
6094 if (ret_val)
6095 return ret_val;
6096 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
6097 (uint16_t)(hw->phy_spd_default &
6098 ~IGP01E1000_GMII_SPD));
6099 if (ret_val)
6100 return ret_val;
6101 /* Fall Through */
6102 default:
6103 if (hw->media_type == e1000_media_type_fiber) {
6104 ledctl = E1000_READ_REG(hw, LEDCTL);
6105 /* Save current LEDCTL settings */
6106 hw->ledctl_default = ledctl;
6107 /* Turn off LED0 */
6108 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
6109 E1000_LEDCTL_LED0_BLINK |
6110 E1000_LEDCTL_LED0_MODE_MASK);
6111 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
6112 E1000_LEDCTL_LED0_MODE_SHIFT);
6113 E1000_WRITE_REG(hw, LEDCTL, ledctl);
6114 } else if (hw->media_type == e1000_media_type_copper)
6115 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
6116 break;
6117 }
6118
6119 return E1000_SUCCESS;
6120 }
6121
6122
6123 /******************************************************************************
6124 * Used on 82571 and later Si that has LED blink bits.
6125 * Callers must use their own timer and should have already called
6126 * e1000_id_led_init()
6127 * Call e1000_cleanup led() to stop blinking
6128 *
6129 * hw - Struct containing variables accessed by shared code
6130 *****************************************************************************/
6131 int32_t
6132 e1000_blink_led_start(struct e1000_hw *hw)
6133 {
6134 int16_t i;
6135 uint32_t ledctl_blink = 0;
6136
6137 DEBUGFUNC("e1000_id_led_blink_on");
6138
6139 if (hw->mac_type < e1000_82571) {
6140 /* Nothing to do */
6141 return E1000_SUCCESS;
6142 }
6143 if (hw->media_type == e1000_media_type_fiber) {
6144 /* always blink LED0 for PCI-E fiber */
6145 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
6146 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
6147 } else {
6148 /* set the blink bit for each LED that's "on" (0x0E) in ledctl_mode2 */
6149 ledctl_blink = hw->ledctl_mode2;
6150 for (i=0; i < 4; i++)
6151 if (((hw->ledctl_mode2 >> (i * 8)) & 0xFF) ==
6152 E1000_LEDCTL_MODE_LED_ON)
6153 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << (i * 8));
6154 }
6155
6156 E1000_WRITE_REG(hw, LEDCTL, ledctl_blink);
6157
6158 return E1000_SUCCESS;
6159 }
6160
6161 /******************************************************************************
6162 * Restores the saved state of the SW controlable LED.
6163 *
6164 * hw - Struct containing variables accessed by shared code
6165 *****************************************************************************/
6166 int32_t
6167 e1000_cleanup_led(struct e1000_hw *hw)
6168 {
6169 int32_t ret_val = E1000_SUCCESS;
6170
6171 DEBUGFUNC("e1000_cleanup_led");
6172
6173 switch (hw->mac_type) {
6174 case e1000_82542_rev2_0:
6175 case e1000_82542_rev2_1:
6176 case e1000_82543:
6177 case e1000_82544:
6178 /* No cleanup necessary */
6179 break;
6180 case e1000_82541:
6181 case e1000_82547:
6182 case e1000_82541_rev_2:
6183 case e1000_82547_rev_2:
6184 /* Turn on PHY Smart Power Down (if previously enabled) */
6185 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
6186 hw->phy_spd_default);
6187 if (ret_val)
6188 return ret_val;
6189 /* Fall Through */
6190 default:
6191 if (hw->phy_type == e1000_phy_ife) {
6192 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
6193 break;
6194 }
6195 /* Restore LEDCTL settings */
6196 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default);
6197 break;
6198 }
6199
6200 return E1000_SUCCESS;
6201 }
6202
6203 /******************************************************************************
6204 * Turns on the software controllable LED
6205 *
6206 * hw - Struct containing variables accessed by shared code
6207 *****************************************************************************/
6208 int32_t
6209 e1000_led_on(struct e1000_hw *hw)
6210 {
6211 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
6212
6213 DEBUGFUNC("e1000_led_on");
6214
6215 switch (hw->mac_type) {
6216 case e1000_82542_rev2_0:
6217 case e1000_82542_rev2_1:
6218 case e1000_82543:
6219 /* Set SW Defineable Pin 0 to turn on the LED */
6220 ctrl |= E1000_CTRL_SWDPIN0;
6221 ctrl |= E1000_CTRL_SWDPIO0;
6222 break;
6223 case e1000_82544:
6224 if (hw->media_type == e1000_media_type_fiber) {
6225 /* Set SW Defineable Pin 0 to turn on the LED */
6226 ctrl |= E1000_CTRL_SWDPIN0;
6227 ctrl |= E1000_CTRL_SWDPIO0;
6228 } else {
6229 /* Clear SW Defineable Pin 0 to turn on the LED */
6230 ctrl &= ~E1000_CTRL_SWDPIN0;
6231 ctrl |= E1000_CTRL_SWDPIO0;
6232 }
6233 break;
6234 default:
6235 if (hw->media_type == e1000_media_type_fiber) {
6236 /* Clear SW Defineable Pin 0 to turn on the LED */
6237 ctrl &= ~E1000_CTRL_SWDPIN0;
6238 ctrl |= E1000_CTRL_SWDPIO0;
6239 } else if (hw->phy_type == e1000_phy_ife) {
6240 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6241 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
6242 } else if (hw->media_type == e1000_media_type_copper) {
6243 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2);
6244 return E1000_SUCCESS;
6245 }
6246 break;
6247 }
6248
6249 E1000_WRITE_REG(hw, CTRL, ctrl);
6250
6251 return E1000_SUCCESS;
6252 }
6253
6254 /******************************************************************************
6255 * Turns off the software controllable LED
6256 *
6257 * hw - Struct containing variables accessed by shared code
6258 *****************************************************************************/
6259 int32_t
6260 e1000_led_off(struct e1000_hw *hw)
6261 {
6262 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
6263
6264 DEBUGFUNC("e1000_led_off");
6265
6266 switch (hw->mac_type) {
6267 case e1000_82542_rev2_0:
6268 case e1000_82542_rev2_1:
6269 case e1000_82543:
6270 /* Clear SW Defineable Pin 0 to turn off the LED */
6271 ctrl &= ~E1000_CTRL_SWDPIN0;
6272 ctrl |= E1000_CTRL_SWDPIO0;
6273 break;
6274 case e1000_82544:
6275 if (hw->media_type == e1000_media_type_fiber) {
6276 /* Clear SW Defineable Pin 0 to turn off the LED */
6277 ctrl &= ~E1000_CTRL_SWDPIN0;
6278 ctrl |= E1000_CTRL_SWDPIO0;
6279 } else {
6280 /* Set SW Defineable Pin 0 to turn off the LED */
6281 ctrl |= E1000_CTRL_SWDPIN0;
6282 ctrl |= E1000_CTRL_SWDPIO0;
6283 }
6284 break;
6285 default:
6286 if (hw->media_type == e1000_media_type_fiber) {
6287 /* Set SW Defineable Pin 0 to turn off the LED */
6288 ctrl |= E1000_CTRL_SWDPIN0;
6289 ctrl |= E1000_CTRL_SWDPIO0;
6290 } else if (hw->phy_type == e1000_phy_ife) {
6291 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6292 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
6293 } else if (hw->media_type == e1000_media_type_copper) {
6294 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
6295 return E1000_SUCCESS;
6296 }
6297 break;
6298 }
6299
6300 E1000_WRITE_REG(hw, CTRL, ctrl);
6301
6302 return E1000_SUCCESS;
6303 }
6304
6305 /******************************************************************************
6306 * Clears all hardware statistics counters.
6307 *
6308 * hw - Struct containing variables accessed by shared code
6309 *****************************************************************************/
6310 static void
6311 e1000_clear_hw_cntrs(struct e1000_hw *hw)
6312 {
6313 volatile uint32_t temp;
6314
6315 temp = E1000_READ_REG(hw, CRCERRS);
6316 temp = E1000_READ_REG(hw, SYMERRS);
6317 temp = E1000_READ_REG(hw, MPC);
6318 temp = E1000_READ_REG(hw, SCC);
6319 temp = E1000_READ_REG(hw, ECOL);
6320 temp = E1000_READ_REG(hw, MCC);
6321 temp = E1000_READ_REG(hw, LATECOL);
6322 temp = E1000_READ_REG(hw, COLC);
6323 temp = E1000_READ_REG(hw, DC);
6324 temp = E1000_READ_REG(hw, SEC);
6325 temp = E1000_READ_REG(hw, RLEC);
6326 temp = E1000_READ_REG(hw, XONRXC);
6327 temp = E1000_READ_REG(hw, XONTXC);
6328 temp = E1000_READ_REG(hw, XOFFRXC);
6329 temp = E1000_READ_REG(hw, XOFFTXC);
6330 temp = E1000_READ_REG(hw, FCRUC);
6331
6332 if (hw->mac_type != e1000_ich8lan) {
6333 temp = E1000_READ_REG(hw, PRC64);
6334 temp = E1000_READ_REG(hw, PRC127);
6335 temp = E1000_READ_REG(hw, PRC255);
6336 temp = E1000_READ_REG(hw, PRC511);
6337 temp = E1000_READ_REG(hw, PRC1023);
6338 temp = E1000_READ_REG(hw, PRC1522);
6339 }
6340
6341 temp = E1000_READ_REG(hw, GPRC);
6342 temp = E1000_READ_REG(hw, BPRC);
6343 temp = E1000_READ_REG(hw, MPRC);
6344 temp = E1000_READ_REG(hw, GPTC);
6345 temp = E1000_READ_REG(hw, GORCL);
6346 temp = E1000_READ_REG(hw, GORCH);
6347 temp = E1000_READ_REG(hw, GOTCL);
6348 temp = E1000_READ_REG(hw, GOTCH);
6349 temp = E1000_READ_REG(hw, RNBC);
6350 temp = E1000_READ_REG(hw, RUC);
6351 temp = E1000_READ_REG(hw, RFC);
6352 temp = E1000_READ_REG(hw, ROC);
6353 temp = E1000_READ_REG(hw, RJC);
6354 temp = E1000_READ_REG(hw, TORL);
6355 temp = E1000_READ_REG(hw, TORH);
6356 temp = E1000_READ_REG(hw, TOTL);
6357 temp = E1000_READ_REG(hw, TOTH);
6358 temp = E1000_READ_REG(hw, TPR);
6359 temp = E1000_READ_REG(hw, TPT);
6360
6361 if (hw->mac_type != e1000_ich8lan) {
6362 temp = E1000_READ_REG(hw, PTC64);
6363 temp = E1000_READ_REG(hw, PTC127);
6364 temp = E1000_READ_REG(hw, PTC255);
6365 temp = E1000_READ_REG(hw, PTC511);
6366 temp = E1000_READ_REG(hw, PTC1023);
6367 temp = E1000_READ_REG(hw, PTC1522);
6368 }
6369
6370 temp = E1000_READ_REG(hw, MPTC);
6371 temp = E1000_READ_REG(hw, BPTC);
6372
6373 if (hw->mac_type < e1000_82543) return;
6374
6375 temp = E1000_READ_REG(hw, ALGNERRC);
6376 temp = E1000_READ_REG(hw, RXERRC);
6377 temp = E1000_READ_REG(hw, TNCRS);
6378 temp = E1000_READ_REG(hw, CEXTERR);
6379 temp = E1000_READ_REG(hw, TSCTC);
6380 temp = E1000_READ_REG(hw, TSCTFC);
6381
6382 if (hw->mac_type <= e1000_82544) return;
6383
6384 temp = E1000_READ_REG(hw, MGTPRC);
6385 temp = E1000_READ_REG(hw, MGTPDC);
6386 temp = E1000_READ_REG(hw, MGTPTC);
6387
6388 if (hw->mac_type <= e1000_82547_rev_2) return;
6389
6390 temp = E1000_READ_REG(hw, IAC);
6391 temp = E1000_READ_REG(hw, ICRXOC);
6392
6393 if (hw->mac_type == e1000_ich8lan) return;
6394
6395 temp = E1000_READ_REG(hw, ICRXPTC);
6396 temp = E1000_READ_REG(hw, ICRXATC);
6397 temp = E1000_READ_REG(hw, ICTXPTC);
6398 temp = E1000_READ_REG(hw, ICTXATC);
6399 temp = E1000_READ_REG(hw, ICTXQEC);
6400 temp = E1000_READ_REG(hw, ICTXQMTC);
6401 temp = E1000_READ_REG(hw, ICRXDMTC);
6402 }
6403
6404 /******************************************************************************
6405 * Resets Adaptive IFS to its default state.
6406 *
6407 * hw - Struct containing variables accessed by shared code
6408 *
6409 * Call this after e1000_init_hw. You may override the IFS defaults by setting
6410 * hw->ifs_params_forced to TRUE. However, you must initialize hw->
6411 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
6412 * before calling this function.
6413 *****************************************************************************/
6414 void
6415 e1000_reset_adaptive(struct e1000_hw *hw)
6416 {
6417 DEBUGFUNC("e1000_reset_adaptive");
6418
6419 if (hw->adaptive_ifs) {
6420 if (!hw->ifs_params_forced) {
6421 hw->current_ifs_val = 0;
6422 hw->ifs_min_val = IFS_MIN;
6423 hw->ifs_max_val = IFS_MAX;
6424 hw->ifs_step_size = IFS_STEP;
6425 hw->ifs_ratio = IFS_RATIO;
6426 }
6427 hw->in_ifs_mode = FALSE;
6428 E1000_WRITE_REG(hw, AIT, 0);
6429 } else {
6430 DEBUGOUT("Not in Adaptive IFS mode!\n");
6431 }
6432 }
6433
6434 /******************************************************************************
6435 * Called during the callback/watchdog routine to update IFS value based on
6436 * the ratio of transmits to collisions.
6437 *
6438 * hw - Struct containing variables accessed by shared code
6439 * tx_packets - Number of transmits since last callback
6440 * total_collisions - Number of collisions since last callback
6441 *****************************************************************************/
6442 void
6443 e1000_update_adaptive(struct e1000_hw *hw)
6444 {
6445 DEBUGFUNC("e1000_update_adaptive");
6446
6447 if (hw->adaptive_ifs) {
6448 if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
6449 if (hw->tx_packet_delta > MIN_NUM_XMITS) {
6450 hw->in_ifs_mode = TRUE;
6451 if (hw->current_ifs_val < hw->ifs_max_val) {
6452 if (hw->current_ifs_val == 0)
6453 hw->current_ifs_val = hw->ifs_min_val;
6454 else
6455 hw->current_ifs_val += hw->ifs_step_size;
6456 E1000_WRITE_REG(hw, AIT, hw->current_ifs_val);
6457 }
6458 }
6459 } else {
6460 if (hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
6461 hw->current_ifs_val = 0;
6462 hw->in_ifs_mode = FALSE;
6463 E1000_WRITE_REG(hw, AIT, 0);
6464 }
6465 }
6466 } else {
6467 DEBUGOUT("Not in Adaptive IFS mode!\n");
6468 }
6469 }
6470
6471 /******************************************************************************
6472 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
6473 *
6474 * hw - Struct containing variables accessed by shared code
6475 * frame_len - The length of the frame in question
6476 * mac_addr - The Ethernet destination address of the frame in question
6477 *****************************************************************************/
6478 void
6479 e1000_tbi_adjust_stats(struct e1000_hw *hw,
6480 struct e1000_hw_stats *stats,
6481 uint32_t frame_len,
6482 uint8_t *mac_addr)
6483 {
6484 uint64_t carry_bit;
6485
6486 /* First adjust the frame length. */
6487 frame_len--;
6488 /* We need to adjust the statistics counters, since the hardware
6489 * counters overcount this packet as a CRC error and undercount
6490 * the packet as a good packet
6491 */
6492 /* This packet should not be counted as a CRC error. */
6493 stats->crcerrs--;
6494 /* This packet does count as a Good Packet Received. */
6495 stats->gprc++;
6496
6497 /* Adjust the Good Octets received counters */
6498 carry_bit = 0x80000000 & stats->gorcl;
6499 stats->gorcl += frame_len;
6500 /* If the high bit of Gorcl (the low 32 bits of the Good Octets
6501 * Received Count) was one before the addition,
6502 * AND it is zero after, then we lost the carry out,
6503 * need to add one to Gorch (Good Octets Received Count High).
6504 * This could be simplified if all environments supported
6505 * 64-bit integers.
6506 */
6507 if (carry_bit && ((stats->gorcl & 0x80000000) == 0))
6508 stats->gorch++;
6509 /* Is this a broadcast or multicast? Check broadcast first,
6510 * since the test for a multicast frame will test positive on
6511 * a broadcast frame.
6512 */
6513 if ((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff))
6514 /* Broadcast packet */
6515 stats->bprc++;
6516 else if (*mac_addr & 0x01)
6517 /* Multicast packet */
6518 stats->mprc++;
6519
6520 if (frame_len == hw->max_frame_size) {
6521 /* In this case, the hardware has overcounted the number of
6522 * oversize frames.
6523 */
6524 if (stats->roc > 0)
6525 stats->roc--;
6526 }
6527
6528 /* Adjust the bin counters when the extra byte put the frame in the
6529 * wrong bin. Remember that the frame_len was adjusted above.
6530 */
6531 if (frame_len == 64) {
6532 stats->prc64++;
6533 stats->prc127--;
6534 } else if (frame_len == 127) {
6535 stats->prc127++;
6536 stats->prc255--;
6537 } else if (frame_len == 255) {
6538 stats->prc255++;
6539 stats->prc511--;
6540 } else if (frame_len == 511) {
6541 stats->prc511++;
6542 stats->prc1023--;
6543 } else if (frame_len == 1023) {
6544 stats->prc1023++;
6545 stats->prc1522--;
6546 } else if (frame_len == 1522) {
6547 stats->prc1522++;
6548 }
6549 }
6550
6551 /******************************************************************************
6552 * Gets the current PCI bus type, speed, and width of the hardware
6553 *
6554 * hw - Struct containing variables accessed by shared code
6555 *****************************************************************************/
6556 void
6557 e1000_get_bus_info(struct e1000_hw *hw)
6558 {
6559 uint32_t status;
6560
6561 switch (hw->mac_type) {
6562 case e1000_82542_rev2_0:
6563 case e1000_82542_rev2_1:
6564 hw->bus_type = e1000_bus_type_unknown;
6565 hw->bus_speed = e1000_bus_speed_unknown;
6566 hw->bus_width = e1000_bus_width_unknown;
6567 break;
6568 case e1000_82572:
6569 case e1000_82573:
6570 hw->bus_type = e1000_bus_type_pci_express;
6571 hw->bus_speed = e1000_bus_speed_2500;
6572 hw->bus_width = e1000_bus_width_pciex_1;
6573 break;
6574 case e1000_82571:
6575 case e1000_ich8lan:
6576 case e1000_80003es2lan:
6577 hw->bus_type = e1000_bus_type_pci_express;
6578 hw->bus_speed = e1000_bus_speed_2500;
6579 hw->bus_width = e1000_bus_width_pciex_4;
6580 break;
6581 default:
6582 status = E1000_READ_REG(hw, STATUS);
6583 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
6584 e1000_bus_type_pcix : e1000_bus_type_pci;
6585
6586 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
6587 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
6588 e1000_bus_speed_66 : e1000_bus_speed_120;
6589 } else if (hw->bus_type == e1000_bus_type_pci) {
6590 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
6591 e1000_bus_speed_66 : e1000_bus_speed_33;
6592 } else {
6593 switch (status & E1000_STATUS_PCIX_SPEED) {
6594 case E1000_STATUS_PCIX_SPEED_66:
6595 hw->bus_speed = e1000_bus_speed_66;
6596 break;
6597 case E1000_STATUS_PCIX_SPEED_100:
6598 hw->bus_speed = e1000_bus_speed_100;
6599 break;
6600 case E1000_STATUS_PCIX_SPEED_133:
6601 hw->bus_speed = e1000_bus_speed_133;
6602 break;
6603 default:
6604 hw->bus_speed = e1000_bus_speed_reserved;
6605 break;
6606 }
6607 }
6608 hw->bus_width = (status & E1000_STATUS_BUS64) ?
6609 e1000_bus_width_64 : e1000_bus_width_32;
6610 break;
6611 }
6612 }
6613
6614 /******************************************************************************
6615 * Writes a value to one of the devices registers using port I/O (as opposed to
6616 * memory mapped I/O). Only 82544 and newer devices support port I/O.
6617 *
6618 * hw - Struct containing variables accessed by shared code
6619 * offset - offset to write to
6620 * value - value to write
6621 *****************************************************************************/
6622 static void
6623 e1000_write_reg_io(struct e1000_hw *hw,
6624 uint32_t offset,
6625 uint32_t value)
6626 {
6627 unsigned long io_addr = hw->io_base;
6628 unsigned long io_data = hw->io_base + 4;
6629
6630 e1000_io_write(hw, io_addr, offset);
6631 e1000_io_write(hw, io_data, value);
6632 }
6633
6634 /******************************************************************************
6635 * Estimates the cable length.
6636 *
6637 * hw - Struct containing variables accessed by shared code
6638 * min_length - The estimated minimum length
6639 * max_length - The estimated maximum length
6640 *
6641 * returns: - E1000_ERR_XXX
6642 * E1000_SUCCESS
6643 *
6644 * This function always returns a ranged length (minimum & maximum).
6645 * So for M88 phy's, this function interprets the one value returned from the
6646 * register to the minimum and maximum range.
6647 * For IGP phy's, the function calculates the range by the AGC registers.
6648 *****************************************************************************/
6649 static int32_t
6650 e1000_get_cable_length(struct e1000_hw *hw,
6651 uint16_t *min_length,
6652 uint16_t *max_length)
6653 {
6654 int32_t ret_val;
6655 uint16_t agc_value = 0;
6656 uint16_t i, phy_data;
6657 uint16_t cable_length;
6658
6659 DEBUGFUNC("e1000_get_cable_length");
6660
6661 *min_length = *max_length = 0;
6662
6663 /* Use old method for Phy older than IGP */
6664 if (hw->phy_type == e1000_phy_m88) {
6665
6666 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6667 &phy_data);
6668 if (ret_val)
6669 return ret_val;
6670 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
6671 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
6672
6673 /* Convert the enum value to ranged values */
6674 switch (cable_length) {
6675 case e1000_cable_length_50:
6676 *min_length = 0;
6677 *max_length = e1000_igp_cable_length_50;
6678 break;
6679 case e1000_cable_length_50_80:
6680 *min_length = e1000_igp_cable_length_50;
6681 *max_length = e1000_igp_cable_length_80;
6682 break;
6683 case e1000_cable_length_80_110:
6684 *min_length = e1000_igp_cable_length_80;
6685 *max_length = e1000_igp_cable_length_110;
6686 break;
6687 case e1000_cable_length_110_140:
6688 *min_length = e1000_igp_cable_length_110;
6689 *max_length = e1000_igp_cable_length_140;
6690 break;
6691 case e1000_cable_length_140:
6692 *min_length = e1000_igp_cable_length_140;
6693 *max_length = e1000_igp_cable_length_170;
6694 break;
6695 default:
6696 return -E1000_ERR_PHY;
6697 break;
6698 }
6699 } else if (hw->phy_type == e1000_phy_gg82563) {
6700 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
6701 &phy_data);
6702 if (ret_val)
6703 return ret_val;
6704 cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH;
6705
6706 switch (cable_length) {
6707 case e1000_gg_cable_length_60:
6708 *min_length = 0;
6709 *max_length = e1000_igp_cable_length_60;
6710 break;
6711 case e1000_gg_cable_length_60_115:
6712 *min_length = e1000_igp_cable_length_60;
6713 *max_length = e1000_igp_cable_length_115;
6714 break;
6715 case e1000_gg_cable_length_115_150:
6716 *min_length = e1000_igp_cable_length_115;
6717 *max_length = e1000_igp_cable_length_150;
6718 break;
6719 case e1000_gg_cable_length_150:
6720 *min_length = e1000_igp_cable_length_150;
6721 *max_length = e1000_igp_cable_length_180;
6722 break;
6723 default:
6724 return -E1000_ERR_PHY;
6725 break;
6726 }
6727 } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
6728 uint16_t cur_agc_value;
6729 uint16_t min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
6730 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
6731 {IGP01E1000_PHY_AGC_A,
6732 IGP01E1000_PHY_AGC_B,
6733 IGP01E1000_PHY_AGC_C,
6734 IGP01E1000_PHY_AGC_D};
6735 /* Read the AGC registers for all channels */
6736 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
6737
6738 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
6739 if (ret_val)
6740 return ret_val;
6741
6742 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
6743
6744 /* Value bound check. */
6745 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
6746 (cur_agc_value == 0))
6747 return -E1000_ERR_PHY;
6748
6749 agc_value += cur_agc_value;
6750
6751 /* Update minimal AGC value. */
6752 if (min_agc_value > cur_agc_value)
6753 min_agc_value = cur_agc_value;
6754 }
6755
6756 /* Remove the minimal AGC result for length < 50m */
6757 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
6758 agc_value -= min_agc_value;
6759
6760 /* Get the average length of the remaining 3 channels */
6761 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
6762 } else {
6763 /* Get the average length of all the 4 channels. */
6764 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
6765 }
6766
6767 /* Set the range of the calculated length. */
6768 *min_length = ((e1000_igp_cable_length_table[agc_value] -
6769 IGP01E1000_AGC_RANGE) > 0) ?
6770 (e1000_igp_cable_length_table[agc_value] -
6771 IGP01E1000_AGC_RANGE) : 0;
6772 *max_length = e1000_igp_cable_length_table[agc_value] +
6773 IGP01E1000_AGC_RANGE;
6774 } else if (hw->phy_type == e1000_phy_igp_2 ||
6775 hw->phy_type == e1000_phy_igp_3) {
6776 uint16_t cur_agc_index, max_agc_index = 0;
6777 uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1;
6778 uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
6779 {IGP02E1000_PHY_AGC_A,
6780 IGP02E1000_PHY_AGC_B,
6781 IGP02E1000_PHY_AGC_C,
6782 IGP02E1000_PHY_AGC_D};
6783 /* Read the AGC registers for all channels */
6784 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
6785 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
6786 if (ret_val)
6787 return ret_val;
6788
6789 /* Getting bits 15:9, which represent the combination of course and
6790 * fine gain values. The result is a number that can be put into
6791 * the lookup table to obtain the approximate cable length. */
6792 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
6793 IGP02E1000_AGC_LENGTH_MASK;
6794
6795 /* Array index bound check. */
6796 if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) ||
6797 (cur_agc_index == 0))
6798 return -E1000_ERR_PHY;
6799
6800 /* Remove min & max AGC values from calculation. */
6801 if (e1000_igp_2_cable_length_table[min_agc_index] >
6802 e1000_igp_2_cable_length_table[cur_agc_index])
6803 min_agc_index = cur_agc_index;
6804 if (e1000_igp_2_cable_length_table[max_agc_index] <
6805 e1000_igp_2_cable_length_table[cur_agc_index])
6806 max_agc_index = cur_agc_index;
6807
6808 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
6809 }
6810
6811 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
6812 e1000_igp_2_cable_length_table[max_agc_index]);
6813 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
6814
6815 /* Calculate cable length with the error range of +/- 10 meters. */
6816 *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
6817 (agc_value - IGP02E1000_AGC_RANGE) : 0;
6818 *max_length = agc_value + IGP02E1000_AGC_RANGE;
6819 }
6820
6821 return E1000_SUCCESS;
6822 }
6823
6824 /******************************************************************************
6825 * Check the cable polarity
6826 *
6827 * hw - Struct containing variables accessed by shared code
6828 * polarity - output parameter : 0 - Polarity is not reversed
6829 * 1 - Polarity is reversed.
6830 *
6831 * returns: - E1000_ERR_XXX
6832 * E1000_SUCCESS
6833 *
6834 * For phy's older then IGP, this function simply reads the polarity bit in the
6835 * Phy Status register. For IGP phy's, this bit is valid only if link speed is
6836 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will
6837 * return 0. If the link speed is 1000 Mbps the polarity status is in the
6838 * IGP01E1000_PHY_PCS_INIT_REG.
6839 *****************************************************************************/
6840 static int32_t
6841 e1000_check_polarity(struct e1000_hw *hw,
6842 e1000_rev_polarity *polarity)
6843 {
6844 int32_t ret_val;
6845 uint16_t phy_data;
6846
6847 DEBUGFUNC("e1000_check_polarity");
6848
6849 if ((hw->phy_type == e1000_phy_m88) ||
6850 (hw->phy_type == e1000_phy_gg82563)) {
6851 /* return the Polarity bit in the Status register. */
6852 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6853 &phy_data);
6854 if (ret_val)
6855 return ret_val;
6856 *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >>
6857 M88E1000_PSSR_REV_POLARITY_SHIFT) ?
6858 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
6859
6860 } else if (hw->phy_type == e1000_phy_igp ||
6861 hw->phy_type == e1000_phy_igp_3 ||
6862 hw->phy_type == e1000_phy_igp_2) {
6863 /* Read the Status register to check the speed */
6864 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
6865 &phy_data);
6866 if (ret_val)
6867 return ret_val;
6868
6869 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
6870 * find the polarity status */
6871 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
6872 IGP01E1000_PSSR_SPEED_1000MBPS) {
6873
6874 /* Read the GIG initialization PCS register (0x00B4) */
6875 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
6876 &phy_data);
6877 if (ret_val)
6878 return ret_val;
6879
6880 /* Check the polarity bits */
6881 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ?
6882 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
6883 } else {
6884 /* For 10 Mbps, read the polarity bit in the status register. (for
6885 * 100 Mbps this bit is always 0) */
6886 *polarity = (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ?
6887 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
6888 }
6889 } else if (hw->phy_type == e1000_phy_ife) {
6890 ret_val = e1000_read_phy_reg(hw, IFE_PHY_EXTENDED_STATUS_CONTROL,
6891 &phy_data);
6892 if (ret_val)
6893 return ret_val;
6894 *polarity = ((phy_data & IFE_PESC_POLARITY_REVERSED) >>
6895 IFE_PESC_POLARITY_REVERSED_SHIFT) ?
6896 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
6897 }
6898 return E1000_SUCCESS;
6899 }
6900
6901 /******************************************************************************
6902 * Check if Downshift occured
6903 *
6904 * hw - Struct containing variables accessed by shared code
6905 * downshift - output parameter : 0 - No Downshift ocured.
6906 * 1 - Downshift ocured.
6907 *
6908 * returns: - E1000_ERR_XXX
6909 * E1000_SUCCESS
6910 *
6911 * For phy's older then IGP, this function reads the Downshift bit in the Phy
6912 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the
6913 * Link Health register. In IGP this bit is latched high, so the driver must
6914 * read it immediately after link is established.
6915 *****************************************************************************/
6916 static int32_t
6917 e1000_check_downshift(struct e1000_hw *hw)
6918 {
6919 int32_t ret_val;
6920 uint16_t phy_data;
6921
6922 DEBUGFUNC("e1000_check_downshift");
6923
6924 if (hw->phy_type == e1000_phy_igp ||
6925 hw->phy_type == e1000_phy_igp_3 ||
6926 hw->phy_type == e1000_phy_igp_2) {
6927 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
6928 &phy_data);
6929 if (ret_val)
6930 return ret_val;
6931
6932 hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
6933 } else if ((hw->phy_type == e1000_phy_m88) ||
6934 (hw->phy_type == e1000_phy_gg82563)) {
6935 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6936 &phy_data);
6937 if (ret_val)
6938 return ret_val;
6939
6940 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
6941 M88E1000_PSSR_DOWNSHIFT_SHIFT;
6942 } else if (hw->phy_type == e1000_phy_ife) {
6943 /* e1000_phy_ife supports 10/100 speed only */
6944 hw->speed_downgraded = FALSE;
6945 }
6946
6947 return E1000_SUCCESS;
6948 }
6949
6950 /*****************************************************************************
6951 *
6952 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
6953 * gigabit link is achieved to improve link quality.
6954 *
6955 * hw: Struct containing variables accessed by shared code
6956 *
6957 * returns: - E1000_ERR_PHY if fail to read/write the PHY
6958 * E1000_SUCCESS at any other case.
6959 *
6960 ****************************************************************************/
6961
6962 static int32_t
6963 e1000_config_dsp_after_link_change(struct e1000_hw *hw,
6964 boolean_t link_up)
6965 {
6966 int32_t ret_val;
6967 uint16_t phy_data, phy_saved_data, speed, duplex, i;
6968 uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
6969 {IGP01E1000_PHY_AGC_PARAM_A,
6970 IGP01E1000_PHY_AGC_PARAM_B,
6971 IGP01E1000_PHY_AGC_PARAM_C,
6972 IGP01E1000_PHY_AGC_PARAM_D};
6973 uint16_t min_length, max_length;
6974
6975 DEBUGFUNC("e1000_config_dsp_after_link_change");
6976
6977 if (hw->phy_type != e1000_phy_igp)
6978 return E1000_SUCCESS;
6979
6980 if (link_up) {
6981 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
6982 if (ret_val) {
6983 DEBUGOUT("Error getting link speed and duplex\n");
6984 return ret_val;
6985 }
6986
6987 if (speed == SPEED_1000) {
6988
6989 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
6990 if (ret_val)
6991 return ret_val;
6992
6993 if ((hw->dsp_config_state == e1000_dsp_config_enabled) &&
6994 min_length >= e1000_igp_cable_length_50) {
6995
6996 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
6997 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
6998 &phy_data);
6999 if (ret_val)
7000 return ret_val;
7001
7002 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
7003
7004 ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],
7005 phy_data);
7006 if (ret_val)
7007 return ret_val;
7008 }
7009 hw->dsp_config_state = e1000_dsp_config_activated;
7010 }
7011
7012 if ((hw->ffe_config_state == e1000_ffe_config_enabled) &&
7013 (min_length < e1000_igp_cable_length_50)) {
7014
7015 uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
7016 uint32_t idle_errs = 0;
7017
7018 /* clear previous idle error counts */
7019 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
7020 &phy_data);
7021 if (ret_val)
7022 return ret_val;
7023
7024 for (i = 0; i < ffe_idle_err_timeout; i++) {
7025 udelay(1000);
7026 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
7027 &phy_data);
7028 if (ret_val)
7029 return ret_val;
7030
7031 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
7032 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
7033 hw->ffe_config_state = e1000_ffe_config_active;
7034
7035 ret_val = e1000_write_phy_reg(hw,
7036 IGP01E1000_PHY_DSP_FFE,
7037 IGP01E1000_PHY_DSP_FFE_CM_CP);
7038 if (ret_val)
7039 return ret_val;
7040 break;
7041 }
7042
7043 if (idle_errs)
7044 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100;
7045 }
7046 }
7047 }
7048 } else {
7049 if (hw->dsp_config_state == e1000_dsp_config_activated) {
7050 /* Save off the current value of register 0x2F5B to be restored at
7051 * the end of the routines. */
7052 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
7053
7054 if (ret_val)
7055 return ret_val;
7056
7057 /* Disable the PHY transmitter */
7058 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
7059
7060 if (ret_val)
7061 return ret_val;
7062
7063 mdelay(20);
7064
7065 ret_val = e1000_write_phy_reg(hw, 0x0000,
7066 IGP01E1000_IEEE_FORCE_GIGA);
7067 if (ret_val)
7068 return ret_val;
7069 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
7070 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data);
7071 if (ret_val)
7072 return ret_val;
7073
7074 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
7075 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
7076
7077 ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data);
7078 if (ret_val)
7079 return ret_val;
7080 }
7081
7082 ret_val = e1000_write_phy_reg(hw, 0x0000,
7083 IGP01E1000_IEEE_RESTART_AUTONEG);
7084 if (ret_val)
7085 return ret_val;
7086
7087 mdelay(20);
7088
7089 /* Now enable the transmitter */
7090 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7091
7092 if (ret_val)
7093 return ret_val;
7094
7095 hw->dsp_config_state = e1000_dsp_config_enabled;
7096 }
7097
7098 if (hw->ffe_config_state == e1000_ffe_config_active) {
7099 /* Save off the current value of register 0x2F5B to be restored at
7100 * the end of the routines. */
7101 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
7102
7103 if (ret_val)
7104 return ret_val;
7105
7106 /* Disable the PHY transmitter */
7107 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
7108
7109 if (ret_val)
7110 return ret_val;
7111
7112 mdelay(20);
7113
7114 ret_val = e1000_write_phy_reg(hw, 0x0000,
7115 IGP01E1000_IEEE_FORCE_GIGA);
7116 if (ret_val)
7117 return ret_val;
7118 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
7119 IGP01E1000_PHY_DSP_FFE_DEFAULT);
7120 if (ret_val)
7121 return ret_val;
7122
7123 ret_val = e1000_write_phy_reg(hw, 0x0000,
7124 IGP01E1000_IEEE_RESTART_AUTONEG);
7125 if (ret_val)
7126 return ret_val;
7127
7128 mdelay(20);
7129
7130 /* Now enable the transmitter */
7131 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7132
7133 if (ret_val)
7134 return ret_val;
7135
7136 hw->ffe_config_state = e1000_ffe_config_enabled;
7137 }
7138 }
7139 return E1000_SUCCESS;
7140 }
7141
7142 /*****************************************************************************
7143 * Set PHY to class A mode
7144 * Assumes the following operations will follow to enable the new class mode.
7145 * 1. Do a PHY soft reset
7146 * 2. Restart auto-negotiation or force link.
7147 *
7148 * hw - Struct containing variables accessed by shared code
7149 ****************************************************************************/
7150 static int32_t
7151 e1000_set_phy_mode(struct e1000_hw *hw)
7152 {
7153 int32_t ret_val;
7154 uint16_t eeprom_data;
7155
7156 DEBUGFUNC("e1000_set_phy_mode");
7157
7158 if ((hw->mac_type == e1000_82545_rev_3) &&
7159 (hw->media_type == e1000_media_type_copper)) {
7160 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data);
7161 if (ret_val) {
7162 return ret_val;
7163 }
7164
7165 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
7166 (eeprom_data & EEPROM_PHY_CLASS_A)) {
7167 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B);
7168 if (ret_val)
7169 return ret_val;
7170 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104);
7171 if (ret_val)
7172 return ret_val;
7173
7174 hw->phy_reset_disable = FALSE;
7175 }
7176 }
7177
7178 return E1000_SUCCESS;
7179 }
7180
7181 /*****************************************************************************
7182 *
7183 * This function sets the lplu state according to the active flag. When
7184 * activating lplu this function also disables smart speed and vise versa.
7185 * lplu will not be activated unless the device autonegotiation advertisment
7186 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
7187 * hw: Struct containing variables accessed by shared code
7188 * active - true to enable lplu false to disable lplu.
7189 *
7190 * returns: - E1000_ERR_PHY if fail to read/write the PHY
7191 * E1000_SUCCESS at any other case.
7192 *
7193 ****************************************************************************/
7194
7195 static int32_t
7196 e1000_set_d3_lplu_state(struct e1000_hw *hw,
7197 boolean_t active)
7198 {
7199 uint32_t phy_ctrl = 0;
7200 int32_t ret_val;
7201 uint16_t phy_data;
7202 DEBUGFUNC("e1000_set_d3_lplu_state");
7203
7204 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
7205 && hw->phy_type != e1000_phy_igp_3)
7206 return E1000_SUCCESS;
7207
7208 /* During driver activity LPLU should not be used or it will attain link
7209 * from the lowest speeds starting from 10Mbps. The capability is used for
7210 * Dx transitions and states */
7211 if (hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) {
7212 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
7213 if (ret_val)
7214 return ret_val;
7215 } else if (hw->mac_type == e1000_ich8lan) {
7216 /* MAC writes into PHY register based on the state transition
7217 * and start auto-negotiation. SW driver can overwrite the settings
7218 * in CSR PHY power control E1000_PHY_CTRL register. */
7219 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
7220 } else {
7221 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
7222 if (ret_val)
7223 return ret_val;
7224 }
7225
7226 if (!active) {
7227 if (hw->mac_type == e1000_82541_rev_2 ||
7228 hw->mac_type == e1000_82547_rev_2) {
7229 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
7230 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
7231 if (ret_val)
7232 return ret_val;
7233 } else {
7234 if (hw->mac_type == e1000_ich8lan) {
7235 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
7236 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7237 } else {
7238 phy_data &= ~IGP02E1000_PM_D3_LPLU;
7239 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
7240 phy_data);
7241 if (ret_val)
7242 return ret_val;
7243 }
7244 }
7245
7246 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
7247 * Dx states where the power conservation is most important. During
7248 * driver activity we should enable SmartSpeed, so performance is
7249 * maintained. */
7250 if (hw->smart_speed == e1000_smart_speed_on) {
7251 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7252 &phy_data);
7253 if (ret_val)
7254 return ret_val;
7255
7256 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
7257 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7258 phy_data);
7259 if (ret_val)
7260 return ret_val;
7261 } else if (hw->smart_speed == e1000_smart_speed_off) {
7262 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7263 &phy_data);
7264 if (ret_val)
7265 return ret_val;
7266
7267 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7268 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7269 phy_data);
7270 if (ret_val)
7271 return ret_val;
7272 }
7273
7274 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
7275 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
7276 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
7277
7278 if (hw->mac_type == e1000_82541_rev_2 ||
7279 hw->mac_type == e1000_82547_rev_2) {
7280 phy_data |= IGP01E1000_GMII_FLEX_SPD;
7281 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
7282 if (ret_val)
7283 return ret_val;
7284 } else {
7285 if (hw->mac_type == e1000_ich8lan) {
7286 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
7287 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7288 } else {
7289 phy_data |= IGP02E1000_PM_D3_LPLU;
7290 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
7291 phy_data);
7292 if (ret_val)
7293 return ret_val;
7294 }
7295 }
7296
7297 /* When LPLU is enabled we should disable SmartSpeed */
7298 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
7299 if (ret_val)
7300 return ret_val;
7301
7302 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7303 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
7304 if (ret_val)
7305 return ret_val;
7306
7307 }
7308 return E1000_SUCCESS;
7309 }
7310
7311 /*****************************************************************************
7312 *
7313 * This function sets the lplu d0 state according to the active flag. When
7314 * activating lplu this function also disables smart speed and vise versa.
7315 * lplu will not be activated unless the device autonegotiation advertisment
7316 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
7317 * hw: Struct containing variables accessed by shared code
7318 * active - true to enable lplu false to disable lplu.
7319 *
7320 * returns: - E1000_ERR_PHY if fail to read/write the PHY
7321 * E1000_SUCCESS at any other case.
7322 *
7323 ****************************************************************************/
7324
7325 static int32_t
7326 e1000_set_d0_lplu_state(struct e1000_hw *hw,
7327 boolean_t active)
7328 {
7329 uint32_t phy_ctrl = 0;
7330 int32_t ret_val;
7331 uint16_t phy_data;
7332 DEBUGFUNC("e1000_set_d0_lplu_state");
7333
7334 if (hw->mac_type <= e1000_82547_rev_2)
7335 return E1000_SUCCESS;
7336
7337 if (hw->mac_type == e1000_ich8lan) {
7338 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
7339 } else {
7340 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
7341 if (ret_val)
7342 return ret_val;
7343 }
7344
7345 if (!active) {
7346 if (hw->mac_type == e1000_ich8lan) {
7347 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
7348 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7349 } else {
7350 phy_data &= ~IGP02E1000_PM_D0_LPLU;
7351 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
7352 if (ret_val)
7353 return ret_val;
7354 }
7355
7356 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
7357 * Dx states where the power conservation is most important. During
7358 * driver activity we should enable SmartSpeed, so performance is
7359 * maintained. */
7360 if (hw->smart_speed == e1000_smart_speed_on) {
7361 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7362 &phy_data);
7363 if (ret_val)
7364 return ret_val;
7365
7366 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
7367 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7368 phy_data);
7369 if (ret_val)
7370 return ret_val;
7371 } else if (hw->smart_speed == e1000_smart_speed_off) {
7372 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7373 &phy_data);
7374 if (ret_val)
7375 return ret_val;
7376
7377 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7378 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7379 phy_data);
7380 if (ret_val)
7381 return ret_val;
7382 }
7383
7384
7385 } else {
7386
7387 if (hw->mac_type == e1000_ich8lan) {
7388 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
7389 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7390 } else {
7391 phy_data |= IGP02E1000_PM_D0_LPLU;
7392 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
7393 if (ret_val)
7394 return ret_val;
7395 }
7396
7397 /* When LPLU is enabled we should disable SmartSpeed */
7398 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
7399 if (ret_val)
7400 return ret_val;
7401
7402 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7403 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
7404 if (ret_val)
7405 return ret_val;
7406
7407 }
7408 return E1000_SUCCESS;
7409 }
7410
7411 /******************************************************************************
7412 * Change VCO speed register to improve Bit Error Rate performance of SERDES.
7413 *
7414 * hw - Struct containing variables accessed by shared code
7415 *****************************************************************************/
7416 static int32_t
7417 e1000_set_vco_speed(struct e1000_hw *hw)
7418 {
7419 int32_t ret_val;
7420 uint16_t default_page = 0;
7421 uint16_t phy_data;
7422
7423 DEBUGFUNC("e1000_set_vco_speed");
7424
7425 switch (hw->mac_type) {
7426 case e1000_82545_rev_3:
7427 case e1000_82546_rev_3:
7428 break;
7429 default:
7430 return E1000_SUCCESS;
7431 }
7432
7433 /* Set PHY register 30, page 5, bit 8 to 0 */
7434
7435 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
7436 if (ret_val)
7437 return ret_val;
7438
7439 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
7440 if (ret_val)
7441 return ret_val;
7442
7443 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
7444 if (ret_val)
7445 return ret_val;
7446
7447 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
7448 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
7449 if (ret_val)
7450 return ret_val;
7451
7452 /* Set PHY register 30, page 4, bit 11 to 1 */
7453
7454 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
7455 if (ret_val)
7456 return ret_val;
7457
7458 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
7459 if (ret_val)
7460 return ret_val;
7461
7462 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
7463 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
7464 if (ret_val)
7465 return ret_val;
7466
7467 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
7468 if (ret_val)
7469 return ret_val;
7470
7471 return E1000_SUCCESS;
7472 }
7473
7474
7475 /*****************************************************************************
7476 * This function reads the cookie from ARC ram.
7477 *
7478 * returns: - E1000_SUCCESS .
7479 ****************************************************************************/
7480 static int32_t
7481 e1000_host_if_read_cookie(struct e1000_hw * hw, uint8_t *buffer)
7482 {
7483 uint8_t i;
7484 uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET;
7485 uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH;
7486
7487 length = (length >> 2);
7488 offset = (offset >> 2);
7489
7490 for (i = 0; i < length; i++) {
7491 *((uint32_t *) buffer + i) =
7492 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i);
7493 }
7494 return E1000_SUCCESS;
7495 }
7496
7497
7498 /*****************************************************************************
7499 * This function checks whether the HOST IF is enabled for command operaton
7500 * and also checks whether the previous command is completed.
7501 * It busy waits in case of previous command is not completed.
7502 *
7503 * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or
7504 * timeout
7505 * - E1000_SUCCESS for success.
7506 ****************************************************************************/
7507 static int32_t
7508 e1000_mng_enable_host_if(struct e1000_hw * hw)
7509 {
7510 uint32_t hicr;
7511 uint8_t i;
7512
7513 /* Check that the host interface is enabled. */
7514 hicr = E1000_READ_REG(hw, HICR);
7515 if ((hicr & E1000_HICR_EN) == 0) {
7516 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
7517 return -E1000_ERR_HOST_INTERFACE_COMMAND;
7518 }
7519 /* check the previous command is completed */
7520 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
7521 hicr = E1000_READ_REG(hw, HICR);
7522 if (!(hicr & E1000_HICR_C))
7523 break;
7524 mdelay(1);
7525 }
7526
7527 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
7528 DEBUGOUT("Previous command timeout failed .\n");
7529 return -E1000_ERR_HOST_INTERFACE_COMMAND;
7530 }
7531 return E1000_SUCCESS;
7532 }
7533
7534 /*****************************************************************************
7535 * This function writes the buffer content at the offset given on the host if.
7536 * It also does alignment considerations to do the writes in most efficient way.
7537 * Also fills up the sum of the buffer in *buffer parameter.
7538 *
7539 * returns - E1000_SUCCESS for success.
7540 ****************************************************************************/
7541 static int32_t
7542 e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer,
7543 uint16_t length, uint16_t offset, uint8_t *sum)
7544 {
7545 uint8_t *tmp;
7546 uint8_t *bufptr = buffer;
7547 uint32_t data = 0;
7548 uint16_t remaining, i, j, prev_bytes;
7549
7550 /* sum = only sum of the data and it is not checksum */
7551
7552 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) {
7553 return -E1000_ERR_PARAM;
7554 }
7555
7556 tmp = (uint8_t *)&data;
7557 prev_bytes = offset & 0x3;
7558 offset &= 0xFFFC;
7559 offset >>= 2;
7560
7561 if (prev_bytes) {
7562 data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset);
7563 for (j = prev_bytes; j < sizeof(uint32_t); j++) {
7564 *(tmp + j) = *bufptr++;
7565 *sum += *(tmp + j);
7566 }
7567 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data);
7568 length -= j - prev_bytes;
7569 offset++;
7570 }
7571
7572 remaining = length & 0x3;
7573 length -= remaining;
7574
7575 /* Calculate length in DWORDs */
7576 length >>= 2;
7577
7578 /* The device driver writes the relevant command block into the
7579 * ram area. */
7580 for (i = 0; i < length; i++) {
7581 for (j = 0; j < sizeof(uint32_t); j++) {
7582 *(tmp + j) = *bufptr++;
7583 *sum += *(tmp + j);
7584 }
7585
7586 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
7587 }
7588 if (remaining) {
7589 for (j = 0; j < sizeof(uint32_t); j++) {
7590 if (j < remaining)
7591 *(tmp + j) = *bufptr++;
7592 else
7593 *(tmp + j) = 0;
7594
7595 *sum += *(tmp + j);
7596 }
7597 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
7598 }
7599
7600 return E1000_SUCCESS;
7601 }
7602
7603
7604 /*****************************************************************************
7605 * This function writes the command header after does the checksum calculation.
7606 *
7607 * returns - E1000_SUCCESS for success.
7608 ****************************************************************************/
7609 static int32_t
7610 e1000_mng_write_cmd_header(struct e1000_hw * hw,
7611 struct e1000_host_mng_command_header * hdr)
7612 {
7613 uint16_t i;
7614 uint8_t sum;
7615 uint8_t *buffer;
7616
7617 /* Write the whole command header structure which includes sum of
7618 * the buffer */
7619
7620 uint16_t length = sizeof(struct e1000_host_mng_command_header);
7621
7622 sum = hdr->checksum;
7623 hdr->checksum = 0;
7624
7625 buffer = (uint8_t *) hdr;
7626 i = length;
7627 while (i--)
7628 sum += buffer[i];
7629
7630 hdr->checksum = 0 - sum;
7631
7632 length >>= 2;
7633 /* The device driver writes the relevant command block into the ram area. */
7634 for (i = 0; i < length; i++) {
7635 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i));
7636 E1000_WRITE_FLUSH(hw);
7637 }
7638
7639 return E1000_SUCCESS;
7640 }
7641
7642
7643 /*****************************************************************************
7644 * This function indicates to ARC that a new command is pending which completes
7645 * one write operation by the driver.
7646 *
7647 * returns - E1000_SUCCESS for success.
7648 ****************************************************************************/
7649 static int32_t
7650 e1000_mng_write_commit(struct e1000_hw * hw)
7651 {
7652 uint32_t hicr;
7653
7654 hicr = E1000_READ_REG(hw, HICR);
7655 /* Setting this bit tells the ARC that a new command is pending. */
7656 E1000_WRITE_REG(hw, HICR, hicr | E1000_HICR_C);
7657
7658 return E1000_SUCCESS;
7659 }
7660
7661
7662 /*****************************************************************************
7663 * This function checks the mode of the firmware.
7664 *
7665 * returns - TRUE when the mode is IAMT or FALSE.
7666 ****************************************************************************/
7667 boolean_t
7668 e1000_check_mng_mode(struct e1000_hw *hw)
7669 {
7670 uint32_t fwsm;
7671
7672 fwsm = E1000_READ_REG(hw, FWSM);
7673
7674 if (hw->mac_type == e1000_ich8lan) {
7675 if ((fwsm & E1000_FWSM_MODE_MASK) ==
7676 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
7677 return TRUE;
7678 } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
7679 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
7680 return TRUE;
7681
7682 return FALSE;
7683 }
7684
7685
7686 /*****************************************************************************
7687 * This function writes the dhcp info .
7688 ****************************************************************************/
7689 int32_t
7690 e1000_mng_write_dhcp_info(struct e1000_hw * hw, uint8_t *buffer,
7691 uint16_t length)
7692 {
7693 int32_t ret_val;
7694 struct e1000_host_mng_command_header hdr;
7695
7696 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
7697 hdr.command_length = length;
7698 hdr.reserved1 = 0;
7699 hdr.reserved2 = 0;
7700 hdr.checksum = 0;
7701
7702 ret_val = e1000_mng_enable_host_if(hw);
7703 if (ret_val == E1000_SUCCESS) {
7704 ret_val = e1000_mng_host_if_write(hw, buffer, length, sizeof(hdr),
7705 &(hdr.checksum));
7706 if (ret_val == E1000_SUCCESS) {
7707 ret_val = e1000_mng_write_cmd_header(hw, &hdr);
7708 if (ret_val == E1000_SUCCESS)
7709 ret_val = e1000_mng_write_commit(hw);
7710 }
7711 }
7712 return ret_val;
7713 }
7714
7715
7716 /*****************************************************************************
7717 * This function calculates the checksum.
7718 *
7719 * returns - checksum of buffer contents.
7720 ****************************************************************************/
7721 static uint8_t
7722 e1000_calculate_mng_checksum(char *buffer, uint32_t length)
7723 {
7724 uint8_t sum = 0;
7725 uint32_t i;
7726
7727 if (!buffer)
7728 return 0;
7729
7730 for (i=0; i < length; i++)
7731 sum += buffer[i];
7732
7733 return (uint8_t) (0 - sum);
7734 }
7735
7736 /*****************************************************************************
7737 * This function checks whether tx pkt filtering needs to be enabled or not.
7738 *
7739 * returns - TRUE for packet filtering or FALSE.
7740 ****************************************************************************/
7741 boolean_t
7742 e1000_enable_tx_pkt_filtering(struct e1000_hw *hw)
7743 {
7744 /* called in init as well as watchdog timer functions */
7745
7746 int32_t ret_val, checksum;
7747 boolean_t tx_filter = FALSE;
7748 struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie);
7749 uint8_t *buffer = (uint8_t *) &(hw->mng_cookie);
7750
7751 if (e1000_check_mng_mode(hw)) {
7752 ret_val = e1000_mng_enable_host_if(hw);
7753 if (ret_val == E1000_SUCCESS) {
7754 ret_val = e1000_host_if_read_cookie(hw, buffer);
7755 if (ret_val == E1000_SUCCESS) {
7756 checksum = hdr->checksum;
7757 hdr->checksum = 0;
7758 if ((hdr->signature == E1000_IAMT_SIGNATURE) &&
7759 checksum == e1000_calculate_mng_checksum((char *)buffer,
7760 E1000_MNG_DHCP_COOKIE_LENGTH)) {
7761 if (hdr->status &
7762 E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT)
7763 tx_filter = TRUE;
7764 } else
7765 tx_filter = TRUE;
7766 } else
7767 tx_filter = TRUE;
7768 }
7769 }
7770
7771 hw->tx_pkt_filtering = tx_filter;
7772 return tx_filter;
7773 }
7774
7775 /******************************************************************************
7776 * Verifies the hardware needs to allow ARPs to be processed by the host
7777 *
7778 * hw - Struct containing variables accessed by shared code
7779 *
7780 * returns: - TRUE/FALSE
7781 *
7782 *****************************************************************************/
7783 uint32_t
7784 e1000_enable_mng_pass_thru(struct e1000_hw *hw)
7785 {
7786 uint32_t manc;
7787 uint32_t fwsm, factps;
7788
7789 if (hw->asf_firmware_present) {
7790 manc = E1000_READ_REG(hw, MANC);
7791
7792 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
7793 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
7794 return FALSE;
7795 if (e1000_arc_subsystem_valid(hw) == TRUE) {
7796 fwsm = E1000_READ_REG(hw, FWSM);
7797 factps = E1000_READ_REG(hw, FACTPS);
7798
7799 if (((fwsm & E1000_FWSM_MODE_MASK) ==
7800 (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT)) &&
7801 (factps & E1000_FACTPS_MNGCG))
7802 return TRUE;
7803 } else
7804 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
7805 return TRUE;
7806 }
7807 return FALSE;
7808 }
7809
7810 static int32_t
7811 e1000_polarity_reversal_workaround(struct e1000_hw *hw)
7812 {
7813 int32_t ret_val;
7814 uint16_t mii_status_reg;
7815 uint16_t i;
7816
7817 /* Polarity reversal workaround for forced 10F/10H links. */
7818
7819 /* Disable the transmitter on the PHY */
7820
7821 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
7822 if (ret_val)
7823 return ret_val;
7824 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
7825 if (ret_val)
7826 return ret_val;
7827
7828 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
7829 if (ret_val)
7830 return ret_val;
7831
7832 /* This loop will early-out if the NO link condition has been met. */
7833 for (i = PHY_FORCE_TIME; i > 0; i--) {
7834 /* Read the MII Status Register and wait for Link Status bit
7835 * to be clear.
7836 */
7837
7838 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7839 if (ret_val)
7840 return ret_val;
7841
7842 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7843 if (ret_val)
7844 return ret_val;
7845
7846 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break;
7847 mdelay(100);
7848 }
7849
7850 /* Recommended delay time after link has been lost */
7851 mdelay(1000);
7852
7853 /* Now we will re-enable th transmitter on the PHY */
7854
7855 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
7856 if (ret_val)
7857 return ret_val;
7858 mdelay(50);
7859 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
7860 if (ret_val)
7861 return ret_val;
7862 mdelay(50);
7863 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
7864 if (ret_val)
7865 return ret_val;
7866 mdelay(50);
7867 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
7868 if (ret_val)
7869 return ret_val;
7870
7871 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
7872 if (ret_val)
7873 return ret_val;
7874
7875 /* This loop will early-out if the link condition has been met. */
7876 for (i = PHY_FORCE_TIME; i > 0; i--) {
7877 /* Read the MII Status Register and wait for Link Status bit
7878 * to be set.
7879 */
7880
7881 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7882 if (ret_val)
7883 return ret_val;
7884
7885 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7886 if (ret_val)
7887 return ret_val;
7888
7889 if (mii_status_reg & MII_SR_LINK_STATUS) break;
7890 mdelay(100);
7891 }
7892 return E1000_SUCCESS;
7893 }
7894
7895 /***************************************************************************
7896 *
7897 * Disables PCI-Express master access.
7898 *
7899 * hw: Struct containing variables accessed by shared code
7900 *
7901 * returns: - none.
7902 *
7903 ***************************************************************************/
7904 static void
7905 e1000_set_pci_express_master_disable(struct e1000_hw *hw)
7906 {
7907 uint32_t ctrl;
7908
7909 DEBUGFUNC("e1000_set_pci_express_master_disable");
7910
7911 if (hw->bus_type != e1000_bus_type_pci_express)
7912 return;
7913
7914 ctrl = E1000_READ_REG(hw, CTRL);
7915 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
7916 E1000_WRITE_REG(hw, CTRL, ctrl);
7917 }
7918
7919 /*******************************************************************************
7920 *
7921 * Disables PCI-Express master access and verifies there are no pending requests
7922 *
7923 * hw: Struct containing variables accessed by shared code
7924 *
7925 * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't
7926 * caused the master requests to be disabled.
7927 * E1000_SUCCESS master requests disabled.
7928 *
7929 ******************************************************************************/
7930 int32_t
7931 e1000_disable_pciex_master(struct e1000_hw *hw)
7932 {
7933 int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */
7934
7935 DEBUGFUNC("e1000_disable_pciex_master");
7936
7937 if (hw->bus_type != e1000_bus_type_pci_express)
7938 return E1000_SUCCESS;
7939
7940 e1000_set_pci_express_master_disable(hw);
7941
7942 while (timeout) {
7943 if (!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
7944 break;
7945 else
7946 udelay(100);
7947 timeout--;
7948 }
7949
7950 if (!timeout) {
7951 DEBUGOUT("Master requests are pending.\n");
7952 return -E1000_ERR_MASTER_REQUESTS_PENDING;
7953 }
7954
7955 return E1000_SUCCESS;
7956 }
7957
7958 /*******************************************************************************
7959 *
7960 * Check for EEPROM Auto Read bit done.
7961 *
7962 * hw: Struct containing variables accessed by shared code
7963 *
7964 * returns: - E1000_ERR_RESET if fail to reset MAC
7965 * E1000_SUCCESS at any other case.
7966 *
7967 ******************************************************************************/
7968 static int32_t
7969 e1000_get_auto_rd_done(struct e1000_hw *hw)
7970 {
7971 int32_t timeout = AUTO_READ_DONE_TIMEOUT;
7972
7973 DEBUGFUNC("e1000_get_auto_rd_done");
7974
7975 switch (hw->mac_type) {
7976 default:
7977 msleep(5);
7978 break;
7979 case e1000_82571:
7980 case e1000_82572:
7981 case e1000_82573:
7982 case e1000_80003es2lan:
7983 case e1000_ich8lan:
7984 while (timeout) {
7985 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD)
7986 break;
7987 else msleep(1);
7988 timeout--;
7989 }
7990
7991 if (!timeout) {
7992 DEBUGOUT("Auto read by HW from EEPROM has not completed.\n");
7993 return -E1000_ERR_RESET;
7994 }
7995 break;
7996 }
7997
7998 /* PHY configuration from NVM just starts after EECD_AUTO_RD sets to high.
7999 * Need to wait for PHY configuration completion before accessing NVM
8000 * and PHY. */
8001 if (hw->mac_type == e1000_82573)
8002 msleep(25);
8003
8004 return E1000_SUCCESS;
8005 }
8006
8007 /***************************************************************************
8008 * Checks if the PHY configuration is done
8009 *
8010 * hw: Struct containing variables accessed by shared code
8011 *
8012 * returns: - E1000_ERR_RESET if fail to reset MAC
8013 * E1000_SUCCESS at any other case.
8014 *
8015 ***************************************************************************/
8016 static int32_t
8017 e1000_get_phy_cfg_done(struct e1000_hw *hw)
8018 {
8019 int32_t timeout = PHY_CFG_TIMEOUT;
8020 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
8021
8022 DEBUGFUNC("e1000_get_phy_cfg_done");
8023
8024 switch (hw->mac_type) {
8025 default:
8026 mdelay(10);
8027 break;
8028 case e1000_80003es2lan:
8029 /* Separate *_CFG_DONE_* bit for each port */
8030 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
8031 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
8032 /* Fall Through */
8033 case e1000_82571:
8034 case e1000_82572:
8035 while (timeout) {
8036 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
8037 break;
8038 else
8039 msleep(1);
8040 timeout--;
8041 }
8042 if (!timeout) {
8043 DEBUGOUT("MNG configuration cycle has not completed.\n");
8044 return -E1000_ERR_RESET;
8045 }
8046 break;
8047 }
8048
8049 return E1000_SUCCESS;
8050 }
8051
8052 /***************************************************************************
8053 *
8054 * Using the combination of SMBI and SWESMBI semaphore bits when resetting
8055 * adapter or Eeprom access.
8056 *
8057 * hw: Struct containing variables accessed by shared code
8058 *
8059 * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
8060 * E1000_SUCCESS at any other case.
8061 *
8062 ***************************************************************************/
8063 static int32_t
8064 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
8065 {
8066 int32_t timeout;
8067 uint32_t swsm;
8068
8069 DEBUGFUNC("e1000_get_hw_eeprom_semaphore");
8070
8071 if (!hw->eeprom_semaphore_present)
8072 return E1000_SUCCESS;
8073
8074 if (hw->mac_type == e1000_80003es2lan) {
8075 /* Get the SW semaphore. */
8076 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
8077 return -E1000_ERR_EEPROM;
8078 }
8079
8080 /* Get the FW semaphore. */
8081 timeout = hw->eeprom.word_size + 1;
8082 while (timeout) {
8083 swsm = E1000_READ_REG(hw, SWSM);
8084 swsm |= E1000_SWSM_SWESMBI;
8085 E1000_WRITE_REG(hw, SWSM, swsm);
8086 /* if we managed to set the bit we got the semaphore. */
8087 swsm = E1000_READ_REG(hw, SWSM);
8088 if (swsm & E1000_SWSM_SWESMBI)
8089 break;
8090
8091 udelay(50);
8092 timeout--;
8093 }
8094
8095 if (!timeout) {
8096 /* Release semaphores */
8097 e1000_put_hw_eeprom_semaphore(hw);
8098 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n");
8099 return -E1000_ERR_EEPROM;
8100 }
8101
8102 return E1000_SUCCESS;
8103 }
8104
8105 /***************************************************************************
8106 * This function clears HW semaphore bits.
8107 *
8108 * hw: Struct containing variables accessed by shared code
8109 *
8110 * returns: - None.
8111 *
8112 ***************************************************************************/
8113 static void
8114 e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
8115 {
8116 uint32_t swsm;
8117
8118 DEBUGFUNC("e1000_put_hw_eeprom_semaphore");
8119
8120 if (!hw->eeprom_semaphore_present)
8121 return;
8122
8123 swsm = E1000_READ_REG(hw, SWSM);
8124 if (hw->mac_type == e1000_80003es2lan) {
8125 /* Release both semaphores. */
8126 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
8127 } else
8128 swsm &= ~(E1000_SWSM_SWESMBI);
8129 E1000_WRITE_REG(hw, SWSM, swsm);
8130 }
8131
8132 /***************************************************************************
8133 *
8134 * Obtaining software semaphore bit (SMBI) before resetting PHY.
8135 *
8136 * hw: Struct containing variables accessed by shared code
8137 *
8138 * returns: - E1000_ERR_RESET if fail to obtain semaphore.
8139 * E1000_SUCCESS at any other case.
8140 *
8141 ***************************************************************************/
8142 static int32_t
8143 e1000_get_software_semaphore(struct e1000_hw *hw)
8144 {
8145 int32_t timeout = hw->eeprom.word_size + 1;
8146 uint32_t swsm;
8147
8148 DEBUGFUNC("e1000_get_software_semaphore");
8149
8150 if (hw->mac_type != e1000_80003es2lan) {
8151 return E1000_SUCCESS;
8152 }
8153
8154 while (timeout) {
8155 swsm = E1000_READ_REG(hw, SWSM);
8156 /* If SMBI bit cleared, it is now set and we hold the semaphore */
8157 if (!(swsm & E1000_SWSM_SMBI))
8158 break;
8159 mdelay(1);
8160 timeout--;
8161 }
8162
8163 if (!timeout) {
8164 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
8165 return -E1000_ERR_RESET;
8166 }
8167
8168 return E1000_SUCCESS;
8169 }
8170
8171 /***************************************************************************
8172 *
8173 * Release semaphore bit (SMBI).
8174 *
8175 * hw: Struct containing variables accessed by shared code
8176 *
8177 ***************************************************************************/
8178 static void
8179 e1000_release_software_semaphore(struct e1000_hw *hw)
8180 {
8181 uint32_t swsm;
8182
8183 DEBUGFUNC("e1000_release_software_semaphore");
8184
8185 if (hw->mac_type != e1000_80003es2lan) {
8186 return;
8187 }
8188
8189 swsm = E1000_READ_REG(hw, SWSM);
8190 /* Release the SW semaphores.*/
8191 swsm &= ~E1000_SWSM_SMBI;
8192 E1000_WRITE_REG(hw, SWSM, swsm);
8193 }
8194
8195 /******************************************************************************
8196 * Checks if PHY reset is blocked due to SOL/IDER session, for example.
8197 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
8198 * the caller to figure out how to deal with it.
8199 *
8200 * hw - Struct containing variables accessed by shared code
8201 *
8202 * returns: - E1000_BLK_PHY_RESET
8203 * E1000_SUCCESS
8204 *
8205 *****************************************************************************/
8206 int32_t
8207 e1000_check_phy_reset_block(struct e1000_hw *hw)
8208 {
8209 uint32_t manc = 0;
8210 uint32_t fwsm = 0;
8211
8212 if (hw->mac_type == e1000_ich8lan) {
8213 fwsm = E1000_READ_REG(hw, FWSM);
8214 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
8215 : E1000_BLK_PHY_RESET;
8216 }
8217
8218 if (hw->mac_type > e1000_82547_rev_2)
8219 manc = E1000_READ_REG(hw, MANC);
8220 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
8221 E1000_BLK_PHY_RESET : E1000_SUCCESS;
8222 }
8223
8224 static uint8_t
8225 e1000_arc_subsystem_valid(struct e1000_hw *hw)
8226 {
8227 uint32_t fwsm;
8228
8229 /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC
8230 * may not be provided a DMA clock when no manageability features are
8231 * enabled. We do not want to perform any reads/writes to these registers
8232 * if this is the case. We read FWSM to determine the manageability mode.
8233 */
8234 switch (hw->mac_type) {
8235 case e1000_82571:
8236 case e1000_82572:
8237 case e1000_82573:
8238 case e1000_80003es2lan:
8239 fwsm = E1000_READ_REG(hw, FWSM);
8240 if ((fwsm & E1000_FWSM_MODE_MASK) != 0)
8241 return TRUE;
8242 break;
8243 case e1000_ich8lan:
8244 return TRUE;
8245 default:
8246 break;
8247 }
8248 return FALSE;
8249 }
8250
8251
8252 /******************************************************************************
8253 * Configure PCI-Ex no-snoop
8254 *
8255 * hw - Struct containing variables accessed by shared code.
8256 * no_snoop - Bitmap of no-snoop events.
8257 *
8258 * returns: E1000_SUCCESS
8259 *
8260 *****************************************************************************/
8261 static int32_t
8262 e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop)
8263 {
8264 uint32_t gcr_reg = 0;
8265
8266 DEBUGFUNC("e1000_set_pci_ex_no_snoop");
8267
8268 if (hw->bus_type == e1000_bus_type_unknown)
8269 e1000_get_bus_info(hw);
8270
8271 if (hw->bus_type != e1000_bus_type_pci_express)
8272 return E1000_SUCCESS;
8273
8274 if (no_snoop) {
8275 gcr_reg = E1000_READ_REG(hw, GCR);
8276 gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL);
8277 gcr_reg |= no_snoop;
8278 E1000_WRITE_REG(hw, GCR, gcr_reg);
8279 }
8280 if (hw->mac_type == e1000_ich8lan) {
8281 uint32_t ctrl_ext;
8282
8283 E1000_WRITE_REG(hw, GCR, PCI_EX_82566_SNOOP_ALL);
8284
8285 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
8286 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
8287 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
8288 }
8289
8290 return E1000_SUCCESS;
8291 }
8292
8293 /***************************************************************************
8294 *
8295 * Get software semaphore FLAG bit (SWFLAG).
8296 * SWFLAG is used to synchronize the access to all shared resource between
8297 * SW, FW and HW.
8298 *
8299 * hw: Struct containing variables accessed by shared code
8300 *
8301 ***************************************************************************/
8302 static int32_t
8303 e1000_get_software_flag(struct e1000_hw *hw)
8304 {
8305 int32_t timeout = PHY_CFG_TIMEOUT;
8306 uint32_t extcnf_ctrl;
8307
8308 DEBUGFUNC("e1000_get_software_flag");
8309
8310 if (hw->mac_type == e1000_ich8lan) {
8311 while (timeout) {
8312 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
8313 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
8314 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
8315
8316 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
8317 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
8318 break;
8319 mdelay(1);
8320 timeout--;
8321 }
8322
8323 if (!timeout) {
8324 DEBUGOUT("FW or HW locks the resource too long.\n");
8325 return -E1000_ERR_CONFIG;
8326 }
8327 }
8328
8329 return E1000_SUCCESS;
8330 }
8331
8332 /***************************************************************************
8333 *
8334 * Release software semaphore FLAG bit (SWFLAG).
8335 * SWFLAG is used to synchronize the access to all shared resource between
8336 * SW, FW and HW.
8337 *
8338 * hw: Struct containing variables accessed by shared code
8339 *
8340 ***************************************************************************/
8341 static void
8342 e1000_release_software_flag(struct e1000_hw *hw)
8343 {
8344 uint32_t extcnf_ctrl;
8345
8346 DEBUGFUNC("e1000_release_software_flag");
8347
8348 if (hw->mac_type == e1000_ich8lan) {
8349 extcnf_ctrl= E1000_READ_REG(hw, EXTCNF_CTRL);
8350 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
8351 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
8352 }
8353
8354 return;
8355 }
8356
8357 /******************************************************************************
8358 * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access
8359 * register.
8360 *
8361 * hw - Struct containing variables accessed by shared code
8362 * offset - offset of word in the EEPROM to read
8363 * data - word read from the EEPROM
8364 * words - number of words to read
8365 *****************************************************************************/
8366 static int32_t
8367 e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
8368 uint16_t *data)
8369 {
8370 int32_t error = E1000_SUCCESS;
8371 uint32_t flash_bank = 0;
8372 uint32_t act_offset = 0;
8373 uint32_t bank_offset = 0;
8374 uint16_t word = 0;
8375 uint16_t i = 0;
8376
8377 /* We need to know which is the valid flash bank. In the event
8378 * that we didn't allocate eeprom_shadow_ram, we may not be
8379 * managing flash_bank. So it cannot be trusted and needs
8380 * to be updated with each read.
8381 */
8382 /* Value of bit 22 corresponds to the flash bank we're on. */
8383 flash_bank = (E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL) ? 1 : 0;
8384
8385 /* Adjust offset appropriately if we're on bank 1 - adjust for word size */
8386 bank_offset = flash_bank * (hw->flash_bank_size * 2);
8387
8388 error = e1000_get_software_flag(hw);
8389 if (error != E1000_SUCCESS)
8390 return error;
8391
8392 for (i = 0; i < words; i++) {
8393 if (hw->eeprom_shadow_ram != NULL &&
8394 hw->eeprom_shadow_ram[offset+i].modified == TRUE) {
8395 data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word;
8396 } else {
8397 /* The NVM part needs a byte offset, hence * 2 */
8398 act_offset = bank_offset + ((offset + i) * 2);
8399 error = e1000_read_ich8_word(hw, act_offset, &word);
8400 if (error != E1000_SUCCESS)
8401 break;
8402 data[i] = word;
8403 }
8404 }
8405
8406 e1000_release_software_flag(hw);
8407
8408 return error;
8409 }
8410
8411 /******************************************************************************
8412 * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access
8413 * register. Actually, writes are written to the shadow ram cache in the hw
8414 * structure hw->e1000_shadow_ram. e1000_commit_shadow_ram flushes this to
8415 * the NVM, which occurs when the NVM checksum is updated.
8416 *
8417 * hw - Struct containing variables accessed by shared code
8418 * offset - offset of word in the EEPROM to write
8419 * words - number of words to write
8420 * data - words to write to the EEPROM
8421 *****************************************************************************/
8422 static int32_t
8423 e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
8424 uint16_t *data)
8425 {
8426 uint32_t i = 0;
8427 int32_t error = E1000_SUCCESS;
8428
8429 error = e1000_get_software_flag(hw);
8430 if (error != E1000_SUCCESS)
8431 return error;
8432
8433 /* A driver can write to the NVM only if it has eeprom_shadow_ram
8434 * allocated. Subsequent reads to the modified words are read from
8435 * this cached structure as well. Writes will only go into this
8436 * cached structure unless it's followed by a call to
8437 * e1000_update_eeprom_checksum() where it will commit the changes
8438 * and clear the "modified" field.
8439 */
8440 if (hw->eeprom_shadow_ram != NULL) {
8441 for (i = 0; i < words; i++) {
8442 if ((offset + i) < E1000_SHADOW_RAM_WORDS) {
8443 hw->eeprom_shadow_ram[offset+i].modified = TRUE;
8444 hw->eeprom_shadow_ram[offset+i].eeprom_word = data[i];
8445 } else {
8446 error = -E1000_ERR_EEPROM;
8447 break;
8448 }
8449 }
8450 } else {
8451 /* Drivers have the option to not allocate eeprom_shadow_ram as long
8452 * as they don't perform any NVM writes. An attempt in doing so
8453 * will result in this error.
8454 */
8455 error = -E1000_ERR_EEPROM;
8456 }
8457
8458 e1000_release_software_flag(hw);
8459
8460 return error;
8461 }
8462
8463 /******************************************************************************
8464 * This function does initial flash setup so that a new read/write/erase cycle
8465 * can be started.
8466 *
8467 * hw - The pointer to the hw structure
8468 ****************************************************************************/
8469 static int32_t
8470 e1000_ich8_cycle_init(struct e1000_hw *hw)
8471 {
8472 union ich8_hws_flash_status hsfsts;
8473 int32_t error = E1000_ERR_EEPROM;
8474 int32_t i = 0;
8475
8476 DEBUGFUNC("e1000_ich8_cycle_init");
8477
8478 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8479
8480 /* May be check the Flash Des Valid bit in Hw status */
8481 if (hsfsts.hsf_status.fldesvalid == 0) {
8482 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.");
8483 return error;
8484 }
8485
8486 /* Clear FCERR in Hw status by writing 1 */
8487 /* Clear DAEL in Hw status by writing a 1 */
8488 hsfsts.hsf_status.flcerr = 1;
8489 hsfsts.hsf_status.dael = 1;
8490
8491 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval);
8492
8493 /* Either we should have a hardware SPI cycle in progress bit to check
8494 * against, in order to start a new cycle or FDONE bit should be changed
8495 * in the hardware so that it is 1 after harware reset, which can then be
8496 * used as an indication whether a cycle is in progress or has been
8497 * completed .. we should also have some software semaphore mechanism to
8498 * guard FDONE or the cycle in progress bit so that two threads access to
8499 * those bits can be sequentiallized or a way so that 2 threads dont
8500 * start the cycle at the same time */
8501
8502 if (hsfsts.hsf_status.flcinprog == 0) {
8503 /* There is no cycle running at present, so we can start a cycle */
8504 /* Begin by setting Flash Cycle Done. */
8505 hsfsts.hsf_status.flcdone = 1;
8506 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval);
8507 error = E1000_SUCCESS;
8508 } else {
8509 /* otherwise poll for sometime so the current cycle has a chance
8510 * to end before giving up. */
8511 for (i = 0; i < ICH8_FLASH_COMMAND_TIMEOUT; i++) {
8512 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8513 if (hsfsts.hsf_status.flcinprog == 0) {
8514 error = E1000_SUCCESS;
8515 break;
8516 }
8517 udelay(1);
8518 }
8519 if (error == E1000_SUCCESS) {
8520 /* Successful in waiting for previous cycle to timeout,
8521 * now set the Flash Cycle Done. */
8522 hsfsts.hsf_status.flcdone = 1;
8523 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval);
8524 } else {
8525 DEBUGOUT("Flash controller busy, cannot get access");
8526 }
8527 }
8528 return error;
8529 }
8530
8531 /******************************************************************************
8532 * This function starts a flash cycle and waits for its completion
8533 *
8534 * hw - The pointer to the hw structure
8535 ****************************************************************************/
8536 static int32_t
8537 e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout)
8538 {
8539 union ich8_hws_flash_ctrl hsflctl;
8540 union ich8_hws_flash_status hsfsts;
8541 int32_t error = E1000_ERR_EEPROM;
8542 uint32_t i = 0;
8543
8544 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
8545 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8546 hsflctl.hsf_ctrl.flcgo = 1;
8547 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8548
8549 /* wait till FDONE bit is set to 1 */
8550 do {
8551 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8552 if (hsfsts.hsf_status.flcdone == 1)
8553 break;
8554 udelay(1);
8555 i++;
8556 } while (i < timeout);
8557 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) {
8558 error = E1000_SUCCESS;
8559 }
8560 return error;
8561 }
8562
8563 /******************************************************************************
8564 * Reads a byte or word from the NVM using the ICH8 flash access registers.
8565 *
8566 * hw - The pointer to the hw structure
8567 * index - The index of the byte or word to read.
8568 * size - Size of data to read, 1=byte 2=word
8569 * data - Pointer to the word to store the value read.
8570 *****************************************************************************/
8571 static int32_t
8572 e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index,
8573 uint32_t size, uint16_t* data)
8574 {
8575 union ich8_hws_flash_status hsfsts;
8576 union ich8_hws_flash_ctrl hsflctl;
8577 uint32_t flash_linear_address;
8578 uint32_t flash_data = 0;
8579 int32_t error = -E1000_ERR_EEPROM;
8580 int32_t count = 0;
8581
8582 DEBUGFUNC("e1000_read_ich8_data");
8583
8584 if (size < 1 || size > 2 || data == 0x0 ||
8585 index > ICH8_FLASH_LINEAR_ADDR_MASK)
8586 return error;
8587
8588 flash_linear_address = (ICH8_FLASH_LINEAR_ADDR_MASK & index) +
8589 hw->flash_base_addr;
8590
8591 do {
8592 udelay(1);
8593 /* Steps */
8594 error = e1000_ich8_cycle_init(hw);
8595 if (error != E1000_SUCCESS)
8596 break;
8597
8598 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8599 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8600 hsflctl.hsf_ctrl.fldbcount = size - 1;
8601 hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_READ;
8602 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8603
8604 /* Write the last 24 bits of index into Flash Linear address field in
8605 * Flash Address */
8606 /* TODO: TBD maybe check the index against the size of flash */
8607
8608 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address);
8609
8610 error = e1000_ich8_flash_cycle(hw, ICH8_FLASH_COMMAND_TIMEOUT);
8611
8612 /* Check if FCERR is set to 1, if set to 1, clear it and try the whole
8613 * sequence a few more times, else read in (shift in) the Flash Data0,
8614 * the order is least significant byte first msb to lsb */
8615 if (error == E1000_SUCCESS) {
8616 flash_data = E1000_READ_ICH8_REG(hw, ICH8_FLASH_FDATA0);
8617 if (size == 1) {
8618 *data = (uint8_t)(flash_data & 0x000000FF);
8619 } else if (size == 2) {
8620 *data = (uint16_t)(flash_data & 0x0000FFFF);
8621 }
8622 break;
8623 } else {
8624 /* If we've gotten here, then things are probably completely hosed,
8625 * but if the error condition is detected, it won't hurt to give
8626 * it another try...ICH8_FLASH_CYCLE_REPEAT_COUNT times.
8627 */
8628 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8629 if (hsfsts.hsf_status.flcerr == 1) {
8630 /* Repeat for some time before giving up. */
8631 continue;
8632 } else if (hsfsts.hsf_status.flcdone == 0) {
8633 DEBUGOUT("Timeout error - flash cycle did not complete.");
8634 break;
8635 }
8636 }
8637 } while (count++ < ICH8_FLASH_CYCLE_REPEAT_COUNT);
8638
8639 return error;
8640 }
8641
8642 /******************************************************************************
8643 * Writes One /two bytes to the NVM using the ICH8 flash access registers.
8644 *
8645 * hw - The pointer to the hw structure
8646 * index - The index of the byte/word to read.
8647 * size - Size of data to read, 1=byte 2=word
8648 * data - The byte(s) to write to the NVM.
8649 *****************************************************************************/
8650 static int32_t
8651 e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size,
8652 uint16_t data)
8653 {
8654 union ich8_hws_flash_status hsfsts;
8655 union ich8_hws_flash_ctrl hsflctl;
8656 uint32_t flash_linear_address;
8657 uint32_t flash_data = 0;
8658 int32_t error = -E1000_ERR_EEPROM;
8659 int32_t count = 0;
8660
8661 DEBUGFUNC("e1000_write_ich8_data");
8662
8663 if (size < 1 || size > 2 || data > size * 0xff ||
8664 index > ICH8_FLASH_LINEAR_ADDR_MASK)
8665 return error;
8666
8667 flash_linear_address = (ICH8_FLASH_LINEAR_ADDR_MASK & index) +
8668 hw->flash_base_addr;
8669
8670 do {
8671 udelay(1);
8672 /* Steps */
8673 error = e1000_ich8_cycle_init(hw);
8674 if (error != E1000_SUCCESS)
8675 break;
8676
8677 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8678 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8679 hsflctl.hsf_ctrl.fldbcount = size -1;
8680 hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_WRITE;
8681 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8682
8683 /* Write the last 24 bits of index into Flash Linear address field in
8684 * Flash Address */
8685 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address);
8686
8687 if (size == 1)
8688 flash_data = (uint32_t)data & 0x00FF;
8689 else
8690 flash_data = (uint32_t)data;
8691
8692 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FDATA0, flash_data);
8693
8694 /* check if FCERR is set to 1 , if set to 1, clear it and try the whole
8695 * sequence a few more times else done */
8696 error = e1000_ich8_flash_cycle(hw, ICH8_FLASH_COMMAND_TIMEOUT);
8697 if (error == E1000_SUCCESS) {
8698 break;
8699 } else {
8700 /* If we're here, then things are most likely completely hosed,
8701 * but if the error condition is detected, it won't hurt to give
8702 * it another try...ICH8_FLASH_CYCLE_REPEAT_COUNT times.
8703 */
8704 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8705 if (hsfsts.hsf_status.flcerr == 1) {
8706 /* Repeat for some time before giving up. */
8707 continue;
8708 } else if (hsfsts.hsf_status.flcdone == 0) {
8709 DEBUGOUT("Timeout error - flash cycle did not complete.");
8710 break;
8711 }
8712 }
8713 } while (count++ < ICH8_FLASH_CYCLE_REPEAT_COUNT);
8714
8715 return error;
8716 }
8717
8718 /******************************************************************************
8719 * Reads a single byte from the NVM using the ICH8 flash access registers.
8720 *
8721 * hw - pointer to e1000_hw structure
8722 * index - The index of the byte to read.
8723 * data - Pointer to a byte to store the value read.
8724 *****************************************************************************/
8725 static int32_t
8726 e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t* data)
8727 {
8728 int32_t status = E1000_SUCCESS;
8729 uint16_t word = 0;
8730
8731 status = e1000_read_ich8_data(hw, index, 1, &word);
8732 if (status == E1000_SUCCESS) {
8733 *data = (uint8_t)word;
8734 }
8735
8736 return status;
8737 }
8738
8739 /******************************************************************************
8740 * Writes a single byte to the NVM using the ICH8 flash access registers.
8741 * Performs verification by reading back the value and then going through
8742 * a retry algorithm before giving up.
8743 *
8744 * hw - pointer to e1000_hw structure
8745 * index - The index of the byte to write.
8746 * byte - The byte to write to the NVM.
8747 *****************************************************************************/
8748 static int32_t
8749 e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte)
8750 {
8751 int32_t error = E1000_SUCCESS;
8752 int32_t program_retries;
8753 uint8_t temp_byte;
8754
8755 e1000_write_ich8_byte(hw, index, byte);
8756 udelay(100);
8757
8758 for (program_retries = 0; program_retries < 100; program_retries++) {
8759 e1000_read_ich8_byte(hw, index, &temp_byte);
8760 if (temp_byte == byte)
8761 break;
8762 udelay(10);
8763 e1000_write_ich8_byte(hw, index, byte);
8764 udelay(100);
8765 }
8766 if (program_retries == 100)
8767 error = E1000_ERR_EEPROM;
8768
8769 return error;
8770 }
8771
8772 /******************************************************************************
8773 * Writes a single byte to the NVM using the ICH8 flash access registers.
8774 *
8775 * hw - pointer to e1000_hw structure
8776 * index - The index of the byte to read.
8777 * data - The byte to write to the NVM.
8778 *****************************************************************************/
8779 static int32_t
8780 e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t data)
8781 {
8782 int32_t status = E1000_SUCCESS;
8783 uint16_t word = (uint16_t)data;
8784
8785 status = e1000_write_ich8_data(hw, index, 1, word);
8786
8787 return status;
8788 }
8789
8790 /******************************************************************************
8791 * Reads a word from the NVM using the ICH8 flash access registers.
8792 *
8793 * hw - pointer to e1000_hw structure
8794 * index - The starting byte index of the word to read.
8795 * data - Pointer to a word to store the value read.
8796 *****************************************************************************/
8797 static int32_t
8798 e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data)
8799 {
8800 int32_t status = E1000_SUCCESS;
8801 status = e1000_read_ich8_data(hw, index, 2, data);
8802 return status;
8803 }
8804
8805 /******************************************************************************
8806 * Writes a word to the NVM using the ICH8 flash access registers.
8807 *
8808 * hw - pointer to e1000_hw structure
8809 * index - The starting byte index of the word to read.
8810 * data - The word to write to the NVM.
8811 *****************************************************************************/
8812 #if 0
8813 int32_t
8814 e1000_write_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t data)
8815 {
8816 int32_t status = E1000_SUCCESS;
8817 status = e1000_write_ich8_data(hw, index, 2, data);
8818 return status;
8819 }
8820 #endif /* 0 */
8821
8822 /******************************************************************************
8823 * Erases the bank specified. Each bank is a 4k block. Segments are 0 based.
8824 * segment N is 4096 * N + flash_reg_addr.
8825 *
8826 * hw - pointer to e1000_hw structure
8827 * segment - 0 for first segment, 1 for second segment, etc.
8828 *****************************************************************************/
8829 static int32_t
8830 e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t segment)
8831 {
8832 union ich8_hws_flash_status hsfsts;
8833 union ich8_hws_flash_ctrl hsflctl;
8834 uint32_t flash_linear_address;
8835 int32_t count = 0;
8836 int32_t error = E1000_ERR_EEPROM;
8837 int32_t iteration, seg_size;
8838 int32_t sector_size;
8839 int32_t j = 0;
8840 int32_t error_flag = 0;
8841
8842 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8843
8844 /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */
8845 /* 00: The Hw sector is 256 bytes, hence we need to erase 16
8846 * consecutive sectors. The start index for the nth Hw sector can be
8847 * calculated as = segment * 4096 + n * 256
8848 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
8849 * The start index for the nth Hw sector can be calculated
8850 * as = segment * 4096
8851 * 10: Error condition
8852 * 11: The Hw sector size is much bigger than the size asked to
8853 * erase...error condition */
8854 if (hsfsts.hsf_status.berasesz == 0x0) {
8855 /* Hw sector size 256 */
8856 sector_size = seg_size = ICH8_FLASH_SEG_SIZE_256;
8857 iteration = ICH8_FLASH_SECTOR_SIZE / ICH8_FLASH_SEG_SIZE_256;
8858 } else if (hsfsts.hsf_status.berasesz == 0x1) {
8859 sector_size = seg_size = ICH8_FLASH_SEG_SIZE_4K;
8860 iteration = 1;
8861 } else if (hsfsts.hsf_status.berasesz == 0x3) {
8862 sector_size = seg_size = ICH8_FLASH_SEG_SIZE_64K;
8863 iteration = 1;
8864 } else {
8865 return error;
8866 }
8867
8868 for (j = 0; j < iteration ; j++) {
8869 do {
8870 count++;
8871 /* Steps */
8872 error = e1000_ich8_cycle_init(hw);
8873 if (error != E1000_SUCCESS) {
8874 error_flag = 1;
8875 break;
8876 }
8877
8878 /* Write a value 11 (block Erase) in Flash Cycle field in Hw flash
8879 * Control */
8880 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8881 hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_ERASE;
8882 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8883
8884 /* Write the last 24 bits of an index within the block into Flash
8885 * Linear address field in Flash Address. This probably needs to
8886 * be calculated here based off the on-chip segment size and the
8887 * software segment size assumed (4K) */
8888 /* TBD */
8889 flash_linear_address = segment * sector_size + j * seg_size;
8890 flash_linear_address &= ICH8_FLASH_LINEAR_ADDR_MASK;
8891 flash_linear_address += hw->flash_base_addr;
8892
8893 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address);
8894
8895 error = e1000_ich8_flash_cycle(hw, 1000000);
8896 /* Check if FCERR is set to 1. If 1, clear it and try the whole
8897 * sequence a few more times else Done */
8898 if (error == E1000_SUCCESS) {
8899 break;
8900 } else {
8901 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8902 if (hsfsts.hsf_status.flcerr == 1) {
8903 /* repeat for some time before giving up */
8904 continue;
8905 } else if (hsfsts.hsf_status.flcdone == 0) {
8906 error_flag = 1;
8907 break;
8908 }
8909 }
8910 } while ((count < ICH8_FLASH_CYCLE_REPEAT_COUNT) && !error_flag);
8911 if (error_flag == 1)
8912 break;
8913 }
8914 if (error_flag != 1)
8915 error = E1000_SUCCESS;
8916 return error;
8917 }
8918
8919 static int32_t
8920 e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
8921 uint32_t cnf_base_addr, uint32_t cnf_size)
8922 {
8923 uint32_t ret_val = E1000_SUCCESS;
8924 uint16_t word_addr, reg_data, reg_addr;
8925 uint16_t i;
8926
8927 /* cnf_base_addr is in DWORD */
8928 word_addr = (uint16_t)(cnf_base_addr << 1);
8929
8930 /* cnf_size is returned in size of dwords */
8931 for (i = 0; i < cnf_size; i++) {
8932 ret_val = e1000_read_eeprom(hw, (word_addr + i*2), 1, &reg_data);
8933 if (ret_val)
8934 return ret_val;
8935
8936 ret_val = e1000_read_eeprom(hw, (word_addr + i*2 + 1), 1, &reg_addr);
8937 if (ret_val)
8938 return ret_val;
8939
8940 ret_val = e1000_get_software_flag(hw);
8941 if (ret_val != E1000_SUCCESS)
8942 return ret_val;
8943
8944 ret_val = e1000_write_phy_reg_ex(hw, (uint32_t)reg_addr, reg_data);
8945
8946 e1000_release_software_flag(hw);
8947 }
8948
8949 return ret_val;
8950 }
8951
8952
8953 static int32_t
8954 e1000_init_lcd_from_nvm(struct e1000_hw *hw)
8955 {
8956 uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop;
8957
8958 if (hw->phy_type != e1000_phy_igp_3)
8959 return E1000_SUCCESS;
8960
8961 /* Check if SW needs configure the PHY */
8962 reg_data = E1000_READ_REG(hw, FEXTNVM);
8963 if (!(reg_data & FEXTNVM_SW_CONFIG))
8964 return E1000_SUCCESS;
8965
8966 /* Wait for basic configuration completes before proceeding*/
8967 loop = 0;
8968 do {
8969 reg_data = E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE;
8970 udelay(100);
8971 loop++;
8972 } while ((!reg_data) && (loop < 50));
8973
8974 /* Clear the Init Done bit for the next init event */
8975 reg_data = E1000_READ_REG(hw, STATUS);
8976 reg_data &= ~E1000_STATUS_LAN_INIT_DONE;
8977 E1000_WRITE_REG(hw, STATUS, reg_data);
8978
8979 /* Make sure HW does not configure LCD from PHY extended configuration
8980 before SW configuration */
8981 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
8982 if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) {
8983 reg_data = E1000_READ_REG(hw, EXTCNF_SIZE);
8984 cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH;
8985 cnf_size >>= 16;
8986 if (cnf_size) {
8987 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
8988 cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER;
8989 /* cnf_base_addr is in DWORD */
8990 cnf_base_addr >>= 16;
8991
8992 /* Configure LCD from extended configuration region. */
8993 ret_val = e1000_init_lcd_from_nvm_config_region(hw, cnf_base_addr,
8994 cnf_size);
8995 if (ret_val)
8996 return ret_val;
8997 }
8998 }
8999
9000 return E1000_SUCCESS;
9001 }
9002
9003
9004
Support for the Chinese Samsung S3C2440 based development boards