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Linux 2.6.30-rc4
[linux-2.6/mini2440.git] / drivers / net / bnx2x.h
bloba329bee25550ded2b08b6903b889d702037464d6
1 /* bnx2x.h: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2009 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 */
13
14 #ifndef BNX2X_H
15 #define BNX2X_H
16
17 /* compilation time flags */
18
19 /* define this to make the driver freeze on error to allow getting debug info
20 * (you will need to reboot afterwards) */
21 /* #define BNX2X_STOP_ON_ERROR */
22
23 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
24 #define BCM_VLAN 1
25 #endif
26
27
28 #define BNX2X_MULTI_QUEUE
29
30 #define BNX2X_NEW_NAPI
31
32
33 #include "bnx2x_reg.h"
34 #include "bnx2x_fw_defs.h"
35 #include "bnx2x_hsi.h"
36 #include "bnx2x_link.h"
37
38 /* error/debug prints */
39
40 #define DRV_MODULE_NAME "bnx2x"
41 #define PFX DRV_MODULE_NAME ": "
42
43 /* for messages that are currently off */
44 #define BNX2X_MSG_OFF 0
45 #define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */
46 #define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */
47 #define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */
48 #define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */
49 #define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */
50 #define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */
51
52 #define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */
53
54 /* regular debug print */
55 #define DP(__mask, __fmt, __args...) do { \
56 if (bp->msglevel & (__mask)) \
57 printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
58 bp->dev ? (bp->dev->name) : "?", ##__args); \
59 } while (0)
60
61 /* errors debug print */
62 #define BNX2X_DBG_ERR(__fmt, __args...) do { \
63 if (bp->msglevel & NETIF_MSG_PROBE) \
64 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
65 bp->dev ? (bp->dev->name) : "?", ##__args); \
66 } while (0)
67
68 /* for errors (never masked) */
69 #define BNX2X_ERR(__fmt, __args...) do { \
70 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
71 bp->dev ? (bp->dev->name) : "?", ##__args); \
72 } while (0)
73
74 /* before we have a dev->name use dev_info() */
75 #define BNX2X_DEV_INFO(__fmt, __args...) do { \
76 if (bp->msglevel & NETIF_MSG_PROBE) \
77 dev_info(&bp->pdev->dev, __fmt, ##__args); \
78 } while (0)
79
80
81 #ifdef BNX2X_STOP_ON_ERROR
82 #define bnx2x_panic() do { \
83 bp->panic = 1; \
84 BNX2X_ERR("driver assert\n"); \
85 bnx2x_int_disable(bp); \
86 bnx2x_panic_dump(bp); \
87 } while (0)
88 #else
89 #define bnx2x_panic() do { \
90 BNX2X_ERR("driver assert\n"); \
91 bnx2x_panic_dump(bp); \
92 } while (0)
93 #endif
94
95
96 #define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff)
97 #define U64_HI(x) (u32)(((u64)(x)) >> 32)
98 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
99
100
101 #define REG_ADDR(bp, offset) (bp->regview + offset)
102
103 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
104 #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
105
106 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
107 #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
108 #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
109
110 #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
111 #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
112
113 #define REG_RD_DMAE(bp, offset, valp, len32) \
114 do { \
115 bnx2x_read_dmae(bp, offset, len32);\
116 memcpy(valp, bnx2x_sp(bp, wb_data[0]), len32 * 4); \
117 } while (0)
118
119 #define REG_WR_DMAE(bp, offset, valp, len32) \
120 do { \
121 memcpy(bnx2x_sp(bp, wb_data[0]), valp, len32 * 4); \
122 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
123 offset, len32); \
124 } while (0)
125
126 #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
127 offsetof(struct shmem_region, field))
128 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
129 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
130
131 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
132 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
133
134
135 /* fast path */
136
137 struct sw_rx_bd {
138 struct sk_buff *skb;
139 DECLARE_PCI_UNMAP_ADDR(mapping)
140 };
141
142 struct sw_tx_bd {
143 struct sk_buff *skb;
144 u16 first_bd;
145 };
146
147 struct sw_rx_page {
148 struct page *page;
149 DECLARE_PCI_UNMAP_ADDR(mapping)
150 };
151
152
153 /* MC hsi */
154 #define BCM_PAGE_SHIFT 12
155 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
156 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
157 #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
158
159 #define PAGES_PER_SGE_SHIFT 0
160 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
161 #define SGE_PAGE_SIZE PAGE_SIZE
162 #define SGE_PAGE_SHIFT PAGE_SHIFT
163 #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))addr)
164
165 /* SGE ring related macros */
166 #define NUM_RX_SGE_PAGES 2
167 #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
168 #define MAX_RX_SGE_CNT (RX_SGE_CNT - 2)
169 /* RX_SGE_CNT is promised to be a power of 2 */
170 #define RX_SGE_MASK (RX_SGE_CNT - 1)
171 #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
172 #define MAX_RX_SGE (NUM_RX_SGE - 1)
173 #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
174 (MAX_RX_SGE_CNT - 1)) ? (x) + 3 : (x) + 1)
175 #define RX_SGE(x) ((x) & MAX_RX_SGE)
176
177 /* SGE producer mask related macros */
178 /* Number of bits in one sge_mask array element */
179 #define RX_SGE_MASK_ELEM_SZ 64
180 #define RX_SGE_MASK_ELEM_SHIFT 6
181 #define RX_SGE_MASK_ELEM_MASK ((u64)RX_SGE_MASK_ELEM_SZ - 1)
182
183 /* Creates a bitmask of all ones in less significant bits.
184 idx - index of the most significant bit in the created mask */
185 #define RX_SGE_ONES_MASK(idx) \
186 (((u64)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1)
187 #define RX_SGE_MASK_ELEM_ONE_MASK ((u64)(~0))
188
189 /* Number of u64 elements in SGE mask array */
190 #define RX_SGE_MASK_LEN ((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \
191 RX_SGE_MASK_ELEM_SZ)
192 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
193 #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
194
195
196 struct bnx2x_eth_q_stats {
197 u32 total_bytes_received_hi;
198 u32 total_bytes_received_lo;
199 u32 total_bytes_transmitted_hi;
200 u32 total_bytes_transmitted_lo;
201 u32 total_unicast_packets_received_hi;
202 u32 total_unicast_packets_received_lo;
203 u32 total_multicast_packets_received_hi;
204 u32 total_multicast_packets_received_lo;
205 u32 total_broadcast_packets_received_hi;
206 u32 total_broadcast_packets_received_lo;
207 u32 total_unicast_packets_transmitted_hi;
208 u32 total_unicast_packets_transmitted_lo;
209 u32 total_multicast_packets_transmitted_hi;
210 u32 total_multicast_packets_transmitted_lo;
211 u32 total_broadcast_packets_transmitted_hi;
212 u32 total_broadcast_packets_transmitted_lo;
213 u32 valid_bytes_received_hi;
214 u32 valid_bytes_received_lo;
215
216 u32 error_bytes_received_hi;
217 u32 error_bytes_received_lo;
218 u32 etherstatsoverrsizepkts_hi;
219 u32 etherstatsoverrsizepkts_lo;
220 u32 no_buff_discard_hi;
221 u32 no_buff_discard_lo;
222
223 u32 driver_xoff;
224 u32 rx_err_discard_pkt;
225 u32 rx_skb_alloc_failed;
226 u32 hw_csum_err;
227 };
228
229 #define BNX2X_NUM_Q_STATS 11
230 #define Q_STATS_OFFSET32(stat_name) \
231 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4)
232
233 struct bnx2x_fastpath {
234
235 struct napi_struct napi;
236
237 struct host_status_block *status_blk;
238 dma_addr_t status_blk_mapping;
239
240 struct eth_tx_db_data *hw_tx_prods;
241 dma_addr_t tx_prods_mapping;
242
243 struct sw_tx_bd *tx_buf_ring;
244
245 struct eth_tx_bd *tx_desc_ring;
246 dma_addr_t tx_desc_mapping;
247
248 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
249 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */
250
251 struct eth_rx_bd *rx_desc_ring;
252 dma_addr_t rx_desc_mapping;
253
254 union eth_rx_cqe *rx_comp_ring;
255 dma_addr_t rx_comp_mapping;
256
257 /* SGE ring */
258 struct eth_rx_sge *rx_sge_ring;
259 dma_addr_t rx_sge_mapping;
260
261 u64 sge_mask[RX_SGE_MASK_LEN];
262
263 int state;
264 #define BNX2X_FP_STATE_CLOSED 0
265 #define BNX2X_FP_STATE_IRQ 0x80000
266 #define BNX2X_FP_STATE_OPENING 0x90000
267 #define BNX2X_FP_STATE_OPEN 0xa0000
268 #define BNX2X_FP_STATE_HALTING 0xb0000
269 #define BNX2X_FP_STATE_HALTED 0xc0000
270
271 u8 index; /* number in fp array */
272 u8 cl_id; /* eth client id */
273 u8 sb_id; /* status block number in HW */
274
275 u16 tx_pkt_prod;
276 u16 tx_pkt_cons;
277 u16 tx_bd_prod;
278 u16 tx_bd_cons;
279 __le16 *tx_cons_sb;
280
281 __le16 fp_c_idx;
282 __le16 fp_u_idx;
283
284 u16 rx_bd_prod;
285 u16 rx_bd_cons;
286 u16 rx_comp_prod;
287 u16 rx_comp_cons;
288 u16 rx_sge_prod;
289 /* The last maximal completed SGE */
290 u16 last_max_sge;
291 __le16 *rx_cons_sb;
292 __le16 *rx_bd_cons_sb;
293
294 unsigned long tx_pkt,
295 rx_pkt,
296 rx_calls;
297 /* TPA related */
298 struct sw_rx_bd tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H];
299 u8 tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H];
300 #define BNX2X_TPA_START 1
301 #define BNX2X_TPA_STOP 2
302 u8 disable_tpa;
303 #ifdef BNX2X_STOP_ON_ERROR
304 u64 tpa_queue_used;
305 #endif
306
307 struct tstorm_per_client_stats old_tclient;
308 struct ustorm_per_client_stats old_uclient;
309 struct xstorm_per_client_stats old_xclient;
310 struct bnx2x_eth_q_stats eth_q_stats;
311
312 char name[IFNAMSIZ];
313 struct bnx2x *bp; /* parent */
314 };
315
316 #define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
317
318 #define BNX2X_HAS_WORK(fp) (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))
319
320
321 /* MC hsi */
322 #define MAX_FETCH_BD 13 /* HW max BDs per packet */
323 #define RX_COPY_THRESH 92
324
325 #define NUM_TX_RINGS 16
326 #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_tx_bd))
327 #define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
328 #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
329 #define MAX_TX_BD (NUM_TX_BD - 1)
330 #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
331 #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
332 (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
333 #define TX_BD(x) ((x) & MAX_TX_BD)
334 #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
335
336 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
337 #define NUM_RX_RINGS 8
338 #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
339 #define MAX_RX_DESC_CNT (RX_DESC_CNT - 2)
340 #define RX_DESC_MASK (RX_DESC_CNT - 1)
341 #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
342 #define MAX_RX_BD (NUM_RX_BD - 1)
343 #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
344 #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
345 (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1)
346 #define RX_BD(x) ((x) & MAX_RX_BD)
347
348 /* As long as CQE is 4 times bigger than BD entry we have to allocate
349 4 times more pages for CQ ring in order to keep it balanced with
350 BD ring */
351 #define NUM_RCQ_RINGS (NUM_RX_RINGS * 4)
352 #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
353 #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - 1)
354 #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
355 #define MAX_RCQ_BD (NUM_RCQ_BD - 1)
356 #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
357 #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
358 (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
359 #define RCQ_BD(x) ((x) & MAX_RCQ_BD)
360
361
362 /* This is needed for determining of last_max */
363 #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
364
365 #define __SGE_MASK_SET_BIT(el, bit) \
366 do { \
367 el = ((el) | ((u64)0x1 << (bit))); \
368 } while (0)
369
370 #define __SGE_MASK_CLEAR_BIT(el, bit) \
371 do { \
372 el = ((el) & (~((u64)0x1 << (bit)))); \
373 } while (0)
374
375 #define SGE_MASK_SET_BIT(fp, idx) \
376 __SGE_MASK_SET_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
377 ((idx) & RX_SGE_MASK_ELEM_MASK))
378
379 #define SGE_MASK_CLEAR_BIT(fp, idx) \
380 __SGE_MASK_CLEAR_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
381 ((idx) & RX_SGE_MASK_ELEM_MASK))
382
383
384 /* used on a CID received from the HW */
385 #define SW_CID(x) (le32_to_cpu(x) & \
386 (COMMON_RAMROD_ETH_RX_CQE_CID >> 7))
387 #define CQE_CMD(x) (le32_to_cpu(x) >> \
388 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
389
390 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
391 le32_to_cpu((bd)->addr_lo))
392 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
393
394
395 #define DPM_TRIGER_TYPE 0x40
396 #define DOORBELL(bp, cid, val) \
397 do { \
398 writel((u32)val, (bp)->doorbells + (BCM_PAGE_SIZE * cid) + \
399 DPM_TRIGER_TYPE); \
400 } while (0)
401
402
403 /* TX CSUM helpers */
404 #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
405 skb->csum_offset)
406 #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
407 skb->csum_offset))
408
409 #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
410
411 #define XMIT_PLAIN 0
412 #define XMIT_CSUM_V4 0x1
413 #define XMIT_CSUM_V6 0x2
414 #define XMIT_CSUM_TCP 0x4
415 #define XMIT_GSO_V4 0x8
416 #define XMIT_GSO_V6 0x10
417
418 #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6)
419 #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6)
420
421
422 /* stuff added to make the code fit 80Col */
423
424 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
425
426 #define TPA_TYPE_START ETH_FAST_PATH_RX_CQE_START_FLG
427 #define TPA_TYPE_END ETH_FAST_PATH_RX_CQE_END_FLG
428 #define TPA_TYPE(cqe_fp_flags) ((cqe_fp_flags) & \
429 (TPA_TYPE_START | TPA_TYPE_END))
430
431 #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
432
433 #define BNX2X_IP_CSUM_ERR(cqe) \
434 (!((cqe)->fast_path_cqe.status_flags & \
435 ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \
436 ((cqe)->fast_path_cqe.type_error_flags & \
437 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG))
438
439 #define BNX2X_L4_CSUM_ERR(cqe) \
440 (!((cqe)->fast_path_cqe.status_flags & \
441 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \
442 ((cqe)->fast_path_cqe.type_error_flags & \
443 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
444
445 #define BNX2X_RX_CSUM_OK(cqe) \
446 (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe)))
447
448 #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
449 (((le16_to_cpu(flags) & \
450 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
451 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
452 == PRS_FLAG_OVERETH_IPV4)
453 #define BNX2X_RX_SUM_FIX(cqe) \
454 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
455
456
457 #define FP_USB_FUNC_OFF (2 + 2*HC_USTORM_SB_NUM_INDICES)
458 #define FP_CSB_FUNC_OFF (2 + 2*HC_CSTORM_SB_NUM_INDICES)
459
460 #define U_SB_ETH_RX_CQ_INDEX HC_INDEX_U_ETH_RX_CQ_CONS
461 #define U_SB_ETH_RX_BD_INDEX HC_INDEX_U_ETH_RX_BD_CONS
462 #define C_SB_ETH_TX_CQ_INDEX HC_INDEX_C_ETH_TX_CQ_CONS
463
464 #define BNX2X_RX_SB_INDEX \
465 (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_CQ_INDEX])
466
467 #define BNX2X_RX_SB_BD_INDEX \
468 (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_BD_INDEX])
469
470 #define BNX2X_RX_SB_INDEX_NUM \
471 (((U_SB_ETH_RX_CQ_INDEX << \
472 USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT) & \
473 USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER) | \
474 ((U_SB_ETH_RX_BD_INDEX << \
475 USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT) & \
476 USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER))
477
478 #define BNX2X_TX_SB_INDEX \
479 (&fp->status_blk->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX])
480
481
482 /* end of fast path */
483
484 /* common */
485
486 struct bnx2x_common {
487
488 u32 chip_id;
489 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
490 #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
491
492 #define CHIP_NUM(bp) (bp->common.chip_id >> 16)
493 #define CHIP_NUM_57710 0x164e
494 #define CHIP_NUM_57711 0x164f
495 #define CHIP_NUM_57711E 0x1650
496 #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
497 #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
498 #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
499 #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
500 CHIP_IS_57711E(bp))
501 #define IS_E1H_OFFSET CHIP_IS_E1H(bp)
502
503 #define CHIP_REV(bp) (bp->common.chip_id & 0x0000f000)
504 #define CHIP_REV_Ax 0x00000000
505 /* assume maximum 5 revisions */
506 #define CHIP_REV_IS_SLOW(bp) (CHIP_REV(bp) > 0x00005000)
507 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
508 #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
509 !(CHIP_REV(bp) & 0x00001000))
510 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
511 #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
512 (CHIP_REV(bp) & 0x00001000))
513
514 #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
515 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
516
517 #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
518 #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
519
520 int flash_size;
521 #define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
522 #define NVRAM_TIMEOUT_COUNT 30000
523 #define NVRAM_PAGE_SIZE 256
524
525 u32 shmem_base;
526
527 u32 hw_config;
528
529 u32 bc_ver;
530 };
531
532
533 /* end of common */
534
535 /* port */
536
537 struct nig_stats {
538 u32 brb_discard;
539 u32 brb_packet;
540 u32 brb_truncate;
541 u32 flow_ctrl_discard;
542 u32 flow_ctrl_octets;
543 u32 flow_ctrl_packet;
544 u32 mng_discard;
545 u32 mng_octet_inp;
546 u32 mng_octet_out;
547 u32 mng_packet_inp;
548 u32 mng_packet_out;
549 u32 pbf_octets;
550 u32 pbf_packet;
551 u32 safc_inp;
552 u32 egress_mac_pkt0_lo;
553 u32 egress_mac_pkt0_hi;
554 u32 egress_mac_pkt1_lo;
555 u32 egress_mac_pkt1_hi;
556 };
557
558 struct bnx2x_port {
559 u32 pmf;
560
561 u32 link_config;
562
563 u32 supported;
564 /* link settings - missing defines */
565 #define SUPPORTED_2500baseX_Full (1 << 15)
566
567 u32 advertising;
568 /* link settings - missing defines */
569 #define ADVERTISED_2500baseX_Full (1 << 15)
570
571 u32 phy_addr;
572
573 /* used to synchronize phy accesses */
574 struct mutex phy_mutex;
575 int need_hw_lock;
576
577 u32 port_stx;
578
579 struct nig_stats old_nig_stats;
580 };
581
582 /* end of port */
583
584
585 enum bnx2x_stats_event {
586 STATS_EVENT_PMF = 0,
587 STATS_EVENT_LINK_UP,
588 STATS_EVENT_UPDATE,
589 STATS_EVENT_STOP,
590 STATS_EVENT_MAX
591 };
592
593 enum bnx2x_stats_state {
594 STATS_STATE_DISABLED = 0,
595 STATS_STATE_ENABLED,
596 STATS_STATE_MAX
597 };
598
599 struct bnx2x_eth_stats {
600 u32 total_bytes_received_hi;
601 u32 total_bytes_received_lo;
602 u32 total_bytes_transmitted_hi;
603 u32 total_bytes_transmitted_lo;
604 u32 total_unicast_packets_received_hi;
605 u32 total_unicast_packets_received_lo;
606 u32 total_multicast_packets_received_hi;
607 u32 total_multicast_packets_received_lo;
608 u32 total_broadcast_packets_received_hi;
609 u32 total_broadcast_packets_received_lo;
610 u32 total_unicast_packets_transmitted_hi;
611 u32 total_unicast_packets_transmitted_lo;
612 u32 total_multicast_packets_transmitted_hi;
613 u32 total_multicast_packets_transmitted_lo;
614 u32 total_broadcast_packets_transmitted_hi;
615 u32 total_broadcast_packets_transmitted_lo;
616 u32 valid_bytes_received_hi;
617 u32 valid_bytes_received_lo;
618
619 u32 error_bytes_received_hi;
620 u32 error_bytes_received_lo;
621 u32 etherstatsoverrsizepkts_hi;
622 u32 etherstatsoverrsizepkts_lo;
623 u32 no_buff_discard_hi;
624 u32 no_buff_discard_lo;
625
626 u32 rx_stat_ifhcinbadoctets_hi;
627 u32 rx_stat_ifhcinbadoctets_lo;
628 u32 tx_stat_ifhcoutbadoctets_hi;
629 u32 tx_stat_ifhcoutbadoctets_lo;
630 u32 rx_stat_dot3statsfcserrors_hi;
631 u32 rx_stat_dot3statsfcserrors_lo;
632 u32 rx_stat_dot3statsalignmenterrors_hi;
633 u32 rx_stat_dot3statsalignmenterrors_lo;
634 u32 rx_stat_dot3statscarriersenseerrors_hi;
635 u32 rx_stat_dot3statscarriersenseerrors_lo;
636 u32 rx_stat_falsecarriererrors_hi;
637 u32 rx_stat_falsecarriererrors_lo;
638 u32 rx_stat_etherstatsundersizepkts_hi;
639 u32 rx_stat_etherstatsundersizepkts_lo;
640 u32 rx_stat_dot3statsframestoolong_hi;
641 u32 rx_stat_dot3statsframestoolong_lo;
642 u32 rx_stat_etherstatsfragments_hi;
643 u32 rx_stat_etherstatsfragments_lo;
644 u32 rx_stat_etherstatsjabbers_hi;
645 u32 rx_stat_etherstatsjabbers_lo;
646 u32 rx_stat_maccontrolframesreceived_hi;
647 u32 rx_stat_maccontrolframesreceived_lo;
648 u32 rx_stat_bmac_xpf_hi;
649 u32 rx_stat_bmac_xpf_lo;
650 u32 rx_stat_bmac_xcf_hi;
651 u32 rx_stat_bmac_xcf_lo;
652 u32 rx_stat_xoffstateentered_hi;
653 u32 rx_stat_xoffstateentered_lo;
654 u32 rx_stat_xonpauseframesreceived_hi;
655 u32 rx_stat_xonpauseframesreceived_lo;
656 u32 rx_stat_xoffpauseframesreceived_hi;
657 u32 rx_stat_xoffpauseframesreceived_lo;
658 u32 tx_stat_outxonsent_hi;
659 u32 tx_stat_outxonsent_lo;
660 u32 tx_stat_outxoffsent_hi;
661 u32 tx_stat_outxoffsent_lo;
662 u32 tx_stat_flowcontroldone_hi;
663 u32 tx_stat_flowcontroldone_lo;
664 u32 tx_stat_etherstatscollisions_hi;
665 u32 tx_stat_etherstatscollisions_lo;
666 u32 tx_stat_dot3statssinglecollisionframes_hi;
667 u32 tx_stat_dot3statssinglecollisionframes_lo;
668 u32 tx_stat_dot3statsmultiplecollisionframes_hi;
669 u32 tx_stat_dot3statsmultiplecollisionframes_lo;
670 u32 tx_stat_dot3statsdeferredtransmissions_hi;
671 u32 tx_stat_dot3statsdeferredtransmissions_lo;
672 u32 tx_stat_dot3statsexcessivecollisions_hi;
673 u32 tx_stat_dot3statsexcessivecollisions_lo;
674 u32 tx_stat_dot3statslatecollisions_hi;
675 u32 tx_stat_dot3statslatecollisions_lo;
676 u32 tx_stat_etherstatspkts64octets_hi;
677 u32 tx_stat_etherstatspkts64octets_lo;
678 u32 tx_stat_etherstatspkts65octetsto127octets_hi;
679 u32 tx_stat_etherstatspkts65octetsto127octets_lo;
680 u32 tx_stat_etherstatspkts128octetsto255octets_hi;
681 u32 tx_stat_etherstatspkts128octetsto255octets_lo;
682 u32 tx_stat_etherstatspkts256octetsto511octets_hi;
683 u32 tx_stat_etherstatspkts256octetsto511octets_lo;
684 u32 tx_stat_etherstatspkts512octetsto1023octets_hi;
685 u32 tx_stat_etherstatspkts512octetsto1023octets_lo;
686 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi;
687 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo;
688 u32 tx_stat_etherstatspktsover1522octets_hi;
689 u32 tx_stat_etherstatspktsover1522octets_lo;
690 u32 tx_stat_bmac_2047_hi;
691 u32 tx_stat_bmac_2047_lo;
692 u32 tx_stat_bmac_4095_hi;
693 u32 tx_stat_bmac_4095_lo;
694 u32 tx_stat_bmac_9216_hi;
695 u32 tx_stat_bmac_9216_lo;
696 u32 tx_stat_bmac_16383_hi;
697 u32 tx_stat_bmac_16383_lo;
698 u32 tx_stat_dot3statsinternalmactransmiterrors_hi;
699 u32 tx_stat_dot3statsinternalmactransmiterrors_lo;
700 u32 tx_stat_bmac_ufl_hi;
701 u32 tx_stat_bmac_ufl_lo;
702
703 u32 pause_frames_received_hi;
704 u32 pause_frames_received_lo;
705 u32 pause_frames_sent_hi;
706 u32 pause_frames_sent_lo;
707
708 u32 etherstatspkts1024octetsto1522octets_hi;
709 u32 etherstatspkts1024octetsto1522octets_lo;
710 u32 etherstatspktsover1522octets_hi;
711 u32 etherstatspktsover1522octets_lo;
712
713 u32 brb_drop_hi;
714 u32 brb_drop_lo;
715 u32 brb_truncate_hi;
716 u32 brb_truncate_lo;
717
718 u32 mac_filter_discard;
719 u32 xxoverflow_discard;
720 u32 brb_truncate_discard;
721 u32 mac_discard;
722
723 u32 driver_xoff;
724 u32 rx_err_discard_pkt;
725 u32 rx_skb_alloc_failed;
726 u32 hw_csum_err;
727
728 u32 nig_timer_max;
729 };
730
731 #define BNX2X_NUM_STATS 41
732 #define STATS_OFFSET32(stat_name) \
733 (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
734
735
736 #define MAX_CONTEXT 16
737
738 union cdu_context {
739 struct eth_context eth;
740 char pad[1024];
741 };
742
743 #define MAX_DMAE_C 8
744
745 /* DMA memory not used in fastpath */
746 struct bnx2x_slowpath {
747 union cdu_context context[MAX_CONTEXT];
748 struct eth_stats_query fw_stats;
749 struct mac_configuration_cmd mac_config;
750 struct mac_configuration_cmd mcast_config;
751
752 /* used by dmae command executer */
753 struct dmae_command dmae[MAX_DMAE_C];
754
755 u32 stats_comp;
756 union mac_stats mac_stats;
757 struct nig_stats nig_stats;
758 struct host_port_stats port_stats;
759 struct host_func_stats func_stats;
760
761 u32 wb_comp;
762 u32 wb_data[4];
763 };
764
765 #define bnx2x_sp(bp, var) (&bp->slowpath->var)
766 #define bnx2x_sp_mapping(bp, var) \
767 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
768
769
770 /* attn group wiring */
771 #define MAX_DYNAMIC_ATTN_GRPS 8
772
773 struct attn_route {
774 u32 sig[4];
775 };
776
777 struct bnx2x {
778 /* Fields used in the tx and intr/napi performance paths
779 * are grouped together in the beginning of the structure
780 */
781 struct bnx2x_fastpath fp[MAX_CONTEXT];
782 void __iomem *regview;
783 void __iomem *doorbells;
784 #define BNX2X_DB_SIZE (16*BCM_PAGE_SIZE)
785
786 struct net_device *dev;
787 struct pci_dev *pdev;
788
789 atomic_t intr_sem;
790 struct msix_entry msix_table[MAX_CONTEXT+1];
791 #define INT_MODE_INTx 1
792 #define INT_MODE_MSI 2
793 #define INT_MODE_MSIX 3
794
795 int tx_ring_size;
796
797 #ifdef BCM_VLAN
798 struct vlan_group *vlgrp;
799 #endif
800
801 u32 rx_csum;
802 u32 rx_buf_size;
803 #define ETH_OVREHEAD (ETH_HLEN + 8) /* 8 for CRC + VLAN */
804 #define ETH_MIN_PACKET_SIZE 60
805 #define ETH_MAX_PACKET_SIZE 1500
806 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
807
808 /* Max supported alignment is 256 (8 shift) */
809 #define BNX2X_RX_ALIGN_SHIFT ((L1_CACHE_SHIFT < 8) ? \
810 L1_CACHE_SHIFT : 8)
811 #define BNX2X_RX_ALIGN (1 << BNX2X_RX_ALIGN_SHIFT)
812
813 struct host_def_status_block *def_status_blk;
814 #define DEF_SB_ID 16
815 __le16 def_c_idx;
816 __le16 def_u_idx;
817 __le16 def_x_idx;
818 __le16 def_t_idx;
819 __le16 def_att_idx;
820 u32 attn_state;
821 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
822
823 /* slow path ring */
824 struct eth_spe *spq;
825 dma_addr_t spq_mapping;
826 u16 spq_prod_idx;
827 struct eth_spe *spq_prod_bd;
828 struct eth_spe *spq_last_bd;
829 __le16 *dsb_sp_prod;
830 u16 spq_left; /* serialize spq */
831 /* used to synchronize spq accesses */
832 spinlock_t spq_lock;
833
834 /* Flags for marking that there is a STAT_QUERY or
835 SET_MAC ramrod pending */
836 u8 stats_pending;
837 u8 set_mac_pending;
838
839 /* End of fields used in the performance code paths */
840
841 int panic;
842 int msglevel;
843
844 u32 flags;
845 #define PCIX_FLAG 1
846 #define PCI_32BIT_FLAG 2
847 #define ONE_PORT_FLAG 4
848 #define NO_WOL_FLAG 8
849 #define USING_DAC_FLAG 0x10
850 #define USING_MSIX_FLAG 0x20
851 #define USING_MSI_FLAG 0x40
852 #define TPA_ENABLE_FLAG 0x80
853 #define NO_MCP_FLAG 0x100
854 #define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG)
855 #define HW_VLAN_TX_FLAG 0x400
856 #define HW_VLAN_RX_FLAG 0x800
857
858 int func;
859 #define BP_PORT(bp) (bp->func % PORT_MAX)
860 #define BP_FUNC(bp) (bp->func)
861 #define BP_E1HVN(bp) (bp->func >> 1)
862 #define BP_L_ID(bp) (BP_E1HVN(bp) << 2)
863
864 int pm_cap;
865 int pcie_cap;
866 int mrrs;
867
868 struct delayed_work sp_task;
869 struct work_struct reset_task;
870
871 struct timer_list timer;
872 int current_interval;
873
874 u16 fw_seq;
875 u16 fw_drv_pulse_wr_seq;
876 u32 func_stx;
877
878 struct link_params link_params;
879 struct link_vars link_vars;
880
881 struct bnx2x_common common;
882 struct bnx2x_port port;
883
884 struct cmng_struct_per_port cmng;
885 u32 vn_weight_sum;
886
887 u32 mf_config;
888 u16 e1hov;
889 u8 e1hmf;
890 #define IS_E1HMF(bp) (bp->e1hmf != 0)
891
892 u8 wol;
893
894 int rx_ring_size;
895
896 u16 tx_quick_cons_trip_int;
897 u16 tx_quick_cons_trip;
898 u16 tx_ticks_int;
899 u16 tx_ticks;
900
901 u16 rx_quick_cons_trip_int;
902 u16 rx_quick_cons_trip;
903 u16 rx_ticks_int;
904 u16 rx_ticks;
905
906 u32 lin_cnt;
907
908 int state;
909 #define BNX2X_STATE_CLOSED 0
910 #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
911 #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
912 #define BNX2X_STATE_OPEN 0x3000
913 #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
914 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
915 #define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000
916 #define BNX2X_STATE_DISABLED 0xd000
917 #define BNX2X_STATE_DIAG 0xe000
918 #define BNX2X_STATE_ERROR 0xf000
919
920 int multi_mode;
921 int num_rx_queues;
922 int num_tx_queues;
923
924 u32 rx_mode;
925 #define BNX2X_RX_MODE_NONE 0
926 #define BNX2X_RX_MODE_NORMAL 1
927 #define BNX2X_RX_MODE_ALLMULTI 2
928 #define BNX2X_RX_MODE_PROMISC 3
929 #define BNX2X_MAX_MULTICAST 64
930 #define BNX2X_MAX_EMUL_MULTI 16
931
932 dma_addr_t def_status_blk_mapping;
933
934 struct bnx2x_slowpath *slowpath;
935 dma_addr_t slowpath_mapping;
936
937 #ifdef BCM_ISCSI
938 void *t1;
939 dma_addr_t t1_mapping;
940 void *t2;
941 dma_addr_t t2_mapping;
942 void *timers;
943 dma_addr_t timers_mapping;
944 void *qm;
945 dma_addr_t qm_mapping;
946 #endif
947
948 int dmae_ready;
949 /* used to synchronize dmae accesses */
950 struct mutex dmae_mutex;
951 struct dmae_command init_dmae;
952
953 /* used to synchronize stats collecting */
954 int stats_state;
955 /* used by dmae command loader */
956 struct dmae_command stats_dmae;
957 int executer_idx;
958
959 u16 stats_counter;
960 struct bnx2x_eth_stats eth_stats;
961
962 struct z_stream_s *strm;
963 void *gunzip_buf;
964 dma_addr_t gunzip_mapping;
965 int gunzip_outlen;
966 #define FW_BUF_SIZE 0x8000
967
968 };
969
970
971 #define BNX2X_MAX_QUEUES(bp) (IS_E1HMF(bp) ? (MAX_CONTEXT / E1HVN_MAX) : \
972 MAX_CONTEXT)
973 #define BNX2X_NUM_QUEUES(bp) max(bp->num_rx_queues, bp->num_tx_queues)
974 #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1)
975
976 #define for_each_rx_queue(bp, var) \
977 for (var = 0; var < bp->num_rx_queues; var++)
978 #define for_each_tx_queue(bp, var) \
979 for (var = 0; var < bp->num_tx_queues; var++)
980 #define for_each_queue(bp, var) \
981 for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++)
982 #define for_each_nondefault_queue(bp, var) \
983 for (var = 1; var < BNX2X_NUM_QUEUES(bp); var++)
984
985
986 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
987 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
988 u32 len32);
989 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
990 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
991 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
992
993 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
994 int wait)
995 {
996 u32 val;
997
998 do {
999 val = REG_RD(bp, reg);
1000 if (val == expected)
1001 break;
1002 ms -= wait;
1003 msleep(wait);
1004
1005 } while (ms > 0);
1006
1007 return val;
1008 }
1009
1010
1011 /* load/unload mode */
1012 #define LOAD_NORMAL 0
1013 #define LOAD_OPEN 1
1014 #define LOAD_DIAG 2
1015 #define UNLOAD_NORMAL 0
1016 #define UNLOAD_CLOSE 1
1017
1018
1019 /* DMAE command defines */
1020 #define DMAE_CMD_SRC_PCI 0
1021 #define DMAE_CMD_SRC_GRC DMAE_COMMAND_SRC
1022
1023 #define DMAE_CMD_DST_PCI (1 << DMAE_COMMAND_DST_SHIFT)
1024 #define DMAE_CMD_DST_GRC (2 << DMAE_COMMAND_DST_SHIFT)
1025
1026 #define DMAE_CMD_C_DST_PCI 0
1027 #define DMAE_CMD_C_DST_GRC (1 << DMAE_COMMAND_C_DST_SHIFT)
1028
1029 #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
1030
1031 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
1032 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
1033 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
1034 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
1035
1036 #define DMAE_CMD_PORT_0 0
1037 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
1038
1039 #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
1040 #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
1041 #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
1042
1043 #define DMAE_LEN32_RD_MAX 0x80
1044 #define DMAE_LEN32_WR_MAX 0x400
1045
1046 #define DMAE_COMP_VAL 0xe0d0d0ae
1047
1048 #define MAX_DMAE_C_PER_PORT 8
1049 #define INIT_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \
1050 BP_E1HVN(bp))
1051 #define PMF_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \
1052 E1HVN_MAX)
1053
1054
1055 /* PCIE link and speed */
1056 #define PCICFG_LINK_WIDTH 0x1f00000
1057 #define PCICFG_LINK_WIDTH_SHIFT 20
1058 #define PCICFG_LINK_SPEED 0xf0000
1059 #define PCICFG_LINK_SPEED_SHIFT 16
1060
1061
1062 #define BNX2X_NUM_TESTS 7
1063
1064 #define BNX2X_PHY_LOOPBACK 0
1065 #define BNX2X_MAC_LOOPBACK 1
1066 #define BNX2X_PHY_LOOPBACK_FAILED 1
1067 #define BNX2X_MAC_LOOPBACK_FAILED 2
1068 #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
1069 BNX2X_PHY_LOOPBACK_FAILED)
1070
1071
1072 #define STROM_ASSERT_ARRAY_SIZE 50
1073
1074
1075 /* must be used on a CID before placing it on a HW ring */
1076 #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | (BP_E1HVN(bp) << 17) | x)
1077
1078 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
1079 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
1080
1081
1082 #define BNX2X_BTR 3
1083 #define MAX_SPQ_PENDING 8
1084
1085
1086 /* CMNG constants
1087 derived from lab experiments, and not from system spec calculations !!! */
1088 #define DEF_MIN_RATE 100
1089 /* resolution of the rate shaping timer - 100 usec */
1090 #define RS_PERIODIC_TIMEOUT_USEC 100
1091 /* resolution of fairness algorithm in usecs -
1092 coefficient for calculating the actual t fair */
1093 #define T_FAIR_COEF 10000000
1094 /* number of bytes in single QM arbitration cycle -
1095 coefficient for calculating the fairness timer */
1096 #define QM_ARB_BYTES 40000
1097 #define FAIR_MEM 2
1098
1099
1100 #define ATTN_NIG_FOR_FUNC (1L << 8)
1101 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
1102 #define GPIO_2_FUNC (1L << 10)
1103 #define GPIO_3_FUNC (1L << 11)
1104 #define GPIO_4_FUNC (1L << 12)
1105 #define ATTN_GENERAL_ATTN_1 (1L << 13)
1106 #define ATTN_GENERAL_ATTN_2 (1L << 14)
1107 #define ATTN_GENERAL_ATTN_3 (1L << 15)
1108 #define ATTN_GENERAL_ATTN_4 (1L << 13)
1109 #define ATTN_GENERAL_ATTN_5 (1L << 14)
1110 #define ATTN_GENERAL_ATTN_6 (1L << 15)
1111
1112 #define ATTN_HARD_WIRED_MASK 0xff00
1113 #define ATTENTION_ID 4
1114
1115
1116 /* stuff added to make the code fit 80Col */
1117
1118 #define BNX2X_PMF_LINK_ASSERT \
1119 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
1120
1121 #define BNX2X_MC_ASSERT_BITS \
1122 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1123 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1124 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1125 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
1126
1127 #define BNX2X_MCP_ASSERT \
1128 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
1129
1130 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
1131 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
1132 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
1133 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
1134 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
1135 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
1136 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
1137
1138 #define HW_INTERRUT_ASSERT_SET_0 \
1139 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
1140 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
1141 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
1142 AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT)
1143 #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
1144 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
1145 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
1146 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
1147 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR)
1148 #define HW_INTERRUT_ASSERT_SET_1 \
1149 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
1150 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
1151 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
1152 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
1153 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
1154 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
1155 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
1156 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
1157 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
1158 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
1159 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
1160 #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\
1161 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
1162 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
1163 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
1164 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
1165 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
1166 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
1167 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
1168 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
1169 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
1170 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR)
1171 #define HW_INTERRUT_ASSERT_SET_2 \
1172 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
1173 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
1174 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
1175 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
1176 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
1177 #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
1178 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
1179 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
1180 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
1181 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
1182 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
1183 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
1184
1185
1186 #define MULTI_FLAGS(bp) \
1187 (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \
1188 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \
1189 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \
1190 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
1191 (bp->multi_mode << \
1192 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT))
1193
1194 #define MULTI_MASK 0x7f
1195
1196
1197 #define DEF_USB_FUNC_OFF (2 + 2*HC_USTORM_DEF_SB_NUM_INDICES)
1198 #define DEF_CSB_FUNC_OFF (2 + 2*HC_CSTORM_DEF_SB_NUM_INDICES)
1199 #define DEF_XSB_FUNC_OFF (2 + 2*HC_XSTORM_DEF_SB_NUM_INDICES)
1200 #define DEF_TSB_FUNC_OFF (2 + 2*HC_TSTORM_DEF_SB_NUM_INDICES)
1201
1202 #define C_DEF_SB_SP_INDEX HC_INDEX_DEF_C_ETH_SLOW_PATH
1203
1204 #define BNX2X_SP_DSB_INDEX \
1205 (&bp->def_status_blk->c_def_status_block.index_values[C_DEF_SB_SP_INDEX])
1206
1207
1208 #define CAM_IS_INVALID(x) \
1209 (x.target_table_entry.flags == TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1210
1211 #define CAM_INVALIDATE(x) \
1212 (x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1213
1214
1215 /* Number of u32 elements in MC hash array */
1216 #define MC_HASH_SIZE 8
1217 #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
1218 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
1219
1220
1221 #ifndef PXP2_REG_PXP2_INT_STS
1222 #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
1223 #endif
1224
1225 /* MISC_REG_RESET_REG - this is here for the hsi to work don't touch */
1226
1227 #endif /* bnx2x.h */
Support for the Chinese Samsung S3C2440 based development boards