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ext3: fix hang on umount with quotas when journal is aborted
[linux-2.6/mini2440.git] / include / asm-x86 / processor.h
blob2e7974ec77eca6e94b2ee503d02580a87db717a2
1 #ifndef __ASM_X86_PROCESSOR_H
2 #define __ASM_X86_PROCESSOR_H
3
4 #include <asm/processor-flags.h>
5
6 /* migration helper, for KVM - will be removed in 2.6.25: */
7 #define Xgt_desc_struct desc_ptr
8
9 /* Forward declaration, a strange C thing */
10 struct task_struct;
11 struct mm_struct;
12
13 #include <asm/vm86.h>
14 #include <asm/math_emu.h>
15 #include <asm/segment.h>
16 #include <asm/types.h>
17 #include <asm/sigcontext.h>
18 #include <asm/current.h>
19 #include <asm/cpufeature.h>
20 #include <asm/system.h>
21 #include <asm/page.h>
22 #include <asm/percpu.h>
23 #include <asm/msr.h>
24 #include <asm/desc_defs.h>
25 #include <asm/nops.h>
26
27 #include <linux/personality.h>
28 #include <linux/cpumask.h>
29 #include <linux/cache.h>
30 #include <linux/threads.h>
31 #include <linux/init.h>
32
33 /*
34 * Default implementation of macro that returns current
35 * instruction pointer ("program counter").
36 */
37 static inline void *current_text_addr(void)
38 {
39 void *pc;
40
41 asm volatile("mov $1f, %0; 1:":"=r" (pc));
42
43 return pc;
44 }
45
46 #ifdef CONFIG_X86_VSMP
47 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
48 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
49 #else
50 # define ARCH_MIN_TASKALIGN 16
51 # define ARCH_MIN_MMSTRUCT_ALIGN 0
52 #endif
53
54 /*
55 * CPU type and hardware bug flags. Kept separately for each CPU.
56 * Members of this structure are referenced in head.S, so think twice
57 * before touching them. [mj]
58 */
59
60 struct cpuinfo_x86 {
61 __u8 x86; /* CPU family */
62 __u8 x86_vendor; /* CPU vendor */
63 __u8 x86_model;
64 __u8 x86_mask;
65 #ifdef CONFIG_X86_32
66 char wp_works_ok; /* It doesn't on 386's */
67
68 /* Problems on some 486Dx4's and old 386's: */
69 char hlt_works_ok;
70 char hard_math;
71 char rfu;
72 char fdiv_bug;
73 char f00f_bug;
74 char coma_bug;
75 char pad0;
76 #else
77 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
78 int x86_tlbsize;
79 __u8 x86_virt_bits;
80 __u8 x86_phys_bits;
81 /* CPUID returned core id bits: */
82 __u8 x86_coreid_bits;
83 /* Max extended CPUID function supported: */
84 __u32 extended_cpuid_level;
85 #endif
86 /* Maximum supported CPUID level, -1=no CPUID: */
87 int cpuid_level;
88 __u32 x86_capability[NCAPINTS];
89 char x86_vendor_id[16];
90 char x86_model_id[64];
91 /* in KB - valid for CPUS which support this call: */
92 int x86_cache_size;
93 int x86_cache_alignment; /* In bytes */
94 int x86_power;
95 unsigned long loops_per_jiffy;
96 #ifdef CONFIG_SMP
97 /* cpus sharing the last level cache: */
98 cpumask_t llc_shared_map;
99 #endif
100 /* cpuid returned max cores value: */
101 u16 x86_max_cores;
102 u16 apicid;
103 u16 initial_apicid;
104 u16 x86_clflush_size;
105 #ifdef CONFIG_SMP
106 /* number of cores as seen by the OS: */
107 u16 booted_cores;
108 /* Physical processor id: */
109 u16 phys_proc_id;
110 /* Core id: */
111 u16 cpu_core_id;
112 /* Index into per_cpu list: */
113 u16 cpu_index;
114 #endif
115 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
116
117 #define X86_VENDOR_INTEL 0
118 #define X86_VENDOR_CYRIX 1
119 #define X86_VENDOR_AMD 2
120 #define X86_VENDOR_UMC 3
121 #define X86_VENDOR_CENTAUR 5
122 #define X86_VENDOR_TRANSMETA 7
123 #define X86_VENDOR_NSC 8
124 #define X86_VENDOR_NUM 9
125
126 #define X86_VENDOR_UNKNOWN 0xff
127
128 /*
129 * capabilities of CPUs
130 */
131 extern struct cpuinfo_x86 boot_cpu_data;
132 extern struct cpuinfo_x86 new_cpu_data;
133
134 extern struct tss_struct doublefault_tss;
135 extern __u32 cleared_cpu_caps[NCAPINTS];
136
137 #ifdef CONFIG_SMP
138 DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info);
139 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
140 #define current_cpu_data cpu_data(smp_processor_id())
141 #else
142 #define cpu_data(cpu) boot_cpu_data
143 #define current_cpu_data boot_cpu_data
144 #endif
145
146 static inline int hlt_works(int cpu)
147 {
148 #ifdef CONFIG_X86_32
149 return cpu_data(cpu).hlt_works_ok;
150 #else
151 return 1;
152 #endif
153 }
154
155 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
156
157 extern void cpu_detect(struct cpuinfo_x86 *c);
158
159 extern void identify_cpu(struct cpuinfo_x86 *);
160 extern void identify_boot_cpu(void);
161 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
162 extern void print_cpu_info(struct cpuinfo_x86 *);
163 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
164 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
165 extern unsigned short num_cache_leaves;
166
167 #if defined(CONFIG_X86_HT) || defined(CONFIG_X86_64)
168 extern void detect_ht(struct cpuinfo_x86 *c);
169 #else
170 static inline void detect_ht(struct cpuinfo_x86 *c) {}
171 #endif
172
173 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
174 unsigned int *ecx, unsigned int *edx)
175 {
176 /* ecx is often an input as well as an output. */
177 asm("cpuid"
178 : "=a" (*eax),
179 "=b" (*ebx),
180 "=c" (*ecx),
181 "=d" (*edx)
182 : "0" (*eax), "2" (*ecx));
183 }
184
185 static inline void load_cr3(pgd_t *pgdir)
186 {
187 write_cr3(__pa(pgdir));
188 }
189
190 #ifdef CONFIG_X86_32
191 /* This is the TSS defined by the hardware. */
192 struct x86_hw_tss {
193 unsigned short back_link, __blh;
194 unsigned long sp0;
195 unsigned short ss0, __ss0h;
196 unsigned long sp1;
197 /* ss1 caches MSR_IA32_SYSENTER_CS: */
198 unsigned short ss1, __ss1h;
199 unsigned long sp2;
200 unsigned short ss2, __ss2h;
201 unsigned long __cr3;
202 unsigned long ip;
203 unsigned long flags;
204 unsigned long ax;
205 unsigned long cx;
206 unsigned long dx;
207 unsigned long bx;
208 unsigned long sp;
209 unsigned long bp;
210 unsigned long si;
211 unsigned long di;
212 unsigned short es, __esh;
213 unsigned short cs, __csh;
214 unsigned short ss, __ssh;
215 unsigned short ds, __dsh;
216 unsigned short fs, __fsh;
217 unsigned short gs, __gsh;
218 unsigned short ldt, __ldth;
219 unsigned short trace;
220 unsigned short io_bitmap_base;
221
222 } __attribute__((packed));
223 #else
224 struct x86_hw_tss {
225 u32 reserved1;
226 u64 sp0;
227 u64 sp1;
228 u64 sp2;
229 u64 reserved2;
230 u64 ist[7];
231 u32 reserved3;
232 u32 reserved4;
233 u16 reserved5;
234 u16 io_bitmap_base;
235
236 } __attribute__((packed)) ____cacheline_aligned;
237 #endif
238
239 /*
240 * IO-bitmap sizes:
241 */
242 #define IO_BITMAP_BITS 65536
243 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
244 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
245 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
246 #define INVALID_IO_BITMAP_OFFSET 0x8000
247 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
248
249 struct tss_struct {
250 /*
251 * The hardware state:
252 */
253 struct x86_hw_tss x86_tss;
254
255 /*
256 * The extra 1 is there because the CPU will access an
257 * additional byte beyond the end of the IO permission
258 * bitmap. The extra byte must be all 1 bits, and must
259 * be within the limit.
260 */
261 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
262 /*
263 * Cache the current maximum and the last task that used the bitmap:
264 */
265 unsigned long io_bitmap_max;
266 struct thread_struct *io_bitmap_owner;
267
268 /*
269 * Pad the TSS to be cacheline-aligned (size is 0x100):
270 */
271 unsigned long __cacheline_filler[35];
272 /*
273 * .. and then another 0x100 bytes for the emergency kernel stack:
274 */
275 unsigned long stack[64];
276
277 } __attribute__((packed));
278
279 DECLARE_PER_CPU(struct tss_struct, init_tss);
280
281 /*
282 * Save the original ist values for checking stack pointers during debugging
283 */
284 struct orig_ist {
285 unsigned long ist[7];
286 };
287
288 #define MXCSR_DEFAULT 0x1f80
289
290 struct i387_fsave_struct {
291 u32 cwd; /* FPU Control Word */
292 u32 swd; /* FPU Status Word */
293 u32 twd; /* FPU Tag Word */
294 u32 fip; /* FPU IP Offset */
295 u32 fcs; /* FPU IP Selector */
296 u32 foo; /* FPU Operand Pointer Offset */
297 u32 fos; /* FPU Operand Pointer Selector */
298
299 /* 8*10 bytes for each FP-reg = 80 bytes: */
300 u32 st_space[20];
301
302 /* Software status information [not touched by FSAVE ]: */
303 u32 status;
304 };
305
306 struct i387_fxsave_struct {
307 u16 cwd; /* Control Word */
308 u16 swd; /* Status Word */
309 u16 twd; /* Tag Word */
310 u16 fop; /* Last Instruction Opcode */
311 union {
312 struct {
313 u64 rip; /* Instruction Pointer */
314 u64 rdp; /* Data Pointer */
315 };
316 struct {
317 u32 fip; /* FPU IP Offset */
318 u32 fcs; /* FPU IP Selector */
319 u32 foo; /* FPU Operand Offset */
320 u32 fos; /* FPU Operand Selector */
321 };
322 };
323 u32 mxcsr; /* MXCSR Register State */
324 u32 mxcsr_mask; /* MXCSR Mask */
325
326 /* 8*16 bytes for each FP-reg = 128 bytes: */
327 u32 st_space[32];
328
329 /* 16*16 bytes for each XMM-reg = 256 bytes: */
330 u32 xmm_space[64];
331
332 u32 padding[24];
333
334 } __attribute__((aligned(16)));
335
336 struct i387_soft_struct {
337 u32 cwd;
338 u32 swd;
339 u32 twd;
340 u32 fip;
341 u32 fcs;
342 u32 foo;
343 u32 fos;
344 /* 8*10 bytes for each FP-reg = 80 bytes: */
345 u32 st_space[20];
346 u8 ftop;
347 u8 changed;
348 u8 lookahead;
349 u8 no_update;
350 u8 rm;
351 u8 alimit;
352 struct info *info;
353 u32 entry_eip;
354 };
355
356 union thread_xstate {
357 struct i387_fsave_struct fsave;
358 struct i387_fxsave_struct fxsave;
359 struct i387_soft_struct soft;
360 };
361
362 #ifdef CONFIG_X86_64
363 DECLARE_PER_CPU(struct orig_ist, orig_ist);
364 #endif
365
366 extern void print_cpu_info(struct cpuinfo_x86 *);
367 extern unsigned int xstate_size;
368 extern void free_thread_xstate(struct task_struct *);
369 extern struct kmem_cache *task_xstate_cachep;
370 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
371 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
372 extern unsigned short num_cache_leaves;
373
374 struct thread_struct {
375 /* Cached TLS descriptors: */
376 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
377 unsigned long sp0;
378 unsigned long sp;
379 #ifdef CONFIG_X86_32
380 unsigned long sysenter_cs;
381 #else
382 unsigned long usersp; /* Copy from PDA */
383 unsigned short es;
384 unsigned short ds;
385 unsigned short fsindex;
386 unsigned short gsindex;
387 #endif
388 unsigned long ip;
389 unsigned long fs;
390 unsigned long gs;
391 /* Hardware debugging registers: */
392 unsigned long debugreg0;
393 unsigned long debugreg1;
394 unsigned long debugreg2;
395 unsigned long debugreg3;
396 unsigned long debugreg6;
397 unsigned long debugreg7;
398 /* Fault info: */
399 unsigned long cr2;
400 unsigned long trap_no;
401 unsigned long error_code;
402 /* floating point and extended processor state */
403 union thread_xstate *xstate;
404 #ifdef CONFIG_X86_32
405 /* Virtual 86 mode info */
406 struct vm86_struct __user *vm86_info;
407 unsigned long screen_bitmap;
408 unsigned long v86flags;
409 unsigned long v86mask;
410 unsigned long saved_sp0;
411 unsigned int saved_fs;
412 unsigned int saved_gs;
413 #endif
414 /* IO permissions: */
415 unsigned long *io_bitmap_ptr;
416 unsigned long iopl;
417 /* Max allowed port in the bitmap, in bytes: */
418 unsigned io_bitmap_max;
419 /* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set. */
420 unsigned long debugctlmsr;
421 /* Debug Store - if not 0 points to a DS Save Area configuration;
422 * goes into MSR_IA32_DS_AREA */
423 unsigned long ds_area_msr;
424 };
425
426 static inline unsigned long native_get_debugreg(int regno)
427 {
428 unsigned long val = 0; /* Damn you, gcc! */
429
430 switch (regno) {
431 case 0:
432 asm("mov %%db0, %0" :"=r" (val));
433 break;
434 case 1:
435 asm("mov %%db1, %0" :"=r" (val));
436 break;
437 case 2:
438 asm("mov %%db2, %0" :"=r" (val));
439 break;
440 case 3:
441 asm("mov %%db3, %0" :"=r" (val));
442 break;
443 case 6:
444 asm("mov %%db6, %0" :"=r" (val));
445 break;
446 case 7:
447 asm("mov %%db7, %0" :"=r" (val));
448 break;
449 default:
450 BUG();
451 }
452 return val;
453 }
454
455 static inline void native_set_debugreg(int regno, unsigned long value)
456 {
457 switch (regno) {
458 case 0:
459 asm("mov %0, %%db0" ::"r" (value));
460 break;
461 case 1:
462 asm("mov %0, %%db1" ::"r" (value));
463 break;
464 case 2:
465 asm("mov %0, %%db2" ::"r" (value));
466 break;
467 case 3:
468 asm("mov %0, %%db3" ::"r" (value));
469 break;
470 case 6:
471 asm("mov %0, %%db6" ::"r" (value));
472 break;
473 case 7:
474 asm("mov %0, %%db7" ::"r" (value));
475 break;
476 default:
477 BUG();
478 }
479 }
480
481 /*
482 * Set IOPL bits in EFLAGS from given mask
483 */
484 static inline void native_set_iopl_mask(unsigned mask)
485 {
486 #ifdef CONFIG_X86_32
487 unsigned int reg;
488
489 asm volatile ("pushfl;"
490 "popl %0;"
491 "andl %1, %0;"
492 "orl %2, %0;"
493 "pushl %0;"
494 "popfl"
495 : "=&r" (reg)
496 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
497 #endif
498 }
499
500 static inline void
501 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
502 {
503 tss->x86_tss.sp0 = thread->sp0;
504 #ifdef CONFIG_X86_32
505 /* Only happens when SEP is enabled, no need to test "SEP"arately: */
506 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
507 tss->x86_tss.ss1 = thread->sysenter_cs;
508 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
509 }
510 #endif
511 }
512
513 static inline void native_swapgs(void)
514 {
515 #ifdef CONFIG_X86_64
516 asm volatile("swapgs" ::: "memory");
517 #endif
518 }
519
520 #ifdef CONFIG_PARAVIRT
521 #include <asm/paravirt.h>
522 #else
523 #define __cpuid native_cpuid
524 #define paravirt_enabled() 0
525
526 /*
527 * These special macros can be used to get or set a debugging register
528 */
529 #define get_debugreg(var, register) \
530 (var) = native_get_debugreg(register)
531 #define set_debugreg(value, register) \
532 native_set_debugreg(register, value)
533
534 static inline void load_sp0(struct tss_struct *tss,
535 struct thread_struct *thread)
536 {
537 native_load_sp0(tss, thread);
538 }
539
540 #define set_iopl_mask native_set_iopl_mask
541 #define SWAPGS swapgs
542 #endif /* CONFIG_PARAVIRT */
543
544 /*
545 * Save the cr4 feature set we're using (ie
546 * Pentium 4MB enable and PPro Global page
547 * enable), so that any CPU's that boot up
548 * after us can get the correct flags.
549 */
550 extern unsigned long mmu_cr4_features;
551
552 static inline void set_in_cr4(unsigned long mask)
553 {
554 unsigned cr4;
555
556 mmu_cr4_features |= mask;
557 cr4 = read_cr4();
558 cr4 |= mask;
559 write_cr4(cr4);
560 }
561
562 static inline void clear_in_cr4(unsigned long mask)
563 {
564 unsigned cr4;
565
566 mmu_cr4_features &= ~mask;
567 cr4 = read_cr4();
568 cr4 &= ~mask;
569 write_cr4(cr4);
570 }
571
572 struct microcode_header {
573 unsigned int hdrver;
574 unsigned int rev;
575 unsigned int date;
576 unsigned int sig;
577 unsigned int cksum;
578 unsigned int ldrver;
579 unsigned int pf;
580 unsigned int datasize;
581 unsigned int totalsize;
582 unsigned int reserved[3];
583 };
584
585 struct microcode {
586 struct microcode_header hdr;
587 unsigned int bits[0];
588 };
589
590 typedef struct microcode microcode_t;
591 typedef struct microcode_header microcode_header_t;
592
593 /* microcode format is extended from prescott processors */
594 struct extended_signature {
595 unsigned int sig;
596 unsigned int pf;
597 unsigned int cksum;
598 };
599
600 struct extended_sigtable {
601 unsigned int count;
602 unsigned int cksum;
603 unsigned int reserved[3];
604 struct extended_signature sigs[0];
605 };
606
607 typedef struct {
608 unsigned long seg;
609 } mm_segment_t;
610
611
612 /*
613 * create a kernel thread without removing it from tasklists
614 */
615 extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
616
617 /* Free all resources held by a thread. */
618 extern void release_thread(struct task_struct *);
619
620 /* Prepare to copy thread state - unlazy all lazy state */
621 extern void prepare_to_copy(struct task_struct *tsk);
622
623 unsigned long get_wchan(struct task_struct *p);
624
625 /*
626 * Generic CPUID function
627 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
628 * resulting in stale register contents being returned.
629 */
630 static inline void cpuid(unsigned int op,
631 unsigned int *eax, unsigned int *ebx,
632 unsigned int *ecx, unsigned int *edx)
633 {
634 *eax = op;
635 *ecx = 0;
636 __cpuid(eax, ebx, ecx, edx);
637 }
638
639 /* Some CPUID calls want 'count' to be placed in ecx */
640 static inline void cpuid_count(unsigned int op, int count,
641 unsigned int *eax, unsigned int *ebx,
642 unsigned int *ecx, unsigned int *edx)
643 {
644 *eax = op;
645 *ecx = count;
646 __cpuid(eax, ebx, ecx, edx);
647 }
648
649 /*
650 * CPUID functions returning a single datum
651 */
652 static inline unsigned int cpuid_eax(unsigned int op)
653 {
654 unsigned int eax, ebx, ecx, edx;
655
656 cpuid(op, &eax, &ebx, &ecx, &edx);
657
658 return eax;
659 }
660
661 static inline unsigned int cpuid_ebx(unsigned int op)
662 {
663 unsigned int eax, ebx, ecx, edx;
664
665 cpuid(op, &eax, &ebx, &ecx, &edx);
666
667 return ebx;
668 }
669
670 static inline unsigned int cpuid_ecx(unsigned int op)
671 {
672 unsigned int eax, ebx, ecx, edx;
673
674 cpuid(op, &eax, &ebx, &ecx, &edx);
675
676 return ecx;
677 }
678
679 static inline unsigned int cpuid_edx(unsigned int op)
680 {
681 unsigned int eax, ebx, ecx, edx;
682
683 cpuid(op, &eax, &ebx, &ecx, &edx);
684
685 return edx;
686 }
687
688 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
689 static inline void rep_nop(void)
690 {
691 asm volatile("rep; nop" ::: "memory");
692 }
693
694 static inline void cpu_relax(void)
695 {
696 rep_nop();
697 }
698
699 /* Stop speculative execution: */
700 static inline void sync_core(void)
701 {
702 int tmp;
703
704 asm volatile("cpuid" : "=a" (tmp) : "0" (1)
705 : "ebx", "ecx", "edx", "memory");
706 }
707
708 static inline void __monitor(const void *eax, unsigned long ecx,
709 unsigned long edx)
710 {
711 /* "monitor %eax, %ecx, %edx;" */
712 asm volatile(".byte 0x0f, 0x01, 0xc8;"
713 :: "a" (eax), "c" (ecx), "d"(edx));
714 }
715
716 static inline void __mwait(unsigned long eax, unsigned long ecx)
717 {
718 /* "mwait %eax, %ecx;" */
719 asm volatile(".byte 0x0f, 0x01, 0xc9;"
720 :: "a" (eax), "c" (ecx));
721 }
722
723 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
724 {
725 trace_hardirqs_on();
726 /* "mwait %eax, %ecx;" */
727 asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
728 :: "a" (eax), "c" (ecx));
729 }
730
731 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
732
733 extern int force_mwait;
734
735 extern void select_idle_routine(const struct cpuinfo_x86 *c);
736
737 extern unsigned long boot_option_idle_override;
738
739 extern void enable_sep_cpu(void);
740 extern int sysenter_setup(void);
741
742 /* Defined in head.S */
743 extern struct desc_ptr early_gdt_descr;
744
745 extern void cpu_set_gdt(int);
746 extern void switch_to_new_gdt(void);
747 extern void cpu_init(void);
748 extern void init_gdt(int cpu);
749
750 static inline void update_debugctlmsr(unsigned long debugctlmsr)
751 {
752 #ifndef CONFIG_X86_DEBUGCTLMSR
753 if (boot_cpu_data.x86 < 6)
754 return;
755 #endif
756 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
757 }
758
759 /*
760 * from system description table in BIOS. Mostly for MCA use, but
761 * others may find it useful:
762 */
763 extern unsigned int machine_id;
764 extern unsigned int machine_submodel_id;
765 extern unsigned int BIOS_revision;
766
767 /* Boot loader type from the setup header: */
768 extern int bootloader_type;
769
770 extern char ignore_fpu_irq;
771
772 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
773 #define ARCH_HAS_PREFETCHW
774 #define ARCH_HAS_SPINLOCK_PREFETCH
775
776 #ifdef CONFIG_X86_32
777 # define BASE_PREFETCH ASM_NOP4
778 # define ARCH_HAS_PREFETCH
779 #else
780 # define BASE_PREFETCH "prefetcht0 (%1)"
781 #endif
782
783 /*
784 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
785 *
786 * It's not worth to care about 3dnow prefetches for the K6
787 * because they are microcoded there and very slow.
788 */
789 static inline void prefetch(const void *x)
790 {
791 alternative_input(BASE_PREFETCH,
792 "prefetchnta (%1)",
793 X86_FEATURE_XMM,
794 "r" (x));
795 }
796
797 /*
798 * 3dnow prefetch to get an exclusive cache line.
799 * Useful for spinlocks to avoid one state transition in the
800 * cache coherency protocol:
801 */
802 static inline void prefetchw(const void *x)
803 {
804 alternative_input(BASE_PREFETCH,
805 "prefetchw (%1)",
806 X86_FEATURE_3DNOW,
807 "r" (x));
808 }
809
810 static inline void spin_lock_prefetch(const void *x)
811 {
812 prefetchw(x);
813 }
814
815 #ifdef CONFIG_X86_32
816 /*
817 * User space process size: 3GB (default).
818 */
819 #define TASK_SIZE PAGE_OFFSET
820 #define STACK_TOP TASK_SIZE
821 #define STACK_TOP_MAX STACK_TOP
822
823 #define INIT_THREAD { \
824 .sp0 = sizeof(init_stack) + (long)&init_stack, \
825 .vm86_info = NULL, \
826 .sysenter_cs = __KERNEL_CS, \
827 .io_bitmap_ptr = NULL, \
828 .fs = __KERNEL_PERCPU, \
829 }
830
831 /*
832 * Note that the .io_bitmap member must be extra-big. This is because
833 * the CPU will access an additional byte beyond the end of the IO
834 * permission bitmap. The extra byte must be all 1 bits, and must
835 * be within the limit.
836 */
837 #define INIT_TSS { \
838 .x86_tss = { \
839 .sp0 = sizeof(init_stack) + (long)&init_stack, \
840 .ss0 = __KERNEL_DS, \
841 .ss1 = __KERNEL_CS, \
842 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
843 }, \
844 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \
845 }
846
847 extern unsigned long thread_saved_pc(struct task_struct *tsk);
848
849 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
850 #define KSTK_TOP(info) \
851 ({ \
852 unsigned long *__ptr = (unsigned long *)(info); \
853 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
854 })
855
856 /*
857 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
858 * This is necessary to guarantee that the entire "struct pt_regs"
859 * is accessable even if the CPU haven't stored the SS/ESP registers
860 * on the stack (interrupt gate does not save these registers
861 * when switching to the same priv ring).
862 * Therefore beware: accessing the ss/esp fields of the
863 * "struct pt_regs" is possible, but they may contain the
864 * completely wrong values.
865 */
866 #define task_pt_regs(task) \
867 ({ \
868 struct pt_regs *__regs__; \
869 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
870 __regs__ - 1; \
871 })
872
873 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
874
875 #else
876 /*
877 * User space process size. 47bits minus one guard page.
878 */
879 #define TASK_SIZE64 ((1UL << 47) - PAGE_SIZE)
880
881 /* This decides where the kernel will search for a free chunk of vm
882 * space during mmap's.
883 */
884 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
885 0xc0000000 : 0xFFFFe000)
886
887 #define TASK_SIZE (test_thread_flag(TIF_IA32) ? \
888 IA32_PAGE_OFFSET : TASK_SIZE64)
889 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? \
890 IA32_PAGE_OFFSET : TASK_SIZE64)
891
892 #define STACK_TOP TASK_SIZE
893 #define STACK_TOP_MAX TASK_SIZE64
894
895 #define INIT_THREAD { \
896 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
897 }
898
899 #define INIT_TSS { \
900 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
901 }
902
903 /*
904 * Return saved PC of a blocked thread.
905 * What is this good for? it will be always the scheduler or ret_from_fork.
906 */
907 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
908
909 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
910 #define KSTK_ESP(tsk) -1 /* sorry. doesn't work for syscall. */
911 #endif /* CONFIG_X86_64 */
912
913 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
914 unsigned long new_sp);
915
916 /*
917 * This decides where the kernel will search for a free chunk of vm
918 * space during mmap's.
919 */
920 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
921
922 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
923
924 /* Get/set a process' ability to use the timestamp counter instruction */
925 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
926 #define SET_TSC_CTL(val) set_tsc_mode((val))
927
928 extern int get_tsc_mode(unsigned long adr);
929 extern int set_tsc_mode(unsigned int val);
930
931 #endif
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