x86: unmask CPUID levels on Intel CPUs
[linux-2.6/mini2440.git] / drivers / staging / meilhaus / me8200_di_reg.h
blobb9a619d31c2cef0aa682a69d68708ef0cfaf504b
1 /**
2 * @file me8200_di_reg.h
4 * @brief ME-8200 digital input subdevice register definitions.
5 * @note Copyright (C) 2007 Meilhaus Electronic GmbH (support@meilhaus.de)
6 * @author Guenter Gebhardt
7 */
9 /*
10 * Copyright (C) 2007 Meilhaus Electronic GmbH (support@meilhaus.de)
12 * This file is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
27 #ifndef _ME8200_DI_REG_H_
28 #define _ME8200_DI_REG_H_
30 #ifdef __KERNEL__
32 // Common registry for whole family.
33 #define ME8200_DI_PORT_0_REG 0x3 // R
34 #define ME8200_DI_PORT_1_REG 0x4 // R
36 #define ME8200_DI_MASK_0_REG 0x5 // R/W
37 #define ME8200_DI_MASK_1_REG 0x6 // R/W
39 #define ME8200_DI_COMPARE_0_REG 0xA // R/W
40 #define ME8200_DI_COMPARE_1_REG 0xB // R/W
42 #define ME8200_DI_IRQ_CTRL_REG 0xC // R/W
44 #ifndef ME8200_IRQ_MODE_REG
45 # define ME8200_IRQ_MODE_REG 0xD // R/W
46 #endif
48 // This registry are for all versions
49 #define ME8200_DI_CHANGE_0_REG 0xE // R
50 #define ME8200_DI_CHANGE_1_REG 0xF // R
52 #define ME8200_DI_IRQ_CTRL_BIT_CLEAR 0x4
53 #define ME8200_DI_IRQ_CTRL_BIT_ENABLE 0x8
55 // This registry are for firmware versions 7 and later
56 #define ME8200_DI_EXTEND_CHANGE_0_LOW_REG 0x10 // R
57 #define ME8200_DI_EXTEND_CHANGE_0_HIGH_REG 0x11 // R
58 #define ME8200_DI_EXTEND_CHANGE_1_LOW_REG 0x12 // R
59 #define ME8200_DI_EXTEND_CHANGE_1_HIGH_REG 0x13 // R
61 #ifndef ME8200_FIRMWARE_VERSION_REG
62 # define ME8200_FIRMWARE_VERSION_REG 0x14 // R
63 #endif
65 // Bit definitions
66 #define ME8200_DI_IRQ_CTRL_MASK_EDGE 0x3
67 #define ME8200_DI_IRQ_CTRL_MASK_EDGE_RISING 0x0
68 #define ME8200_DI_IRQ_CTRL_MASK_EDGE_FALLING 0x1
69 #define ME8200_DI_IRQ_CTRL_MASK_EDGE_ANY 0x3
71 // Others
72 #define ME8200_DI_IRQ_CTRL_SHIFT 4
74 #endif
75 #endif