2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
7 * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
10 #include <linux/init.h>
11 #include <linux/kernel.h>
12 #include <linux/sched.h>
14 #include <linux/bitops.h>
16 #include <asm/bcache.h>
17 #include <asm/bootinfo.h>
18 #include <asm/cache.h>
19 #include <asm/cacheops.h>
21 #include <asm/cpu-features.h>
24 #include <asm/pgtable.h>
25 #include <asm/r4kcache.h>
26 #include <asm/system.h>
27 #include <asm/mmu_context.h>
29 #include <asm/cacheflush.h> /* for run_uncached() */
33 * Special Variant of smp_call_function for use by cache functions:
36 * o collapses to normal function call on UP kernels
37 * o collapses to normal function call on systems with a single shared
40 static inline void r4k_on_each_cpu(void (*func
) (void *info
), void *info
,
45 #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
46 smp_call_function(func
, info
, retry
, wait
);
55 static unsigned long icache_size __read_mostly
;
56 static unsigned long dcache_size __read_mostly
;
57 static unsigned long scache_size __read_mostly
;
60 * Dummy cache handling routines for machines without boardcaches
62 static void cache_noop(void) {}
64 static struct bcache_ops no_sc_ops
= {
65 .bc_enable
= (void *)cache_noop
,
66 .bc_disable
= (void *)cache_noop
,
67 .bc_wback_inv
= (void *)cache_noop
,
68 .bc_inv
= (void *)cache_noop
71 struct bcache_ops
*bcops
= &no_sc_ops
;
73 #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010)
74 #define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020)
76 #define R4600_HIT_CACHEOP_WAR_IMPL \
78 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \
79 *(volatile unsigned long *)CKSEG1; \
80 if (R4600_V1_HIT_CACHEOP_WAR) \
81 __asm__ __volatile__("nop;nop;nop;nop"); \
84 static void (*r4k_blast_dcache_page
)(unsigned long addr
);
86 static inline void r4k_blast_dcache_page_dc32(unsigned long addr
)
88 R4600_HIT_CACHEOP_WAR_IMPL
;
89 blast_dcache32_page(addr
);
92 static void __init
r4k_blast_dcache_page_setup(void)
94 unsigned long dc_lsize
= cpu_dcache_line_size();
97 r4k_blast_dcache_page
= (void *)cache_noop
;
98 else if (dc_lsize
== 16)
99 r4k_blast_dcache_page
= blast_dcache16_page
;
100 else if (dc_lsize
== 32)
101 r4k_blast_dcache_page
= r4k_blast_dcache_page_dc32
;
104 static void (* r4k_blast_dcache_page_indexed
)(unsigned long addr
);
106 static void __init
r4k_blast_dcache_page_indexed_setup(void)
108 unsigned long dc_lsize
= cpu_dcache_line_size();
111 r4k_blast_dcache_page_indexed
= (void *)cache_noop
;
112 else if (dc_lsize
== 16)
113 r4k_blast_dcache_page_indexed
= blast_dcache16_page_indexed
;
114 else if (dc_lsize
== 32)
115 r4k_blast_dcache_page_indexed
= blast_dcache32_page_indexed
;
118 static void (* r4k_blast_dcache
)(void);
120 static void __init
r4k_blast_dcache_setup(void)
122 unsigned long dc_lsize
= cpu_dcache_line_size();
125 r4k_blast_dcache
= (void *)cache_noop
;
126 else if (dc_lsize
== 16)
127 r4k_blast_dcache
= blast_dcache16
;
128 else if (dc_lsize
== 32)
129 r4k_blast_dcache
= blast_dcache32
;
132 /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
133 #define JUMP_TO_ALIGN(order) \
134 __asm__ __volatile__( \
136 ".align\t" #order "\n\t" \
139 #define CACHE32_UNROLL32_ALIGN JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
140 #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11)
142 static inline void blast_r4600_v1_icache32(void)
146 local_irq_save(flags
);
148 local_irq_restore(flags
);
151 static inline void tx49_blast_icache32(void)
153 unsigned long start
= INDEX_BASE
;
154 unsigned long end
= start
+ current_cpu_data
.icache
.waysize
;
155 unsigned long ws_inc
= 1UL << current_cpu_data
.icache
.waybit
;
156 unsigned long ws_end
= current_cpu_data
.icache
.ways
<<
157 current_cpu_data
.icache
.waybit
;
158 unsigned long ws
, addr
;
160 CACHE32_UNROLL32_ALIGN2
;
161 /* I'm in even chunk. blast odd chunks */
162 for (ws
= 0; ws
< ws_end
; ws
+= ws_inc
)
163 for (addr
= start
+ 0x400; addr
< end
; addr
+= 0x400 * 2)
164 cache32_unroll32(addr
|ws
,Index_Invalidate_I
);
165 CACHE32_UNROLL32_ALIGN
;
166 /* I'm in odd chunk. blast even chunks */
167 for (ws
= 0; ws
< ws_end
; ws
+= ws_inc
)
168 for (addr
= start
; addr
< end
; addr
+= 0x400 * 2)
169 cache32_unroll32(addr
|ws
,Index_Invalidate_I
);
172 static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page
)
176 local_irq_save(flags
);
177 blast_icache32_page_indexed(page
);
178 local_irq_restore(flags
);
181 static inline void tx49_blast_icache32_page_indexed(unsigned long page
)
183 unsigned long indexmask
= current_cpu_data
.icache
.waysize
- 1;
184 unsigned long start
= INDEX_BASE
+ (page
& indexmask
);
185 unsigned long end
= start
+ PAGE_SIZE
;
186 unsigned long ws_inc
= 1UL << current_cpu_data
.icache
.waybit
;
187 unsigned long ws_end
= current_cpu_data
.icache
.ways
<<
188 current_cpu_data
.icache
.waybit
;
189 unsigned long ws
, addr
;
191 CACHE32_UNROLL32_ALIGN2
;
192 /* I'm in even chunk. blast odd chunks */
193 for (ws
= 0; ws
< ws_end
; ws
+= ws_inc
)
194 for (addr
= start
+ 0x400; addr
< end
; addr
+= 0x400 * 2)
195 cache32_unroll32(addr
|ws
,Index_Invalidate_I
);
196 CACHE32_UNROLL32_ALIGN
;
197 /* I'm in odd chunk. blast even chunks */
198 for (ws
= 0; ws
< ws_end
; ws
+= ws_inc
)
199 for (addr
= start
; addr
< end
; addr
+= 0x400 * 2)
200 cache32_unroll32(addr
|ws
,Index_Invalidate_I
);
203 static void (* r4k_blast_icache_page
)(unsigned long addr
);
205 static void __init
r4k_blast_icache_page_setup(void)
207 unsigned long ic_lsize
= cpu_icache_line_size();
210 r4k_blast_icache_page
= (void *)cache_noop
;
211 else if (ic_lsize
== 16)
212 r4k_blast_icache_page
= blast_icache16_page
;
213 else if (ic_lsize
== 32)
214 r4k_blast_icache_page
= blast_icache32_page
;
215 else if (ic_lsize
== 64)
216 r4k_blast_icache_page
= blast_icache64_page
;
220 static void (* r4k_blast_icache_page_indexed
)(unsigned long addr
);
222 static void __init
r4k_blast_icache_page_indexed_setup(void)
224 unsigned long ic_lsize
= cpu_icache_line_size();
227 r4k_blast_icache_page_indexed
= (void *)cache_noop
;
228 else if (ic_lsize
== 16)
229 r4k_blast_icache_page_indexed
= blast_icache16_page_indexed
;
230 else if (ic_lsize
== 32) {
231 if (R4600_V1_INDEX_ICACHEOP_WAR
&& cpu_is_r4600_v1_x())
232 r4k_blast_icache_page_indexed
=
233 blast_icache32_r4600_v1_page_indexed
;
234 else if (TX49XX_ICACHE_INDEX_INV_WAR
)
235 r4k_blast_icache_page_indexed
=
236 tx49_blast_icache32_page_indexed
;
238 r4k_blast_icache_page_indexed
=
239 blast_icache32_page_indexed
;
240 } else if (ic_lsize
== 64)
241 r4k_blast_icache_page_indexed
= blast_icache64_page_indexed
;
244 static void (* r4k_blast_icache
)(void);
246 static void __init
r4k_blast_icache_setup(void)
248 unsigned long ic_lsize
= cpu_icache_line_size();
251 r4k_blast_icache
= (void *)cache_noop
;
252 else if (ic_lsize
== 16)
253 r4k_blast_icache
= blast_icache16
;
254 else if (ic_lsize
== 32) {
255 if (R4600_V1_INDEX_ICACHEOP_WAR
&& cpu_is_r4600_v1_x())
256 r4k_blast_icache
= blast_r4600_v1_icache32
;
257 else if (TX49XX_ICACHE_INDEX_INV_WAR
)
258 r4k_blast_icache
= tx49_blast_icache32
;
260 r4k_blast_icache
= blast_icache32
;
261 } else if (ic_lsize
== 64)
262 r4k_blast_icache
= blast_icache64
;
265 static void (* r4k_blast_scache_page
)(unsigned long addr
);
267 static void __init
r4k_blast_scache_page_setup(void)
269 unsigned long sc_lsize
= cpu_scache_line_size();
271 if (scache_size
== 0)
272 r4k_blast_scache_page
= (void *)cache_noop
;
273 else if (sc_lsize
== 16)
274 r4k_blast_scache_page
= blast_scache16_page
;
275 else if (sc_lsize
== 32)
276 r4k_blast_scache_page
= blast_scache32_page
;
277 else if (sc_lsize
== 64)
278 r4k_blast_scache_page
= blast_scache64_page
;
279 else if (sc_lsize
== 128)
280 r4k_blast_scache_page
= blast_scache128_page
;
283 static void (* r4k_blast_scache_page_indexed
)(unsigned long addr
);
285 static void __init
r4k_blast_scache_page_indexed_setup(void)
287 unsigned long sc_lsize
= cpu_scache_line_size();
289 if (scache_size
== 0)
290 r4k_blast_scache_page_indexed
= (void *)cache_noop
;
291 else if (sc_lsize
== 16)
292 r4k_blast_scache_page_indexed
= blast_scache16_page_indexed
;
293 else if (sc_lsize
== 32)
294 r4k_blast_scache_page_indexed
= blast_scache32_page_indexed
;
295 else if (sc_lsize
== 64)
296 r4k_blast_scache_page_indexed
= blast_scache64_page_indexed
;
297 else if (sc_lsize
== 128)
298 r4k_blast_scache_page_indexed
= blast_scache128_page_indexed
;
301 static void (* r4k_blast_scache
)(void);
303 static void __init
r4k_blast_scache_setup(void)
305 unsigned long sc_lsize
= cpu_scache_line_size();
307 if (scache_size
== 0)
308 r4k_blast_scache
= (void *)cache_noop
;
309 else if (sc_lsize
== 16)
310 r4k_blast_scache
= blast_scache16
;
311 else if (sc_lsize
== 32)
312 r4k_blast_scache
= blast_scache32
;
313 else if (sc_lsize
== 64)
314 r4k_blast_scache
= blast_scache64
;
315 else if (sc_lsize
== 128)
316 r4k_blast_scache
= blast_scache128
;
320 * This is former mm's flush_cache_all() which really should be
321 * flush_cache_vunmap these days ...
323 static inline void local_r4k_flush_cache_all(void * args
)
328 static void r4k_flush_cache_all(void)
330 if (!cpu_has_dc_aliases
)
333 r4k_on_each_cpu(local_r4k_flush_cache_all
, NULL
, 1, 1);
336 static inline void local_r4k___flush_cache_all(void * args
)
341 switch (current_cpu_data
.cputype
) {
353 static void r4k___flush_cache_all(void)
355 r4k_on_each_cpu(local_r4k___flush_cache_all
, NULL
, 1, 1);
358 static inline void local_r4k_flush_cache_range(void * args
)
360 struct vm_area_struct
*vma
= args
;
362 if (!(cpu_context(smp_processor_id(), vma
->vm_mm
)))
368 static void r4k_flush_cache_range(struct vm_area_struct
*vma
,
369 unsigned long start
, unsigned long end
)
371 if (!cpu_has_dc_aliases
)
374 r4k_on_each_cpu(local_r4k_flush_cache_range
, vma
, 1, 1);
377 static inline void local_r4k_flush_cache_mm(void * args
)
379 struct mm_struct
*mm
= args
;
381 if (!cpu_context(smp_processor_id(), mm
))
387 * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we
388 * only flush the primary caches but R10000 and R12000 behave sane ...
390 if (current_cpu_data
.cputype
== CPU_R4000SC
||
391 current_cpu_data
.cputype
== CPU_R4000MC
||
392 current_cpu_data
.cputype
== CPU_R4400SC
||
393 current_cpu_data
.cputype
== CPU_R4400MC
)
397 static void r4k_flush_cache_mm(struct mm_struct
*mm
)
399 if (!cpu_has_dc_aliases
)
402 r4k_on_each_cpu(local_r4k_flush_cache_mm
, mm
, 1, 1);
405 struct flush_cache_page_args
{
406 struct vm_area_struct
*vma
;
411 static inline void local_r4k_flush_cache_page(void *args
)
413 struct flush_cache_page_args
*fcp_args
= args
;
414 struct vm_area_struct
*vma
= fcp_args
->vma
;
415 unsigned long addr
= fcp_args
->addr
;
416 unsigned long paddr
= fcp_args
->pfn
<< PAGE_SHIFT
;
417 int exec
= vma
->vm_flags
& VM_EXEC
;
418 struct mm_struct
*mm
= vma
->vm_mm
;
425 * If ownes no valid ASID yet, cannot possibly have gotten
426 * this page into the cache.
428 if (cpu_context(smp_processor_id(), mm
) == 0)
432 pgdp
= pgd_offset(mm
, addr
);
433 pudp
= pud_offset(pgdp
, addr
);
434 pmdp
= pmd_offset(pudp
, addr
);
435 ptep
= pte_offset(pmdp
, addr
);
438 * If the page isn't marked valid, the page cannot possibly be
441 if (!(pte_val(*ptep
) & _PAGE_PRESENT
))
445 * Doing flushes for another ASID than the current one is
446 * too difficult since stupid R4k caches do a TLB translation
447 * for every cache flush operation. So we do indexed flushes
448 * in that case, which doesn't overly flush the cache too much.
450 if ((mm
== current
->active_mm
) && (pte_val(*ptep
) & _PAGE_VALID
)) {
451 if (cpu_has_dc_aliases
|| (exec
&& !cpu_has_ic_fills_f_dc
)) {
452 r4k_blast_dcache_page(addr
);
453 if (exec
&& !cpu_icache_snoops_remote_store
)
454 r4k_blast_scache_page(addr
);
457 r4k_blast_icache_page(addr
);
463 * Do indexed flush, too much work to get the (possible) TLB refills
466 if (cpu_has_dc_aliases
|| (exec
&& !cpu_has_ic_fills_f_dc
)) {
467 r4k_blast_dcache_page_indexed(cpu_has_pindexed_dcache
?
469 if (exec
&& !cpu_icache_snoops_remote_store
) {
470 r4k_blast_scache_page_indexed(paddr
);
474 if (cpu_has_vtag_icache
&& mm
== current
->active_mm
) {
475 int cpu
= smp_processor_id();
477 if (cpu_context(cpu
, mm
) != 0)
478 drop_mmu_context(mm
, cpu
);
480 r4k_blast_icache_page_indexed(addr
);
484 static void r4k_flush_cache_page(struct vm_area_struct
*vma
,
485 unsigned long addr
, unsigned long pfn
)
487 struct flush_cache_page_args args
;
493 r4k_on_each_cpu(local_r4k_flush_cache_page
, &args
, 1, 1);
496 static inline void local_r4k_flush_data_cache_page(void * addr
)
498 r4k_blast_dcache_page((unsigned long) addr
);
501 static void r4k_flush_data_cache_page(unsigned long addr
)
503 r4k_on_each_cpu(local_r4k_flush_data_cache_page
, (void *) addr
, 1, 1);
506 struct flush_icache_range_args
{
511 static inline void local_r4k_flush_icache_range(void *args
)
513 struct flush_icache_range_args
*fir_args
= args
;
514 unsigned long start
= fir_args
->start
;
515 unsigned long end
= fir_args
->end
;
517 if (!cpu_has_ic_fills_f_dc
) {
518 if (end
- start
>= dcache_size
) {
521 R4600_HIT_CACHEOP_WAR_IMPL
;
522 protected_blast_dcache_range(start
, end
);
525 if (!cpu_icache_snoops_remote_store
&& scache_size
) {
526 if (end
- start
> scache_size
)
529 protected_blast_scache_range(start
, end
);
533 if (end
- start
> icache_size
)
536 protected_blast_icache_range(start
, end
);
539 static void r4k_flush_icache_range(unsigned long start
, unsigned long end
)
541 struct flush_icache_range_args args
;
546 r4k_on_each_cpu(local_r4k_flush_icache_range
, &args
, 1, 1);
547 instruction_hazard();
550 #ifdef CONFIG_DMA_NONCOHERENT
552 static void r4k_dma_cache_wback_inv(unsigned long addr
, unsigned long size
)
554 /* Catch bad driver code */
557 if (cpu_has_inclusive_pcaches
) {
558 if (size
>= scache_size
)
561 blast_scache_range(addr
, addr
+ size
);
566 * Either no secondary cache or the available caches don't have the
567 * subset property so we have to flush the primary caches
570 if (size
>= dcache_size
) {
573 R4600_HIT_CACHEOP_WAR_IMPL
;
574 blast_dcache_range(addr
, addr
+ size
);
577 bc_wback_inv(addr
, size
);
580 static void r4k_dma_cache_inv(unsigned long addr
, unsigned long size
)
582 /* Catch bad driver code */
585 if (cpu_has_inclusive_pcaches
) {
586 if (size
>= scache_size
)
589 blast_scache_range(addr
, addr
+ size
);
593 if (size
>= dcache_size
) {
596 R4600_HIT_CACHEOP_WAR_IMPL
;
597 blast_dcache_range(addr
, addr
+ size
);
602 #endif /* CONFIG_DMA_NONCOHERENT */
605 * While we're protected against bad userland addresses we don't care
606 * very much about what happens in that case. Usually a segmentation
607 * fault will dump the process later on anyway ...
609 static void local_r4k_flush_cache_sigtramp(void * arg
)
611 unsigned long ic_lsize
= cpu_icache_line_size();
612 unsigned long dc_lsize
= cpu_dcache_line_size();
613 unsigned long sc_lsize
= cpu_scache_line_size();
614 unsigned long addr
= (unsigned long) arg
;
616 R4600_HIT_CACHEOP_WAR_IMPL
;
618 protected_writeback_dcache_line(addr
& ~(dc_lsize
- 1));
619 if (!cpu_icache_snoops_remote_store
&& scache_size
)
620 protected_writeback_scache_line(addr
& ~(sc_lsize
- 1));
622 protected_flush_icache_line(addr
& ~(ic_lsize
- 1));
623 if (MIPS4K_ICACHE_REFILL_WAR
) {
624 __asm__
__volatile__ (
639 : "i" (Hit_Invalidate_I
));
641 if (MIPS_CACHE_SYNC_WAR
)
642 __asm__
__volatile__ ("sync");
645 static void r4k_flush_cache_sigtramp(unsigned long addr
)
647 r4k_on_each_cpu(local_r4k_flush_cache_sigtramp
, (void *) addr
, 1, 1);
650 static void r4k_flush_icache_all(void)
652 if (cpu_has_vtag_icache
)
656 static inline void rm7k_erratum31(void)
658 const unsigned long ic_lsize
= 32;
661 /* RM7000 erratum #31. The icache is screwed at startup. */
665 for (addr
= INDEX_BASE
; addr
<= INDEX_BASE
+ 4096; addr
+= ic_lsize
) {
666 __asm__
__volatile__ (
670 "cache\t%1, 0(%0)\n\t"
671 "cache\t%1, 0x1000(%0)\n\t"
672 "cache\t%1, 0x2000(%0)\n\t"
673 "cache\t%1, 0x3000(%0)\n\t"
674 "cache\t%2, 0(%0)\n\t"
675 "cache\t%2, 0x1000(%0)\n\t"
676 "cache\t%2, 0x2000(%0)\n\t"
677 "cache\t%2, 0x3000(%0)\n\t"
678 "cache\t%1, 0(%0)\n\t"
679 "cache\t%1, 0x1000(%0)\n\t"
680 "cache\t%1, 0x2000(%0)\n\t"
681 "cache\t%1, 0x3000(%0)\n\t"
684 : "r" (addr
), "i" (Index_Store_Tag_I
), "i" (Fill
));
688 static char *way_string
[] __initdata
= { NULL
, "direct mapped", "2-way",
689 "3-way", "4-way", "5-way", "6-way", "7-way", "8-way"
692 static void __init
probe_pcache(void)
694 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
695 unsigned int config
= read_c0_config();
696 unsigned int prid
= read_c0_prid();
697 unsigned long config1
;
700 switch (c
->cputype
) {
701 case CPU_R4600
: /* QED style two way caches? */
705 icache_size
= 1 << (12 + ((config
& CONF_IC
) >> 9));
706 c
->icache
.linesz
= 16 << ((config
& CONF_IB
) >> 5);
708 c
->icache
.waybit
= __ffs(icache_size
/2);
710 dcache_size
= 1 << (12 + ((config
& CONF_DC
) >> 6));
711 c
->dcache
.linesz
= 16 << ((config
& CONF_DB
) >> 4);
713 c
->dcache
.waybit
= __ffs(dcache_size
/2);
715 c
->options
|= MIPS_CPU_CACHE_CDEX_P
;
720 icache_size
= 1 << (12 + ((config
& CONF_IC
) >> 9));
721 c
->icache
.linesz
= 16 << ((config
& CONF_IB
) >> 5);
725 dcache_size
= 1 << (12 + ((config
& CONF_DC
) >> 6));
726 c
->dcache
.linesz
= 16 << ((config
& CONF_DB
) >> 4);
728 c
->dcache
.waybit
= 0;
730 c
->options
|= MIPS_CPU_CACHE_CDEX_P
;
734 icache_size
= 1 << (12 + ((config
& CONF_IC
) >> 9));
735 c
->icache
.linesz
= 16 << ((config
& CONF_IB
) >> 5);
739 dcache_size
= 1 << (12 + ((config
& CONF_DC
) >> 6));
740 c
->dcache
.linesz
= 16 << ((config
& CONF_DB
) >> 4);
742 c
->dcache
.waybit
= 0;
744 c
->options
|= MIPS_CPU_CACHE_CDEX_P
;
745 c
->options
|= MIPS_CPU_PREFETCH
;
755 icache_size
= 1 << (12 + ((config
& CONF_IC
) >> 9));
756 c
->icache
.linesz
= 16 << ((config
& CONF_IB
) >> 5);
758 c
->icache
.waybit
= 0; /* doesn't matter */
760 dcache_size
= 1 << (12 + ((config
& CONF_DC
) >> 6));
761 c
->dcache
.linesz
= 16 << ((config
& CONF_DB
) >> 4);
763 c
->dcache
.waybit
= 0; /* does not matter */
765 c
->options
|= MIPS_CPU_CACHE_CDEX_P
;
771 icache_size
= 1 << (12 + ((config
& R10K_CONF_IC
) >> 29));
772 c
->icache
.linesz
= 64;
774 c
->icache
.waybit
= 0;
776 dcache_size
= 1 << (12 + ((config
& R10K_CONF_DC
) >> 26));
777 c
->dcache
.linesz
= 32;
779 c
->dcache
.waybit
= 0;
781 c
->options
|= MIPS_CPU_PREFETCH
;
785 write_c0_config(config
& ~VR41_CONF_P4K
);
787 /* Workaround for cache instruction bug of VR4131 */
788 if (c
->processor_id
== 0x0c80U
|| c
->processor_id
== 0x0c81U
||
789 c
->processor_id
== 0x0c82U
) {
790 config
|= 0x00400000U
;
791 if (c
->processor_id
== 0x0c80U
)
792 config
|= VR41_CONF_BP
;
793 write_c0_config(config
);
795 c
->options
|= MIPS_CPU_CACHE_CDEX_P
;
797 icache_size
= 1 << (10 + ((config
& CONF_IC
) >> 9));
798 c
->icache
.linesz
= 16 << ((config
& CONF_IB
) >> 5);
800 c
->icache
.waybit
= __ffs(icache_size
/2);
802 dcache_size
= 1 << (10 + ((config
& CONF_DC
) >> 6));
803 c
->dcache
.linesz
= 16 << ((config
& CONF_DB
) >> 4);
805 c
->dcache
.waybit
= __ffs(dcache_size
/2);
814 icache_size
= 1 << (10 + ((config
& CONF_IC
) >> 9));
815 c
->icache
.linesz
= 16 << ((config
& CONF_IB
) >> 5);
817 c
->icache
.waybit
= 0; /* doesn't matter */
819 dcache_size
= 1 << (10 + ((config
& CONF_DC
) >> 6));
820 c
->dcache
.linesz
= 16 << ((config
& CONF_DB
) >> 4);
822 c
->dcache
.waybit
= 0; /* does not matter */
824 c
->options
|= MIPS_CPU_CACHE_CDEX_P
;
831 icache_size
= 1 << (12 + ((config
& CONF_IC
) >> 9));
832 c
->icache
.linesz
= 16 << ((config
& CONF_IB
) >> 5);
834 c
->icache
.waybit
= __ffs(icache_size
/ c
->icache
.ways
);
836 dcache_size
= 1 << (12 + ((config
& CONF_DC
) >> 6));
837 c
->dcache
.linesz
= 16 << ((config
& CONF_DB
) >> 4);
839 c
->dcache
.waybit
= __ffs(dcache_size
/ c
->dcache
.ways
);
841 #if !defined(CONFIG_SMP) || !defined(RM9000_CDEX_SMP_WAR)
842 c
->options
|= MIPS_CPU_CACHE_CDEX_P
;
844 c
->options
|= MIPS_CPU_PREFETCH
;
848 if (!(config
& MIPS_CONF_M
))
849 panic("Don't know how to probe P-caches on this cpu.");
852 * So we seem to be a MIPS32 or MIPS64 CPU
853 * So let's probe the I-cache ...
855 config1
= read_c0_config1();
857 if ((lsize
= ((config1
>> 19) & 7)))
858 c
->icache
.linesz
= 2 << lsize
;
860 c
->icache
.linesz
= lsize
;
861 c
->icache
.sets
= 64 << ((config1
>> 22) & 7);
862 c
->icache
.ways
= 1 + ((config1
>> 16) & 7);
864 icache_size
= c
->icache
.sets
*
867 c
->icache
.waybit
= __ffs(icache_size
/c
->icache
.ways
);
869 if (config
& 0x8) /* VI bit */
870 c
->icache
.flags
|= MIPS_CACHE_VTAG
;
873 * Now probe the MIPS32 / MIPS64 data cache.
877 if ((lsize
= ((config1
>> 10) & 7)))
878 c
->dcache
.linesz
= 2 << lsize
;
880 c
->dcache
.linesz
= lsize
;
881 c
->dcache
.sets
= 64 << ((config1
>> 13) & 7);
882 c
->dcache
.ways
= 1 + ((config1
>> 7) & 7);
884 dcache_size
= c
->dcache
.sets
*
887 c
->dcache
.waybit
= __ffs(dcache_size
/c
->dcache
.ways
);
889 c
->options
|= MIPS_CPU_PREFETCH
;
894 * Processor configuration sanity check for the R4000SC erratum
895 * #5. With page sizes larger than 32kB there is no possibility
896 * to get a VCE exception anymore so we don't care about this
897 * misconfiguration. The case is rather theoretical anyway;
898 * presumably no vendor is shipping his hardware in the "bad"
901 if ((prid
& 0xff00) == PRID_IMP_R4000
&& (prid
& 0xff) < 0x40 &&
902 !(config
& CONF_SC
) && c
->icache
.linesz
!= 16 &&
904 panic("Improper R4000SC processor configuration detected");
906 /* compute a couple of other cache variables */
907 c
->icache
.waysize
= icache_size
/ c
->icache
.ways
;
908 c
->dcache
.waysize
= dcache_size
/ c
->dcache
.ways
;
910 c
->icache
.sets
= c
->icache
.linesz
?
911 icache_size
/ (c
->icache
.linesz
* c
->icache
.ways
) : 0;
912 c
->dcache
.sets
= c
->dcache
.linesz
?
913 dcache_size
/ (c
->dcache
.linesz
* c
->dcache
.ways
) : 0;
916 * R10000 and R12000 P-caches are odd in a positive way. They're 32kB
917 * 2-way virtually indexed so normally would suffer from aliases. So
918 * normally they'd suffer from aliases but magic in the hardware deals
919 * with that for us so we don't need to take care ourselves.
921 switch (c
->cputype
) {
924 c
->dcache
.flags
|= MIPS_CACHE_PINDEX
;
933 if ((read_c0_config7() & (1 << 16))) {
934 /* effectively physically indexed dcache,
935 thus no virtual aliases. */
936 c
->dcache
.flags
|= MIPS_CACHE_PINDEX
;
940 if (c
->dcache
.waysize
> PAGE_SIZE
)
941 c
->dcache
.flags
|= MIPS_CACHE_ALIASES
;
944 switch (c
->cputype
) {
947 * Some older 20Kc chips doesn't have the 'VI' bit in
948 * the config register.
950 c
->icache
.flags
|= MIPS_CACHE_VTAG
;
958 c
->icache
.flags
|= MIPS_CACHE_IC_F_DC
;
962 printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
964 cpu_has_vtag_icache
? "virtually tagged" : "physically tagged",
965 way_string
[c
->icache
.ways
], c
->icache
.linesz
);
967 printk("Primary data cache %ldkB, %s, linesize %d bytes.\n",
968 dcache_size
>> 10, way_string
[c
->dcache
.ways
], c
->dcache
.linesz
);
972 * If you even _breathe_ on this function, look at the gcc output and make sure
973 * it does not pop things on and off the stack for the cache sizing loop that
974 * executes in KSEG1 space or else you will crash and burn badly. You have
977 static int __init
probe_scache(void)
979 extern unsigned long stext
;
980 unsigned long flags
, addr
, begin
, end
, pow2
;
981 unsigned int config
= read_c0_config();
982 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
985 if (config
& CONF_SC
)
988 begin
= (unsigned long) &stext
;
989 begin
&= ~((4 * 1024 * 1024) - 1);
990 end
= begin
+ (4 * 1024 * 1024);
993 * This is such a bitch, you'd think they would make it easy to do
994 * this. Away you daemons of stupidity!
996 local_irq_save(flags
);
998 /* Fill each size-multiple cache line with a valid tag. */
1000 for (addr
= begin
; addr
< end
; addr
= (begin
+ pow2
)) {
1001 unsigned long *p
= (unsigned long *) addr
;
1002 __asm__
__volatile__("nop" : : "r" (*p
)); /* whee... */
1006 /* Load first line with zero (therefore invalid) tag. */
1009 __asm__
__volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
1010 cache_op(Index_Store_Tag_I
, begin
);
1011 cache_op(Index_Store_Tag_D
, begin
);
1012 cache_op(Index_Store_Tag_SD
, begin
);
1014 /* Now search for the wrap around point. */
1015 pow2
= (128 * 1024);
1017 for (addr
= begin
+ (128 * 1024); addr
< end
; addr
= begin
+ pow2
) {
1018 cache_op(Index_Load_Tag_SD
, addr
);
1019 __asm__
__volatile__("nop; nop; nop; nop;"); /* hazard... */
1020 if (!read_c0_taglo())
1024 local_irq_restore(flags
);
1028 c
->scache
.linesz
= 16 << ((config
& R4K_CONF_SB
) >> 22);
1030 c
->dcache
.waybit
= 0; /* does not matter */
1035 extern int r5k_sc_init(void);
1036 extern int rm7k_sc_init(void);
1037 extern int mips_sc_init(void);
1039 static void __init
setup_scache(void)
1041 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
1042 unsigned int config
= read_c0_config();
1046 * Do the probing thing on R4000SC and R4400SC processors. Other
1047 * processors don't have a S-cache that would be relevant to the
1048 * Linux memory managment.
1050 switch (c
->cputype
) {
1055 sc_present
= run_uncached(probe_scache
);
1057 c
->options
|= MIPS_CPU_CACHE_CDEX_S
;
1063 scache_size
= 0x80000 << ((config
& R10K_CONF_SS
) >> 16);
1064 c
->scache
.linesz
= 64 << ((config
>> 13) & 1);
1066 c
->scache
.waybit
= 0;
1072 #ifdef CONFIG_R5000_CPU_SCACHE
1079 #ifdef CONFIG_RM7000_CPU_SCACHE
1085 if (c
->isa_level
== MIPS_CPU_ISA_M32R1
||
1086 c
->isa_level
== MIPS_CPU_ISA_M32R2
||
1087 c
->isa_level
== MIPS_CPU_ISA_M64R1
||
1088 c
->isa_level
== MIPS_CPU_ISA_M64R2
) {
1089 #ifdef CONFIG_MIPS_CPU_SCACHE
1090 if (mips_sc_init ()) {
1091 scache_size
= c
->scache
.ways
* c
->scache
.sets
* c
->scache
.linesz
;
1092 printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
1094 way_string
[c
->scache
.ways
], c
->scache
.linesz
);
1097 if (!(c
->scache
.flags
& MIPS_CACHE_NOT_PRESENT
))
1098 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
1108 /* compute a couple of other cache variables */
1109 c
->scache
.waysize
= scache_size
/ c
->scache
.ways
;
1111 c
->scache
.sets
= scache_size
/ (c
->scache
.linesz
* c
->scache
.ways
);
1113 printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1114 scache_size
>> 10, way_string
[c
->scache
.ways
], c
->scache
.linesz
);
1116 c
->options
|= MIPS_CPU_INCLUSIVE_CACHES
;
1119 void au1x00_fixup_config_od(void)
1122 * c0_config.od (bit 19) was write only (and read as 0)
1123 * on the early revisions of Alchemy SOCs. It disables the bus
1124 * transaction overlapping and needs to be set to fix various errata.
1126 switch (read_c0_prid()) {
1127 case 0x00030100: /* Au1000 DA */
1128 case 0x00030201: /* Au1000 HA */
1129 case 0x00030202: /* Au1000 HB */
1130 case 0x01030200: /* Au1500 AB */
1132 * Au1100 errata actually keeps silence about this bit, so we set it
1133 * just in case for those revisions that require it to be set according
1134 * to arch/mips/au1000/common/cputable.c
1136 case 0x02030200: /* Au1100 AB */
1137 case 0x02030201: /* Au1100 BA */
1138 case 0x02030202: /* Au1100 BC */
1139 set_c0_config(1 << 19);
1144 static void __init
coherency_setup(void)
1146 change_c0_config(CONF_CM_CMASK
, CONF_CM_DEFAULT
);
1149 * c0_status.cu=0 specifies that updates by the sc instruction use
1150 * the coherency mode specified by the TLB; 1 means cachable
1151 * coherent update on write will be used. Not all processors have
1152 * this bit and; some wire it to zero, others like Toshiba had the
1153 * silly idea of putting something else there ...
1155 switch (current_cpu_data
.cputype
) {
1162 clear_c0_config(CONF_CU
);
1165 * We need to catch the early Alchemy SOCs with
1166 * the write-only co_config.od bit and set it back to one...
1168 case CPU_AU1000
: /* rev. DA, HA, HB */
1169 case CPU_AU1100
: /* rev. AB, BA, BC ?? */
1170 case CPU_AU1500
: /* rev. AB */
1171 au1x00_fixup_config_od();
1176 void __init
r4k_cache_init(void)
1178 extern void build_clear_page(void);
1179 extern void build_copy_page(void);
1180 extern char except_vec2_generic
;
1181 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
1183 /* Default cache error handler for R4000 and R5000 family */
1184 set_uncached_handler (0x100, &except_vec2_generic
, 0x80);
1189 r4k_blast_dcache_page_setup();
1190 r4k_blast_dcache_page_indexed_setup();
1191 r4k_blast_dcache_setup();
1192 r4k_blast_icache_page_setup();
1193 r4k_blast_icache_page_indexed_setup();
1194 r4k_blast_icache_setup();
1195 r4k_blast_scache_page_setup();
1196 r4k_blast_scache_page_indexed_setup();
1197 r4k_blast_scache_setup();
1200 * Some MIPS32 and MIPS64 processors have physically indexed caches.
1201 * This code supports virtually indexed processors and will be
1202 * unnecessarily inefficient on physically indexed processors.
1204 if (c
->dcache
.linesz
)
1205 shm_align_mask
= max_t( unsigned long,
1206 c
->dcache
.sets
* c
->dcache
.linesz
- 1,
1209 shm_align_mask
= PAGE_SIZE
-1;
1210 flush_cache_all
= r4k_flush_cache_all
;
1211 __flush_cache_all
= r4k___flush_cache_all
;
1212 flush_cache_mm
= r4k_flush_cache_mm
;
1213 flush_cache_page
= r4k_flush_cache_page
;
1214 flush_cache_range
= r4k_flush_cache_range
;
1216 flush_cache_sigtramp
= r4k_flush_cache_sigtramp
;
1217 flush_icache_all
= r4k_flush_icache_all
;
1218 local_flush_data_cache_page
= local_r4k_flush_data_cache_page
;
1219 flush_data_cache_page
= r4k_flush_data_cache_page
;
1220 flush_icache_range
= r4k_flush_icache_range
;
1222 #ifdef CONFIG_DMA_NONCOHERENT
1223 _dma_cache_wback_inv
= r4k_dma_cache_wback_inv
;
1224 _dma_cache_wback
= r4k_dma_cache_wback_inv
;
1225 _dma_cache_inv
= r4k_dma_cache_inv
;
1230 local_r4k___flush_cache_all(NULL
);