2 * Performance counter x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
10 * For licencing details see kernel-base/COPYING
13 #include <linux/perf_counter.h>
14 #include <linux/capability.h>
15 #include <linux/notifier.h>
16 #include <linux/hardirq.h>
17 #include <linux/kprobes.h>
18 #include <linux/module.h>
19 #include <linux/kdebug.h>
20 #include <linux/sched.h>
21 #include <linux/uaccess.h>
22 #include <linux/highmem.h>
25 #include <asm/stacktrace.h>
28 static u64 perf_counter_mask __read_mostly
;
30 struct cpu_hw_counters
{
31 struct perf_counter
*counters
[X86_PMC_IDX_MAX
];
32 unsigned long used_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
33 unsigned long active_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
34 unsigned long interrupts
;
39 * struct x86_pmu - generic x86 pmu
44 int (*handle_irq
)(struct pt_regs
*);
45 void (*disable_all
)(void);
46 void (*enable_all
)(void);
47 void (*enable
)(struct hw_perf_counter
*, int);
48 void (*disable
)(struct hw_perf_counter
*, int);
51 u64 (*event_map
)(int);
52 u64 (*raw_event
)(u64
);
55 int num_counters_fixed
;
63 static struct x86_pmu x86_pmu __read_mostly
;
65 static DEFINE_PER_CPU(struct cpu_hw_counters
, cpu_hw_counters
) = {
70 * Not sure about some of these
72 static const u64 p6_perfmon_event_map
[] =
74 [PERF_COUNT_HW_CPU_CYCLES
] = 0x0079,
75 [PERF_COUNT_HW_INSTRUCTIONS
] = 0x00c0,
76 [PERF_COUNT_HW_CACHE_REFERENCES
] = 0x0f2e,
77 [PERF_COUNT_HW_CACHE_MISSES
] = 0x012e,
78 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS
] = 0x00c4,
79 [PERF_COUNT_HW_BRANCH_MISSES
] = 0x00c5,
80 [PERF_COUNT_HW_BUS_CYCLES
] = 0x0062,
83 static u64
p6_pmu_event_map(int event
)
85 return p6_perfmon_event_map
[event
];
89 * Counter setting that is specified not to count anything.
90 * We use this to effectively disable a counter.
92 * L2_RQSTS with 0 MESI unit mask.
94 #define P6_NOP_COUNTER 0x0000002EULL
96 static u64
p6_pmu_raw_event(u64 event
)
98 #define P6_EVNTSEL_EVENT_MASK 0x000000FFULL
99 #define P6_EVNTSEL_UNIT_MASK 0x0000FF00ULL
100 #define P6_EVNTSEL_EDGE_MASK 0x00040000ULL
101 #define P6_EVNTSEL_INV_MASK 0x00800000ULL
102 #define P6_EVNTSEL_COUNTER_MASK 0xFF000000ULL
104 #define P6_EVNTSEL_MASK \
105 (P6_EVNTSEL_EVENT_MASK | \
106 P6_EVNTSEL_UNIT_MASK | \
107 P6_EVNTSEL_EDGE_MASK | \
108 P6_EVNTSEL_INV_MASK | \
109 P6_EVNTSEL_COUNTER_MASK)
111 return event
& P6_EVNTSEL_MASK
;
116 * Intel PerfMon v3. Used on Core2 and later.
118 static const u64 intel_perfmon_event_map
[] =
120 [PERF_COUNT_HW_CPU_CYCLES
] = 0x003c,
121 [PERF_COUNT_HW_INSTRUCTIONS
] = 0x00c0,
122 [PERF_COUNT_HW_CACHE_REFERENCES
] = 0x4f2e,
123 [PERF_COUNT_HW_CACHE_MISSES
] = 0x412e,
124 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS
] = 0x00c4,
125 [PERF_COUNT_HW_BRANCH_MISSES
] = 0x00c5,
126 [PERF_COUNT_HW_BUS_CYCLES
] = 0x013c,
129 static u64
intel_pmu_event_map(int event
)
131 return intel_perfmon_event_map
[event
];
135 * Generalized hw caching related event table, filled
136 * in on a per model basis. A value of 0 means
137 * 'not supported', -1 means 'event makes no sense on
138 * this CPU', any other value means the raw event
142 #define C(x) PERF_COUNT_HW_CACHE_##x
144 static u64 __read_mostly hw_cache_event_ids
145 [PERF_COUNT_HW_CACHE_MAX
]
146 [PERF_COUNT_HW_CACHE_OP_MAX
]
147 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
149 static const u64 nehalem_hw_cache_event_ids
150 [PERF_COUNT_HW_CACHE_MAX
]
151 [PERF_COUNT_HW_CACHE_OP_MAX
]
152 [PERF_COUNT_HW_CACHE_RESULT_MAX
] =
156 [ C(RESULT_ACCESS
) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
157 [ C(RESULT_MISS
) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
160 [ C(RESULT_ACCESS
) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
161 [ C(RESULT_MISS
) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
163 [ C(OP_PREFETCH
) ] = {
164 [ C(RESULT_ACCESS
) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
165 [ C(RESULT_MISS
) ] = 0x024e, /* L1D_PREFETCH.MISS */
170 [ C(RESULT_ACCESS
) ] = 0x0380, /* L1I.READS */
171 [ C(RESULT_MISS
) ] = 0x0280, /* L1I.MISSES */
174 [ C(RESULT_ACCESS
) ] = -1,
175 [ C(RESULT_MISS
) ] = -1,
177 [ C(OP_PREFETCH
) ] = {
178 [ C(RESULT_ACCESS
) ] = 0x0,
179 [ C(RESULT_MISS
) ] = 0x0,
184 [ C(RESULT_ACCESS
) ] = 0x0324, /* L2_RQSTS.LOADS */
185 [ C(RESULT_MISS
) ] = 0x0224, /* L2_RQSTS.LD_MISS */
188 [ C(RESULT_ACCESS
) ] = 0x0c24, /* L2_RQSTS.RFOS */
189 [ C(RESULT_MISS
) ] = 0x0824, /* L2_RQSTS.RFO_MISS */
191 [ C(OP_PREFETCH
) ] = {
192 [ C(RESULT_ACCESS
) ] = 0x4f2e, /* LLC Reference */
193 [ C(RESULT_MISS
) ] = 0x412e, /* LLC Misses */
198 [ C(RESULT_ACCESS
) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
199 [ C(RESULT_MISS
) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
202 [ C(RESULT_ACCESS
) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
203 [ C(RESULT_MISS
) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
205 [ C(OP_PREFETCH
) ] = {
206 [ C(RESULT_ACCESS
) ] = 0x0,
207 [ C(RESULT_MISS
) ] = 0x0,
212 [ C(RESULT_ACCESS
) ] = 0x01c0, /* INST_RETIRED.ANY_P */
213 [ C(RESULT_MISS
) ] = 0x20c8, /* ITLB_MISS_RETIRED */
216 [ C(RESULT_ACCESS
) ] = -1,
217 [ C(RESULT_MISS
) ] = -1,
219 [ C(OP_PREFETCH
) ] = {
220 [ C(RESULT_ACCESS
) ] = -1,
221 [ C(RESULT_MISS
) ] = -1,
226 [ C(RESULT_ACCESS
) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
227 [ C(RESULT_MISS
) ] = 0x03e8, /* BPU_CLEARS.ANY */
230 [ C(RESULT_ACCESS
) ] = -1,
231 [ C(RESULT_MISS
) ] = -1,
233 [ C(OP_PREFETCH
) ] = {
234 [ C(RESULT_ACCESS
) ] = -1,
235 [ C(RESULT_MISS
) ] = -1,
240 static const u64 core2_hw_cache_event_ids
241 [PERF_COUNT_HW_CACHE_MAX
]
242 [PERF_COUNT_HW_CACHE_OP_MAX
]
243 [PERF_COUNT_HW_CACHE_RESULT_MAX
] =
247 [ C(RESULT_ACCESS
) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
248 [ C(RESULT_MISS
) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
251 [ C(RESULT_ACCESS
) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
252 [ C(RESULT_MISS
) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
254 [ C(OP_PREFETCH
) ] = {
255 [ C(RESULT_ACCESS
) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
256 [ C(RESULT_MISS
) ] = 0,
261 [ C(RESULT_ACCESS
) ] = 0x0080, /* L1I.READS */
262 [ C(RESULT_MISS
) ] = 0x0081, /* L1I.MISSES */
265 [ C(RESULT_ACCESS
) ] = -1,
266 [ C(RESULT_MISS
) ] = -1,
268 [ C(OP_PREFETCH
) ] = {
269 [ C(RESULT_ACCESS
) ] = 0,
270 [ C(RESULT_MISS
) ] = 0,
275 [ C(RESULT_ACCESS
) ] = 0x4f29, /* L2_LD.MESI */
276 [ C(RESULT_MISS
) ] = 0x4129, /* L2_LD.ISTATE */
279 [ C(RESULT_ACCESS
) ] = 0x4f2A, /* L2_ST.MESI */
280 [ C(RESULT_MISS
) ] = 0x412A, /* L2_ST.ISTATE */
282 [ C(OP_PREFETCH
) ] = {
283 [ C(RESULT_ACCESS
) ] = 0,
284 [ C(RESULT_MISS
) ] = 0,
289 [ C(RESULT_ACCESS
) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
290 [ C(RESULT_MISS
) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
293 [ C(RESULT_ACCESS
) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
294 [ C(RESULT_MISS
) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
296 [ C(OP_PREFETCH
) ] = {
297 [ C(RESULT_ACCESS
) ] = 0,
298 [ C(RESULT_MISS
) ] = 0,
303 [ C(RESULT_ACCESS
) ] = 0x00c0, /* INST_RETIRED.ANY_P */
304 [ C(RESULT_MISS
) ] = 0x1282, /* ITLBMISSES */
307 [ C(RESULT_ACCESS
) ] = -1,
308 [ C(RESULT_MISS
) ] = -1,
310 [ C(OP_PREFETCH
) ] = {
311 [ C(RESULT_ACCESS
) ] = -1,
312 [ C(RESULT_MISS
) ] = -1,
317 [ C(RESULT_ACCESS
) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
318 [ C(RESULT_MISS
) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
321 [ C(RESULT_ACCESS
) ] = -1,
322 [ C(RESULT_MISS
) ] = -1,
324 [ C(OP_PREFETCH
) ] = {
325 [ C(RESULT_ACCESS
) ] = -1,
326 [ C(RESULT_MISS
) ] = -1,
331 static const u64 atom_hw_cache_event_ids
332 [PERF_COUNT_HW_CACHE_MAX
]
333 [PERF_COUNT_HW_CACHE_OP_MAX
]
334 [PERF_COUNT_HW_CACHE_RESULT_MAX
] =
338 [ C(RESULT_ACCESS
) ] = 0x2140, /* L1D_CACHE.LD */
339 [ C(RESULT_MISS
) ] = 0,
342 [ C(RESULT_ACCESS
) ] = 0x2240, /* L1D_CACHE.ST */
343 [ C(RESULT_MISS
) ] = 0,
345 [ C(OP_PREFETCH
) ] = {
346 [ C(RESULT_ACCESS
) ] = 0x0,
347 [ C(RESULT_MISS
) ] = 0,
352 [ C(RESULT_ACCESS
) ] = 0x0380, /* L1I.READS */
353 [ C(RESULT_MISS
) ] = 0x0280, /* L1I.MISSES */
356 [ C(RESULT_ACCESS
) ] = -1,
357 [ C(RESULT_MISS
) ] = -1,
359 [ C(OP_PREFETCH
) ] = {
360 [ C(RESULT_ACCESS
) ] = 0,
361 [ C(RESULT_MISS
) ] = 0,
366 [ C(RESULT_ACCESS
) ] = 0x4f29, /* L2_LD.MESI */
367 [ C(RESULT_MISS
) ] = 0x4129, /* L2_LD.ISTATE */
370 [ C(RESULT_ACCESS
) ] = 0x4f2A, /* L2_ST.MESI */
371 [ C(RESULT_MISS
) ] = 0x412A, /* L2_ST.ISTATE */
373 [ C(OP_PREFETCH
) ] = {
374 [ C(RESULT_ACCESS
) ] = 0,
375 [ C(RESULT_MISS
) ] = 0,
380 [ C(RESULT_ACCESS
) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
381 [ C(RESULT_MISS
) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
384 [ C(RESULT_ACCESS
) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
385 [ C(RESULT_MISS
) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
387 [ C(OP_PREFETCH
) ] = {
388 [ C(RESULT_ACCESS
) ] = 0,
389 [ C(RESULT_MISS
) ] = 0,
394 [ C(RESULT_ACCESS
) ] = 0x00c0, /* INST_RETIRED.ANY_P */
395 [ C(RESULT_MISS
) ] = 0x0282, /* ITLB.MISSES */
398 [ C(RESULT_ACCESS
) ] = -1,
399 [ C(RESULT_MISS
) ] = -1,
401 [ C(OP_PREFETCH
) ] = {
402 [ C(RESULT_ACCESS
) ] = -1,
403 [ C(RESULT_MISS
) ] = -1,
408 [ C(RESULT_ACCESS
) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
409 [ C(RESULT_MISS
) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
412 [ C(RESULT_ACCESS
) ] = -1,
413 [ C(RESULT_MISS
) ] = -1,
415 [ C(OP_PREFETCH
) ] = {
416 [ C(RESULT_ACCESS
) ] = -1,
417 [ C(RESULT_MISS
) ] = -1,
422 static u64
intel_pmu_raw_event(u64 event
)
424 #define CORE_EVNTSEL_EVENT_MASK 0x000000FFULL
425 #define CORE_EVNTSEL_UNIT_MASK 0x0000FF00ULL
426 #define CORE_EVNTSEL_EDGE_MASK 0x00040000ULL
427 #define CORE_EVNTSEL_INV_MASK 0x00800000ULL
428 #define CORE_EVNTSEL_COUNTER_MASK 0xFF000000ULL
430 #define CORE_EVNTSEL_MASK \
431 (CORE_EVNTSEL_EVENT_MASK | \
432 CORE_EVNTSEL_UNIT_MASK | \
433 CORE_EVNTSEL_EDGE_MASK | \
434 CORE_EVNTSEL_INV_MASK | \
435 CORE_EVNTSEL_COUNTER_MASK)
437 return event
& CORE_EVNTSEL_MASK
;
440 static const u64 amd_hw_cache_event_ids
441 [PERF_COUNT_HW_CACHE_MAX
]
442 [PERF_COUNT_HW_CACHE_OP_MAX
]
443 [PERF_COUNT_HW_CACHE_RESULT_MAX
] =
447 [ C(RESULT_ACCESS
) ] = 0x0040, /* Data Cache Accesses */
448 [ C(RESULT_MISS
) ] = 0x0041, /* Data Cache Misses */
451 [ C(RESULT_ACCESS
) ] = 0x0142, /* Data Cache Refills :system */
452 [ C(RESULT_MISS
) ] = 0,
454 [ C(OP_PREFETCH
) ] = {
455 [ C(RESULT_ACCESS
) ] = 0x0267, /* Data Prefetcher :attempts */
456 [ C(RESULT_MISS
) ] = 0x0167, /* Data Prefetcher :cancelled */
461 [ C(RESULT_ACCESS
) ] = 0x0080, /* Instruction cache fetches */
462 [ C(RESULT_MISS
) ] = 0x0081, /* Instruction cache misses */
465 [ C(RESULT_ACCESS
) ] = -1,
466 [ C(RESULT_MISS
) ] = -1,
468 [ C(OP_PREFETCH
) ] = {
469 [ C(RESULT_ACCESS
) ] = 0x014B, /* Prefetch Instructions :Load */
470 [ C(RESULT_MISS
) ] = 0,
475 [ C(RESULT_ACCESS
) ] = 0x037D, /* Requests to L2 Cache :IC+DC */
476 [ C(RESULT_MISS
) ] = 0x037E, /* L2 Cache Misses : IC+DC */
479 [ C(RESULT_ACCESS
) ] = 0x017F, /* L2 Fill/Writeback */
480 [ C(RESULT_MISS
) ] = 0,
482 [ C(OP_PREFETCH
) ] = {
483 [ C(RESULT_ACCESS
) ] = 0,
484 [ C(RESULT_MISS
) ] = 0,
489 [ C(RESULT_ACCESS
) ] = 0x0040, /* Data Cache Accesses */
490 [ C(RESULT_MISS
) ] = 0x0046, /* L1 DTLB and L2 DLTB Miss */
493 [ C(RESULT_ACCESS
) ] = 0,
494 [ C(RESULT_MISS
) ] = 0,
496 [ C(OP_PREFETCH
) ] = {
497 [ C(RESULT_ACCESS
) ] = 0,
498 [ C(RESULT_MISS
) ] = 0,
503 [ C(RESULT_ACCESS
) ] = 0x0080, /* Instruction fecthes */
504 [ C(RESULT_MISS
) ] = 0x0085, /* Instr. fetch ITLB misses */
507 [ C(RESULT_ACCESS
) ] = -1,
508 [ C(RESULT_MISS
) ] = -1,
510 [ C(OP_PREFETCH
) ] = {
511 [ C(RESULT_ACCESS
) ] = -1,
512 [ C(RESULT_MISS
) ] = -1,
517 [ C(RESULT_ACCESS
) ] = 0x00c2, /* Retired Branch Instr. */
518 [ C(RESULT_MISS
) ] = 0x00c3, /* Retired Mispredicted BI */
521 [ C(RESULT_ACCESS
) ] = -1,
522 [ C(RESULT_MISS
) ] = -1,
524 [ C(OP_PREFETCH
) ] = {
525 [ C(RESULT_ACCESS
) ] = -1,
526 [ C(RESULT_MISS
) ] = -1,
532 * AMD Performance Monitor K7 and later.
534 static const u64 amd_perfmon_event_map
[] =
536 [PERF_COUNT_HW_CPU_CYCLES
] = 0x0076,
537 [PERF_COUNT_HW_INSTRUCTIONS
] = 0x00c0,
538 [PERF_COUNT_HW_CACHE_REFERENCES
] = 0x0080,
539 [PERF_COUNT_HW_CACHE_MISSES
] = 0x0081,
540 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS
] = 0x00c4,
541 [PERF_COUNT_HW_BRANCH_MISSES
] = 0x00c5,
544 static u64
amd_pmu_event_map(int event
)
546 return amd_perfmon_event_map
[event
];
549 static u64
amd_pmu_raw_event(u64 event
)
551 #define K7_EVNTSEL_EVENT_MASK 0x7000000FFULL
552 #define K7_EVNTSEL_UNIT_MASK 0x00000FF00ULL
553 #define K7_EVNTSEL_EDGE_MASK 0x000040000ULL
554 #define K7_EVNTSEL_INV_MASK 0x000800000ULL
555 #define K7_EVNTSEL_COUNTER_MASK 0x0FF000000ULL
557 #define K7_EVNTSEL_MASK \
558 (K7_EVNTSEL_EVENT_MASK | \
559 K7_EVNTSEL_UNIT_MASK | \
560 K7_EVNTSEL_EDGE_MASK | \
561 K7_EVNTSEL_INV_MASK | \
562 K7_EVNTSEL_COUNTER_MASK)
564 return event
& K7_EVNTSEL_MASK
;
568 * Propagate counter elapsed time into the generic counter.
569 * Can only be executed on the CPU where the counter is active.
570 * Returns the delta events processed.
573 x86_perf_counter_update(struct perf_counter
*counter
,
574 struct hw_perf_counter
*hwc
, int idx
)
576 int shift
= 64 - x86_pmu
.counter_bits
;
577 u64 prev_raw_count
, new_raw_count
;
581 * Careful: an NMI might modify the previous counter value.
583 * Our tactic to handle this is to first atomically read and
584 * exchange a new raw count - then add that new-prev delta
585 * count to the generic counter atomically:
588 prev_raw_count
= atomic64_read(&hwc
->prev_count
);
589 rdmsrl(hwc
->counter_base
+ idx
, new_raw_count
);
591 if (atomic64_cmpxchg(&hwc
->prev_count
, prev_raw_count
,
592 new_raw_count
) != prev_raw_count
)
596 * Now we have the new raw value and have updated the prev
597 * timestamp already. We can now calculate the elapsed delta
598 * (counter-)time and add that to the generic counter.
600 * Careful, not all hw sign-extends above the physical width
603 delta
= (new_raw_count
<< shift
) - (prev_raw_count
<< shift
);
606 atomic64_add(delta
, &counter
->count
);
607 atomic64_sub(delta
, &hwc
->period_left
);
609 return new_raw_count
;
612 static atomic_t active_counters
;
613 static DEFINE_MUTEX(pmc_reserve_mutex
);
615 static bool reserve_pmc_hardware(void)
617 #ifdef CONFIG_X86_LOCAL_APIC
620 if (nmi_watchdog
== NMI_LOCAL_APIC
)
621 disable_lapic_nmi_watchdog();
623 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
624 if (!reserve_perfctr_nmi(x86_pmu
.perfctr
+ i
))
628 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
629 if (!reserve_evntsel_nmi(x86_pmu
.eventsel
+ i
))
636 #ifdef CONFIG_X86_LOCAL_APIC
638 for (i
--; i
>= 0; i
--)
639 release_evntsel_nmi(x86_pmu
.eventsel
+ i
);
641 i
= x86_pmu
.num_counters
;
644 for (i
--; i
>= 0; i
--)
645 release_perfctr_nmi(x86_pmu
.perfctr
+ i
);
647 if (nmi_watchdog
== NMI_LOCAL_APIC
)
648 enable_lapic_nmi_watchdog();
654 static void release_pmc_hardware(void)
656 #ifdef CONFIG_X86_LOCAL_APIC
659 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
660 release_perfctr_nmi(x86_pmu
.perfctr
+ i
);
661 release_evntsel_nmi(x86_pmu
.eventsel
+ i
);
664 if (nmi_watchdog
== NMI_LOCAL_APIC
)
665 enable_lapic_nmi_watchdog();
669 static void hw_perf_counter_destroy(struct perf_counter
*counter
)
671 if (atomic_dec_and_mutex_lock(&active_counters
, &pmc_reserve_mutex
)) {
672 release_pmc_hardware();
673 mutex_unlock(&pmc_reserve_mutex
);
677 static inline int x86_pmu_initialized(void)
679 return x86_pmu
.handle_irq
!= NULL
;
683 set_ext_hw_attr(struct hw_perf_counter
*hwc
, struct perf_counter_attr
*attr
)
685 unsigned int cache_type
, cache_op
, cache_result
;
688 config
= attr
->config
;
690 cache_type
= (config
>> 0) & 0xff;
691 if (cache_type
>= PERF_COUNT_HW_CACHE_MAX
)
694 cache_op
= (config
>> 8) & 0xff;
695 if (cache_op
>= PERF_COUNT_HW_CACHE_OP_MAX
)
698 cache_result
= (config
>> 16) & 0xff;
699 if (cache_result
>= PERF_COUNT_HW_CACHE_RESULT_MAX
)
702 val
= hw_cache_event_ids
[cache_type
][cache_op
][cache_result
];
716 * Setup the hardware configuration for a given attr_type
718 static int __hw_perf_counter_init(struct perf_counter
*counter
)
720 struct perf_counter_attr
*attr
= &counter
->attr
;
721 struct hw_perf_counter
*hwc
= &counter
->hw
;
725 if (!x86_pmu_initialized())
729 if (!atomic_inc_not_zero(&active_counters
)) {
730 mutex_lock(&pmc_reserve_mutex
);
731 if (atomic_read(&active_counters
) == 0 && !reserve_pmc_hardware())
734 atomic_inc(&active_counters
);
735 mutex_unlock(&pmc_reserve_mutex
);
742 * (keep 'enabled' bit clear for now)
744 hwc
->config
= ARCH_PERFMON_EVENTSEL_INT
;
747 * Count user and OS events unless requested not to.
749 if (!attr
->exclude_user
)
750 hwc
->config
|= ARCH_PERFMON_EVENTSEL_USR
;
751 if (!attr
->exclude_kernel
)
752 hwc
->config
|= ARCH_PERFMON_EVENTSEL_OS
;
754 if (!hwc
->sample_period
) {
755 hwc
->sample_period
= x86_pmu
.max_period
;
756 hwc
->last_period
= hwc
->sample_period
;
757 atomic64_set(&hwc
->period_left
, hwc
->sample_period
);
760 * If we have a PMU initialized but no APIC
761 * interrupts, we cannot sample hardware
762 * counters (user-space has to fall back and
763 * sample via a hrtimer based software counter):
769 counter
->destroy
= hw_perf_counter_destroy
;
772 * Raw event type provide the config in the event structure
774 if (attr
->type
== PERF_TYPE_RAW
) {
775 hwc
->config
|= x86_pmu
.raw_event(attr
->config
);
779 if (attr
->type
== PERF_TYPE_HW_CACHE
)
780 return set_ext_hw_attr(hwc
, attr
);
782 if (attr
->config
>= x86_pmu
.max_events
)
788 config
= x86_pmu
.event_map(attr
->config
);
796 hwc
->config
|= config
;
801 static void p6_pmu_disable_all(void)
803 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
812 /* p6 only has one enable register */
813 rdmsrl(MSR_P6_EVNTSEL0
, val
);
814 val
&= ~ARCH_PERFMON_EVENTSEL0_ENABLE
;
815 wrmsrl(MSR_P6_EVNTSEL0
, val
);
818 static void intel_pmu_disable_all(void)
820 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, 0);
823 static void amd_pmu_disable_all(void)
825 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
833 * ensure we write the disable before we start disabling the
834 * counters proper, so that amd_pmu_enable_counter() does the
839 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
842 if (!test_bit(idx
, cpuc
->active_mask
))
844 rdmsrl(MSR_K7_EVNTSEL0
+ idx
, val
);
845 if (!(val
& ARCH_PERFMON_EVENTSEL0_ENABLE
))
847 val
&= ~ARCH_PERFMON_EVENTSEL0_ENABLE
;
848 wrmsrl(MSR_K7_EVNTSEL0
+ idx
, val
);
852 void hw_perf_disable(void)
854 if (!x86_pmu_initialized())
856 return x86_pmu
.disable_all();
859 static void p6_pmu_enable_all(void)
861 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
870 /* p6 only has one enable register */
871 rdmsrl(MSR_P6_EVNTSEL0
, val
);
872 val
|= ARCH_PERFMON_EVENTSEL0_ENABLE
;
873 wrmsrl(MSR_P6_EVNTSEL0
, val
);
876 static void intel_pmu_enable_all(void)
878 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, x86_pmu
.intel_ctrl
);
881 static void amd_pmu_enable_all(void)
883 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
892 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
893 struct perf_counter
*counter
= cpuc
->counters
[idx
];
896 if (!test_bit(idx
, cpuc
->active_mask
))
899 val
= counter
->hw
.config
;
900 val
|= ARCH_PERFMON_EVENTSEL0_ENABLE
;
901 wrmsrl(MSR_K7_EVNTSEL0
+ idx
, val
);
905 void hw_perf_enable(void)
907 if (!x86_pmu_initialized())
909 x86_pmu
.enable_all();
912 static inline u64
intel_pmu_get_status(void)
916 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
921 static inline void intel_pmu_ack_status(u64 ack
)
923 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, ack
);
926 static inline void x86_pmu_enable_counter(struct hw_perf_counter
*hwc
, int idx
)
928 (void)checking_wrmsrl(hwc
->config_base
+ idx
,
929 hwc
->config
| ARCH_PERFMON_EVENTSEL0_ENABLE
);
932 static inline void x86_pmu_disable_counter(struct hw_perf_counter
*hwc
, int idx
)
934 (void)checking_wrmsrl(hwc
->config_base
+ idx
, hwc
->config
);
938 intel_pmu_disable_fixed(struct hw_perf_counter
*hwc
, int __idx
)
940 int idx
= __idx
- X86_PMC_IDX_FIXED
;
943 mask
= 0xfULL
<< (idx
* 4);
945 rdmsrl(hwc
->config_base
, ctrl_val
);
947 (void)checking_wrmsrl(hwc
->config_base
, ctrl_val
);
951 p6_pmu_disable_counter(struct hw_perf_counter
*hwc
, int idx
)
953 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
954 u64 val
= P6_NOP_COUNTER
;
957 val
|= ARCH_PERFMON_EVENTSEL0_ENABLE
;
959 (void)checking_wrmsrl(hwc
->config_base
+ idx
, val
);
963 intel_pmu_disable_counter(struct hw_perf_counter
*hwc
, int idx
)
965 if (unlikely(hwc
->config_base
== MSR_ARCH_PERFMON_FIXED_CTR_CTRL
)) {
966 intel_pmu_disable_fixed(hwc
, idx
);
970 x86_pmu_disable_counter(hwc
, idx
);
974 amd_pmu_disable_counter(struct hw_perf_counter
*hwc
, int idx
)
976 x86_pmu_disable_counter(hwc
, idx
);
979 static DEFINE_PER_CPU(u64
, prev_left
[X86_PMC_IDX_MAX
]);
982 * Set the next IRQ period, based on the hwc->period_left value.
983 * To be called with the counter disabled in hw:
986 x86_perf_counter_set_period(struct perf_counter
*counter
,
987 struct hw_perf_counter
*hwc
, int idx
)
989 s64 left
= atomic64_read(&hwc
->period_left
);
990 s64 period
= hwc
->sample_period
;
994 * If we are way outside a reasoable range then just skip forward:
996 if (unlikely(left
<= -period
)) {
998 atomic64_set(&hwc
->period_left
, left
);
999 hwc
->last_period
= period
;
1003 if (unlikely(left
<= 0)) {
1005 atomic64_set(&hwc
->period_left
, left
);
1006 hwc
->last_period
= period
;
1010 * Quirk: certain CPUs dont like it if just 1 event is left:
1012 if (unlikely(left
< 2))
1015 if (left
> x86_pmu
.max_period
)
1016 left
= x86_pmu
.max_period
;
1018 per_cpu(prev_left
[idx
], smp_processor_id()) = left
;
1021 * The hw counter starts counting from this counter offset,
1022 * mark it to be able to extra future deltas:
1024 atomic64_set(&hwc
->prev_count
, (u64
)-left
);
1026 err
= checking_wrmsrl(hwc
->counter_base
+ idx
,
1027 (u64
)(-left
) & x86_pmu
.counter_mask
);
1029 perf_counter_update_userpage(counter
);
1035 intel_pmu_enable_fixed(struct hw_perf_counter
*hwc
, int __idx
)
1037 int idx
= __idx
- X86_PMC_IDX_FIXED
;
1038 u64 ctrl_val
, bits
, mask
;
1042 * Enable IRQ generation (0x8),
1043 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
1047 if (hwc
->config
& ARCH_PERFMON_EVENTSEL_USR
)
1049 if (hwc
->config
& ARCH_PERFMON_EVENTSEL_OS
)
1052 mask
= 0xfULL
<< (idx
* 4);
1054 rdmsrl(hwc
->config_base
, ctrl_val
);
1057 err
= checking_wrmsrl(hwc
->config_base
, ctrl_val
);
1060 static void p6_pmu_enable_counter(struct hw_perf_counter
*hwc
, int idx
)
1062 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
1067 val
|= ARCH_PERFMON_EVENTSEL0_ENABLE
;
1069 (void)checking_wrmsrl(hwc
->config_base
+ idx
, val
);
1073 static void intel_pmu_enable_counter(struct hw_perf_counter
*hwc
, int idx
)
1075 if (unlikely(hwc
->config_base
== MSR_ARCH_PERFMON_FIXED_CTR_CTRL
)) {
1076 intel_pmu_enable_fixed(hwc
, idx
);
1080 x86_pmu_enable_counter(hwc
, idx
);
1083 static void amd_pmu_enable_counter(struct hw_perf_counter
*hwc
, int idx
)
1085 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
1088 x86_pmu_enable_counter(hwc
, idx
);
1092 fixed_mode_idx(struct perf_counter
*counter
, struct hw_perf_counter
*hwc
)
1096 if (!x86_pmu
.num_counters_fixed
)
1099 event
= hwc
->config
& ARCH_PERFMON_EVENT_MASK
;
1101 if (unlikely(event
== x86_pmu
.event_map(PERF_COUNT_HW_INSTRUCTIONS
)))
1102 return X86_PMC_IDX_FIXED_INSTRUCTIONS
;
1103 if (unlikely(event
== x86_pmu
.event_map(PERF_COUNT_HW_CPU_CYCLES
)))
1104 return X86_PMC_IDX_FIXED_CPU_CYCLES
;
1105 if (unlikely(event
== x86_pmu
.event_map(PERF_COUNT_HW_BUS_CYCLES
)))
1106 return X86_PMC_IDX_FIXED_BUS_CYCLES
;
1112 * Find a PMC slot for the freshly enabled / scheduled in counter:
1114 static int x86_pmu_enable(struct perf_counter
*counter
)
1116 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
1117 struct hw_perf_counter
*hwc
= &counter
->hw
;
1120 idx
= fixed_mode_idx(counter
, hwc
);
1123 * Try to get the fixed counter, if that is already taken
1124 * then try to get a generic counter:
1126 if (test_and_set_bit(idx
, cpuc
->used_mask
))
1129 hwc
->config_base
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
1131 * We set it so that counter_base + idx in wrmsr/rdmsr maps to
1132 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
1135 MSR_ARCH_PERFMON_FIXED_CTR0
- X86_PMC_IDX_FIXED
;
1139 /* Try to get the previous generic counter again */
1140 if (test_and_set_bit(idx
, cpuc
->used_mask
)) {
1142 idx
= find_first_zero_bit(cpuc
->used_mask
,
1143 x86_pmu
.num_counters
);
1144 if (idx
== x86_pmu
.num_counters
)
1147 set_bit(idx
, cpuc
->used_mask
);
1150 hwc
->config_base
= x86_pmu
.eventsel
;
1151 hwc
->counter_base
= x86_pmu
.perfctr
;
1154 perf_counters_lapic_init();
1156 x86_pmu
.disable(hwc
, idx
);
1158 cpuc
->counters
[idx
] = counter
;
1159 set_bit(idx
, cpuc
->active_mask
);
1161 x86_perf_counter_set_period(counter
, hwc
, idx
);
1162 x86_pmu
.enable(hwc
, idx
);
1164 perf_counter_update_userpage(counter
);
1169 static void x86_pmu_unthrottle(struct perf_counter
*counter
)
1171 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
1172 struct hw_perf_counter
*hwc
= &counter
->hw
;
1174 if (WARN_ON_ONCE(hwc
->idx
>= X86_PMC_IDX_MAX
||
1175 cpuc
->counters
[hwc
->idx
] != counter
))
1178 x86_pmu
.enable(hwc
, hwc
->idx
);
1181 void perf_counter_print_debug(void)
1183 u64 ctrl
, status
, overflow
, pmc_ctrl
, pmc_count
, prev_left
, fixed
;
1184 struct cpu_hw_counters
*cpuc
;
1185 unsigned long flags
;
1188 if (!x86_pmu
.num_counters
)
1191 local_irq_save(flags
);
1193 cpu
= smp_processor_id();
1194 cpuc
= &per_cpu(cpu_hw_counters
, cpu
);
1196 if (x86_pmu
.version
>= 2) {
1197 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
1198 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
1199 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, overflow
);
1200 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL
, fixed
);
1203 pr_info("CPU#%d: ctrl: %016llx\n", cpu
, ctrl
);
1204 pr_info("CPU#%d: status: %016llx\n", cpu
, status
);
1205 pr_info("CPU#%d: overflow: %016llx\n", cpu
, overflow
);
1206 pr_info("CPU#%d: fixed: %016llx\n", cpu
, fixed
);
1208 pr_info("CPU#%d: used: %016llx\n", cpu
, *(u64
*)cpuc
->used_mask
);
1210 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1211 rdmsrl(x86_pmu
.eventsel
+ idx
, pmc_ctrl
);
1212 rdmsrl(x86_pmu
.perfctr
+ idx
, pmc_count
);
1214 prev_left
= per_cpu(prev_left
[idx
], cpu
);
1216 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1217 cpu
, idx
, pmc_ctrl
);
1218 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1219 cpu
, idx
, pmc_count
);
1220 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1221 cpu
, idx
, prev_left
);
1223 for (idx
= 0; idx
< x86_pmu
.num_counters_fixed
; idx
++) {
1224 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0
+ idx
, pmc_count
);
1226 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1227 cpu
, idx
, pmc_count
);
1229 local_irq_restore(flags
);
1232 static void x86_pmu_disable(struct perf_counter
*counter
)
1234 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
1235 struct hw_perf_counter
*hwc
= &counter
->hw
;
1239 * Must be done before we disable, otherwise the nmi handler
1240 * could reenable again:
1242 clear_bit(idx
, cpuc
->active_mask
);
1243 x86_pmu
.disable(hwc
, idx
);
1246 * Make sure the cleared pointer becomes visible before we
1247 * (potentially) free the counter:
1252 * Drain the remaining delta count out of a counter
1253 * that we are disabling:
1255 x86_perf_counter_update(counter
, hwc
, idx
);
1256 cpuc
->counters
[idx
] = NULL
;
1257 clear_bit(idx
, cpuc
->used_mask
);
1259 perf_counter_update_userpage(counter
);
1263 * Save and restart an expired counter. Called by NMI contexts,
1264 * so it has to be careful about preempting normal counter ops:
1266 static int intel_pmu_save_and_restart(struct perf_counter
*counter
)
1268 struct hw_perf_counter
*hwc
= &counter
->hw
;
1272 x86_perf_counter_update(counter
, hwc
, idx
);
1273 ret
= x86_perf_counter_set_period(counter
, hwc
, idx
);
1275 if (counter
->state
== PERF_COUNTER_STATE_ACTIVE
)
1276 intel_pmu_enable_counter(hwc
, idx
);
1281 static void intel_pmu_reset(void)
1283 unsigned long flags
;
1286 if (!x86_pmu
.num_counters
)
1289 local_irq_save(flags
);
1291 printk("clearing PMU state on CPU#%d\n", smp_processor_id());
1293 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1294 checking_wrmsrl(x86_pmu
.eventsel
+ idx
, 0ull);
1295 checking_wrmsrl(x86_pmu
.perfctr
+ idx
, 0ull);
1297 for (idx
= 0; idx
< x86_pmu
.num_counters_fixed
; idx
++) {
1298 checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0
+ idx
, 0ull);
1301 local_irq_restore(flags
);
1304 static int p6_pmu_handle_irq(struct pt_regs
*regs
)
1306 struct perf_sample_data data
;
1307 struct cpu_hw_counters
*cpuc
;
1308 struct perf_counter
*counter
;
1309 struct hw_perf_counter
*hwc
;
1310 int idx
, handled
= 0;
1316 cpuc
= &__get_cpu_var(cpu_hw_counters
);
1318 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1319 if (!test_bit(idx
, cpuc
->active_mask
))
1322 counter
= cpuc
->counters
[idx
];
1325 val
= x86_perf_counter_update(counter
, hwc
, idx
);
1326 if (val
& (1ULL << (x86_pmu
.counter_bits
- 1)))
1333 data
.period
= counter
->hw
.last_period
;
1335 if (!x86_perf_counter_set_period(counter
, hwc
, idx
))
1338 if (perf_counter_overflow(counter
, 1, &data
))
1339 p6_pmu_disable_counter(hwc
, idx
);
1343 inc_irq_stat(apic_perf_irqs
);
1349 * This handler is triggered by the local APIC, so the APIC IRQ handling
1352 static int intel_pmu_handle_irq(struct pt_regs
*regs
)
1354 struct perf_sample_data data
;
1355 struct cpu_hw_counters
*cpuc
;
1362 cpuc
= &__get_cpu_var(cpu_hw_counters
);
1365 status
= intel_pmu_get_status();
1373 if (++loops
> 100) {
1374 WARN_ONCE(1, "perfcounters: irq loop stuck!\n");
1375 perf_counter_print_debug();
1381 inc_irq_stat(apic_perf_irqs
);
1383 for_each_bit(bit
, (unsigned long *)&status
, X86_PMC_IDX_MAX
) {
1384 struct perf_counter
*counter
= cpuc
->counters
[bit
];
1386 clear_bit(bit
, (unsigned long *) &status
);
1387 if (!test_bit(bit
, cpuc
->active_mask
))
1390 if (!intel_pmu_save_and_restart(counter
))
1393 data
.period
= counter
->hw
.last_period
;
1395 if (perf_counter_overflow(counter
, 1, &data
))
1396 intel_pmu_disable_counter(&counter
->hw
, bit
);
1399 intel_pmu_ack_status(ack
);
1402 * Repeat if there is more work to be done:
1404 status
= intel_pmu_get_status();
1413 static int amd_pmu_handle_irq(struct pt_regs
*regs
)
1415 struct perf_sample_data data
;
1416 struct cpu_hw_counters
*cpuc
;
1417 struct perf_counter
*counter
;
1418 struct hw_perf_counter
*hwc
;
1419 int idx
, handled
= 0;
1425 cpuc
= &__get_cpu_var(cpu_hw_counters
);
1427 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1428 if (!test_bit(idx
, cpuc
->active_mask
))
1431 counter
= cpuc
->counters
[idx
];
1434 val
= x86_perf_counter_update(counter
, hwc
, idx
);
1435 if (val
& (1ULL << (x86_pmu
.counter_bits
- 1)))
1442 data
.period
= counter
->hw
.last_period
;
1444 if (!x86_perf_counter_set_period(counter
, hwc
, idx
))
1447 if (perf_counter_overflow(counter
, 1, &data
))
1448 amd_pmu_disable_counter(hwc
, idx
);
1452 inc_irq_stat(apic_perf_irqs
);
1457 void smp_perf_pending_interrupt(struct pt_regs
*regs
)
1461 inc_irq_stat(apic_pending_irqs
);
1462 perf_counter_do_pending();
1466 void set_perf_counter_pending(void)
1468 #ifdef CONFIG_X86_LOCAL_APIC
1469 apic
->send_IPI_self(LOCAL_PENDING_VECTOR
);
1473 void perf_counters_lapic_init(void)
1475 #ifdef CONFIG_X86_LOCAL_APIC
1476 if (!x86_pmu
.apic
|| !x86_pmu_initialized())
1480 * Always use NMI for PMU
1482 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1486 static int __kprobes
1487 perf_counter_nmi_handler(struct notifier_block
*self
,
1488 unsigned long cmd
, void *__args
)
1490 struct die_args
*args
= __args
;
1491 struct pt_regs
*regs
;
1493 if (!atomic_read(&active_counters
))
1507 #ifdef CONFIG_X86_LOCAL_APIC
1508 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1511 * Can't rely on the handled return value to say it was our NMI, two
1512 * counters could trigger 'simultaneously' raising two back-to-back NMIs.
1514 * If the first NMI handles both, the latter will be empty and daze
1517 x86_pmu
.handle_irq(regs
);
1522 static __read_mostly
struct notifier_block perf_counter_nmi_notifier
= {
1523 .notifier_call
= perf_counter_nmi_handler
,
1528 static struct x86_pmu p6_pmu
= {
1530 .handle_irq
= p6_pmu_handle_irq
,
1531 .disable_all
= p6_pmu_disable_all
,
1532 .enable_all
= p6_pmu_enable_all
,
1533 .enable
= p6_pmu_enable_counter
,
1534 .disable
= p6_pmu_disable_counter
,
1535 .eventsel
= MSR_P6_EVNTSEL0
,
1536 .perfctr
= MSR_P6_PERFCTR0
,
1537 .event_map
= p6_pmu_event_map
,
1538 .raw_event
= p6_pmu_raw_event
,
1539 .max_events
= ARRAY_SIZE(p6_perfmon_event_map
),
1541 .max_period
= (1ULL << 31) - 1,
1545 * Counters have 40 bits implemented. However they are designed such
1546 * that bits [32-39] are sign extensions of bit 31. As such the
1547 * effective width of a counter for P6-like PMU is 32 bits only.
1549 * See IA-32 Intel Architecture Software developer manual Vol 3B
1552 .counter_mask
= (1ULL << 32) - 1,
1555 static struct x86_pmu intel_pmu
= {
1557 .handle_irq
= intel_pmu_handle_irq
,
1558 .disable_all
= intel_pmu_disable_all
,
1559 .enable_all
= intel_pmu_enable_all
,
1560 .enable
= intel_pmu_enable_counter
,
1561 .disable
= intel_pmu_disable_counter
,
1562 .eventsel
= MSR_ARCH_PERFMON_EVENTSEL0
,
1563 .perfctr
= MSR_ARCH_PERFMON_PERFCTR0
,
1564 .event_map
= intel_pmu_event_map
,
1565 .raw_event
= intel_pmu_raw_event
,
1566 .max_events
= ARRAY_SIZE(intel_perfmon_event_map
),
1569 * Intel PMCs cannot be accessed sanely above 32 bit width,
1570 * so we install an artificial 1<<31 period regardless of
1571 * the generic counter period:
1573 .max_period
= (1ULL << 31) - 1,
1576 static struct x86_pmu amd_pmu
= {
1578 .handle_irq
= amd_pmu_handle_irq
,
1579 .disable_all
= amd_pmu_disable_all
,
1580 .enable_all
= amd_pmu_enable_all
,
1581 .enable
= amd_pmu_enable_counter
,
1582 .disable
= amd_pmu_disable_counter
,
1583 .eventsel
= MSR_K7_EVNTSEL0
,
1584 .perfctr
= MSR_K7_PERFCTR0
,
1585 .event_map
= amd_pmu_event_map
,
1586 .raw_event
= amd_pmu_raw_event
,
1587 .max_events
= ARRAY_SIZE(amd_perfmon_event_map
),
1590 .counter_mask
= (1ULL << 48) - 1,
1592 /* use highest bit to detect overflow */
1593 .max_period
= (1ULL << 47) - 1,
1596 static int p6_pmu_init(void)
1598 switch (boot_cpu_data
.x86_model
) {
1600 case 3: /* Pentium Pro */
1602 case 6: /* Pentium II */
1605 case 11: /* Pentium III */
1612 pr_cont("unsupported p6 CPU model %d ",
1613 boot_cpu_data
.x86_model
);
1619 if (!cpu_has_apic
) {
1620 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1621 pr_info("no hardware sampling interrupt available.\n");
1628 static int intel_pmu_init(void)
1630 union cpuid10_edx edx
;
1631 union cpuid10_eax eax
;
1632 unsigned int unused
;
1636 if (!cpu_has(&boot_cpu_data
, X86_FEATURE_ARCH_PERFMON
)) {
1637 /* check for P6 processor family */
1638 if (boot_cpu_data
.x86
== 6) {
1639 return p6_pmu_init();
1646 * Check whether the Architectural PerfMon supports
1647 * Branch Misses Retired Event or not.
1649 cpuid(10, &eax
.full
, &ebx
, &unused
, &edx
.full
);
1650 if (eax
.split
.mask_length
<= ARCH_PERFMON_BRANCH_MISSES_RETIRED
)
1653 version
= eax
.split
.version_id
;
1657 x86_pmu
= intel_pmu
;
1658 x86_pmu
.version
= version
;
1659 x86_pmu
.num_counters
= eax
.split
.num_counters
;
1660 x86_pmu
.counter_bits
= eax
.split
.bit_width
;
1661 x86_pmu
.counter_mask
= (1ULL << eax
.split
.bit_width
) - 1;
1664 * Quirk: v2 perfmon does not report fixed-purpose counters, so
1665 * assume at least 3 counters:
1667 x86_pmu
.num_counters_fixed
= max((int)edx
.split
.num_counters_fixed
, 3);
1670 * Install the hw-cache-events table:
1672 switch (boot_cpu_data
.x86_model
) {
1673 case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
1674 case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
1675 case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
1676 case 29: /* six-core 45 nm xeon "Dunnington" */
1677 memcpy(hw_cache_event_ids
, core2_hw_cache_event_ids
,
1678 sizeof(hw_cache_event_ids
));
1680 pr_cont("Core2 events, ");
1684 memcpy(hw_cache_event_ids
, nehalem_hw_cache_event_ids
,
1685 sizeof(hw_cache_event_ids
));
1687 pr_cont("Nehalem/Corei7 events, ");
1690 memcpy(hw_cache_event_ids
, atom_hw_cache_event_ids
,
1691 sizeof(hw_cache_event_ids
));
1693 pr_cont("Atom events, ");
1699 static int amd_pmu_init(void)
1701 /* Performance-monitoring supported from K7 and later: */
1702 if (boot_cpu_data
.x86
< 6)
1707 /* Events are common for all AMDs */
1708 memcpy(hw_cache_event_ids
, amd_hw_cache_event_ids
,
1709 sizeof(hw_cache_event_ids
));
1714 void __init
init_hw_perf_counters(void)
1718 pr_info("Performance Counters: ");
1720 switch (boot_cpu_data
.x86_vendor
) {
1721 case X86_VENDOR_INTEL
:
1722 err
= intel_pmu_init();
1724 case X86_VENDOR_AMD
:
1725 err
= amd_pmu_init();
1731 pr_cont("no PMU driver, software counters only.\n");
1735 pr_cont("%s PMU driver.\n", x86_pmu
.name
);
1737 if (x86_pmu
.num_counters
> X86_PMC_MAX_GENERIC
) {
1738 WARN(1, KERN_ERR
"hw perf counters %d > max(%d), clipping!",
1739 x86_pmu
.num_counters
, X86_PMC_MAX_GENERIC
);
1740 x86_pmu
.num_counters
= X86_PMC_MAX_GENERIC
;
1742 perf_counter_mask
= (1 << x86_pmu
.num_counters
) - 1;
1743 perf_max_counters
= x86_pmu
.num_counters
;
1745 if (x86_pmu
.num_counters_fixed
> X86_PMC_MAX_FIXED
) {
1746 WARN(1, KERN_ERR
"hw perf counters fixed %d > max(%d), clipping!",
1747 x86_pmu
.num_counters_fixed
, X86_PMC_MAX_FIXED
);
1748 x86_pmu
.num_counters_fixed
= X86_PMC_MAX_FIXED
;
1751 perf_counter_mask
|=
1752 ((1LL << x86_pmu
.num_counters_fixed
)-1) << X86_PMC_IDX_FIXED
;
1753 x86_pmu
.intel_ctrl
= perf_counter_mask
;
1755 perf_counters_lapic_init();
1756 register_die_notifier(&perf_counter_nmi_notifier
);
1758 pr_info("... version: %d\n", x86_pmu
.version
);
1759 pr_info("... bit width: %d\n", x86_pmu
.counter_bits
);
1760 pr_info("... generic counters: %d\n", x86_pmu
.num_counters
);
1761 pr_info("... value mask: %016Lx\n", x86_pmu
.counter_mask
);
1762 pr_info("... max period: %016Lx\n", x86_pmu
.max_period
);
1763 pr_info("... fixed-purpose counters: %d\n", x86_pmu
.num_counters_fixed
);
1764 pr_info("... counter mask: %016Lx\n", perf_counter_mask
);
1767 static inline void x86_pmu_read(struct perf_counter
*counter
)
1769 x86_perf_counter_update(counter
, &counter
->hw
, counter
->hw
.idx
);
1772 static const struct pmu pmu
= {
1773 .enable
= x86_pmu_enable
,
1774 .disable
= x86_pmu_disable
,
1775 .read
= x86_pmu_read
,
1776 .unthrottle
= x86_pmu_unthrottle
,
1779 const struct pmu
*hw_perf_counter_init(struct perf_counter
*counter
)
1783 err
= __hw_perf_counter_init(counter
);
1785 return ERR_PTR(err
);
1795 void callchain_store(struct perf_callchain_entry
*entry
, u64 ip
)
1797 if (entry
->nr
< PERF_MAX_STACK_DEPTH
)
1798 entry
->ip
[entry
->nr
++] = ip
;
1801 static DEFINE_PER_CPU(struct perf_callchain_entry
, irq_entry
);
1802 static DEFINE_PER_CPU(struct perf_callchain_entry
, nmi_entry
);
1803 static DEFINE_PER_CPU(int, in_nmi_frame
);
1807 backtrace_warning_symbol(void *data
, char *msg
, unsigned long symbol
)
1809 /* Ignore warnings */
1812 static void backtrace_warning(void *data
, char *msg
)
1814 /* Ignore warnings */
1817 static int backtrace_stack(void *data
, char *name
)
1819 per_cpu(in_nmi_frame
, smp_processor_id()) =
1820 x86_is_stack_id(NMI_STACK
, name
);
1825 static void backtrace_address(void *data
, unsigned long addr
, int reliable
)
1827 struct perf_callchain_entry
*entry
= data
;
1829 if (per_cpu(in_nmi_frame
, smp_processor_id()))
1833 callchain_store(entry
, addr
);
1836 static const struct stacktrace_ops backtrace_ops
= {
1837 .warning
= backtrace_warning
,
1838 .warning_symbol
= backtrace_warning_symbol
,
1839 .stack
= backtrace_stack
,
1840 .address
= backtrace_address
,
1843 #include "../dumpstack.h"
1846 perf_callchain_kernel(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1848 callchain_store(entry
, PERF_CONTEXT_KERNEL
);
1849 callchain_store(entry
, regs
->ip
);
1851 dump_trace(NULL
, regs
, NULL
, 0, &backtrace_ops
, entry
);
1855 * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
1857 static unsigned long
1858 copy_from_user_nmi(void *to
, const void __user
*from
, unsigned long n
)
1860 unsigned long offset
, addr
= (unsigned long)from
;
1861 int type
= in_nmi() ? KM_NMI
: KM_IRQ0
;
1862 unsigned long size
, len
= 0;
1868 ret
= __get_user_pages_fast(addr
, 1, 0, &page
);
1872 offset
= addr
& (PAGE_SIZE
- 1);
1873 size
= min(PAGE_SIZE
- offset
, n
- len
);
1875 map
= kmap_atomic(page
, type
);
1876 memcpy(to
, map
+offset
, size
);
1877 kunmap_atomic(map
, type
);
1889 static int copy_stack_frame(const void __user
*fp
, struct stack_frame
*frame
)
1891 unsigned long bytes
;
1893 bytes
= copy_from_user_nmi(frame
, fp
, sizeof(*frame
));
1895 return bytes
== sizeof(*frame
);
1899 perf_callchain_user(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1901 struct stack_frame frame
;
1902 const void __user
*fp
;
1904 if (!user_mode(regs
))
1905 regs
= task_pt_regs(current
);
1907 fp
= (void __user
*)regs
->bp
;
1909 callchain_store(entry
, PERF_CONTEXT_USER
);
1910 callchain_store(entry
, regs
->ip
);
1912 while (entry
->nr
< PERF_MAX_STACK_DEPTH
) {
1913 frame
.next_frame
= NULL
;
1914 frame
.return_address
= 0;
1916 if (!copy_stack_frame(fp
, &frame
))
1919 if ((unsigned long)fp
< regs
->sp
)
1922 callchain_store(entry
, frame
.return_address
);
1923 fp
= frame
.next_frame
;
1928 perf_do_callchain(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1935 is_user
= user_mode(regs
);
1937 if (!current
|| current
->pid
== 0)
1940 if (is_user
&& current
->state
!= TASK_RUNNING
)
1944 perf_callchain_kernel(regs
, entry
);
1947 perf_callchain_user(regs
, entry
);
1950 struct perf_callchain_entry
*perf_callchain(struct pt_regs
*regs
)
1952 struct perf_callchain_entry
*entry
;
1955 entry
= &__get_cpu_var(nmi_entry
);
1957 entry
= &__get_cpu_var(irq_entry
);
1961 perf_do_callchain(regs
, entry
);