2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
21 #include <linux/kvm_host.h>
22 #include <linux/module.h>
23 #include <linux/kernel.h>
25 #include <linux/highmem.h>
26 #include <linux/sched.h>
27 #include <linux/moduleparam.h>
28 #include "kvm_cache_regs.h"
34 #include <asm/virtext.h>
36 #define __ex(x) __kvm_handle_fault_on_reboot(x)
38 MODULE_AUTHOR("Qumranet");
39 MODULE_LICENSE("GPL");
41 static int __read_mostly bypass_guest_pf
= 1;
42 module_param(bypass_guest_pf
, bool, S_IRUGO
);
44 static int __read_mostly enable_vpid
= 1;
45 module_param_named(vpid
, enable_vpid
, bool, 0444);
47 static int __read_mostly flexpriority_enabled
= 1;
48 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
50 static int __read_mostly enable_ept
= 1;
51 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
53 static int __read_mostly emulate_invalid_guest_state
= 0;
54 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
64 struct list_head local_vcpus_link
;
65 unsigned long host_rsp
;
68 u32 idt_vectoring_info
;
69 struct kvm_msr_entry
*guest_msrs
;
70 struct kvm_msr_entry
*host_msrs
;
75 int msr_offset_kernel_gs_base
;
80 u16 fs_sel
, gs_sel
, ldt_sel
;
81 int gs_ldt_reload_needed
;
83 int guest_efer_loaded
;
93 bool emulation_required
;
94 enum emulation_result invalid_state_emulation_result
;
96 /* Support for vnmi-less CPUs */
97 int soft_vnmi_blocked
;
99 s64 vnmi_blocked_time
;
102 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
104 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
107 static int init_rmode(struct kvm
*kvm
);
108 static u64
construct_eptp(unsigned long root_hpa
);
110 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
111 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
112 static DEFINE_PER_CPU(struct list_head
, vcpus_on_cpu
);
114 static unsigned long *vmx_io_bitmap_a
;
115 static unsigned long *vmx_io_bitmap_b
;
116 static unsigned long *vmx_msr_bitmap_legacy
;
117 static unsigned long *vmx_msr_bitmap_longmode
;
119 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
120 static DEFINE_SPINLOCK(vmx_vpid_lock
);
122 static struct vmcs_config
{
126 u32 pin_based_exec_ctrl
;
127 u32 cpu_based_exec_ctrl
;
128 u32 cpu_based_2nd_exec_ctrl
;
133 static struct vmx_capability
{
138 #define VMX_SEGMENT_FIELD(seg) \
139 [VCPU_SREG_##seg] = { \
140 .selector = GUEST_##seg##_SELECTOR, \
141 .base = GUEST_##seg##_BASE, \
142 .limit = GUEST_##seg##_LIMIT, \
143 .ar_bytes = GUEST_##seg##_AR_BYTES, \
146 static struct kvm_vmx_segment_field
{
151 } kvm_vmx_segment_fields
[] = {
152 VMX_SEGMENT_FIELD(CS
),
153 VMX_SEGMENT_FIELD(DS
),
154 VMX_SEGMENT_FIELD(ES
),
155 VMX_SEGMENT_FIELD(FS
),
156 VMX_SEGMENT_FIELD(GS
),
157 VMX_SEGMENT_FIELD(SS
),
158 VMX_SEGMENT_FIELD(TR
),
159 VMX_SEGMENT_FIELD(LDTR
),
163 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
164 * away by decrementing the array size.
166 static const u32 vmx_msr_index
[] = {
168 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
, MSR_KERNEL_GS_BASE
,
170 MSR_EFER
, MSR_K6_STAR
,
172 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
174 static void load_msrs(struct kvm_msr_entry
*e
, int n
)
178 for (i
= 0; i
< n
; ++i
)
179 wrmsrl(e
[i
].index
, e
[i
].data
);
182 static void save_msrs(struct kvm_msr_entry
*e
, int n
)
186 for (i
= 0; i
< n
; ++i
)
187 rdmsrl(e
[i
].index
, e
[i
].data
);
190 static inline int is_page_fault(u32 intr_info
)
192 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
193 INTR_INFO_VALID_MASK
)) ==
194 (INTR_TYPE_HARD_EXCEPTION
| PF_VECTOR
| INTR_INFO_VALID_MASK
);
197 static inline int is_no_device(u32 intr_info
)
199 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
200 INTR_INFO_VALID_MASK
)) ==
201 (INTR_TYPE_HARD_EXCEPTION
| NM_VECTOR
| INTR_INFO_VALID_MASK
);
204 static inline int is_invalid_opcode(u32 intr_info
)
206 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
207 INTR_INFO_VALID_MASK
)) ==
208 (INTR_TYPE_HARD_EXCEPTION
| UD_VECTOR
| INTR_INFO_VALID_MASK
);
211 static inline int is_external_interrupt(u32 intr_info
)
213 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
214 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
217 static inline int cpu_has_vmx_msr_bitmap(void)
219 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
222 static inline int cpu_has_vmx_tpr_shadow(void)
224 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
227 static inline int vm_need_tpr_shadow(struct kvm
*kvm
)
229 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm
));
232 static inline int cpu_has_secondary_exec_ctrls(void)
234 return vmcs_config
.cpu_based_exec_ctrl
&
235 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
238 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
240 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
241 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
244 static inline bool cpu_has_vmx_flexpriority(void)
246 return cpu_has_vmx_tpr_shadow() &&
247 cpu_has_vmx_virtualize_apic_accesses();
250 static inline int cpu_has_vmx_invept_individual_addr(void)
252 return !!(vmx_capability
.ept
& VMX_EPT_EXTENT_INDIVIDUAL_BIT
);
255 static inline int cpu_has_vmx_invept_context(void)
257 return !!(vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
);
260 static inline int cpu_has_vmx_invept_global(void)
262 return !!(vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
);
265 static inline int cpu_has_vmx_ept(void)
267 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
268 SECONDARY_EXEC_ENABLE_EPT
;
271 static inline int vm_need_virtualize_apic_accesses(struct kvm
*kvm
)
273 return flexpriority_enabled
&&
274 (cpu_has_vmx_virtualize_apic_accesses()) &&
275 (irqchip_in_kernel(kvm
));
278 static inline int cpu_has_vmx_vpid(void)
280 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
281 SECONDARY_EXEC_ENABLE_VPID
;
284 static inline int cpu_has_virtual_nmis(void)
286 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
289 static inline bool report_flexpriority(void)
291 return flexpriority_enabled
;
294 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
298 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
299 if (vmx
->guest_msrs
[i
].index
== msr
)
304 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
310 } operand
= { vpid
, 0, gva
};
312 asm volatile (__ex(ASM_VMX_INVVPID
)
313 /* CF==1 or ZF==1 --> rc = -1 */
315 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
318 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
322 } operand
= {eptp
, gpa
};
324 asm volatile (__ex(ASM_VMX_INVEPT
)
325 /* CF==1 or ZF==1 --> rc = -1 */
326 "; ja 1f ; ud2 ; 1:\n"
327 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
330 static struct kvm_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
334 i
= __find_msr_index(vmx
, msr
);
336 return &vmx
->guest_msrs
[i
];
340 static void vmcs_clear(struct vmcs
*vmcs
)
342 u64 phys_addr
= __pa(vmcs
);
345 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
346 : "=g"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
349 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
353 static void __vcpu_clear(void *arg
)
355 struct vcpu_vmx
*vmx
= arg
;
356 int cpu
= raw_smp_processor_id();
358 if (vmx
->vcpu
.cpu
== cpu
)
359 vmcs_clear(vmx
->vmcs
);
360 if (per_cpu(current_vmcs
, cpu
) == vmx
->vmcs
)
361 per_cpu(current_vmcs
, cpu
) = NULL
;
362 rdtscll(vmx
->vcpu
.arch
.host_tsc
);
363 list_del(&vmx
->local_vcpus_link
);
368 static void vcpu_clear(struct vcpu_vmx
*vmx
)
370 if (vmx
->vcpu
.cpu
== -1)
372 smp_call_function_single(vmx
->vcpu
.cpu
, __vcpu_clear
, vmx
, 1);
375 static inline void vpid_sync_vcpu_all(struct vcpu_vmx
*vmx
)
380 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vmx
->vpid
, 0);
383 static inline void ept_sync_global(void)
385 if (cpu_has_vmx_invept_global())
386 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
389 static inline void ept_sync_context(u64 eptp
)
392 if (cpu_has_vmx_invept_context())
393 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
399 static inline void ept_sync_individual_addr(u64 eptp
, gpa_t gpa
)
402 if (cpu_has_vmx_invept_individual_addr())
403 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR
,
406 ept_sync_context(eptp
);
410 static unsigned long vmcs_readl(unsigned long field
)
414 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX
)
415 : "=a"(value
) : "d"(field
) : "cc");
419 static u16
vmcs_read16(unsigned long field
)
421 return vmcs_readl(field
);
424 static u32
vmcs_read32(unsigned long field
)
426 return vmcs_readl(field
);
429 static u64
vmcs_read64(unsigned long field
)
432 return vmcs_readl(field
);
434 return vmcs_readl(field
) | ((u64
)vmcs_readl(field
+1) << 32);
438 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
440 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
441 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
445 static void vmcs_writel(unsigned long field
, unsigned long value
)
449 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
450 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
452 vmwrite_error(field
, value
);
455 static void vmcs_write16(unsigned long field
, u16 value
)
457 vmcs_writel(field
, value
);
460 static void vmcs_write32(unsigned long field
, u32 value
)
462 vmcs_writel(field
, value
);
465 static void vmcs_write64(unsigned long field
, u64 value
)
467 vmcs_writel(field
, value
);
468 #ifndef CONFIG_X86_64
470 vmcs_writel(field
+1, value
>> 32);
474 static void vmcs_clear_bits(unsigned long field
, u32 mask
)
476 vmcs_writel(field
, vmcs_readl(field
) & ~mask
);
479 static void vmcs_set_bits(unsigned long field
, u32 mask
)
481 vmcs_writel(field
, vmcs_readl(field
) | mask
);
484 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
488 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
);
489 if (!vcpu
->fpu_active
)
490 eb
|= 1u << NM_VECTOR
;
491 if (vcpu
->guest_debug
& KVM_GUESTDBG_ENABLE
) {
492 if (vcpu
->guest_debug
&
493 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
494 eb
|= 1u << DB_VECTOR
;
495 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
496 eb
|= 1u << BP_VECTOR
;
498 if (vcpu
->arch
.rmode
.active
)
501 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
502 vmcs_write32(EXCEPTION_BITMAP
, eb
);
505 static void reload_tss(void)
508 * VT restores TR but not its size. Useless.
510 struct descriptor_table gdt
;
511 struct desc_struct
*descs
;
514 descs
= (void *)gdt
.base
;
515 descs
[GDT_ENTRY_TSS
].type
= 9; /* available TSS */
519 static void load_transition_efer(struct vcpu_vmx
*vmx
)
521 int efer_offset
= vmx
->msr_offset_efer
;
522 u64 host_efer
= vmx
->host_msrs
[efer_offset
].data
;
523 u64 guest_efer
= vmx
->guest_msrs
[efer_offset
].data
;
529 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
532 ignore_bits
= EFER_NX
| EFER_SCE
;
534 ignore_bits
|= EFER_LMA
| EFER_LME
;
535 /* SCE is meaningful only in long mode on Intel */
536 if (guest_efer
& EFER_LMA
)
537 ignore_bits
&= ~(u64
)EFER_SCE
;
539 if ((guest_efer
& ~ignore_bits
) == (host_efer
& ~ignore_bits
))
542 vmx
->host_state
.guest_efer_loaded
= 1;
543 guest_efer
&= ~ignore_bits
;
544 guest_efer
|= host_efer
& ignore_bits
;
545 wrmsrl(MSR_EFER
, guest_efer
);
546 vmx
->vcpu
.stat
.efer_reload
++;
549 static void reload_host_efer(struct vcpu_vmx
*vmx
)
551 if (vmx
->host_state
.guest_efer_loaded
) {
552 vmx
->host_state
.guest_efer_loaded
= 0;
553 load_msrs(vmx
->host_msrs
+ vmx
->msr_offset_efer
, 1);
557 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
559 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
561 if (vmx
->host_state
.loaded
)
564 vmx
->host_state
.loaded
= 1;
566 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
567 * allow segment selectors with cpl > 0 or ti == 1.
569 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
570 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
571 vmx
->host_state
.fs_sel
= kvm_read_fs();
572 if (!(vmx
->host_state
.fs_sel
& 7)) {
573 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
574 vmx
->host_state
.fs_reload_needed
= 0;
576 vmcs_write16(HOST_FS_SELECTOR
, 0);
577 vmx
->host_state
.fs_reload_needed
= 1;
579 vmx
->host_state
.gs_sel
= kvm_read_gs();
580 if (!(vmx
->host_state
.gs_sel
& 7))
581 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
583 vmcs_write16(HOST_GS_SELECTOR
, 0);
584 vmx
->host_state
.gs_ldt_reload_needed
= 1;
588 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
589 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
591 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
592 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
596 if (is_long_mode(&vmx
->vcpu
))
597 save_msrs(vmx
->host_msrs
+
598 vmx
->msr_offset_kernel_gs_base
, 1);
601 load_msrs(vmx
->guest_msrs
, vmx
->save_nmsrs
);
602 load_transition_efer(vmx
);
605 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
609 if (!vmx
->host_state
.loaded
)
612 ++vmx
->vcpu
.stat
.host_state_reload
;
613 vmx
->host_state
.loaded
= 0;
614 if (vmx
->host_state
.fs_reload_needed
)
615 kvm_load_fs(vmx
->host_state
.fs_sel
);
616 if (vmx
->host_state
.gs_ldt_reload_needed
) {
617 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
619 * If we have to reload gs, we must take care to
620 * preserve our gs base.
622 local_irq_save(flags
);
623 kvm_load_gs(vmx
->host_state
.gs_sel
);
625 wrmsrl(MSR_GS_BASE
, vmcs_readl(HOST_GS_BASE
));
627 local_irq_restore(flags
);
630 save_msrs(vmx
->guest_msrs
, vmx
->save_nmsrs
);
631 load_msrs(vmx
->host_msrs
, vmx
->save_nmsrs
);
632 reload_host_efer(vmx
);
635 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
638 __vmx_load_host_state(vmx
);
643 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
644 * vcpu mutex is already taken.
646 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
648 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
649 u64 phys_addr
= __pa(vmx
->vmcs
);
650 u64 tsc_this
, delta
, new_offset
;
652 if (vcpu
->cpu
!= cpu
) {
654 kvm_migrate_timers(vcpu
);
655 vpid_sync_vcpu_all(vmx
);
657 list_add(&vmx
->local_vcpus_link
,
658 &per_cpu(vcpus_on_cpu
, cpu
));
662 if (per_cpu(current_vmcs
, cpu
) != vmx
->vmcs
) {
665 per_cpu(current_vmcs
, cpu
) = vmx
->vmcs
;
666 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
667 : "=g"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
670 printk(KERN_ERR
"kvm: vmptrld %p/%llx fail\n",
671 vmx
->vmcs
, phys_addr
);
674 if (vcpu
->cpu
!= cpu
) {
675 struct descriptor_table dt
;
676 unsigned long sysenter_esp
;
680 * Linux uses per-cpu TSS and GDT, so set these when switching
683 vmcs_writel(HOST_TR_BASE
, kvm_read_tr_base()); /* 22.2.4 */
685 vmcs_writel(HOST_GDTR_BASE
, dt
.base
); /* 22.2.4 */
687 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
688 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
691 * Make sure the time stamp counter is monotonous.
694 if (tsc_this
< vcpu
->arch
.host_tsc
) {
695 delta
= vcpu
->arch
.host_tsc
- tsc_this
;
696 new_offset
= vmcs_read64(TSC_OFFSET
) + delta
;
697 vmcs_write64(TSC_OFFSET
, new_offset
);
702 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
704 __vmx_load_host_state(to_vmx(vcpu
));
707 static void vmx_fpu_activate(struct kvm_vcpu
*vcpu
)
709 if (vcpu
->fpu_active
)
711 vcpu
->fpu_active
= 1;
712 vmcs_clear_bits(GUEST_CR0
, X86_CR0_TS
);
713 if (vcpu
->arch
.cr0
& X86_CR0_TS
)
714 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
);
715 update_exception_bitmap(vcpu
);
718 static void vmx_fpu_deactivate(struct kvm_vcpu
*vcpu
)
720 if (!vcpu
->fpu_active
)
722 vcpu
->fpu_active
= 0;
723 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
);
724 update_exception_bitmap(vcpu
);
727 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
729 return vmcs_readl(GUEST_RFLAGS
);
732 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
734 if (vcpu
->arch
.rmode
.active
)
735 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
736 vmcs_writel(GUEST_RFLAGS
, rflags
);
739 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
742 u32 interruptibility
;
744 rip
= kvm_rip_read(vcpu
);
745 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
746 kvm_rip_write(vcpu
, rip
);
749 * We emulated an instruction, so temporary interrupt blocking
750 * should be removed, if set.
752 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
753 if (interruptibility
& 3)
754 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
755 interruptibility
& ~3);
756 vcpu
->arch
.interrupt_window_open
= 1;
759 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
760 bool has_error_code
, u32 error_code
)
762 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
763 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
765 if (has_error_code
) {
766 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
767 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
770 if (vcpu
->arch
.rmode
.active
) {
771 vmx
->rmode
.irq
.pending
= true;
772 vmx
->rmode
.irq
.vector
= nr
;
773 vmx
->rmode
.irq
.rip
= kvm_rip_read(vcpu
);
774 if (nr
== BP_VECTOR
|| nr
== OF_VECTOR
)
775 vmx
->rmode
.irq
.rip
++;
776 intr_info
|= INTR_TYPE_SOFT_INTR
;
777 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
778 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
, 1);
779 kvm_rip_write(vcpu
, vmx
->rmode
.irq
.rip
- 1);
783 if (nr
== BP_VECTOR
|| nr
== OF_VECTOR
) {
784 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
, 1);
785 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
787 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
789 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
792 static bool vmx_exception_injected(struct kvm_vcpu
*vcpu
)
798 * Swap MSR entry in host/guest MSR entry array.
801 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
803 struct kvm_msr_entry tmp
;
805 tmp
= vmx
->guest_msrs
[to
];
806 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
807 vmx
->guest_msrs
[from
] = tmp
;
808 tmp
= vmx
->host_msrs
[to
];
809 vmx
->host_msrs
[to
] = vmx
->host_msrs
[from
];
810 vmx
->host_msrs
[from
] = tmp
;
815 * Set up the vmcs to automatically save and restore system
816 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
817 * mode, as fiddling with msrs is very expensive.
819 static void setup_msrs(struct vcpu_vmx
*vmx
)
822 unsigned long *msr_bitmap
;
824 vmx_load_host_state(vmx
);
827 if (is_long_mode(&vmx
->vcpu
)) {
830 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
832 move_msr_up(vmx
, index
, save_nmsrs
++);
833 index
= __find_msr_index(vmx
, MSR_LSTAR
);
835 move_msr_up(vmx
, index
, save_nmsrs
++);
836 index
= __find_msr_index(vmx
, MSR_CSTAR
);
838 move_msr_up(vmx
, index
, save_nmsrs
++);
839 index
= __find_msr_index(vmx
, MSR_KERNEL_GS_BASE
);
841 move_msr_up(vmx
, index
, save_nmsrs
++);
843 * MSR_K6_STAR is only needed on long mode guests, and only
844 * if efer.sce is enabled.
846 index
= __find_msr_index(vmx
, MSR_K6_STAR
);
847 if ((index
>= 0) && (vmx
->vcpu
.arch
.shadow_efer
& EFER_SCE
))
848 move_msr_up(vmx
, index
, save_nmsrs
++);
851 vmx
->save_nmsrs
= save_nmsrs
;
854 vmx
->msr_offset_kernel_gs_base
=
855 __find_msr_index(vmx
, MSR_KERNEL_GS_BASE
);
857 vmx
->msr_offset_efer
= __find_msr_index(vmx
, MSR_EFER
);
859 if (cpu_has_vmx_msr_bitmap()) {
860 if (is_long_mode(&vmx
->vcpu
))
861 msr_bitmap
= vmx_msr_bitmap_longmode
;
863 msr_bitmap
= vmx_msr_bitmap_legacy
;
865 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
870 * reads and returns guest's timestamp counter "register"
871 * guest_tsc = host_tsc + tsc_offset -- 21.3
873 static u64
guest_read_tsc(void)
875 u64 host_tsc
, tsc_offset
;
878 tsc_offset
= vmcs_read64(TSC_OFFSET
);
879 return host_tsc
+ tsc_offset
;
883 * writes 'guest_tsc' into guest's timestamp counter "register"
884 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
886 static void guest_write_tsc(u64 guest_tsc
, u64 host_tsc
)
888 vmcs_write64(TSC_OFFSET
, guest_tsc
- host_tsc
);
892 * Reads an msr value (of 'msr_index') into 'pdata'.
893 * Returns 0 on success, non-0 otherwise.
894 * Assumes vcpu_load() was already called.
896 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
899 struct kvm_msr_entry
*msr
;
902 printk(KERN_ERR
"BUG: get_msr called with NULL pdata\n");
909 data
= vmcs_readl(GUEST_FS_BASE
);
912 data
= vmcs_readl(GUEST_GS_BASE
);
915 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
917 case MSR_IA32_TIME_STAMP_COUNTER
:
918 data
= guest_read_tsc();
920 case MSR_IA32_SYSENTER_CS
:
921 data
= vmcs_read32(GUEST_SYSENTER_CS
);
923 case MSR_IA32_SYSENTER_EIP
:
924 data
= vmcs_readl(GUEST_SYSENTER_EIP
);
926 case MSR_IA32_SYSENTER_ESP
:
927 data
= vmcs_readl(GUEST_SYSENTER_ESP
);
930 vmx_load_host_state(to_vmx(vcpu
));
931 msr
= find_msr_entry(to_vmx(vcpu
), msr_index
);
936 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
944 * Writes msr value into into the appropriate "register".
945 * Returns 0 on success, non-0 otherwise.
946 * Assumes vcpu_load() was already called.
948 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
950 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
951 struct kvm_msr_entry
*msr
;
957 vmx_load_host_state(vmx
);
958 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
962 vmcs_writel(GUEST_FS_BASE
, data
);
965 vmcs_writel(GUEST_GS_BASE
, data
);
968 case MSR_IA32_SYSENTER_CS
:
969 vmcs_write32(GUEST_SYSENTER_CS
, data
);
971 case MSR_IA32_SYSENTER_EIP
:
972 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
974 case MSR_IA32_SYSENTER_ESP
:
975 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
977 case MSR_IA32_TIME_STAMP_COUNTER
:
979 guest_write_tsc(data
, host_tsc
);
981 case MSR_P6_PERFCTR0
:
982 case MSR_P6_PERFCTR1
:
983 case MSR_P6_EVNTSEL0
:
984 case MSR_P6_EVNTSEL1
:
986 * Just discard all writes to the performance counters; this
987 * should keep both older linux and windows 64-bit guests
990 pr_unimpl(vcpu
, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", msr_index
, data
);
993 case MSR_IA32_CR_PAT
:
994 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
995 vmcs_write64(GUEST_IA32_PAT
, data
);
996 vcpu
->arch
.pat
= data
;
999 /* Otherwise falls through to kvm_set_msr_common */
1001 vmx_load_host_state(vmx
);
1002 msr
= find_msr_entry(vmx
, msr_index
);
1007 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
1013 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
1015 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
1018 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
1021 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
1028 static int set_guest_debug(struct kvm_vcpu
*vcpu
, struct kvm_guest_debug
*dbg
)
1030 int old_debug
= vcpu
->guest_debug
;
1031 unsigned long flags
;
1033 vcpu
->guest_debug
= dbg
->control
;
1034 if (!(vcpu
->guest_debug
& KVM_GUESTDBG_ENABLE
))
1035 vcpu
->guest_debug
= 0;
1037 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)
1038 vmcs_writel(GUEST_DR7
, dbg
->arch
.debugreg
[7]);
1040 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
1042 flags
= vmcs_readl(GUEST_RFLAGS
);
1043 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
1044 flags
|= X86_EFLAGS_TF
| X86_EFLAGS_RF
;
1045 else if (old_debug
& KVM_GUESTDBG_SINGLESTEP
)
1046 flags
&= ~(X86_EFLAGS_TF
| X86_EFLAGS_RF
);
1047 vmcs_writel(GUEST_RFLAGS
, flags
);
1049 update_exception_bitmap(vcpu
);
1054 static int vmx_get_irq(struct kvm_vcpu
*vcpu
)
1056 if (!vcpu
->arch
.interrupt
.pending
)
1058 return vcpu
->arch
.interrupt
.nr
;
1061 static __init
int cpu_has_kvm_support(void)
1063 return cpu_has_vmx();
1066 static __init
int vmx_disabled_by_bios(void)
1070 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
1071 return (msr
& (FEATURE_CONTROL_LOCKED
|
1072 FEATURE_CONTROL_VMXON_ENABLED
))
1073 == FEATURE_CONTROL_LOCKED
;
1074 /* locked but not enabled */
1077 static void hardware_enable(void *garbage
)
1079 int cpu
= raw_smp_processor_id();
1080 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
1083 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu
, cpu
));
1084 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
1085 if ((old
& (FEATURE_CONTROL_LOCKED
|
1086 FEATURE_CONTROL_VMXON_ENABLED
))
1087 != (FEATURE_CONTROL_LOCKED
|
1088 FEATURE_CONTROL_VMXON_ENABLED
))
1089 /* enable and lock */
1090 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
|
1091 FEATURE_CONTROL_LOCKED
|
1092 FEATURE_CONTROL_VMXON_ENABLED
);
1093 write_cr4(read_cr4() | X86_CR4_VMXE
); /* FIXME: not cpu hotplug safe */
1094 asm volatile (ASM_VMX_VMXON_RAX
1095 : : "a"(&phys_addr
), "m"(phys_addr
)
1099 static void vmclear_local_vcpus(void)
1101 int cpu
= raw_smp_processor_id();
1102 struct vcpu_vmx
*vmx
, *n
;
1104 list_for_each_entry_safe(vmx
, n
, &per_cpu(vcpus_on_cpu
, cpu
),
1110 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1113 static void kvm_cpu_vmxoff(void)
1115 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
1116 write_cr4(read_cr4() & ~X86_CR4_VMXE
);
1119 static void hardware_disable(void *garbage
)
1121 vmclear_local_vcpus();
1125 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
1126 u32 msr
, u32
*result
)
1128 u32 vmx_msr_low
, vmx_msr_high
;
1129 u32 ctl
= ctl_min
| ctl_opt
;
1131 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
1133 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
1134 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
1136 /* Ensure minimum (required) set of control bits are supported. */
1144 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
1146 u32 vmx_msr_low
, vmx_msr_high
;
1147 u32 min
, opt
, min2
, opt2
;
1148 u32 _pin_based_exec_control
= 0;
1149 u32 _cpu_based_exec_control
= 0;
1150 u32 _cpu_based_2nd_exec_control
= 0;
1151 u32 _vmexit_control
= 0;
1152 u32 _vmentry_control
= 0;
1154 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
1155 opt
= PIN_BASED_VIRTUAL_NMIS
;
1156 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
1157 &_pin_based_exec_control
) < 0)
1160 min
= CPU_BASED_HLT_EXITING
|
1161 #ifdef CONFIG_X86_64
1162 CPU_BASED_CR8_LOAD_EXITING
|
1163 CPU_BASED_CR8_STORE_EXITING
|
1165 CPU_BASED_CR3_LOAD_EXITING
|
1166 CPU_BASED_CR3_STORE_EXITING
|
1167 CPU_BASED_USE_IO_BITMAPS
|
1168 CPU_BASED_MOV_DR_EXITING
|
1169 CPU_BASED_USE_TSC_OFFSETING
|
1170 CPU_BASED_INVLPG_EXITING
;
1171 opt
= CPU_BASED_TPR_SHADOW
|
1172 CPU_BASED_USE_MSR_BITMAPS
|
1173 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1174 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
1175 &_cpu_based_exec_control
) < 0)
1177 #ifdef CONFIG_X86_64
1178 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
1179 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
1180 ~CPU_BASED_CR8_STORE_EXITING
;
1182 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
1184 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
1185 SECONDARY_EXEC_WBINVD_EXITING
|
1186 SECONDARY_EXEC_ENABLE_VPID
|
1187 SECONDARY_EXEC_ENABLE_EPT
;
1188 if (adjust_vmx_controls(min2
, opt2
,
1189 MSR_IA32_VMX_PROCBASED_CTLS2
,
1190 &_cpu_based_2nd_exec_control
) < 0)
1193 #ifndef CONFIG_X86_64
1194 if (!(_cpu_based_2nd_exec_control
&
1195 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
1196 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
1198 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
1199 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1201 min
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
1202 CPU_BASED_CR3_STORE_EXITING
|
1203 CPU_BASED_INVLPG_EXITING
);
1204 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
1205 &_cpu_based_exec_control
) < 0)
1207 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
1208 vmx_capability
.ept
, vmx_capability
.vpid
);
1211 if (!cpu_has_vmx_vpid())
1214 if (!cpu_has_vmx_ept())
1217 if (!cpu_has_vmx_flexpriority())
1218 flexpriority_enabled
= 0;
1221 #ifdef CONFIG_X86_64
1222 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
1224 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
;
1225 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
1226 &_vmexit_control
) < 0)
1230 opt
= VM_ENTRY_LOAD_IA32_PAT
;
1231 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
1232 &_vmentry_control
) < 0)
1235 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
1237 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1238 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
1241 #ifdef CONFIG_X86_64
1242 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1243 if (vmx_msr_high
& (1u<<16))
1247 /* Require Write-Back (WB) memory type for VMCS accesses. */
1248 if (((vmx_msr_high
>> 18) & 15) != 6)
1251 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
1252 vmcs_conf
->order
= get_order(vmcs_config
.size
);
1253 vmcs_conf
->revision_id
= vmx_msr_low
;
1255 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
1256 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
1257 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
1258 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
1259 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
1264 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
1266 int node
= cpu_to_node(cpu
);
1270 pages
= alloc_pages_node(node
, GFP_KERNEL
, vmcs_config
.order
);
1273 vmcs
= page_address(pages
);
1274 memset(vmcs
, 0, vmcs_config
.size
);
1275 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
1279 static struct vmcs
*alloc_vmcs(void)
1281 return alloc_vmcs_cpu(raw_smp_processor_id());
1284 static void free_vmcs(struct vmcs
*vmcs
)
1286 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
1289 static void free_kvm_area(void)
1293 for_each_online_cpu(cpu
)
1294 free_vmcs(per_cpu(vmxarea
, cpu
));
1297 static __init
int alloc_kvm_area(void)
1301 for_each_online_cpu(cpu
) {
1304 vmcs
= alloc_vmcs_cpu(cpu
);
1310 per_cpu(vmxarea
, cpu
) = vmcs
;
1315 static __init
int hardware_setup(void)
1317 if (setup_vmcs_config(&vmcs_config
) < 0)
1320 if (boot_cpu_has(X86_FEATURE_NX
))
1321 kvm_enable_efer_bits(EFER_NX
);
1323 return alloc_kvm_area();
1326 static __exit
void hardware_unsetup(void)
1331 static void fix_pmode_dataseg(int seg
, struct kvm_save_segment
*save
)
1333 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1335 if (vmcs_readl(sf
->base
) == save
->base
&& (save
->base
& AR_S_MASK
)) {
1336 vmcs_write16(sf
->selector
, save
->selector
);
1337 vmcs_writel(sf
->base
, save
->base
);
1338 vmcs_write32(sf
->limit
, save
->limit
);
1339 vmcs_write32(sf
->ar_bytes
, save
->ar
);
1341 u32 dpl
= (vmcs_read16(sf
->selector
) & SELECTOR_RPL_MASK
)
1343 vmcs_write32(sf
->ar_bytes
, 0x93 | dpl
);
1347 static void enter_pmode(struct kvm_vcpu
*vcpu
)
1349 unsigned long flags
;
1350 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1352 vmx
->emulation_required
= 1;
1353 vcpu
->arch
.rmode
.active
= 0;
1355 vmcs_writel(GUEST_TR_BASE
, vcpu
->arch
.rmode
.tr
.base
);
1356 vmcs_write32(GUEST_TR_LIMIT
, vcpu
->arch
.rmode
.tr
.limit
);
1357 vmcs_write32(GUEST_TR_AR_BYTES
, vcpu
->arch
.rmode
.tr
.ar
);
1359 flags
= vmcs_readl(GUEST_RFLAGS
);
1360 flags
&= ~(X86_EFLAGS_IOPL
| X86_EFLAGS_VM
);
1361 flags
|= (vcpu
->arch
.rmode
.save_iopl
<< IOPL_SHIFT
);
1362 vmcs_writel(GUEST_RFLAGS
, flags
);
1364 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
1365 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
1367 update_exception_bitmap(vcpu
);
1369 if (emulate_invalid_guest_state
)
1372 fix_pmode_dataseg(VCPU_SREG_ES
, &vcpu
->arch
.rmode
.es
);
1373 fix_pmode_dataseg(VCPU_SREG_DS
, &vcpu
->arch
.rmode
.ds
);
1374 fix_pmode_dataseg(VCPU_SREG_GS
, &vcpu
->arch
.rmode
.gs
);
1375 fix_pmode_dataseg(VCPU_SREG_FS
, &vcpu
->arch
.rmode
.fs
);
1377 vmcs_write16(GUEST_SS_SELECTOR
, 0);
1378 vmcs_write32(GUEST_SS_AR_BYTES
, 0x93);
1380 vmcs_write16(GUEST_CS_SELECTOR
,
1381 vmcs_read16(GUEST_CS_SELECTOR
) & ~SELECTOR_RPL_MASK
);
1382 vmcs_write32(GUEST_CS_AR_BYTES
, 0x9b);
1385 static gva_t
rmode_tss_base(struct kvm
*kvm
)
1387 if (!kvm
->arch
.tss_addr
) {
1388 gfn_t base_gfn
= kvm
->memslots
[0].base_gfn
+
1389 kvm
->memslots
[0].npages
- 3;
1390 return base_gfn
<< PAGE_SHIFT
;
1392 return kvm
->arch
.tss_addr
;
1395 static void fix_rmode_seg(int seg
, struct kvm_save_segment
*save
)
1397 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1399 save
->selector
= vmcs_read16(sf
->selector
);
1400 save
->base
= vmcs_readl(sf
->base
);
1401 save
->limit
= vmcs_read32(sf
->limit
);
1402 save
->ar
= vmcs_read32(sf
->ar_bytes
);
1403 vmcs_write16(sf
->selector
, save
->base
>> 4);
1404 vmcs_write32(sf
->base
, save
->base
& 0xfffff);
1405 vmcs_write32(sf
->limit
, 0xffff);
1406 vmcs_write32(sf
->ar_bytes
, 0xf3);
1409 static void enter_rmode(struct kvm_vcpu
*vcpu
)
1411 unsigned long flags
;
1412 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1414 vmx
->emulation_required
= 1;
1415 vcpu
->arch
.rmode
.active
= 1;
1417 vcpu
->arch
.rmode
.tr
.base
= vmcs_readl(GUEST_TR_BASE
);
1418 vmcs_writel(GUEST_TR_BASE
, rmode_tss_base(vcpu
->kvm
));
1420 vcpu
->arch
.rmode
.tr
.limit
= vmcs_read32(GUEST_TR_LIMIT
);
1421 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
1423 vcpu
->arch
.rmode
.tr
.ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
1424 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
1426 flags
= vmcs_readl(GUEST_RFLAGS
);
1427 vcpu
->arch
.rmode
.save_iopl
1428 = (flags
& X86_EFLAGS_IOPL
) >> IOPL_SHIFT
;
1430 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
1432 vmcs_writel(GUEST_RFLAGS
, flags
);
1433 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
1434 update_exception_bitmap(vcpu
);
1436 if (emulate_invalid_guest_state
)
1437 goto continue_rmode
;
1439 vmcs_write16(GUEST_SS_SELECTOR
, vmcs_readl(GUEST_SS_BASE
) >> 4);
1440 vmcs_write32(GUEST_SS_LIMIT
, 0xffff);
1441 vmcs_write32(GUEST_SS_AR_BYTES
, 0xf3);
1443 vmcs_write32(GUEST_CS_AR_BYTES
, 0xf3);
1444 vmcs_write32(GUEST_CS_LIMIT
, 0xffff);
1445 if (vmcs_readl(GUEST_CS_BASE
) == 0xffff0000)
1446 vmcs_writel(GUEST_CS_BASE
, 0xf0000);
1447 vmcs_write16(GUEST_CS_SELECTOR
, vmcs_readl(GUEST_CS_BASE
) >> 4);
1449 fix_rmode_seg(VCPU_SREG_ES
, &vcpu
->arch
.rmode
.es
);
1450 fix_rmode_seg(VCPU_SREG_DS
, &vcpu
->arch
.rmode
.ds
);
1451 fix_rmode_seg(VCPU_SREG_GS
, &vcpu
->arch
.rmode
.gs
);
1452 fix_rmode_seg(VCPU_SREG_FS
, &vcpu
->arch
.rmode
.fs
);
1455 kvm_mmu_reset_context(vcpu
);
1456 init_rmode(vcpu
->kvm
);
1459 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
1461 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1462 struct kvm_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
1464 vcpu
->arch
.shadow_efer
= efer
;
1467 if (efer
& EFER_LMA
) {
1468 vmcs_write32(VM_ENTRY_CONTROLS
,
1469 vmcs_read32(VM_ENTRY_CONTROLS
) |
1470 VM_ENTRY_IA32E_MODE
);
1473 vmcs_write32(VM_ENTRY_CONTROLS
,
1474 vmcs_read32(VM_ENTRY_CONTROLS
) &
1475 ~VM_ENTRY_IA32E_MODE
);
1477 msr
->data
= efer
& ~EFER_LME
;
1482 #ifdef CONFIG_X86_64
1484 static void enter_lmode(struct kvm_vcpu
*vcpu
)
1488 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
1489 if ((guest_tr_ar
& AR_TYPE_MASK
) != AR_TYPE_BUSY_64_TSS
) {
1490 printk(KERN_DEBUG
"%s: tss fixup for long mode. \n",
1492 vmcs_write32(GUEST_TR_AR_BYTES
,
1493 (guest_tr_ar
& ~AR_TYPE_MASK
)
1494 | AR_TYPE_BUSY_64_TSS
);
1496 vcpu
->arch
.shadow_efer
|= EFER_LMA
;
1497 vmx_set_efer(vcpu
, vcpu
->arch
.shadow_efer
);
1500 static void exit_lmode(struct kvm_vcpu
*vcpu
)
1502 vcpu
->arch
.shadow_efer
&= ~EFER_LMA
;
1504 vmcs_write32(VM_ENTRY_CONTROLS
,
1505 vmcs_read32(VM_ENTRY_CONTROLS
)
1506 & ~VM_ENTRY_IA32E_MODE
);
1511 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
1513 vpid_sync_vcpu_all(to_vmx(vcpu
));
1515 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
1518 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
1520 vcpu
->arch
.cr4
&= KVM_GUEST_CR4_MASK
;
1521 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & ~KVM_GUEST_CR4_MASK
;
1524 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
1526 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
1527 if (!load_pdptrs(vcpu
, vcpu
->arch
.cr3
)) {
1528 printk(KERN_ERR
"EPT: Fail to load pdptrs!\n");
1531 vmcs_write64(GUEST_PDPTR0
, vcpu
->arch
.pdptrs
[0]);
1532 vmcs_write64(GUEST_PDPTR1
, vcpu
->arch
.pdptrs
[1]);
1533 vmcs_write64(GUEST_PDPTR2
, vcpu
->arch
.pdptrs
[2]);
1534 vmcs_write64(GUEST_PDPTR3
, vcpu
->arch
.pdptrs
[3]);
1538 static void vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
1540 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
1542 struct kvm_vcpu
*vcpu
)
1544 if (!(cr0
& X86_CR0_PG
)) {
1545 /* From paging/starting to nonpaging */
1546 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
1547 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
1548 (CPU_BASED_CR3_LOAD_EXITING
|
1549 CPU_BASED_CR3_STORE_EXITING
));
1550 vcpu
->arch
.cr0
= cr0
;
1551 vmx_set_cr4(vcpu
, vcpu
->arch
.cr4
);
1552 *hw_cr0
|= X86_CR0_PE
| X86_CR0_PG
;
1553 *hw_cr0
&= ~X86_CR0_WP
;
1554 } else if (!is_paging(vcpu
)) {
1555 /* From nonpaging to paging */
1556 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
1557 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
1558 ~(CPU_BASED_CR3_LOAD_EXITING
|
1559 CPU_BASED_CR3_STORE_EXITING
));
1560 vcpu
->arch
.cr0
= cr0
;
1561 vmx_set_cr4(vcpu
, vcpu
->arch
.cr4
);
1562 if (!(vcpu
->arch
.cr0
& X86_CR0_WP
))
1563 *hw_cr0
&= ~X86_CR0_WP
;
1567 static void ept_update_paging_mode_cr4(unsigned long *hw_cr4
,
1568 struct kvm_vcpu
*vcpu
)
1570 if (!is_paging(vcpu
)) {
1571 *hw_cr4
&= ~X86_CR4_PAE
;
1572 *hw_cr4
|= X86_CR4_PSE
;
1573 } else if (!(vcpu
->arch
.cr4
& X86_CR4_PAE
))
1574 *hw_cr4
&= ~X86_CR4_PAE
;
1577 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
1579 unsigned long hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
) |
1580 KVM_VM_CR0_ALWAYS_ON
;
1582 vmx_fpu_deactivate(vcpu
);
1584 if (vcpu
->arch
.rmode
.active
&& (cr0
& X86_CR0_PE
))
1587 if (!vcpu
->arch
.rmode
.active
&& !(cr0
& X86_CR0_PE
))
1590 #ifdef CONFIG_X86_64
1591 if (vcpu
->arch
.shadow_efer
& EFER_LME
) {
1592 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
1594 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
1600 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
1602 vmcs_writel(CR0_READ_SHADOW
, cr0
);
1603 vmcs_writel(GUEST_CR0
, hw_cr0
);
1604 vcpu
->arch
.cr0
= cr0
;
1606 if (!(cr0
& X86_CR0_TS
) || !(cr0
& X86_CR0_PE
))
1607 vmx_fpu_activate(vcpu
);
1610 static u64
construct_eptp(unsigned long root_hpa
)
1614 /* TODO write the value reading from MSR */
1615 eptp
= VMX_EPT_DEFAULT_MT
|
1616 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
1617 eptp
|= (root_hpa
& PAGE_MASK
);
1622 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
1624 unsigned long guest_cr3
;
1629 eptp
= construct_eptp(cr3
);
1630 vmcs_write64(EPT_POINTER
, eptp
);
1631 ept_sync_context(eptp
);
1632 ept_load_pdptrs(vcpu
);
1633 guest_cr3
= is_paging(vcpu
) ? vcpu
->arch
.cr3
:
1634 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
1637 vmx_flush_tlb(vcpu
);
1638 vmcs_writel(GUEST_CR3
, guest_cr3
);
1639 if (vcpu
->arch
.cr0
& X86_CR0_PE
)
1640 vmx_fpu_deactivate(vcpu
);
1643 static void vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
1645 unsigned long hw_cr4
= cr4
| (vcpu
->arch
.rmode
.active
?
1646 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
1648 vcpu
->arch
.cr4
= cr4
;
1650 ept_update_paging_mode_cr4(&hw_cr4
, vcpu
);
1652 vmcs_writel(CR4_READ_SHADOW
, cr4
);
1653 vmcs_writel(GUEST_CR4
, hw_cr4
);
1656 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
1658 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1660 return vmcs_readl(sf
->base
);
1663 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
1664 struct kvm_segment
*var
, int seg
)
1666 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1669 var
->base
= vmcs_readl(sf
->base
);
1670 var
->limit
= vmcs_read32(sf
->limit
);
1671 var
->selector
= vmcs_read16(sf
->selector
);
1672 ar
= vmcs_read32(sf
->ar_bytes
);
1673 if ((ar
& AR_UNUSABLE_MASK
) && !emulate_invalid_guest_state
)
1675 var
->type
= ar
& 15;
1676 var
->s
= (ar
>> 4) & 1;
1677 var
->dpl
= (ar
>> 5) & 3;
1678 var
->present
= (ar
>> 7) & 1;
1679 var
->avl
= (ar
>> 12) & 1;
1680 var
->l
= (ar
>> 13) & 1;
1681 var
->db
= (ar
>> 14) & 1;
1682 var
->g
= (ar
>> 15) & 1;
1683 var
->unusable
= (ar
>> 16) & 1;
1686 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
1688 struct kvm_segment kvm_seg
;
1690 if (!(vcpu
->arch
.cr0
& X86_CR0_PE
)) /* if real mode */
1693 if (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
) /* if virtual 8086 */
1696 vmx_get_segment(vcpu
, &kvm_seg
, VCPU_SREG_CS
);
1697 return kvm_seg
.selector
& 3;
1700 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
1707 ar
= var
->type
& 15;
1708 ar
|= (var
->s
& 1) << 4;
1709 ar
|= (var
->dpl
& 3) << 5;
1710 ar
|= (var
->present
& 1) << 7;
1711 ar
|= (var
->avl
& 1) << 12;
1712 ar
|= (var
->l
& 1) << 13;
1713 ar
|= (var
->db
& 1) << 14;
1714 ar
|= (var
->g
& 1) << 15;
1716 if (ar
== 0) /* a 0 value means unusable */
1717 ar
= AR_UNUSABLE_MASK
;
1722 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
1723 struct kvm_segment
*var
, int seg
)
1725 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1728 if (vcpu
->arch
.rmode
.active
&& seg
== VCPU_SREG_TR
) {
1729 vcpu
->arch
.rmode
.tr
.selector
= var
->selector
;
1730 vcpu
->arch
.rmode
.tr
.base
= var
->base
;
1731 vcpu
->arch
.rmode
.tr
.limit
= var
->limit
;
1732 vcpu
->arch
.rmode
.tr
.ar
= vmx_segment_access_rights(var
);
1735 vmcs_writel(sf
->base
, var
->base
);
1736 vmcs_write32(sf
->limit
, var
->limit
);
1737 vmcs_write16(sf
->selector
, var
->selector
);
1738 if (vcpu
->arch
.rmode
.active
&& var
->s
) {
1740 * Hack real-mode segments into vm86 compatibility.
1742 if (var
->base
== 0xffff0000 && var
->selector
== 0xf000)
1743 vmcs_writel(sf
->base
, 0xf0000);
1746 ar
= vmx_segment_access_rights(var
);
1747 vmcs_write32(sf
->ar_bytes
, ar
);
1750 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
1752 u32 ar
= vmcs_read32(GUEST_CS_AR_BYTES
);
1754 *db
= (ar
>> 14) & 1;
1755 *l
= (ar
>> 13) & 1;
1758 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
1760 dt
->limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
1761 dt
->base
= vmcs_readl(GUEST_IDTR_BASE
);
1764 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
1766 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->limit
);
1767 vmcs_writel(GUEST_IDTR_BASE
, dt
->base
);
1770 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
1772 dt
->limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
1773 dt
->base
= vmcs_readl(GUEST_GDTR_BASE
);
1776 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
1778 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->limit
);
1779 vmcs_writel(GUEST_GDTR_BASE
, dt
->base
);
1782 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
1784 struct kvm_segment var
;
1787 vmx_get_segment(vcpu
, &var
, seg
);
1788 ar
= vmx_segment_access_rights(&var
);
1790 if (var
.base
!= (var
.selector
<< 4))
1792 if (var
.limit
!= 0xffff)
1800 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
1802 struct kvm_segment cs
;
1803 unsigned int cs_rpl
;
1805 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
1806 cs_rpl
= cs
.selector
& SELECTOR_RPL_MASK
;
1810 if (~cs
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_ACCESSES_MASK
))
1814 if (cs
.type
& AR_TYPE_WRITEABLE_MASK
) {
1815 if (cs
.dpl
> cs_rpl
)
1818 if (cs
.dpl
!= cs_rpl
)
1824 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1828 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
1830 struct kvm_segment ss
;
1831 unsigned int ss_rpl
;
1833 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
1834 ss_rpl
= ss
.selector
& SELECTOR_RPL_MASK
;
1838 if (ss
.type
!= 3 && ss
.type
!= 7)
1842 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
1850 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
1852 struct kvm_segment var
;
1855 vmx_get_segment(vcpu
, &var
, seg
);
1856 rpl
= var
.selector
& SELECTOR_RPL_MASK
;
1864 if (~var
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_WRITEABLE_MASK
)) {
1865 if (var
.dpl
< rpl
) /* DPL < RPL */
1869 /* TODO: Add other members to kvm_segment_field to allow checking for other access
1875 static bool tr_valid(struct kvm_vcpu
*vcpu
)
1877 struct kvm_segment tr
;
1879 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
1883 if (tr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
1885 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
1893 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
1895 struct kvm_segment ldtr
;
1897 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
1901 if (ldtr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
1911 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
1913 struct kvm_segment cs
, ss
;
1915 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
1916 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
1918 return ((cs
.selector
& SELECTOR_RPL_MASK
) ==
1919 (ss
.selector
& SELECTOR_RPL_MASK
));
1923 * Check if guest state is valid. Returns true if valid, false if
1925 * We assume that registers are always usable
1927 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
1929 /* real mode guest state checks */
1930 if (!(vcpu
->arch
.cr0
& X86_CR0_PE
)) {
1931 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
1933 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
1935 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
1937 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
1939 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
1941 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
1944 /* protected mode guest state checks */
1945 if (!cs_ss_rpl_check(vcpu
))
1947 if (!code_segment_valid(vcpu
))
1949 if (!stack_segment_valid(vcpu
))
1951 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
1953 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
1955 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
1957 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
1959 if (!tr_valid(vcpu
))
1961 if (!ldtr_valid(vcpu
))
1965 * - Add checks on RIP
1966 * - Add checks on RFLAGS
1972 static int init_rmode_tss(struct kvm
*kvm
)
1974 gfn_t fn
= rmode_tss_base(kvm
) >> PAGE_SHIFT
;
1979 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
1982 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
1983 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
1984 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
1987 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
1990 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
1994 r
= kvm_write_guest_page(kvm
, fn
, &data
,
1995 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
2005 static int init_rmode_identity_map(struct kvm
*kvm
)
2008 pfn_t identity_map_pfn
;
2013 if (unlikely(!kvm
->arch
.ept_identity_pagetable
)) {
2014 printk(KERN_ERR
"EPT: identity-mapping pagetable "
2015 "haven't been allocated!\n");
2018 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
2021 identity_map_pfn
= VMX_EPT_IDENTITY_PAGETABLE_ADDR
>> PAGE_SHIFT
;
2022 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
2025 /* Set up identity-mapping pagetable for EPT in real mode */
2026 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
2027 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
2028 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
2029 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
2030 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
2034 kvm
->arch
.ept_identity_pagetable_done
= true;
2040 static void seg_setup(int seg
)
2042 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
2044 vmcs_write16(sf
->selector
, 0);
2045 vmcs_writel(sf
->base
, 0);
2046 vmcs_write32(sf
->limit
, 0xffff);
2047 vmcs_write32(sf
->ar_bytes
, 0xf3);
2050 static int alloc_apic_access_page(struct kvm
*kvm
)
2052 struct kvm_userspace_memory_region kvm_userspace_mem
;
2055 down_write(&kvm
->slots_lock
);
2056 if (kvm
->arch
.apic_access_page
)
2058 kvm_userspace_mem
.slot
= APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
;
2059 kvm_userspace_mem
.flags
= 0;
2060 kvm_userspace_mem
.guest_phys_addr
= 0xfee00000ULL
;
2061 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
2062 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
, 0);
2066 kvm
->arch
.apic_access_page
= gfn_to_page(kvm
, 0xfee00);
2068 up_write(&kvm
->slots_lock
);
2072 static int alloc_identity_pagetable(struct kvm
*kvm
)
2074 struct kvm_userspace_memory_region kvm_userspace_mem
;
2077 down_write(&kvm
->slots_lock
);
2078 if (kvm
->arch
.ept_identity_pagetable
)
2080 kvm_userspace_mem
.slot
= IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
;
2081 kvm_userspace_mem
.flags
= 0;
2082 kvm_userspace_mem
.guest_phys_addr
= VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
2083 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
2084 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
, 0);
2088 kvm
->arch
.ept_identity_pagetable
= gfn_to_page(kvm
,
2089 VMX_EPT_IDENTITY_PAGETABLE_ADDR
>> PAGE_SHIFT
);
2091 up_write(&kvm
->slots_lock
);
2095 static void allocate_vpid(struct vcpu_vmx
*vmx
)
2102 spin_lock(&vmx_vpid_lock
);
2103 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
2104 if (vpid
< VMX_NR_VPIDS
) {
2106 __set_bit(vpid
, vmx_vpid_bitmap
);
2108 spin_unlock(&vmx_vpid_lock
);
2111 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
, u32 msr
)
2113 int f
= sizeof(unsigned long);
2115 if (!cpu_has_vmx_msr_bitmap())
2119 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2120 * have the write-low and read-high bitmap offsets the wrong way round.
2121 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2123 if (msr
<= 0x1fff) {
2124 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
); /* read-low */
2125 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
); /* write-low */
2126 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
2128 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
); /* read-high */
2129 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
); /* write-high */
2133 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
2136 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
, msr
);
2137 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
, msr
);
2141 * Sets up the vmcs for emulated real mode.
2143 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
2145 u32 host_sysenter_cs
, msr_low
, msr_high
;
2147 u64 host_pat
, tsc_this
, tsc_base
;
2149 struct descriptor_table dt
;
2151 unsigned long kvm_vmx_return
;
2155 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
2156 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
2158 if (cpu_has_vmx_msr_bitmap())
2159 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
2161 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
2164 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
,
2165 vmcs_config
.pin_based_exec_ctrl
);
2167 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
2168 if (!vm_need_tpr_shadow(vmx
->vcpu
.kvm
)) {
2169 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
2170 #ifdef CONFIG_X86_64
2171 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
2172 CPU_BASED_CR8_LOAD_EXITING
;
2176 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
2177 CPU_BASED_CR3_LOAD_EXITING
|
2178 CPU_BASED_INVLPG_EXITING
;
2179 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
2181 if (cpu_has_secondary_exec_ctrls()) {
2182 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
2183 if (!vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
2185 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
2187 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
2189 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
2190 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
2193 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, !!bypass_guest_pf
);
2194 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, !!bypass_guest_pf
);
2195 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
2197 vmcs_writel(HOST_CR0
, read_cr0()); /* 22.2.3 */
2198 vmcs_writel(HOST_CR4
, read_cr4()); /* 22.2.3, 22.2.5 */
2199 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2201 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
2202 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
2203 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
2204 vmcs_write16(HOST_FS_SELECTOR
, kvm_read_fs()); /* 22.2.4 */
2205 vmcs_write16(HOST_GS_SELECTOR
, kvm_read_gs()); /* 22.2.4 */
2206 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
2207 #ifdef CONFIG_X86_64
2208 rdmsrl(MSR_FS_BASE
, a
);
2209 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
2210 rdmsrl(MSR_GS_BASE
, a
);
2211 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
2213 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
2214 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
2217 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
2220 vmcs_writel(HOST_IDTR_BASE
, dt
.base
); /* 22.2.4 */
2222 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return
));
2223 vmcs_writel(HOST_RIP
, kvm_vmx_return
); /* 22.2.5 */
2224 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
2225 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
2226 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
2228 rdmsr(MSR_IA32_SYSENTER_CS
, host_sysenter_cs
, junk
);
2229 vmcs_write32(HOST_IA32_SYSENTER_CS
, host_sysenter_cs
);
2230 rdmsrl(MSR_IA32_SYSENTER_ESP
, a
);
2231 vmcs_writel(HOST_IA32_SYSENTER_ESP
, a
); /* 22.2.3 */
2232 rdmsrl(MSR_IA32_SYSENTER_EIP
, a
);
2233 vmcs_writel(HOST_IA32_SYSENTER_EIP
, a
); /* 22.2.3 */
2235 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
2236 rdmsr(MSR_IA32_CR_PAT
, msr_low
, msr_high
);
2237 host_pat
= msr_low
| ((u64
) msr_high
<< 32);
2238 vmcs_write64(HOST_IA32_PAT
, host_pat
);
2240 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
2241 rdmsr(MSR_IA32_CR_PAT
, msr_low
, msr_high
);
2242 host_pat
= msr_low
| ((u64
) msr_high
<< 32);
2243 /* Write the default value follow host pat */
2244 vmcs_write64(GUEST_IA32_PAT
, host_pat
);
2245 /* Keep arch.pat sync with GUEST_IA32_PAT */
2246 vmx
->vcpu
.arch
.pat
= host_pat
;
2249 for (i
= 0; i
< NR_VMX_MSR
; ++i
) {
2250 u32 index
= vmx_msr_index
[i
];
2251 u32 data_low
, data_high
;
2255 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
2257 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
2259 data
= data_low
| ((u64
)data_high
<< 32);
2260 vmx
->host_msrs
[j
].index
= index
;
2261 vmx
->host_msrs
[j
].reserved
= 0;
2262 vmx
->host_msrs
[j
].data
= data
;
2263 vmx
->guest_msrs
[j
] = vmx
->host_msrs
[j
];
2267 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
2269 /* 22.2.1, 20.8.1 */
2270 vmcs_write32(VM_ENTRY_CONTROLS
, vmcs_config
.vmentry_ctrl
);
2272 vmcs_writel(CR0_GUEST_HOST_MASK
, ~0UL);
2273 vmcs_writel(CR4_GUEST_HOST_MASK
, KVM_GUEST_CR4_MASK
);
2275 tsc_base
= vmx
->vcpu
.kvm
->arch
.vm_init_tsc
;
2277 if (tsc_this
< vmx
->vcpu
.kvm
->arch
.vm_init_tsc
)
2278 tsc_base
= tsc_this
;
2280 guest_write_tsc(0, tsc_base
);
2285 static int init_rmode(struct kvm
*kvm
)
2287 if (!init_rmode_tss(kvm
))
2289 if (!init_rmode_identity_map(kvm
))
2294 static int vmx_vcpu_reset(struct kvm_vcpu
*vcpu
)
2296 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2300 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
));
2301 down_read(&vcpu
->kvm
->slots_lock
);
2302 if (!init_rmode(vmx
->vcpu
.kvm
)) {
2307 vmx
->vcpu
.arch
.rmode
.active
= 0;
2309 vmx
->soft_vnmi_blocked
= 0;
2311 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
2312 kvm_set_cr8(&vmx
->vcpu
, 0);
2313 msr
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
2314 if (vmx
->vcpu
.vcpu_id
== 0)
2315 msr
|= MSR_IA32_APICBASE_BSP
;
2316 kvm_set_apic_base(&vmx
->vcpu
, msr
);
2318 fx_init(&vmx
->vcpu
);
2320 seg_setup(VCPU_SREG_CS
);
2322 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2323 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2325 if (vmx
->vcpu
.vcpu_id
== 0) {
2326 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
2327 vmcs_writel(GUEST_CS_BASE
, 0x000f0000);
2329 vmcs_write16(GUEST_CS_SELECTOR
, vmx
->vcpu
.arch
.sipi_vector
<< 8);
2330 vmcs_writel(GUEST_CS_BASE
, vmx
->vcpu
.arch
.sipi_vector
<< 12);
2333 seg_setup(VCPU_SREG_DS
);
2334 seg_setup(VCPU_SREG_ES
);
2335 seg_setup(VCPU_SREG_FS
);
2336 seg_setup(VCPU_SREG_GS
);
2337 seg_setup(VCPU_SREG_SS
);
2339 vmcs_write16(GUEST_TR_SELECTOR
, 0);
2340 vmcs_writel(GUEST_TR_BASE
, 0);
2341 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
2342 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
2344 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
2345 vmcs_writel(GUEST_LDTR_BASE
, 0);
2346 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
2347 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
2349 vmcs_write32(GUEST_SYSENTER_CS
, 0);
2350 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
2351 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
2353 vmcs_writel(GUEST_RFLAGS
, 0x02);
2354 if (vmx
->vcpu
.vcpu_id
== 0)
2355 kvm_rip_write(vcpu
, 0xfff0);
2357 kvm_rip_write(vcpu
, 0);
2358 kvm_register_write(vcpu
, VCPU_REGS_RSP
, 0);
2360 vmcs_writel(GUEST_DR7
, 0x400);
2362 vmcs_writel(GUEST_GDTR_BASE
, 0);
2363 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
2365 vmcs_writel(GUEST_IDTR_BASE
, 0);
2366 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
2368 vmcs_write32(GUEST_ACTIVITY_STATE
, 0);
2369 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
2370 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
2372 /* Special registers */
2373 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
2377 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
2379 if (cpu_has_vmx_tpr_shadow()) {
2380 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
2381 if (vm_need_tpr_shadow(vmx
->vcpu
.kvm
))
2382 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
2383 page_to_phys(vmx
->vcpu
.arch
.apic
->regs_page
));
2384 vmcs_write32(TPR_THRESHOLD
, 0);
2387 if (vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
2388 vmcs_write64(APIC_ACCESS_ADDR
,
2389 page_to_phys(vmx
->vcpu
.kvm
->arch
.apic_access_page
));
2392 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
2394 vmx
->vcpu
.arch
.cr0
= 0x60000010;
2395 vmx_set_cr0(&vmx
->vcpu
, vmx
->vcpu
.arch
.cr0
); /* enter rmode */
2396 vmx_set_cr4(&vmx
->vcpu
, 0);
2397 vmx_set_efer(&vmx
->vcpu
, 0);
2398 vmx_fpu_activate(&vmx
->vcpu
);
2399 update_exception_bitmap(&vmx
->vcpu
);
2401 vpid_sync_vcpu_all(vmx
);
2405 /* HACK: Don't enable emulation on guest boot/reset */
2406 vmx
->emulation_required
= 0;
2409 up_read(&vcpu
->kvm
->slots_lock
);
2413 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
2415 u32 cpu_based_vm_exec_control
;
2417 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
2418 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
2419 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
2422 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
2424 u32 cpu_based_vm_exec_control
;
2426 if (!cpu_has_virtual_nmis()) {
2427 enable_irq_window(vcpu
);
2431 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
2432 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_NMI_PENDING
;
2433 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
2436 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
, int irq
)
2438 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2440 KVMTRACE_1D(INJ_VIRQ
, vcpu
, (u32
)irq
, handler
);
2442 ++vcpu
->stat
.irq_injections
;
2443 if (vcpu
->arch
.rmode
.active
) {
2444 vmx
->rmode
.irq
.pending
= true;
2445 vmx
->rmode
.irq
.vector
= irq
;
2446 vmx
->rmode
.irq
.rip
= kvm_rip_read(vcpu
);
2447 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
2448 irq
| INTR_TYPE_SOFT_INTR
| INTR_INFO_VALID_MASK
);
2449 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
, 1);
2450 kvm_rip_write(vcpu
, vmx
->rmode
.irq
.rip
- 1);
2453 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
2454 irq
| INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
2457 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
2459 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2461 if (!cpu_has_virtual_nmis()) {
2463 * Tracking the NMI-blocked state in software is built upon
2464 * finding the next open IRQ window. This, in turn, depends on
2465 * well-behaving guests: They have to keep IRQs disabled at
2466 * least as long as the NMI handler runs. Otherwise we may
2467 * cause NMI nesting, maybe breaking the guest. But as this is
2468 * highly unlikely, we can live with the residual risk.
2470 vmx
->soft_vnmi_blocked
= 1;
2471 vmx
->vnmi_blocked_time
= 0;
2474 ++vcpu
->stat
.nmi_injections
;
2475 if (vcpu
->arch
.rmode
.active
) {
2476 vmx
->rmode
.irq
.pending
= true;
2477 vmx
->rmode
.irq
.vector
= NMI_VECTOR
;
2478 vmx
->rmode
.irq
.rip
= kvm_rip_read(vcpu
);
2479 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
2480 NMI_VECTOR
| INTR_TYPE_SOFT_INTR
|
2481 INTR_INFO_VALID_MASK
);
2482 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
, 1);
2483 kvm_rip_write(vcpu
, vmx
->rmode
.irq
.rip
- 1);
2486 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
2487 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
2490 static void vmx_update_window_states(struct kvm_vcpu
*vcpu
)
2492 u32 guest_intr
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2494 vcpu
->arch
.nmi_window_open
=
2495 !(guest_intr
& (GUEST_INTR_STATE_STI
|
2496 GUEST_INTR_STATE_MOV_SS
|
2497 GUEST_INTR_STATE_NMI
));
2498 if (!cpu_has_virtual_nmis() && to_vmx(vcpu
)->soft_vnmi_blocked
)
2499 vcpu
->arch
.nmi_window_open
= 0;
2501 vcpu
->arch
.interrupt_window_open
=
2502 ((vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
2503 !(guest_intr
& (GUEST_INTR_STATE_STI
|
2504 GUEST_INTR_STATE_MOV_SS
)));
2507 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
2509 vmx_update_window_states(vcpu
);
2510 return vcpu
->arch
.interrupt_window_open
;
2513 static void do_interrupt_requests(struct kvm_vcpu
*vcpu
,
2514 struct kvm_run
*kvm_run
)
2516 vmx_update_window_states(vcpu
);
2518 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
2519 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
2520 GUEST_INTR_STATE_STI
|
2521 GUEST_INTR_STATE_MOV_SS
);
2523 if (vcpu
->arch
.nmi_pending
&& !vcpu
->arch
.nmi_injected
) {
2524 if (vcpu
->arch
.interrupt
.pending
) {
2525 enable_nmi_window(vcpu
);
2526 } else if (vcpu
->arch
.nmi_window_open
) {
2527 vcpu
->arch
.nmi_pending
= false;
2528 vcpu
->arch
.nmi_injected
= true;
2530 enable_nmi_window(vcpu
);
2534 if (vcpu
->arch
.nmi_injected
) {
2535 vmx_inject_nmi(vcpu
);
2536 if (vcpu
->arch
.nmi_pending
)
2537 enable_nmi_window(vcpu
);
2538 else if (vcpu
->arch
.irq_summary
2539 || kvm_run
->request_interrupt_window
)
2540 enable_irq_window(vcpu
);
2544 if (vcpu
->arch
.interrupt_window_open
) {
2545 if (vcpu
->arch
.irq_summary
&& !vcpu
->arch
.interrupt
.pending
)
2546 kvm_queue_interrupt(vcpu
, kvm_pop_irq(vcpu
));
2548 if (vcpu
->arch
.interrupt
.pending
)
2549 vmx_inject_irq(vcpu
, vcpu
->arch
.interrupt
.nr
);
2551 if (!vcpu
->arch
.interrupt_window_open
&&
2552 (vcpu
->arch
.irq_summary
|| kvm_run
->request_interrupt_window
))
2553 enable_irq_window(vcpu
);
2556 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
2559 struct kvm_userspace_memory_region tss_mem
= {
2560 .slot
= TSS_PRIVATE_MEMSLOT
,
2561 .guest_phys_addr
= addr
,
2562 .memory_size
= PAGE_SIZE
* 3,
2566 ret
= kvm_set_memory_region(kvm
, &tss_mem
, 0);
2569 kvm
->arch
.tss_addr
= addr
;
2573 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
2574 int vec
, u32 err_code
)
2577 * Instruction with address size override prefix opcode 0x67
2578 * Cause the #SS fault with 0 error code in VM86 mode.
2580 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0)
2581 if (emulate_instruction(vcpu
, NULL
, 0, 0, 0) == EMULATE_DONE
)
2584 * Forward all other exceptions that are valid in real mode.
2585 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2586 * the required debugging infrastructure rework.
2590 if (vcpu
->guest_debug
&
2591 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
2593 kvm_queue_exception(vcpu
, vec
);
2596 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
2607 kvm_queue_exception(vcpu
, vec
);
2613 static int handle_exception(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2615 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2616 u32 intr_info
, ex_no
, error_code
;
2617 unsigned long cr2
, rip
, dr6
;
2619 enum emulation_result er
;
2621 vect_info
= vmx
->idt_vectoring_info
;
2622 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
2624 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
2625 !is_page_fault(intr_info
))
2626 printk(KERN_ERR
"%s: unexpected, vectoring info 0x%x "
2627 "intr info 0x%x\n", __func__
, vect_info
, intr_info
);
2629 if (!irqchip_in_kernel(vcpu
->kvm
) && is_external_interrupt(vect_info
)) {
2630 int irq
= vect_info
& VECTORING_INFO_VECTOR_MASK
;
2631 kvm_push_irq(vcpu
, irq
);
2634 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
)
2635 return 1; /* already handled by vmx_vcpu_run() */
2637 if (is_no_device(intr_info
)) {
2638 vmx_fpu_activate(vcpu
);
2642 if (is_invalid_opcode(intr_info
)) {
2643 er
= emulate_instruction(vcpu
, kvm_run
, 0, 0, EMULTYPE_TRAP_UD
);
2644 if (er
!= EMULATE_DONE
)
2645 kvm_queue_exception(vcpu
, UD_VECTOR
);
2650 rip
= kvm_rip_read(vcpu
);
2651 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
2652 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
2653 if (is_page_fault(intr_info
)) {
2654 /* EPT won't cause page fault directly */
2657 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
2658 KVMTRACE_3D(PAGE_FAULT
, vcpu
, error_code
, (u32
)cr2
,
2659 (u32
)((u64
)cr2
>> 32), handler
);
2660 if (vcpu
->arch
.interrupt
.pending
|| vcpu
->arch
.exception
.pending
)
2661 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
2662 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
);
2665 if (vcpu
->arch
.rmode
.active
&&
2666 handle_rmode_exception(vcpu
, intr_info
& INTR_INFO_VECTOR_MASK
,
2668 if (vcpu
->arch
.halt_request
) {
2669 vcpu
->arch
.halt_request
= 0;
2670 return kvm_emulate_halt(vcpu
);
2675 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
2678 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
2679 if (!(vcpu
->guest_debug
&
2680 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
2681 vcpu
->arch
.dr6
= dr6
| DR6_FIXED_1
;
2682 kvm_queue_exception(vcpu
, DB_VECTOR
);
2685 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
2686 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
2689 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
2690 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
2691 kvm_run
->debug
.arch
.exception
= ex_no
;
2694 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
2695 kvm_run
->ex
.exception
= ex_no
;
2696 kvm_run
->ex
.error_code
= error_code
;
2702 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
,
2703 struct kvm_run
*kvm_run
)
2705 ++vcpu
->stat
.irq_exits
;
2706 KVMTRACE_1D(INTR
, vcpu
, vmcs_read32(VM_EXIT_INTR_INFO
), handler
);
2710 static int handle_triple_fault(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2712 kvm_run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
2716 static int handle_io(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2718 unsigned long exit_qualification
;
2719 int size
, in
, string
;
2722 ++vcpu
->stat
.io_exits
;
2723 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
2724 string
= (exit_qualification
& 16) != 0;
2727 if (emulate_instruction(vcpu
,
2728 kvm_run
, 0, 0, 0) == EMULATE_DO_MMIO
)
2733 size
= (exit_qualification
& 7) + 1;
2734 in
= (exit_qualification
& 8) != 0;
2735 port
= exit_qualification
>> 16;
2737 skip_emulated_instruction(vcpu
);
2738 return kvm_emulate_pio(vcpu
, kvm_run
, in
, size
, port
);
2742 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
2745 * Patch in the VMCALL instruction:
2747 hypercall
[0] = 0x0f;
2748 hypercall
[1] = 0x01;
2749 hypercall
[2] = 0xc1;
2752 static int handle_cr(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2754 unsigned long exit_qualification
;
2758 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
2759 cr
= exit_qualification
& 15;
2760 reg
= (exit_qualification
>> 8) & 15;
2761 switch ((exit_qualification
>> 4) & 3) {
2762 case 0: /* mov to cr */
2763 KVMTRACE_3D(CR_WRITE
, vcpu
, (u32
)cr
,
2764 (u32
)kvm_register_read(vcpu
, reg
),
2765 (u32
)((u64
)kvm_register_read(vcpu
, reg
) >> 32),
2769 kvm_set_cr0(vcpu
, kvm_register_read(vcpu
, reg
));
2770 skip_emulated_instruction(vcpu
);
2773 kvm_set_cr3(vcpu
, kvm_register_read(vcpu
, reg
));
2774 skip_emulated_instruction(vcpu
);
2777 kvm_set_cr4(vcpu
, kvm_register_read(vcpu
, reg
));
2778 skip_emulated_instruction(vcpu
);
2781 kvm_set_cr8(vcpu
, kvm_register_read(vcpu
, reg
));
2782 skip_emulated_instruction(vcpu
);
2783 if (irqchip_in_kernel(vcpu
->kvm
))
2785 kvm_run
->exit_reason
= KVM_EXIT_SET_TPR
;
2790 vmx_fpu_deactivate(vcpu
);
2791 vcpu
->arch
.cr0
&= ~X86_CR0_TS
;
2792 vmcs_writel(CR0_READ_SHADOW
, vcpu
->arch
.cr0
);
2793 vmx_fpu_activate(vcpu
);
2794 KVMTRACE_0D(CLTS
, vcpu
, handler
);
2795 skip_emulated_instruction(vcpu
);
2797 case 1: /*mov from cr*/
2800 kvm_register_write(vcpu
, reg
, vcpu
->arch
.cr3
);
2801 KVMTRACE_3D(CR_READ
, vcpu
, (u32
)cr
,
2802 (u32
)kvm_register_read(vcpu
, reg
),
2803 (u32
)((u64
)kvm_register_read(vcpu
, reg
) >> 32),
2805 skip_emulated_instruction(vcpu
);
2808 kvm_register_write(vcpu
, reg
, kvm_get_cr8(vcpu
));
2809 KVMTRACE_2D(CR_READ
, vcpu
, (u32
)cr
,
2810 (u32
)kvm_register_read(vcpu
, reg
), handler
);
2811 skip_emulated_instruction(vcpu
);
2816 kvm_lmsw(vcpu
, (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f);
2818 skip_emulated_instruction(vcpu
);
2823 kvm_run
->exit_reason
= 0;
2824 pr_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
2825 (int)(exit_qualification
>> 4) & 3, cr
);
2829 static int handle_dr(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2831 unsigned long exit_qualification
;
2835 dr
= vmcs_readl(GUEST_DR7
);
2838 * As the vm-exit takes precedence over the debug trap, we
2839 * need to emulate the latter, either for the host or the
2840 * guest debugging itself.
2842 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
2843 kvm_run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
2844 kvm_run
->debug
.arch
.dr7
= dr
;
2845 kvm_run
->debug
.arch
.pc
=
2846 vmcs_readl(GUEST_CS_BASE
) +
2847 vmcs_readl(GUEST_RIP
);
2848 kvm_run
->debug
.arch
.exception
= DB_VECTOR
;
2849 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
2852 vcpu
->arch
.dr7
&= ~DR7_GD
;
2853 vcpu
->arch
.dr6
|= DR6_BD
;
2854 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
2855 kvm_queue_exception(vcpu
, DB_VECTOR
);
2860 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
2861 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
2862 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
2863 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
2866 val
= vcpu
->arch
.db
[dr
];
2869 val
= vcpu
->arch
.dr6
;
2872 val
= vcpu
->arch
.dr7
;
2877 kvm_register_write(vcpu
, reg
, val
);
2878 KVMTRACE_2D(DR_READ
, vcpu
, (u32
)dr
, (u32
)val
, handler
);
2880 val
= vcpu
->arch
.regs
[reg
];
2883 vcpu
->arch
.db
[dr
] = val
;
2884 if (!(vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
))
2885 vcpu
->arch
.eff_db
[dr
] = val
;
2888 if (vcpu
->arch
.cr4
& X86_CR4_DE
)
2889 kvm_queue_exception(vcpu
, UD_VECTOR
);
2892 if (val
& 0xffffffff00000000ULL
) {
2893 kvm_queue_exception(vcpu
, GP_VECTOR
);
2896 vcpu
->arch
.dr6
= (val
& DR6_VOLATILE
) | DR6_FIXED_1
;
2899 if (val
& 0xffffffff00000000ULL
) {
2900 kvm_queue_exception(vcpu
, GP_VECTOR
);
2903 vcpu
->arch
.dr7
= (val
& DR7_VOLATILE
) | DR7_FIXED_1
;
2904 if (!(vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)) {
2905 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
2906 vcpu
->arch
.switch_db_regs
=
2907 (val
& DR7_BP_EN_MASK
);
2911 KVMTRACE_2D(DR_WRITE
, vcpu
, (u32
)dr
, (u32
)val
, handler
);
2913 skip_emulated_instruction(vcpu
);
2917 static int handle_cpuid(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2919 kvm_emulate_cpuid(vcpu
);
2923 static int handle_rdmsr(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2925 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
2928 if (vmx_get_msr(vcpu
, ecx
, &data
)) {
2929 kvm_inject_gp(vcpu
, 0);
2933 KVMTRACE_3D(MSR_READ
, vcpu
, ecx
, (u32
)data
, (u32
)(data
>> 32),
2936 /* FIXME: handling of bits 32:63 of rax, rdx */
2937 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = data
& -1u;
2938 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (data
>> 32) & -1u;
2939 skip_emulated_instruction(vcpu
);
2943 static int handle_wrmsr(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2945 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
2946 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
2947 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
2949 KVMTRACE_3D(MSR_WRITE
, vcpu
, ecx
, (u32
)data
, (u32
)(data
>> 32),
2952 if (vmx_set_msr(vcpu
, ecx
, data
) != 0) {
2953 kvm_inject_gp(vcpu
, 0);
2957 skip_emulated_instruction(vcpu
);
2961 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
,
2962 struct kvm_run
*kvm_run
)
2967 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
,
2968 struct kvm_run
*kvm_run
)
2970 u32 cpu_based_vm_exec_control
;
2972 /* clear pending irq */
2973 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
2974 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
2975 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
2977 KVMTRACE_0D(PEND_INTR
, vcpu
, handler
);
2978 ++vcpu
->stat
.irq_window_exits
;
2981 * If the user space waits to inject interrupts, exit as soon as
2984 if (kvm_run
->request_interrupt_window
&&
2985 !vcpu
->arch
.irq_summary
) {
2986 kvm_run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
2992 static int handle_halt(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2994 skip_emulated_instruction(vcpu
);
2995 return kvm_emulate_halt(vcpu
);
2998 static int handle_vmcall(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
3000 skip_emulated_instruction(vcpu
);
3001 kvm_emulate_hypercall(vcpu
);
3005 static int handle_invlpg(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
3007 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3009 kvm_mmu_invlpg(vcpu
, exit_qualification
);
3010 skip_emulated_instruction(vcpu
);
3014 static int handle_wbinvd(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
3016 skip_emulated_instruction(vcpu
);
3017 /* TODO: Add support for VT-d/pass-through device */
3021 static int handle_apic_access(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
3023 unsigned long exit_qualification
;
3024 enum emulation_result er
;
3025 unsigned long offset
;
3027 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3028 offset
= exit_qualification
& 0xffful
;
3030 er
= emulate_instruction(vcpu
, kvm_run
, 0, 0, 0);
3032 if (er
!= EMULATE_DONE
) {
3034 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3041 static int handle_task_switch(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
3043 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3044 unsigned long exit_qualification
;
3048 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3050 reason
= (u32
)exit_qualification
>> 30;
3051 if (reason
== TASK_SWITCH_GATE
&& vmx
->vcpu
.arch
.nmi_injected
&&
3052 (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
3053 (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
)
3054 == INTR_TYPE_NMI_INTR
) {
3055 vcpu
->arch
.nmi_injected
= false;
3056 if (cpu_has_virtual_nmis())
3057 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
3058 GUEST_INTR_STATE_NMI
);
3060 tss_selector
= exit_qualification
;
3062 if (!kvm_task_switch(vcpu
, tss_selector
, reason
))
3065 /* clear all local breakpoint enable flags */
3066 vmcs_writel(GUEST_DR7
, vmcs_readl(GUEST_DR7
) & ~55);
3069 * TODO: What about debug traps on tss switch?
3070 * Are we supposed to inject them and update dr6?
3076 static int handle_ept_violation(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
3078 unsigned long exit_qualification
;
3082 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3084 if (exit_qualification
& (1 << 6)) {
3085 printk(KERN_ERR
"EPT: GPA exceeds GAW!\n");
3089 gla_validity
= (exit_qualification
>> 7) & 0x3;
3090 if (gla_validity
!= 0x3 && gla_validity
!= 0x1 && gla_validity
!= 0) {
3091 printk(KERN_ERR
"EPT: Handling EPT violation failed!\n");
3092 printk(KERN_ERR
"EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3093 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS
),
3094 vmcs_readl(GUEST_LINEAR_ADDRESS
));
3095 printk(KERN_ERR
"EPT: Exit qualification is 0x%lx\n",
3096 (long unsigned int)exit_qualification
);
3097 kvm_run
->exit_reason
= KVM_EXIT_UNKNOWN
;
3098 kvm_run
->hw
.hardware_exit_reason
= 0;
3102 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
3103 return kvm_mmu_page_fault(vcpu
, gpa
& PAGE_MASK
, 0);
3106 static int handle_nmi_window(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
3108 u32 cpu_based_vm_exec_control
;
3110 /* clear pending NMI */
3111 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
3112 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
3113 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
3114 ++vcpu
->stat
.nmi_window_exits
;
3119 static void handle_invalid_guest_state(struct kvm_vcpu
*vcpu
,
3120 struct kvm_run
*kvm_run
)
3122 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3123 enum emulation_result err
= EMULATE_DONE
;
3128 while (!guest_state_valid(vcpu
)) {
3129 err
= emulate_instruction(vcpu
, kvm_run
, 0, 0, 0);
3131 if (err
== EMULATE_DO_MMIO
)
3134 if (err
!= EMULATE_DONE
) {
3135 kvm_report_emulation_failure(vcpu
, "emulation failure");
3139 if (signal_pending(current
))
3145 local_irq_disable();
3148 vmx
->invalid_state_emulation_result
= err
;
3152 * The exit handlers return 1 if the exit was handled fully and guest execution
3153 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3154 * to be done to userspace and return 0.
3156 static int (*kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
,
3157 struct kvm_run
*kvm_run
) = {
3158 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
3159 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
3160 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
3161 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
3162 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
3163 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
3164 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
3165 [EXIT_REASON_CPUID
] = handle_cpuid
,
3166 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
3167 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
3168 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
3169 [EXIT_REASON_HLT
] = handle_halt
,
3170 [EXIT_REASON_INVLPG
] = handle_invlpg
,
3171 [EXIT_REASON_VMCALL
] = handle_vmcall
,
3172 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
3173 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
3174 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
3175 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
3176 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
3179 static const int kvm_vmx_max_exit_handlers
=
3180 ARRAY_SIZE(kvm_vmx_exit_handlers
);
3183 * The guest has exited. See if we can fix it or if we need userspace
3186 static int vmx_handle_exit(struct kvm_run
*kvm_run
, struct kvm_vcpu
*vcpu
)
3188 u32 exit_reason
= vmcs_read32(VM_EXIT_REASON
);
3189 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3190 u32 vectoring_info
= vmx
->idt_vectoring_info
;
3192 KVMTRACE_3D(VMEXIT
, vcpu
, exit_reason
, (u32
)kvm_rip_read(vcpu
),
3193 (u32
)((u64
)kvm_rip_read(vcpu
) >> 32), entryexit
);
3195 /* If we need to emulate an MMIO from handle_invalid_guest_state
3196 * we just return 0 */
3197 if (vmx
->emulation_required
&& emulate_invalid_guest_state
) {
3198 if (guest_state_valid(vcpu
))
3199 vmx
->emulation_required
= 0;
3200 return vmx
->invalid_state_emulation_result
!= EMULATE_DO_MMIO
;
3203 /* Access CR3 don't cause VMExit in paging mode, so we need
3204 * to sync with guest real CR3. */
3205 if (enable_ept
&& is_paging(vcpu
)) {
3206 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
3207 ept_load_pdptrs(vcpu
);
3210 if (unlikely(vmx
->fail
)) {
3211 kvm_run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
3212 kvm_run
->fail_entry
.hardware_entry_failure_reason
3213 = vmcs_read32(VM_INSTRUCTION_ERROR
);
3217 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
3218 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
3219 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
3220 exit_reason
!= EXIT_REASON_TASK_SWITCH
))
3221 printk(KERN_WARNING
"%s: unexpected, valid vectoring info "
3222 "(0x%x) and exit reason is 0x%x\n",
3223 __func__
, vectoring_info
, exit_reason
);
3225 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
)) {
3226 if (vcpu
->arch
.interrupt_window_open
) {
3227 vmx
->soft_vnmi_blocked
= 0;
3228 vcpu
->arch
.nmi_window_open
= 1;
3229 } else if (vmx
->vnmi_blocked_time
> 1000000000LL &&
3230 vcpu
->arch
.nmi_pending
) {
3232 * This CPU don't support us in finding the end of an
3233 * NMI-blocked window if the guest runs with IRQs
3234 * disabled. So we pull the trigger after 1 s of
3235 * futile waiting, but inform the user about this.
3237 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
3238 "state on VCPU %d after 1 s timeout\n",
3239 __func__
, vcpu
->vcpu_id
);
3240 vmx
->soft_vnmi_blocked
= 0;
3241 vmx
->vcpu
.arch
.nmi_window_open
= 1;
3245 if (exit_reason
< kvm_vmx_max_exit_handlers
3246 && kvm_vmx_exit_handlers
[exit_reason
])
3247 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
, kvm_run
);
3249 kvm_run
->exit_reason
= KVM_EXIT_UNKNOWN
;
3250 kvm_run
->hw
.hardware_exit_reason
= exit_reason
;
3255 static void update_tpr_threshold(struct kvm_vcpu
*vcpu
)
3259 if (!vm_need_tpr_shadow(vcpu
->kvm
))
3262 if (!kvm_lapic_enabled(vcpu
) ||
3263 ((max_irr
= kvm_lapic_find_highest_irr(vcpu
)) == -1)) {
3264 vmcs_write32(TPR_THRESHOLD
, 0);
3268 tpr
= (kvm_lapic_get_cr8(vcpu
) & 0x0f) << 4;
3269 vmcs_write32(TPR_THRESHOLD
, (max_irr
> tpr
) ? tpr
>> 4 : max_irr
>> 4);
3272 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
3275 u32 idt_vectoring_info
;
3279 bool idtv_info_valid
;
3282 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
3283 if (cpu_has_virtual_nmis()) {
3284 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
3285 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
3288 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3289 * a guest IRET fault.
3291 if (unblock_nmi
&& vector
!= DF_VECTOR
)
3292 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
3293 GUEST_INTR_STATE_NMI
);
3294 } else if (unlikely(vmx
->soft_vnmi_blocked
))
3295 vmx
->vnmi_blocked_time
+=
3296 ktime_to_ns(ktime_sub(ktime_get(), vmx
->entry_time
));
3298 idt_vectoring_info
= vmx
->idt_vectoring_info
;
3299 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
3300 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
3301 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
3302 if (vmx
->vcpu
.arch
.nmi_injected
) {
3305 * Clear bit "block by NMI" before VM entry if a NMI delivery
3308 if (idtv_info_valid
&& type
== INTR_TYPE_NMI_INTR
)
3309 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
3310 GUEST_INTR_STATE_NMI
);
3312 vmx
->vcpu
.arch
.nmi_injected
= false;
3314 kvm_clear_exception_queue(&vmx
->vcpu
);
3315 if (idtv_info_valid
&& (type
== INTR_TYPE_HARD_EXCEPTION
||
3316 type
== INTR_TYPE_SOFT_EXCEPTION
)) {
3317 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
3318 error
= vmcs_read32(IDT_VECTORING_ERROR_CODE
);
3319 kvm_queue_exception_e(&vmx
->vcpu
, vector
, error
);
3321 kvm_queue_exception(&vmx
->vcpu
, vector
);
3322 vmx
->idt_vectoring_info
= 0;
3324 kvm_clear_interrupt_queue(&vmx
->vcpu
);
3325 if (idtv_info_valid
&& type
== INTR_TYPE_EXT_INTR
) {
3326 kvm_queue_interrupt(&vmx
->vcpu
, vector
);
3327 vmx
->idt_vectoring_info
= 0;
3331 static void vmx_intr_assist(struct kvm_vcpu
*vcpu
)
3333 update_tpr_threshold(vcpu
);
3335 vmx_update_window_states(vcpu
);
3337 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
3338 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
3339 GUEST_INTR_STATE_STI
|
3340 GUEST_INTR_STATE_MOV_SS
);
3342 if (vcpu
->arch
.nmi_pending
&& !vcpu
->arch
.nmi_injected
) {
3343 if (vcpu
->arch
.interrupt
.pending
) {
3344 enable_nmi_window(vcpu
);
3345 } else if (vcpu
->arch
.nmi_window_open
) {
3346 vcpu
->arch
.nmi_pending
= false;
3347 vcpu
->arch
.nmi_injected
= true;
3349 enable_nmi_window(vcpu
);
3353 if (vcpu
->arch
.nmi_injected
) {
3354 vmx_inject_nmi(vcpu
);
3355 if (vcpu
->arch
.nmi_pending
)
3356 enable_nmi_window(vcpu
);
3357 else if (kvm_cpu_has_interrupt(vcpu
))
3358 enable_irq_window(vcpu
);
3361 if (!vcpu
->arch
.interrupt
.pending
&& kvm_cpu_has_interrupt(vcpu
)) {
3362 if (vcpu
->arch
.interrupt_window_open
)
3363 kvm_queue_interrupt(vcpu
, kvm_cpu_get_interrupt(vcpu
));
3365 enable_irq_window(vcpu
);
3367 if (vcpu
->arch
.interrupt
.pending
) {
3368 vmx_inject_irq(vcpu
, vcpu
->arch
.interrupt
.nr
);
3369 if (kvm_cpu_has_interrupt(vcpu
))
3370 enable_irq_window(vcpu
);
3375 * Failure to inject an interrupt should give us the information
3376 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3377 * when fetching the interrupt redirection bitmap in the real-mode
3378 * tss, this doesn't happen. So we do it ourselves.
3380 static void fixup_rmode_irq(struct vcpu_vmx
*vmx
)
3382 vmx
->rmode
.irq
.pending
= 0;
3383 if (kvm_rip_read(&vmx
->vcpu
) + 1 != vmx
->rmode
.irq
.rip
)
3385 kvm_rip_write(&vmx
->vcpu
, vmx
->rmode
.irq
.rip
);
3386 if (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) {
3387 vmx
->idt_vectoring_info
&= ~VECTORING_INFO_TYPE_MASK
;
3388 vmx
->idt_vectoring_info
|= INTR_TYPE_EXT_INTR
;
3391 vmx
->idt_vectoring_info
=
3392 VECTORING_INFO_VALID_MASK
3393 | INTR_TYPE_EXT_INTR
3394 | vmx
->rmode
.irq
.vector
;
3397 #ifdef CONFIG_X86_64
3405 static void vmx_vcpu_run(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
3407 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3410 /* Record the guest's net vcpu time for enforced NMI injections. */
3411 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
))
3412 vmx
->entry_time
= ktime_get();
3414 /* Handle invalid guest state instead of entering VMX */
3415 if (vmx
->emulation_required
&& emulate_invalid_guest_state
) {
3416 handle_invalid_guest_state(vcpu
, kvm_run
);
3420 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
3421 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
3422 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
3423 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
3426 * Loading guest fpu may have cleared host cr0.ts
3428 vmcs_writel(HOST_CR0
, read_cr0());
3430 set_debugreg(vcpu
->arch
.dr6
, 6);
3433 /* Store host registers */
3434 "push %%"R
"dx; push %%"R
"bp;"
3436 "cmp %%"R
"sp, %c[host_rsp](%0) \n\t"
3438 "mov %%"R
"sp, %c[host_rsp](%0) \n\t"
3439 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
3441 /* Check if vmlaunch of vmresume is needed */
3442 "cmpl $0, %c[launched](%0) \n\t"
3443 /* Load guest registers. Don't clobber flags. */
3444 "mov %c[cr2](%0), %%"R
"ax \n\t"
3445 "mov %%"R
"ax, %%cr2 \n\t"
3446 "mov %c[rax](%0), %%"R
"ax \n\t"
3447 "mov %c[rbx](%0), %%"R
"bx \n\t"
3448 "mov %c[rdx](%0), %%"R
"dx \n\t"
3449 "mov %c[rsi](%0), %%"R
"si \n\t"
3450 "mov %c[rdi](%0), %%"R
"di \n\t"
3451 "mov %c[rbp](%0), %%"R
"bp \n\t"
3452 #ifdef CONFIG_X86_64
3453 "mov %c[r8](%0), %%r8 \n\t"
3454 "mov %c[r9](%0), %%r9 \n\t"
3455 "mov %c[r10](%0), %%r10 \n\t"
3456 "mov %c[r11](%0), %%r11 \n\t"
3457 "mov %c[r12](%0), %%r12 \n\t"
3458 "mov %c[r13](%0), %%r13 \n\t"
3459 "mov %c[r14](%0), %%r14 \n\t"
3460 "mov %c[r15](%0), %%r15 \n\t"
3462 "mov %c[rcx](%0), %%"R
"cx \n\t" /* kills %0 (ecx) */
3464 /* Enter guest mode */
3465 "jne .Llaunched \n\t"
3466 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
3467 "jmp .Lkvm_vmx_return \n\t"
3468 ".Llaunched: " __ex(ASM_VMX_VMRESUME
) "\n\t"
3469 ".Lkvm_vmx_return: "
3470 /* Save guest registers, load host registers, keep flags */
3471 "xchg %0, (%%"R
"sp) \n\t"
3472 "mov %%"R
"ax, %c[rax](%0) \n\t"
3473 "mov %%"R
"bx, %c[rbx](%0) \n\t"
3474 "push"Q
" (%%"R
"sp); pop"Q
" %c[rcx](%0) \n\t"
3475 "mov %%"R
"dx, %c[rdx](%0) \n\t"
3476 "mov %%"R
"si, %c[rsi](%0) \n\t"
3477 "mov %%"R
"di, %c[rdi](%0) \n\t"
3478 "mov %%"R
"bp, %c[rbp](%0) \n\t"
3479 #ifdef CONFIG_X86_64
3480 "mov %%r8, %c[r8](%0) \n\t"
3481 "mov %%r9, %c[r9](%0) \n\t"
3482 "mov %%r10, %c[r10](%0) \n\t"
3483 "mov %%r11, %c[r11](%0) \n\t"
3484 "mov %%r12, %c[r12](%0) \n\t"
3485 "mov %%r13, %c[r13](%0) \n\t"
3486 "mov %%r14, %c[r14](%0) \n\t"
3487 "mov %%r15, %c[r15](%0) \n\t"
3489 "mov %%cr2, %%"R
"ax \n\t"
3490 "mov %%"R
"ax, %c[cr2](%0) \n\t"
3492 "pop %%"R
"bp; pop %%"R
"bp; pop %%"R
"dx \n\t"
3493 "setbe %c[fail](%0) \n\t"
3494 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
3495 [launched
]"i"(offsetof(struct vcpu_vmx
, launched
)),
3496 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
3497 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
3498 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
3499 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
3500 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
3501 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
3502 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
3503 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
3504 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
3505 #ifdef CONFIG_X86_64
3506 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
3507 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
3508 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
3509 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
3510 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
3511 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
3512 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
3513 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
3515 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
))
3517 , R
"bx", R
"di", R
"si"
3518 #ifdef CONFIG_X86_64
3519 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3523 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
));
3524 vcpu
->arch
.regs_dirty
= 0;
3526 get_debugreg(vcpu
->arch
.dr6
, 6);
3528 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
3529 if (vmx
->rmode
.irq
.pending
)
3530 fixup_rmode_irq(vmx
);
3532 vmx_update_window_states(vcpu
);
3534 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS
));
3537 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
3539 /* We need to handle NMIs before interrupts are enabled */
3540 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
&&
3541 (intr_info
& INTR_INFO_VALID_MASK
)) {
3542 KVMTRACE_0D(NMI
, vcpu
, handler
);
3546 vmx_complete_interrupts(vmx
);
3552 static void vmx_free_vmcs(struct kvm_vcpu
*vcpu
)
3554 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3558 free_vmcs(vmx
->vmcs
);
3563 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
3565 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3567 spin_lock(&vmx_vpid_lock
);
3569 __clear_bit(vmx
->vpid
, vmx_vpid_bitmap
);
3570 spin_unlock(&vmx_vpid_lock
);
3571 vmx_free_vmcs(vcpu
);
3572 kfree(vmx
->host_msrs
);
3573 kfree(vmx
->guest_msrs
);
3574 kvm_vcpu_uninit(vcpu
);
3575 kmem_cache_free(kvm_vcpu_cache
, vmx
);
3578 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
3581 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
3585 return ERR_PTR(-ENOMEM
);
3589 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
3593 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
3594 if (!vmx
->guest_msrs
) {
3599 vmx
->host_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
3600 if (!vmx
->host_msrs
)
3601 goto free_guest_msrs
;
3603 vmx
->vmcs
= alloc_vmcs();
3607 vmcs_clear(vmx
->vmcs
);
3610 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
3611 err
= vmx_vcpu_setup(vmx
);
3612 vmx_vcpu_put(&vmx
->vcpu
);
3616 if (vm_need_virtualize_apic_accesses(kvm
))
3617 if (alloc_apic_access_page(kvm
) != 0)
3621 if (alloc_identity_pagetable(kvm
) != 0)
3627 free_vmcs(vmx
->vmcs
);
3629 kfree(vmx
->host_msrs
);
3631 kfree(vmx
->guest_msrs
);
3633 kvm_vcpu_uninit(&vmx
->vcpu
);
3635 kmem_cache_free(kvm_vcpu_cache
, vmx
);
3636 return ERR_PTR(err
);
3639 static void __init
vmx_check_processor_compat(void *rtn
)
3641 struct vmcs_config vmcs_conf
;
3644 if (setup_vmcs_config(&vmcs_conf
) < 0)
3646 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
3647 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
3648 smp_processor_id());
3653 static int get_ept_level(void)
3655 return VMX_EPT_DEFAULT_GAW
+ 1;
3658 static int vmx_get_mt_mask_shift(void)
3660 return VMX_EPT_MT_EPTE_SHIFT
;
3663 static struct kvm_x86_ops vmx_x86_ops
= {
3664 .cpu_has_kvm_support
= cpu_has_kvm_support
,
3665 .disabled_by_bios
= vmx_disabled_by_bios
,
3666 .hardware_setup
= hardware_setup
,
3667 .hardware_unsetup
= hardware_unsetup
,
3668 .check_processor_compatibility
= vmx_check_processor_compat
,
3669 .hardware_enable
= hardware_enable
,
3670 .hardware_disable
= hardware_disable
,
3671 .cpu_has_accelerated_tpr
= report_flexpriority
,
3673 .vcpu_create
= vmx_create_vcpu
,
3674 .vcpu_free
= vmx_free_vcpu
,
3675 .vcpu_reset
= vmx_vcpu_reset
,
3677 .prepare_guest_switch
= vmx_save_host_state
,
3678 .vcpu_load
= vmx_vcpu_load
,
3679 .vcpu_put
= vmx_vcpu_put
,
3681 .set_guest_debug
= set_guest_debug
,
3682 .get_msr
= vmx_get_msr
,
3683 .set_msr
= vmx_set_msr
,
3684 .get_segment_base
= vmx_get_segment_base
,
3685 .get_segment
= vmx_get_segment
,
3686 .set_segment
= vmx_set_segment
,
3687 .get_cpl
= vmx_get_cpl
,
3688 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
3689 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
3690 .set_cr0
= vmx_set_cr0
,
3691 .set_cr3
= vmx_set_cr3
,
3692 .set_cr4
= vmx_set_cr4
,
3693 .set_efer
= vmx_set_efer
,
3694 .get_idt
= vmx_get_idt
,
3695 .set_idt
= vmx_set_idt
,
3696 .get_gdt
= vmx_get_gdt
,
3697 .set_gdt
= vmx_set_gdt
,
3698 .cache_reg
= vmx_cache_reg
,
3699 .get_rflags
= vmx_get_rflags
,
3700 .set_rflags
= vmx_set_rflags
,
3702 .tlb_flush
= vmx_flush_tlb
,
3704 .run
= vmx_vcpu_run
,
3705 .handle_exit
= vmx_handle_exit
,
3706 .skip_emulated_instruction
= skip_emulated_instruction
,
3707 .patch_hypercall
= vmx_patch_hypercall
,
3708 .get_irq
= vmx_get_irq
,
3709 .set_irq
= vmx_inject_irq
,
3710 .queue_exception
= vmx_queue_exception
,
3711 .exception_injected
= vmx_exception_injected
,
3712 .inject_pending_irq
= vmx_intr_assist
,
3713 .inject_pending_vectors
= do_interrupt_requests
,
3714 .interrupt_allowed
= vmx_interrupt_allowed
,
3715 .set_tss_addr
= vmx_set_tss_addr
,
3716 .get_tdp_level
= get_ept_level
,
3717 .get_mt_mask_shift
= vmx_get_mt_mask_shift
,
3720 static int __init
vmx_init(void)
3724 vmx_io_bitmap_a
= (unsigned long *)__get_free_page(GFP_KERNEL
);
3725 if (!vmx_io_bitmap_a
)
3728 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
3729 if (!vmx_io_bitmap_b
) {
3734 vmx_msr_bitmap_legacy
= (unsigned long *)__get_free_page(GFP_KERNEL
);
3735 if (!vmx_msr_bitmap_legacy
) {
3740 vmx_msr_bitmap_longmode
= (unsigned long *)__get_free_page(GFP_KERNEL
);
3741 if (!vmx_msr_bitmap_longmode
) {
3747 * Allow direct access to the PC debug port (it is often used for I/O
3748 * delays, but the vmexits simply slow things down).
3750 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
3751 clear_bit(0x80, vmx_io_bitmap_a
);
3753 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
3755 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
3756 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
3758 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
3760 r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
), THIS_MODULE
);
3764 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
3765 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
3766 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
3767 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
3768 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
3769 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
3772 bypass_guest_pf
= 0;
3773 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK
|
3774 VMX_EPT_WRITABLE_MASK
);
3775 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
3776 VMX_EPT_EXECUTABLE_MASK
,
3777 VMX_EPT_DEFAULT_MT
<< VMX_EPT_MT_EPTE_SHIFT
);
3782 if (bypass_guest_pf
)
3783 kvm_mmu_set_nonpresent_ptes(~0xffeull
, 0ull);
3790 free_page((unsigned long)vmx_msr_bitmap_longmode
);
3792 free_page((unsigned long)vmx_msr_bitmap_legacy
);
3794 free_page((unsigned long)vmx_io_bitmap_b
);
3796 free_page((unsigned long)vmx_io_bitmap_a
);
3800 static void __exit
vmx_exit(void)
3802 free_page((unsigned long)vmx_msr_bitmap_legacy
);
3803 free_page((unsigned long)vmx_msr_bitmap_longmode
);
3804 free_page((unsigned long)vmx_io_bitmap_b
);
3805 free_page((unsigned long)vmx_io_bitmap_a
);
3810 module_init(vmx_init
)
3811 module_exit(vmx_exit
)