2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/i2c.h>
29 #include "intel_drv.h"
33 #include "drm_crtc_helper.h"
35 bool intel_pipe_has_type (struct drm_crtc
*crtc
, int type
);
58 #define INTEL_P2_NUM 2
61 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
65 #define I8XX_DOT_MIN 25000
66 #define I8XX_DOT_MAX 350000
67 #define I8XX_VCO_MIN 930000
68 #define I8XX_VCO_MAX 1400000
72 #define I8XX_M_MAX 140
73 #define I8XX_M1_MIN 18
74 #define I8XX_M1_MAX 26
76 #define I8XX_M2_MAX 16
78 #define I8XX_P_MAX 128
80 #define I8XX_P1_MAX 33
81 #define I8XX_P1_LVDS_MIN 1
82 #define I8XX_P1_LVDS_MAX 6
83 #define I8XX_P2_SLOW 4
84 #define I8XX_P2_FAST 2
85 #define I8XX_P2_LVDS_SLOW 14
86 #define I8XX_P2_LVDS_FAST 14 /* No fast option */
87 #define I8XX_P2_SLOW_LIMIT 165000
89 #define I9XX_DOT_MIN 20000
90 #define I9XX_DOT_MAX 400000
91 #define I9XX_VCO_MIN 1400000
92 #define I9XX_VCO_MAX 2800000
96 #define I9XX_M_MAX 120
97 #define I9XX_M1_MIN 10
98 #define I9XX_M1_MAX 22
100 #define I9XX_M2_MAX 9
101 #define I9XX_P_SDVO_DAC_MIN 5
102 #define I9XX_P_SDVO_DAC_MAX 80
103 #define I9XX_P_LVDS_MIN 7
104 #define I9XX_P_LVDS_MAX 98
105 #define I9XX_P1_MIN 1
106 #define I9XX_P1_MAX 8
107 #define I9XX_P2_SDVO_DAC_SLOW 10
108 #define I9XX_P2_SDVO_DAC_FAST 5
109 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
110 #define I9XX_P2_LVDS_SLOW 14
111 #define I9XX_P2_LVDS_FAST 7
112 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
114 #define INTEL_LIMIT_I8XX_DVO_DAC 0
115 #define INTEL_LIMIT_I8XX_LVDS 1
116 #define INTEL_LIMIT_I9XX_SDVO_DAC 2
117 #define INTEL_LIMIT_I9XX_LVDS 3
118 #define INTEL_LIMIT_G4X_SDVO 4
119 #define INTEL_LIMIT_G4X_HDMI_DAC 5
120 #define INTEL_LIMIT_G4X_SINGLE_CHANNEL_LVDS 6
121 #define INTEL_LIMIT_G4X_DUAL_CHANNEL_LVDS 7
123 /*The parameter is for SDVO on G4x platform*/
124 #define G4X_DOT_SDVO_MIN 25000
125 #define G4X_DOT_SDVO_MAX 270000
126 #define G4X_VCO_MIN 1750000
127 #define G4X_VCO_MAX 3500000
128 #define G4X_N_SDVO_MIN 1
129 #define G4X_N_SDVO_MAX 4
130 #define G4X_M_SDVO_MIN 104
131 #define G4X_M_SDVO_MAX 138
132 #define G4X_M1_SDVO_MIN 17
133 #define G4X_M1_SDVO_MAX 23
134 #define G4X_M2_SDVO_MIN 5
135 #define G4X_M2_SDVO_MAX 11
136 #define G4X_P_SDVO_MIN 10
137 #define G4X_P_SDVO_MAX 30
138 #define G4X_P1_SDVO_MIN 1
139 #define G4X_P1_SDVO_MAX 3
140 #define G4X_P2_SDVO_SLOW 10
141 #define G4X_P2_SDVO_FAST 10
142 #define G4X_P2_SDVO_LIMIT 270000
144 /*The parameter is for HDMI_DAC on G4x platform*/
145 #define G4X_DOT_HDMI_DAC_MIN 22000
146 #define G4X_DOT_HDMI_DAC_MAX 400000
147 #define G4X_N_HDMI_DAC_MIN 1
148 #define G4X_N_HDMI_DAC_MAX 4
149 #define G4X_M_HDMI_DAC_MIN 104
150 #define G4X_M_HDMI_DAC_MAX 138
151 #define G4X_M1_HDMI_DAC_MIN 16
152 #define G4X_M1_HDMI_DAC_MAX 23
153 #define G4X_M2_HDMI_DAC_MIN 5
154 #define G4X_M2_HDMI_DAC_MAX 11
155 #define G4X_P_HDMI_DAC_MIN 5
156 #define G4X_P_HDMI_DAC_MAX 80
157 #define G4X_P1_HDMI_DAC_MIN 1
158 #define G4X_P1_HDMI_DAC_MAX 8
159 #define G4X_P2_HDMI_DAC_SLOW 10
160 #define G4X_P2_HDMI_DAC_FAST 5
161 #define G4X_P2_HDMI_DAC_LIMIT 165000
163 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
164 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
165 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
166 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
167 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
168 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
169 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
170 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
171 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
172 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
173 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
174 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
175 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
176 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
177 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
178 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
179 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
180 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
182 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
183 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
184 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
185 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
186 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
187 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
188 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
189 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
190 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
191 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
192 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
193 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
194 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
195 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
196 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
197 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
198 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
199 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
202 static const intel_limit_t intel_limits
[] = {
203 { /* INTEL_LIMIT_I8XX_DVO_DAC */
204 .dot
= { .min
= I8XX_DOT_MIN
, .max
= I8XX_DOT_MAX
},
205 .vco
= { .min
= I8XX_VCO_MIN
, .max
= I8XX_VCO_MAX
},
206 .n
= { .min
= I8XX_N_MIN
, .max
= I8XX_N_MAX
},
207 .m
= { .min
= I8XX_M_MIN
, .max
= I8XX_M_MAX
},
208 .m1
= { .min
= I8XX_M1_MIN
, .max
= I8XX_M1_MAX
},
209 .m2
= { .min
= I8XX_M2_MIN
, .max
= I8XX_M2_MAX
},
210 .p
= { .min
= I8XX_P_MIN
, .max
= I8XX_P_MAX
},
211 .p1
= { .min
= I8XX_P1_MIN
, .max
= I8XX_P1_MAX
},
212 .p2
= { .dot_limit
= I8XX_P2_SLOW_LIMIT
,
213 .p2_slow
= I8XX_P2_SLOW
, .p2_fast
= I8XX_P2_FAST
},
215 { /* INTEL_LIMIT_I8XX_LVDS */
216 .dot
= { .min
= I8XX_DOT_MIN
, .max
= I8XX_DOT_MAX
},
217 .vco
= { .min
= I8XX_VCO_MIN
, .max
= I8XX_VCO_MAX
},
218 .n
= { .min
= I8XX_N_MIN
, .max
= I8XX_N_MAX
},
219 .m
= { .min
= I8XX_M_MIN
, .max
= I8XX_M_MAX
},
220 .m1
= { .min
= I8XX_M1_MIN
, .max
= I8XX_M1_MAX
},
221 .m2
= { .min
= I8XX_M2_MIN
, .max
= I8XX_M2_MAX
},
222 .p
= { .min
= I8XX_P_MIN
, .max
= I8XX_P_MAX
},
223 .p1
= { .min
= I8XX_P1_LVDS_MIN
, .max
= I8XX_P1_LVDS_MAX
},
224 .p2
= { .dot_limit
= I8XX_P2_SLOW_LIMIT
,
225 .p2_slow
= I8XX_P2_LVDS_SLOW
, .p2_fast
= I8XX_P2_LVDS_FAST
},
227 { /* INTEL_LIMIT_I9XX_SDVO_DAC */
228 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
229 .vco
= { .min
= I9XX_VCO_MIN
, .max
= I9XX_VCO_MAX
},
230 .n
= { .min
= I9XX_N_MIN
, .max
= I9XX_N_MAX
},
231 .m
= { .min
= I9XX_M_MIN
, .max
= I9XX_M_MAX
},
232 .m1
= { .min
= I9XX_M1_MIN
, .max
= I9XX_M1_MAX
},
233 .m2
= { .min
= I9XX_M2_MIN
, .max
= I9XX_M2_MAX
},
234 .p
= { .min
= I9XX_P_SDVO_DAC_MIN
, .max
= I9XX_P_SDVO_DAC_MAX
},
235 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
236 .p2
= { .dot_limit
= I9XX_P2_SDVO_DAC_SLOW_LIMIT
,
237 .p2_slow
= I9XX_P2_SDVO_DAC_SLOW
, .p2_fast
= I9XX_P2_SDVO_DAC_FAST
},
239 { /* INTEL_LIMIT_I9XX_LVDS */
240 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
241 .vco
= { .min
= I9XX_VCO_MIN
, .max
= I9XX_VCO_MAX
},
242 .n
= { .min
= I9XX_N_MIN
, .max
= I9XX_N_MAX
},
243 .m
= { .min
= I9XX_M_MIN
, .max
= I9XX_M_MAX
},
244 .m1
= { .min
= I9XX_M1_MIN
, .max
= I9XX_M1_MAX
},
245 .m2
= { .min
= I9XX_M2_MIN
, .max
= I9XX_M2_MAX
},
246 .p
= { .min
= I9XX_P_LVDS_MIN
, .max
= I9XX_P_LVDS_MAX
},
247 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
248 /* The single-channel range is 25-112Mhz, and dual-channel
249 * is 80-224Mhz. Prefer single channel as much as possible.
251 .p2
= { .dot_limit
= I9XX_P2_LVDS_SLOW_LIMIT
,
252 .p2_slow
= I9XX_P2_LVDS_SLOW
, .p2_fast
= I9XX_P2_LVDS_FAST
},
254 /* below parameter and function is for G4X Chipset Family*/
255 { /* INTEL_LIMIT_G4X_SDVO */
256 .dot
= { .min
= G4X_DOT_SDVO_MIN
, .max
= G4X_DOT_SDVO_MAX
},
257 .vco
= { .min
= G4X_VCO_MIN
, .max
= G4X_VCO_MAX
},
258 .n
= { .min
= G4X_N_SDVO_MIN
, .max
= G4X_N_SDVO_MAX
},
259 .m
= { .min
= G4X_M_SDVO_MIN
, .max
= G4X_M_SDVO_MAX
},
260 .m1
= { .min
= G4X_M1_SDVO_MIN
, .max
= G4X_M1_SDVO_MAX
},
261 .m2
= { .min
= G4X_M2_SDVO_MIN
, .max
= G4X_M2_SDVO_MAX
},
262 .p
= { .min
= G4X_P_SDVO_MIN
, .max
= G4X_P_SDVO_MAX
},
263 .p1
= { .min
= G4X_P1_SDVO_MIN
, .max
= G4X_P1_SDVO_MAX
},
264 .p2
= { .dot_limit
= G4X_P2_SDVO_LIMIT
,
265 .p2_slow
= G4X_P2_SDVO_SLOW
,
266 .p2_fast
= G4X_P2_SDVO_FAST
269 { /* INTEL_LIMIT_G4X_HDMI_DAC */
270 .dot
= { .min
= G4X_DOT_HDMI_DAC_MIN
, .max
= G4X_DOT_HDMI_DAC_MAX
},
271 .vco
= { .min
= G4X_VCO_MIN
, .max
= G4X_VCO_MAX
},
272 .n
= { .min
= G4X_N_HDMI_DAC_MIN
, .max
= G4X_N_HDMI_DAC_MAX
},
273 .m
= { .min
= G4X_M_HDMI_DAC_MIN
, .max
= G4X_M_HDMI_DAC_MAX
},
274 .m1
= { .min
= G4X_M1_HDMI_DAC_MIN
, .max
= G4X_M1_HDMI_DAC_MAX
},
275 .m2
= { .min
= G4X_M2_HDMI_DAC_MIN
, .max
= G4X_M2_HDMI_DAC_MAX
},
276 .p
= { .min
= G4X_P_HDMI_DAC_MIN
, .max
= G4X_P_HDMI_DAC_MAX
},
277 .p1
= { .min
= G4X_P1_HDMI_DAC_MIN
, .max
= G4X_P1_HDMI_DAC_MAX
},
278 .p2
= { .dot_limit
= G4X_P2_HDMI_DAC_LIMIT
,
279 .p2_slow
= G4X_P2_HDMI_DAC_SLOW
,
280 .p2_fast
= G4X_P2_HDMI_DAC_FAST
283 { /* INTEL_LIMIT_G4X_SINGLE_CHANNEL_LVDS */
284 .dot
= { .min
= G4X_DOT_SINGLE_CHANNEL_LVDS_MIN
,
285 .max
= G4X_DOT_SINGLE_CHANNEL_LVDS_MAX
},
286 .vco
= { .min
= G4X_VCO_MIN
,
287 .max
= G4X_VCO_MAX
},
288 .n
= { .min
= G4X_N_SINGLE_CHANNEL_LVDS_MIN
,
289 .max
= G4X_N_SINGLE_CHANNEL_LVDS_MAX
},
290 .m
= { .min
= G4X_M_SINGLE_CHANNEL_LVDS_MIN
,
291 .max
= G4X_M_SINGLE_CHANNEL_LVDS_MAX
},
292 .m1
= { .min
= G4X_M1_SINGLE_CHANNEL_LVDS_MIN
,
293 .max
= G4X_M1_SINGLE_CHANNEL_LVDS_MAX
},
294 .m2
= { .min
= G4X_M2_SINGLE_CHANNEL_LVDS_MIN
,
295 .max
= G4X_M2_SINGLE_CHANNEL_LVDS_MAX
},
296 .p
= { .min
= G4X_P_SINGLE_CHANNEL_LVDS_MIN
,
297 .max
= G4X_P_SINGLE_CHANNEL_LVDS_MAX
},
298 .p1
= { .min
= G4X_P1_SINGLE_CHANNEL_LVDS_MIN
,
299 .max
= G4X_P1_SINGLE_CHANNEL_LVDS_MAX
},
300 .p2
= { .dot_limit
= G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT
,
301 .p2_slow
= G4X_P2_SINGLE_CHANNEL_LVDS_SLOW
,
302 .p2_fast
= G4X_P2_SINGLE_CHANNEL_LVDS_FAST
305 { /* INTEL_LIMIT_G4X_DUAL_CHANNEL_LVDS */
306 .dot
= { .min
= G4X_DOT_DUAL_CHANNEL_LVDS_MIN
,
307 .max
= G4X_DOT_DUAL_CHANNEL_LVDS_MAX
},
308 .vco
= { .min
= G4X_VCO_MIN
,
309 .max
= G4X_VCO_MAX
},
310 .n
= { .min
= G4X_N_DUAL_CHANNEL_LVDS_MIN
,
311 .max
= G4X_N_DUAL_CHANNEL_LVDS_MAX
},
312 .m
= { .min
= G4X_M_DUAL_CHANNEL_LVDS_MIN
,
313 .max
= G4X_M_DUAL_CHANNEL_LVDS_MAX
},
314 .m1
= { .min
= G4X_M1_DUAL_CHANNEL_LVDS_MIN
,
315 .max
= G4X_M1_DUAL_CHANNEL_LVDS_MAX
},
316 .m2
= { .min
= G4X_M2_DUAL_CHANNEL_LVDS_MIN
,
317 .max
= G4X_M2_DUAL_CHANNEL_LVDS_MAX
},
318 .p
= { .min
= G4X_P_DUAL_CHANNEL_LVDS_MIN
,
319 .max
= G4X_P_DUAL_CHANNEL_LVDS_MAX
},
320 .p1
= { .min
= G4X_P1_DUAL_CHANNEL_LVDS_MIN
,
321 .max
= G4X_P1_DUAL_CHANNEL_LVDS_MAX
},
322 .p2
= { .dot_limit
= G4X_P2_DUAL_CHANNEL_LVDS_LIMIT
,
323 .p2_slow
= G4X_P2_DUAL_CHANNEL_LVDS_SLOW
,
324 .p2_fast
= G4X_P2_DUAL_CHANNEL_LVDS_FAST
329 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
331 struct drm_device
*dev
= crtc
->dev
;
332 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
333 const intel_limit_t
*limit
;
335 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
336 if ((I915_READ(LVDS
) & LVDS_CLKB_POWER_MASK
) ==
338 /* LVDS with dual channel */
339 limit
= &intel_limits
340 [INTEL_LIMIT_G4X_DUAL_CHANNEL_LVDS
];
342 /* LVDS with dual channel */
343 limit
= &intel_limits
344 [INTEL_LIMIT_G4X_SINGLE_CHANNEL_LVDS
];
345 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
346 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
347 limit
= &intel_limits
[INTEL_LIMIT_G4X_HDMI_DAC
];
348 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
349 limit
= &intel_limits
[INTEL_LIMIT_G4X_SDVO
];
350 } else /* The option is for other outputs */
351 limit
= &intel_limits
[INTEL_LIMIT_I9XX_SDVO_DAC
];
356 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
)
358 struct drm_device
*dev
= crtc
->dev
;
359 const intel_limit_t
*limit
;
362 limit
= intel_g4x_limit(crtc
);
363 } else if (IS_I9XX(dev
)) {
364 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
365 limit
= &intel_limits
[INTEL_LIMIT_I9XX_LVDS
];
367 limit
= &intel_limits
[INTEL_LIMIT_I9XX_SDVO_DAC
];
369 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
370 limit
= &intel_limits
[INTEL_LIMIT_I8XX_LVDS
];
372 limit
= &intel_limits
[INTEL_LIMIT_I8XX_DVO_DAC
];
377 static void intel_clock(int refclk
, intel_clock_t
*clock
)
379 clock
->m
= 5 * (clock
->m1
+ 2) + (clock
->m2
+ 2);
380 clock
->p
= clock
->p1
* clock
->p2
;
381 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
382 clock
->dot
= clock
->vco
/ clock
->p
;
386 * Returns whether any output on the specified pipe is of the specified type
388 bool intel_pipe_has_type (struct drm_crtc
*crtc
, int type
)
390 struct drm_device
*dev
= crtc
->dev
;
391 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
392 struct drm_connector
*l_entry
;
394 list_for_each_entry(l_entry
, &mode_config
->connector_list
, head
) {
395 if (l_entry
->encoder
&&
396 l_entry
->encoder
->crtc
== crtc
) {
397 struct intel_output
*intel_output
= to_intel_output(l_entry
);
398 if (intel_output
->type
== type
)
405 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
407 * Returns whether the given set of divisors are valid for a given refclk with
408 * the given connectors.
411 static bool intel_PLL_is_valid(struct drm_crtc
*crtc
, intel_clock_t
*clock
)
413 const intel_limit_t
*limit
= intel_limit (crtc
);
415 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
416 INTELPllInvalid ("p1 out of range\n");
417 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
418 INTELPllInvalid ("p out of range\n");
419 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
420 INTELPllInvalid ("m2 out of range\n");
421 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
422 INTELPllInvalid ("m1 out of range\n");
423 if (clock
->m1
<= clock
->m2
)
424 INTELPllInvalid ("m1 <= m2\n");
425 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
426 INTELPllInvalid ("m out of range\n");
427 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
428 INTELPllInvalid ("n out of range\n");
429 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
430 INTELPllInvalid ("vco out of range\n");
431 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
432 * connector, etc., rather than just a single range.
434 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
435 INTELPllInvalid ("dot out of range\n");
441 * Returns a set of divisors for the desired target clock with the given
442 * refclk, or FALSE. The returned values represent the clock equation:
443 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
445 static bool intel_find_best_PLL(struct drm_crtc
*crtc
, int target
,
446 int refclk
, intel_clock_t
*best_clock
)
448 struct drm_device
*dev
= crtc
->dev
;
449 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
451 const intel_limit_t
*limit
= intel_limit(crtc
);
454 if (IS_I9XX(dev
) && intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
455 (I915_READ(LVDS
) & LVDS_PORT_EN
) != 0) {
457 * For LVDS, if the panel is on, just rely on its current
458 * settings for dual-channel. We haven't figured out how to
459 * reliably set up different single/dual channel state, if we
462 if ((I915_READ(LVDS
) & LVDS_CLKB_POWER_MASK
) ==
464 clock
.p2
= limit
->p2
.p2_fast
;
466 clock
.p2
= limit
->p2
.p2_slow
;
468 if (target
< limit
->p2
.dot_limit
)
469 clock
.p2
= limit
->p2
.p2_slow
;
471 clock
.p2
= limit
->p2
.p2_fast
;
474 memset (best_clock
, 0, sizeof (*best_clock
));
476 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
477 for (clock
.m2
= limit
->m2
.min
; clock
.m2
< clock
.m1
&&
478 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
479 for (clock
.n
= limit
->n
.min
; clock
.n
<= limit
->n
.max
;
481 for (clock
.p1
= limit
->p1
.min
;
482 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
485 intel_clock(refclk
, &clock
);
487 if (!intel_PLL_is_valid(crtc
, &clock
))
490 this_err
= abs(clock
.dot
- target
);
491 if (this_err
< err
) {
500 return (err
!= target
);
504 intel_wait_for_vblank(struct drm_device
*dev
)
506 /* Wait for 20ms, i.e. one cycle at 50hz. */
511 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
512 struct drm_framebuffer
*old_fb
)
514 struct drm_device
*dev
= crtc
->dev
;
515 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
516 struct drm_i915_master_private
*master_priv
;
517 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
518 struct intel_framebuffer
*intel_fb
;
519 struct drm_i915_gem_object
*obj_priv
;
520 struct drm_gem_object
*obj
;
521 int pipe
= intel_crtc
->pipe
;
522 unsigned long Start
, Offset
;
523 int dspbase
= (pipe
== 0 ? DSPAADDR
: DSPBADDR
);
524 int dspsurf
= (pipe
== 0 ? DSPASURF
: DSPBSURF
);
525 int dspstride
= (pipe
== 0) ? DSPASTRIDE
: DSPBSTRIDE
;
526 int dspcntr_reg
= (pipe
== 0) ? DSPACNTR
: DSPBCNTR
;
527 u32 dspcntr
, alignment
;
532 DRM_DEBUG("No FB bound\n");
541 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe
);
545 intel_fb
= to_intel_framebuffer(crtc
->fb
);
547 obj_priv
= obj
->driver_private
;
549 switch (obj_priv
->tiling_mode
) {
550 case I915_TILING_NONE
:
551 alignment
= 64 * 1024;
554 /* pin() will align the object as required by fence */
558 /* FIXME: Is this true? */
559 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
565 mutex_lock(&dev
->struct_mutex
);
566 ret
= i915_gem_object_pin(intel_fb
->obj
, alignment
);
568 mutex_unlock(&dev
->struct_mutex
);
572 ret
= i915_gem_object_set_to_gtt_domain(intel_fb
->obj
, 1);
574 i915_gem_object_unpin(intel_fb
->obj
);
575 mutex_unlock(&dev
->struct_mutex
);
579 dspcntr
= I915_READ(dspcntr_reg
);
580 /* Mask out pixel format bits in case we change it */
581 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
582 switch (crtc
->fb
->bits_per_pixel
) {
584 dspcntr
|= DISPPLANE_8BPP
;
587 if (crtc
->fb
->depth
== 15)
588 dspcntr
|= DISPPLANE_15_16BPP
;
590 dspcntr
|= DISPPLANE_16BPP
;
594 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
597 DRM_ERROR("Unknown color depth\n");
598 i915_gem_object_unpin(intel_fb
->obj
);
599 mutex_unlock(&dev
->struct_mutex
);
602 I915_WRITE(dspcntr_reg
, dspcntr
);
604 Start
= obj_priv
->gtt_offset
;
605 Offset
= y
* crtc
->fb
->pitch
+ x
* (crtc
->fb
->bits_per_pixel
/ 8);
607 DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start
, Offset
, x
, y
);
608 I915_WRITE(dspstride
, crtc
->fb
->pitch
);
610 I915_WRITE(dspbase
, Offset
);
612 I915_WRITE(dspsurf
, Start
);
615 I915_WRITE(dspbase
, Start
+ Offset
);
619 intel_wait_for_vblank(dev
);
622 intel_fb
= to_intel_framebuffer(old_fb
);
623 i915_gem_object_unpin(intel_fb
->obj
);
625 mutex_unlock(&dev
->struct_mutex
);
627 if (!dev
->primary
->master
)
630 master_priv
= dev
->primary
->master
->driver_priv
;
631 if (!master_priv
->sarea_priv
)
635 master_priv
->sarea_priv
->pipeB_x
= x
;
636 master_priv
->sarea_priv
->pipeB_y
= y
;
638 master_priv
->sarea_priv
->pipeA_x
= x
;
639 master_priv
->sarea_priv
->pipeA_y
= y
;
648 * Sets the power management mode of the pipe and plane.
650 * This code should probably grow support for turning the cursor off and back
651 * on appropriately at the same time as we're turning the pipe off/on.
653 static void intel_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
655 struct drm_device
*dev
= crtc
->dev
;
656 struct drm_i915_master_private
*master_priv
;
657 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
658 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
659 int pipe
= intel_crtc
->pipe
;
660 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
661 int dspcntr_reg
= (pipe
== 0) ? DSPACNTR
: DSPBCNTR
;
662 int dspbase_reg
= (pipe
== 0) ? DSPAADDR
: DSPBADDR
;
663 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
667 /* XXX: When our outputs are all unaware of DPMS modes other than off
668 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
671 case DRM_MODE_DPMS_ON
:
672 case DRM_MODE_DPMS_STANDBY
:
673 case DRM_MODE_DPMS_SUSPEND
:
674 /* Enable the DPLL */
675 temp
= I915_READ(dpll_reg
);
676 if ((temp
& DPLL_VCO_ENABLE
) == 0) {
677 I915_WRITE(dpll_reg
, temp
);
679 /* Wait for the clocks to stabilize. */
681 I915_WRITE(dpll_reg
, temp
| DPLL_VCO_ENABLE
);
683 /* Wait for the clocks to stabilize. */
685 I915_WRITE(dpll_reg
, temp
| DPLL_VCO_ENABLE
);
687 /* Wait for the clocks to stabilize. */
691 /* Enable the pipe */
692 temp
= I915_READ(pipeconf_reg
);
693 if ((temp
& PIPEACONF_ENABLE
) == 0)
694 I915_WRITE(pipeconf_reg
, temp
| PIPEACONF_ENABLE
);
696 /* Enable the plane */
697 temp
= I915_READ(dspcntr_reg
);
698 if ((temp
& DISPLAY_PLANE_ENABLE
) == 0) {
699 I915_WRITE(dspcntr_reg
, temp
| DISPLAY_PLANE_ENABLE
);
700 /* Flush the plane changes */
701 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
704 intel_crtc_load_lut(crtc
);
706 /* Give the overlay scaler a chance to enable if it's on this pipe */
707 //intel_crtc_dpms_video(crtc, true); TODO
709 case DRM_MODE_DPMS_OFF
:
710 /* Give the overlay scaler a chance to disable if it's on this pipe */
711 //intel_crtc_dpms_video(crtc, FALSE); TODO
713 /* Disable the VGA plane that we never use */
714 I915_WRITE(VGACNTRL
, VGA_DISP_DISABLE
);
716 /* Disable display plane */
717 temp
= I915_READ(dspcntr_reg
);
718 if ((temp
& DISPLAY_PLANE_ENABLE
) != 0) {
719 I915_WRITE(dspcntr_reg
, temp
& ~DISPLAY_PLANE_ENABLE
);
720 /* Flush the plane changes */
721 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
722 I915_READ(dspbase_reg
);
726 /* Wait for vblank for the disable to take effect */
727 intel_wait_for_vblank(dev
);
730 /* Next, disable display pipes */
731 temp
= I915_READ(pipeconf_reg
);
732 if ((temp
& PIPEACONF_ENABLE
) != 0) {
733 I915_WRITE(pipeconf_reg
, temp
& ~PIPEACONF_ENABLE
);
734 I915_READ(pipeconf_reg
);
737 /* Wait for vblank for the disable to take effect. */
738 intel_wait_for_vblank(dev
);
740 temp
= I915_READ(dpll_reg
);
741 if ((temp
& DPLL_VCO_ENABLE
) != 0) {
742 I915_WRITE(dpll_reg
, temp
& ~DPLL_VCO_ENABLE
);
746 /* Wait for the clocks to turn off. */
751 if (!dev
->primary
->master
)
754 master_priv
= dev
->primary
->master
->driver_priv
;
755 if (!master_priv
->sarea_priv
)
758 enabled
= crtc
->enabled
&& mode
!= DRM_MODE_DPMS_OFF
;
762 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
763 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
766 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
767 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
770 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe
);
774 intel_crtc
->dpms_mode
= mode
;
777 static void intel_crtc_prepare (struct drm_crtc
*crtc
)
779 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
780 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_OFF
);
783 static void intel_crtc_commit (struct drm_crtc
*crtc
)
785 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
786 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
789 void intel_encoder_prepare (struct drm_encoder
*encoder
)
791 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
792 /* lvds has its own version of prepare see intel_lvds_prepare */
793 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_OFF
);
796 void intel_encoder_commit (struct drm_encoder
*encoder
)
798 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
799 /* lvds has its own version of commit see intel_lvds_commit */
800 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
803 static bool intel_crtc_mode_fixup(struct drm_crtc
*crtc
,
804 struct drm_display_mode
*mode
,
805 struct drm_display_mode
*adjusted_mode
)
811 /** Returns the core display clock speed for i830 - i945 */
812 static int intel_get_core_clock_speed(struct drm_device
*dev
)
815 /* Core clock values taken from the published datasheets.
816 * The 830 may go up to 166 Mhz, which we should check.
820 else if (IS_I915G(dev
))
822 else if (IS_I945GM(dev
) || IS_845G(dev
))
824 else if (IS_I915GM(dev
)) {
827 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
829 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
832 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
833 case GC_DISPLAY_CLOCK_333_MHZ
:
836 case GC_DISPLAY_CLOCK_190_200_MHZ
:
840 } else if (IS_I865G(dev
))
842 else if (IS_I855(dev
)) {
844 /* Assume that the hardware is in the high speed state. This
845 * should be the default.
847 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
848 case GC_CLOCK_133_200
:
849 case GC_CLOCK_100_200
:
851 case GC_CLOCK_166_250
:
853 case GC_CLOCK_100_133
:
856 } else /* 852, 830 */
859 return 0; /* Silence gcc warning */
864 * Return the pipe currently connected to the panel fitter,
865 * or -1 if the panel fitter is not present or not in use
867 static int intel_panel_fitter_pipe (struct drm_device
*dev
)
869 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
872 /* i830 doesn't have a panel fitter */
876 pfit_control
= I915_READ(PFIT_CONTROL
);
878 /* See if the panel fitter is in use */
879 if ((pfit_control
& PFIT_ENABLE
) == 0)
882 /* 965 can place panel fitter on either pipe */
884 return (pfit_control
>> 29) & 0x3;
886 /* older chips can only use pipe 1 */
890 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
891 struct drm_display_mode
*mode
,
892 struct drm_display_mode
*adjusted_mode
,
894 struct drm_framebuffer
*old_fb
)
896 struct drm_device
*dev
= crtc
->dev
;
897 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
898 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
899 int pipe
= intel_crtc
->pipe
;
900 int fp_reg
= (pipe
== 0) ? FPA0
: FPB0
;
901 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
902 int dpll_md_reg
= (intel_crtc
->pipe
== 0) ? DPLL_A_MD
: DPLL_B_MD
;
903 int dspcntr_reg
= (pipe
== 0) ? DSPACNTR
: DSPBCNTR
;
904 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
905 int htot_reg
= (pipe
== 0) ? HTOTAL_A
: HTOTAL_B
;
906 int hblank_reg
= (pipe
== 0) ? HBLANK_A
: HBLANK_B
;
907 int hsync_reg
= (pipe
== 0) ? HSYNC_A
: HSYNC_B
;
908 int vtot_reg
= (pipe
== 0) ? VTOTAL_A
: VTOTAL_B
;
909 int vblank_reg
= (pipe
== 0) ? VBLANK_A
: VBLANK_B
;
910 int vsync_reg
= (pipe
== 0) ? VSYNC_A
: VSYNC_B
;
911 int dspsize_reg
= (pipe
== 0) ? DSPASIZE
: DSPBSIZE
;
912 int dsppos_reg
= (pipe
== 0) ? DSPAPOS
: DSPBPOS
;
913 int pipesrc_reg
= (pipe
== 0) ? PIPEASRC
: PIPEBSRC
;
914 int refclk
, num_outputs
= 0;
916 u32 dpll
= 0, fp
= 0, dspcntr
, pipeconf
;
917 bool ok
, is_sdvo
= false, is_dvo
= false;
918 bool is_crt
= false, is_lvds
= false, is_tv
= false;
919 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
920 struct drm_connector
*connector
;
923 drm_vblank_pre_modeset(dev
, pipe
);
925 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
926 struct intel_output
*intel_output
= to_intel_output(connector
);
928 if (!connector
->encoder
|| connector
->encoder
->crtc
!= crtc
)
931 switch (intel_output
->type
) {
932 case INTEL_OUTPUT_LVDS
:
935 case INTEL_OUTPUT_SDVO
:
936 case INTEL_OUTPUT_HDMI
:
938 if (intel_output
->needs_tv_clock
)
941 case INTEL_OUTPUT_DVO
:
944 case INTEL_OUTPUT_TVOUT
:
947 case INTEL_OUTPUT_ANALOG
:
955 if (is_lvds
&& dev_priv
->lvds_use_ssc
&& num_outputs
< 2) {
956 refclk
= dev_priv
->lvds_ssc_freq
* 1000;
957 DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk
/ 1000);
958 } else if (IS_I9XX(dev
)) {
964 ok
= intel_find_best_PLL(crtc
, adjusted_mode
->clock
, refclk
, &clock
);
966 DRM_ERROR("Couldn't find PLL settings for mode!\n");
970 fp
= clock
.n
<< 16 | clock
.m1
<< 8 | clock
.m2
;
972 dpll
= DPLL_VGA_MODE_DIS
;
975 dpll
|= DPLLB_MODE_LVDS
;
977 dpll
|= DPLLB_MODE_DAC_SERIAL
;
979 dpll
|= DPLL_DVO_HIGH_SPEED
;
980 if (IS_I945G(dev
) || IS_I945GM(dev
)) {
981 int sdvo_pixel_multiply
= adjusted_mode
->clock
/ mode
->clock
;
982 dpll
|= (sdvo_pixel_multiply
- 1) << SDVO_MULTIPLIER_SHIFT_HIRES
;
986 /* compute bitmask from p1 value */
987 dpll
|= (1 << (clock
.p1
- 1)) << 16;
990 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
993 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
996 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
999 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
1003 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
1006 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
1009 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
1011 dpll
|= (clock
.p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
1013 dpll
|= PLL_P2_DIVIDE_BY_4
;
1017 if (is_sdvo
&& is_tv
)
1018 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
1020 /* XXX: just matching BIOS for now */
1021 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
1023 else if (is_lvds
&& dev_priv
->lvds_use_ssc
&& num_outputs
< 2)
1024 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
1026 dpll
|= PLL_REF_INPUT_DREFCLK
;
1028 /* setup pipeconf */
1029 pipeconf
= I915_READ(pipeconf_reg
);
1031 /* Set up the display plane register */
1032 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
1035 dspcntr
|= DISPPLANE_SEL_PIPE_A
;
1037 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
1039 if (pipe
== 0 && !IS_I965G(dev
)) {
1040 /* Enable pixel doubling when the dot clock is > 90% of the (display)
1043 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
1046 if (mode
->clock
> intel_get_core_clock_speed(dev
) * 9 / 10)
1047 pipeconf
|= PIPEACONF_DOUBLE_WIDE
;
1049 pipeconf
&= ~PIPEACONF_DOUBLE_WIDE
;
1052 dspcntr
|= DISPLAY_PLANE_ENABLE
;
1053 pipeconf
|= PIPEACONF_ENABLE
;
1054 dpll
|= DPLL_VCO_ENABLE
;
1057 /* Disable the panel fitter if it was on our pipe */
1058 if (intel_panel_fitter_pipe(dev
) == pipe
)
1059 I915_WRITE(PFIT_CONTROL
, 0);
1061 DRM_DEBUG("Mode for pipe %c:\n", pipe
== 0 ? 'A' : 'B');
1062 drm_mode_debug_printmodeline(mode
);
1065 if (dpll
& DPLL_VCO_ENABLE
) {
1066 I915_WRITE(fp_reg
, fp
);
1067 I915_WRITE(dpll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
1068 I915_READ(dpll_reg
);
1072 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
1073 * This is an exception to the general rule that mode_set doesn't turn
1077 u32 lvds
= I915_READ(LVDS
);
1079 lvds
|= LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
| LVDS_PIPEB_SELECT
;
1080 /* Set the B0-B3 data pairs corresponding to whether we're going to
1081 * set the DPLLs for dual-channel mode or not.
1084 lvds
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
1086 lvds
&= ~(LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
);
1088 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
1089 * appropriately here, but we need to look more thoroughly into how
1090 * panels behave in the two modes.
1093 I915_WRITE(LVDS
, lvds
);
1097 I915_WRITE(fp_reg
, fp
);
1098 I915_WRITE(dpll_reg
, dpll
);
1099 I915_READ(dpll_reg
);
1100 /* Wait for the clocks to stabilize. */
1103 if (IS_I965G(dev
)) {
1104 int sdvo_pixel_multiply
= adjusted_mode
->clock
/ mode
->clock
;
1105 I915_WRITE(dpll_md_reg
, (0 << DPLL_MD_UDI_DIVIDER_SHIFT
) |
1106 ((sdvo_pixel_multiply
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
));
1108 /* write it again -- the BIOS does, after all */
1109 I915_WRITE(dpll_reg
, dpll
);
1111 I915_READ(dpll_reg
);
1112 /* Wait for the clocks to stabilize. */
1115 I915_WRITE(htot_reg
, (adjusted_mode
->crtc_hdisplay
- 1) |
1116 ((adjusted_mode
->crtc_htotal
- 1) << 16));
1117 I915_WRITE(hblank_reg
, (adjusted_mode
->crtc_hblank_start
- 1) |
1118 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
1119 I915_WRITE(hsync_reg
, (adjusted_mode
->crtc_hsync_start
- 1) |
1120 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
1121 I915_WRITE(vtot_reg
, (adjusted_mode
->crtc_vdisplay
- 1) |
1122 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
1123 I915_WRITE(vblank_reg
, (adjusted_mode
->crtc_vblank_start
- 1) |
1124 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
1125 I915_WRITE(vsync_reg
, (adjusted_mode
->crtc_vsync_start
- 1) |
1126 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
1127 /* pipesrc and dspsize control the size that is scaled from, which should
1128 * always be the user's requested size.
1130 I915_WRITE(dspsize_reg
, ((mode
->vdisplay
- 1) << 16) | (mode
->hdisplay
- 1));
1131 I915_WRITE(dsppos_reg
, 0);
1132 I915_WRITE(pipesrc_reg
, ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
1133 I915_WRITE(pipeconf_reg
, pipeconf
);
1134 I915_READ(pipeconf_reg
);
1136 intel_wait_for_vblank(dev
);
1138 I915_WRITE(dspcntr_reg
, dspcntr
);
1140 /* Flush the plane changes */
1141 ret
= intel_pipe_set_base(crtc
, x
, y
, old_fb
);
1145 drm_vblank_post_modeset(dev
, pipe
);
1150 /** Loads the palette/gamma unit for the CRTC with the prepared values */
1151 void intel_crtc_load_lut(struct drm_crtc
*crtc
)
1153 struct drm_device
*dev
= crtc
->dev
;
1154 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1155 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1156 int palreg
= (intel_crtc
->pipe
== 0) ? PALETTE_A
: PALETTE_B
;
1159 /* The clocks have to be on to load the palette. */
1163 for (i
= 0; i
< 256; i
++) {
1164 I915_WRITE(palreg
+ 4 * i
,
1165 (intel_crtc
->lut_r
[i
] << 16) |
1166 (intel_crtc
->lut_g
[i
] << 8) |
1167 intel_crtc
->lut_b
[i
]);
1171 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
1172 struct drm_file
*file_priv
,
1174 uint32_t width
, uint32_t height
)
1176 struct drm_device
*dev
= crtc
->dev
;
1177 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1178 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1179 struct drm_gem_object
*bo
;
1180 struct drm_i915_gem_object
*obj_priv
;
1181 int pipe
= intel_crtc
->pipe
;
1182 uint32_t control
= (pipe
== 0) ? CURACNTR
: CURBCNTR
;
1183 uint32_t base
= (pipe
== 0) ? CURABASE
: CURBBASE
;
1190 /* if we want to turn off the cursor ignore width and height */
1192 DRM_DEBUG("cursor off\n");
1193 temp
= CURSOR_MODE_DISABLE
;
1196 mutex_lock(&dev
->struct_mutex
);
1200 /* Currently we only support 64x64 cursors */
1201 if (width
!= 64 || height
!= 64) {
1202 DRM_ERROR("we currently only support 64x64 cursors\n");
1206 bo
= drm_gem_object_lookup(dev
, file_priv
, handle
);
1210 obj_priv
= bo
->driver_private
;
1212 if (bo
->size
< width
* height
* 4) {
1213 DRM_ERROR("buffer is to small\n");
1218 /* we only need to pin inside GTT if cursor is non-phy */
1219 mutex_lock(&dev
->struct_mutex
);
1220 if (!dev_priv
->cursor_needs_physical
) {
1221 ret
= i915_gem_object_pin(bo
, PAGE_SIZE
);
1223 DRM_ERROR("failed to pin cursor bo\n");
1226 addr
= obj_priv
->gtt_offset
;
1228 ret
= i915_gem_attach_phys_object(dev
, bo
, (pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
);
1230 DRM_ERROR("failed to attach phys object\n");
1233 addr
= obj_priv
->phys_obj
->handle
->busaddr
;
1237 /* set the pipe for the cursor */
1238 temp
|= (pipe
<< 28);
1239 temp
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
1242 I915_WRITE(control
, temp
);
1243 I915_WRITE(base
, addr
);
1245 if (intel_crtc
->cursor_bo
) {
1246 if (dev_priv
->cursor_needs_physical
) {
1247 if (intel_crtc
->cursor_bo
!= bo
)
1248 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
1250 i915_gem_object_unpin(intel_crtc
->cursor_bo
);
1251 drm_gem_object_unreference(intel_crtc
->cursor_bo
);
1253 mutex_unlock(&dev
->struct_mutex
);
1255 intel_crtc
->cursor_addr
= addr
;
1256 intel_crtc
->cursor_bo
= bo
;
1260 mutex_lock(&dev
->struct_mutex
);
1262 drm_gem_object_unreference(bo
);
1263 mutex_unlock(&dev
->struct_mutex
);
1267 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
1269 struct drm_device
*dev
= crtc
->dev
;
1270 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1271 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1272 int pipe
= intel_crtc
->pipe
;
1277 temp
|= (CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
);
1281 temp
|= (CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
);
1285 temp
|= ((x
& CURSOR_POS_MASK
) << CURSOR_X_SHIFT
);
1286 temp
|= ((y
& CURSOR_POS_MASK
) << CURSOR_Y_SHIFT
);
1288 adder
= intel_crtc
->cursor_addr
;
1289 I915_WRITE((pipe
== 0) ? CURAPOS
: CURBPOS
, temp
);
1290 I915_WRITE((pipe
== 0) ? CURABASE
: CURBBASE
, adder
);
1295 /** Sets the color ramps on behalf of RandR */
1296 void intel_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
1297 u16 blue
, int regno
)
1299 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1301 intel_crtc
->lut_r
[regno
] = red
>> 8;
1302 intel_crtc
->lut_g
[regno
] = green
>> 8;
1303 intel_crtc
->lut_b
[regno
] = blue
>> 8;
1306 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
1307 u16
*blue
, uint32_t size
)
1309 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1315 for (i
= 0; i
< 256; i
++) {
1316 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
1317 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
1318 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
1321 intel_crtc_load_lut(crtc
);
1325 * Get a pipe with a simple mode set on it for doing load-based monitor
1328 * It will be up to the load-detect code to adjust the pipe as appropriate for
1329 * its requirements. The pipe will be connected to no other outputs.
1331 * Currently this code will only succeed if there is a pipe with no outputs
1332 * configured for it. In the future, it could choose to temporarily disable
1333 * some outputs to free up a pipe for its use.
1335 * \return crtc, or NULL if no pipes are available.
1338 /* VESA 640x480x72Hz mode to set on the pipe */
1339 static struct drm_display_mode load_detect_mode
= {
1340 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
1341 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
1344 struct drm_crtc
*intel_get_load_detect_pipe(struct intel_output
*intel_output
,
1345 struct drm_display_mode
*mode
,
1348 struct intel_crtc
*intel_crtc
;
1349 struct drm_crtc
*possible_crtc
;
1350 struct drm_crtc
*supported_crtc
=NULL
;
1351 struct drm_encoder
*encoder
= &intel_output
->enc
;
1352 struct drm_crtc
*crtc
= NULL
;
1353 struct drm_device
*dev
= encoder
->dev
;
1354 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
1355 struct drm_crtc_helper_funcs
*crtc_funcs
;
1359 * Algorithm gets a little messy:
1360 * - if the connector already has an assigned crtc, use it (but make
1361 * sure it's on first)
1362 * - try to find the first unused crtc that can drive this connector,
1363 * and use that if we find one
1364 * - if there are no unused crtcs available, try to use the first
1365 * one we found that supports the connector
1368 /* See if we already have a CRTC for this connector */
1369 if (encoder
->crtc
) {
1370 crtc
= encoder
->crtc
;
1371 /* Make sure the crtc and connector are running */
1372 intel_crtc
= to_intel_crtc(crtc
);
1373 *dpms_mode
= intel_crtc
->dpms_mode
;
1374 if (intel_crtc
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
1375 crtc_funcs
= crtc
->helper_private
;
1376 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
1377 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
1382 /* Find an unused one (if possible) */
1383 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
1385 if (!(encoder
->possible_crtcs
& (1 << i
)))
1387 if (!possible_crtc
->enabled
) {
1388 crtc
= possible_crtc
;
1391 if (!supported_crtc
)
1392 supported_crtc
= possible_crtc
;
1396 * If we didn't find an unused CRTC, don't use any.
1402 encoder
->crtc
= crtc
;
1403 intel_output
->load_detect_temp
= true;
1405 intel_crtc
= to_intel_crtc(crtc
);
1406 *dpms_mode
= intel_crtc
->dpms_mode
;
1408 if (!crtc
->enabled
) {
1410 mode
= &load_detect_mode
;
1411 drm_crtc_helper_set_mode(crtc
, mode
, 0, 0, crtc
->fb
);
1413 if (intel_crtc
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
1414 crtc_funcs
= crtc
->helper_private
;
1415 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
1418 /* Add this connector to the crtc */
1419 encoder_funcs
->mode_set(encoder
, &crtc
->mode
, &crtc
->mode
);
1420 encoder_funcs
->commit(encoder
);
1422 /* let the connector get through one full cycle before testing */
1423 intel_wait_for_vblank(dev
);
1428 void intel_release_load_detect_pipe(struct intel_output
*intel_output
, int dpms_mode
)
1430 struct drm_encoder
*encoder
= &intel_output
->enc
;
1431 struct drm_device
*dev
= encoder
->dev
;
1432 struct drm_crtc
*crtc
= encoder
->crtc
;
1433 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
1434 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
1436 if (intel_output
->load_detect_temp
) {
1437 encoder
->crtc
= NULL
;
1438 intel_output
->load_detect_temp
= false;
1439 crtc
->enabled
= drm_helper_crtc_in_use(crtc
);
1440 drm_helper_disable_unused_functions(dev
);
1443 /* Switch crtc and output back off if necessary */
1444 if (crtc
->enabled
&& dpms_mode
!= DRM_MODE_DPMS_ON
) {
1445 if (encoder
->crtc
== crtc
)
1446 encoder_funcs
->dpms(encoder
, dpms_mode
);
1447 crtc_funcs
->dpms(crtc
, dpms_mode
);
1451 /* Returns the clock of the currently programmed mode of the given pipe. */
1452 static int intel_crtc_clock_get(struct drm_device
*dev
, struct drm_crtc
*crtc
)
1454 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1455 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1456 int pipe
= intel_crtc
->pipe
;
1457 u32 dpll
= I915_READ((pipe
== 0) ? DPLL_A
: DPLL_B
);
1459 intel_clock_t clock
;
1461 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
1462 fp
= I915_READ((pipe
== 0) ? FPA0
: FPB0
);
1464 fp
= I915_READ((pipe
== 0) ? FPA1
: FPB1
);
1466 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
1467 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
1468 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
1470 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
1471 DPLL_FPA01_P1_POST_DIV_SHIFT
);
1473 switch (dpll
& DPLL_MODE_MASK
) {
1474 case DPLLB_MODE_DAC_SERIAL
:
1475 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
1478 case DPLLB_MODE_LVDS
:
1479 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
1483 DRM_DEBUG("Unknown DPLL mode %08x in programmed "
1484 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
1488 /* XXX: Handle the 100Mhz refclk */
1489 intel_clock(96000, &clock
);
1491 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
1494 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
1495 DPLL_FPA01_P1_POST_DIV_SHIFT
);
1498 if ((dpll
& PLL_REF_INPUT_MASK
) ==
1499 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
1500 /* XXX: might not be 66MHz */
1501 intel_clock(66000, &clock
);
1503 intel_clock(48000, &clock
);
1505 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
1508 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
1509 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
1511 if (dpll
& PLL_P2_DIVIDE_BY_4
)
1516 intel_clock(48000, &clock
);
1520 /* XXX: It would be nice to validate the clocks, but we can't reuse
1521 * i830PllIsValid() because it relies on the xf86_config connector
1522 * configuration being accurate, which it isn't necessarily.
1528 /** Returns the currently programmed mode of the given pipe. */
1529 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
1530 struct drm_crtc
*crtc
)
1532 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1533 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1534 int pipe
= intel_crtc
->pipe
;
1535 struct drm_display_mode
*mode
;
1536 int htot
= I915_READ((pipe
== 0) ? HTOTAL_A
: HTOTAL_B
);
1537 int hsync
= I915_READ((pipe
== 0) ? HSYNC_A
: HSYNC_B
);
1538 int vtot
= I915_READ((pipe
== 0) ? VTOTAL_A
: VTOTAL_B
);
1539 int vsync
= I915_READ((pipe
== 0) ? VSYNC_A
: VSYNC_B
);
1541 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
1545 mode
->clock
= intel_crtc_clock_get(dev
, crtc
);
1546 mode
->hdisplay
= (htot
& 0xffff) + 1;
1547 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
1548 mode
->hsync_start
= (hsync
& 0xffff) + 1;
1549 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
1550 mode
->vdisplay
= (vtot
& 0xffff) + 1;
1551 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
1552 mode
->vsync_start
= (vsync
& 0xffff) + 1;
1553 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
1555 drm_mode_set_name(mode
);
1556 drm_mode_set_crtcinfo(mode
, 0);
1561 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
1563 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1565 drm_crtc_cleanup(crtc
);
1569 static const struct drm_crtc_helper_funcs intel_helper_funcs
= {
1570 .dpms
= intel_crtc_dpms
,
1571 .mode_fixup
= intel_crtc_mode_fixup
,
1572 .mode_set
= intel_crtc_mode_set
,
1573 .mode_set_base
= intel_pipe_set_base
,
1574 .prepare
= intel_crtc_prepare
,
1575 .commit
= intel_crtc_commit
,
1578 static const struct drm_crtc_funcs intel_crtc_funcs
= {
1579 .cursor_set
= intel_crtc_cursor_set
,
1580 .cursor_move
= intel_crtc_cursor_move
,
1581 .gamma_set
= intel_crtc_gamma_set
,
1582 .set_config
= drm_crtc_helper_set_config
,
1583 .destroy
= intel_crtc_destroy
,
1587 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
1589 struct intel_crtc
*intel_crtc
;
1592 intel_crtc
= kzalloc(sizeof(struct intel_crtc
) + (INTELFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
1593 if (intel_crtc
== NULL
)
1596 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
1598 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
1599 intel_crtc
->pipe
= pipe
;
1600 for (i
= 0; i
< 256; i
++) {
1601 intel_crtc
->lut_r
[i
] = i
;
1602 intel_crtc
->lut_g
[i
] = i
;
1603 intel_crtc
->lut_b
[i
] = i
;
1606 intel_crtc
->cursor_addr
= 0;
1607 intel_crtc
->dpms_mode
= DRM_MODE_DPMS_OFF
;
1608 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
1610 intel_crtc
->mode_set
.crtc
= &intel_crtc
->base
;
1611 intel_crtc
->mode_set
.connectors
= (struct drm_connector
**)(intel_crtc
+ 1);
1612 intel_crtc
->mode_set
.num_connectors
= 0;
1614 if (i915_fbpercrtc
) {
1621 struct drm_crtc
*intel_get_crtc_from_pipe(struct drm_device
*dev
, int pipe
)
1623 struct drm_crtc
*crtc
= NULL
;
1625 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
1626 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1627 if (intel_crtc
->pipe
== pipe
)
1633 static int intel_connector_clones(struct drm_device
*dev
, int type_mask
)
1636 struct drm_connector
*connector
;
1639 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
1640 struct intel_output
*intel_output
= to_intel_output(connector
);
1641 if (type_mask
& (1 << intel_output
->type
))
1642 index_mask
|= (1 << entry
);
1649 static void intel_setup_outputs(struct drm_device
*dev
)
1651 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1652 struct drm_connector
*connector
;
1654 intel_crt_init(dev
);
1656 /* Set up integrated LVDS */
1657 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1658 intel_lvds_init(dev
);
1663 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
1664 found
= intel_sdvo_init(dev
, SDVOB
);
1665 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
))
1666 intel_hdmi_init(dev
, SDVOB
);
1668 if (!IS_G4X(dev
) || (I915_READ(SDVOB
) & SDVO_DETECTED
)) {
1669 found
= intel_sdvo_init(dev
, SDVOC
);
1670 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
))
1671 intel_hdmi_init(dev
, SDVOC
);
1674 intel_dvo_init(dev
);
1676 if (IS_I9XX(dev
) && IS_MOBILE(dev
))
1679 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
1680 struct intel_output
*intel_output
= to_intel_output(connector
);
1681 struct drm_encoder
*encoder
= &intel_output
->enc
;
1682 int crtc_mask
= 0, clone_mask
= 0;
1685 switch(intel_output
->type
) {
1686 case INTEL_OUTPUT_HDMI
:
1687 crtc_mask
= ((1 << 0)|
1689 clone_mask
= ((1 << INTEL_OUTPUT_HDMI
));
1691 case INTEL_OUTPUT_DVO
:
1692 case INTEL_OUTPUT_SDVO
:
1693 crtc_mask
= ((1 << 0)|
1695 clone_mask
= ((1 << INTEL_OUTPUT_ANALOG
) |
1696 (1 << INTEL_OUTPUT_DVO
) |
1697 (1 << INTEL_OUTPUT_SDVO
));
1699 case INTEL_OUTPUT_ANALOG
:
1700 crtc_mask
= ((1 << 0)|
1702 clone_mask
= ((1 << INTEL_OUTPUT_ANALOG
) |
1703 (1 << INTEL_OUTPUT_DVO
) |
1704 (1 << INTEL_OUTPUT_SDVO
));
1706 case INTEL_OUTPUT_LVDS
:
1707 crtc_mask
= (1 << 1);
1708 clone_mask
= (1 << INTEL_OUTPUT_LVDS
);
1710 case INTEL_OUTPUT_TVOUT
:
1711 crtc_mask
= ((1 << 0) |
1713 clone_mask
= (1 << INTEL_OUTPUT_TVOUT
);
1716 encoder
->possible_crtcs
= crtc_mask
;
1717 encoder
->possible_clones
= intel_connector_clones(dev
, clone_mask
);
1721 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
1723 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
1724 struct drm_device
*dev
= fb
->dev
;
1727 intelfb_remove(dev
, fb
);
1729 drm_framebuffer_cleanup(fb
);
1730 mutex_lock(&dev
->struct_mutex
);
1731 drm_gem_object_unreference(intel_fb
->obj
);
1732 mutex_unlock(&dev
->struct_mutex
);
1737 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
1738 struct drm_file
*file_priv
,
1739 unsigned int *handle
)
1741 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
1742 struct drm_gem_object
*object
= intel_fb
->obj
;
1744 return drm_gem_handle_create(file_priv
, object
, handle
);
1747 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
1748 .destroy
= intel_user_framebuffer_destroy
,
1749 .create_handle
= intel_user_framebuffer_create_handle
,
1752 int intel_framebuffer_create(struct drm_device
*dev
,
1753 struct drm_mode_fb_cmd
*mode_cmd
,
1754 struct drm_framebuffer
**fb
,
1755 struct drm_gem_object
*obj
)
1757 struct intel_framebuffer
*intel_fb
;
1760 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
1764 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
1766 DRM_ERROR("framebuffer init failed %d\n", ret
);
1770 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
1772 intel_fb
->obj
= obj
;
1774 *fb
= &intel_fb
->base
;
1780 static struct drm_framebuffer
*
1781 intel_user_framebuffer_create(struct drm_device
*dev
,
1782 struct drm_file
*filp
,
1783 struct drm_mode_fb_cmd
*mode_cmd
)
1785 struct drm_gem_object
*obj
;
1786 struct drm_framebuffer
*fb
;
1789 obj
= drm_gem_object_lookup(dev
, filp
, mode_cmd
->handle
);
1793 ret
= intel_framebuffer_create(dev
, mode_cmd
, &fb
, obj
);
1795 mutex_lock(&dev
->struct_mutex
);
1796 drm_gem_object_unreference(obj
);
1797 mutex_unlock(&dev
->struct_mutex
);
1804 static const struct drm_mode_config_funcs intel_mode_funcs
= {
1805 .fb_create
= intel_user_framebuffer_create
,
1806 .fb_changed
= intelfb_probe
,
1809 void intel_modeset_init(struct drm_device
*dev
)
1814 drm_mode_config_init(dev
);
1816 dev
->mode_config
.min_width
= 0;
1817 dev
->mode_config
.min_height
= 0;
1819 dev
->mode_config
.funcs
= (void *)&intel_mode_funcs
;
1821 if (IS_I965G(dev
)) {
1822 dev
->mode_config
.max_width
= 8192;
1823 dev
->mode_config
.max_height
= 8192;
1825 dev
->mode_config
.max_width
= 2048;
1826 dev
->mode_config
.max_height
= 2048;
1829 /* set memory base */
1831 dev
->mode_config
.fb_base
= pci_resource_start(dev
->pdev
, 2);
1833 dev
->mode_config
.fb_base
= pci_resource_start(dev
->pdev
, 0);
1835 if (IS_MOBILE(dev
) || IS_I9XX(dev
))
1839 DRM_DEBUG("%d display pipe%s available.\n",
1840 num_pipe
, num_pipe
> 1 ? "s" : "");
1842 for (i
= 0; i
< num_pipe
; i
++) {
1843 intel_crtc_init(dev
, i
);
1846 intel_setup_outputs(dev
);
1849 void intel_modeset_cleanup(struct drm_device
*dev
)
1851 drm_mode_config_cleanup(dev
);
1855 /* current intel driver doesn't take advantage of encoders
1856 always give back the encoder for the connector
1858 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
1860 struct intel_output
*intel_output
= to_intel_output(connector
);
1862 return &intel_output
->enc
;