include/drm/i915_drm.h

   1 /*
   2  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial portions
  15  * of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  18  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  20  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  21  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  22  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  23  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #ifndef _I915_DRM_H_
  28 #define _I915_DRM_H_
  29
  30 /* Please note that modifications to all structs defined here are
  31  * subject to backwards-compatibility constraints.
  32  */
  33
  34 #include "drm.h"
  35
  36 /* Each region is a minimum of 16k, and there are at most 255 of them.
  37  */
  38 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
  39                                  * of chars for next/prev indices */
  40 #define I915_LOG_MIN_TEX_REGION_SIZE 14
  41
  42 typedef struct _drm_i915_init {
  43         enum {
  44                 I915_INIT_DMA = 0x01,
  45                 I915_CLEANUP_DMA = 0x02,
  46                 I915_RESUME_DMA = 0x03
  47         } func;
  48         unsigned int mmio_offset;
  49         int sarea_priv_offset;
  50         unsigned int ring_start;
  51         unsigned int ring_end;
  52         unsigned int ring_size;
  53         unsigned int front_offset;
  54         unsigned int back_offset;
  55         unsigned int depth_offset;
  56         unsigned int w;
  57         unsigned int h;
  58         unsigned int pitch;
  59         unsigned int pitch_bits;
  60         unsigned int back_pitch;
  61         unsigned int depth_pitch;
  62         unsigned int cpp;
  63         unsigned int chipset;
  64 } drm_i915_init_t;
  65
  66 typedef struct _drm_i915_sarea {
  67         struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
  68         int last_upload;        /* last time texture was uploaded */
  69         int last_enqueue;       /* last time a buffer was enqueued */
  70         int last_dispatch;      /* age of the most recently dispatched buffer */
  71         int ctxOwner;           /* last context to upload state */
  72         int texAge;
  73         int pf_enabled;         /* is pageflipping allowed? */
  74         int pf_active;
  75         int pf_current_page;    /* which buffer is being displayed? */
  76         int perf_boxes;         /* performance boxes to be displayed */
  77         int width, height;      /* screen size in pixels */
  78
  79         drm_handle_t front_handle;
  80         int front_offset;
  81         int front_size;
  82
  83         drm_handle_t back_handle;
  84         int back_offset;
  85         int back_size;
  86
  87         drm_handle_t depth_handle;
  88         int depth_offset;
  89         int depth_size;
  90
  91         drm_handle_t tex_handle;
  92         int tex_offset;
  93         int tex_size;
  94         int log_tex_granularity;
  95         int pitch;
  96         int rotation;           /* 0, 90, 180 or 270 */
  97         int rotated_offset;
  98         int rotated_size;
  99         int rotated_pitch;
 100         int virtualX, virtualY;
 101
 102         unsigned int front_tiled;
 103         unsigned int back_tiled;
 104         unsigned int depth_tiled;
 105         unsigned int rotated_tiled;
 106         unsigned int rotated2_tiled;
 107
 108         int pipeA_x;
 109         int pipeA_y;
 110         int pipeA_w;
 111         int pipeA_h;
 112         int pipeB_x;
 113         int pipeB_y;
 114         int pipeB_w;
 115         int pipeB_h;
 116
 117         /* fill out some space for old userspace triple buffer */
 118         drm_handle_t unused_handle;
 119         uint32_t unused1, unused2, unused3;
 120
 121         /* buffer object handles for static buffers. May change
 122          * over the lifetime of the client.
 123          */
 124         uint32_t front_bo_handle;
 125         uint32_t back_bo_handle;
 126         uint32_t unused_bo_handle;
 127         uint32_t depth_bo_handle;
 128
 129 } drm_i915_sarea_t;
 130
 131 /* due to userspace building against these headers we need some compat here */
 132 #define planeA_x pipeA_x
 133 #define planeA_y pipeA_y
 134 #define planeA_w pipeA_w
 135 #define planeA_h pipeA_h
 136 #define planeB_x pipeB_x
 137 #define planeB_y pipeB_y
 138 #define planeB_w pipeB_w
 139 #define planeB_h pipeB_h
 140
 141 /* Flags for perf_boxes
 142  */
 143 #define I915_BOX_RING_EMPTY    0x1
 144 #define I915_BOX_FLIP          0x2
 145 #define I915_BOX_WAIT          0x4
 146 #define I915_BOX_TEXTURE_LOAD  0x8
 147 #define I915_BOX_LOST_CONTEXT  0x10
 148
 149 /* I915 specific ioctls
 150  * The device specific ioctl range is 0x40 to 0x79.
 151  */
 152 #define DRM_I915_INIT           0x00
 153 #define DRM_I915_FLUSH          0x01
 154 #define DRM_I915_FLIP           0x02
 155 #define DRM_I915_BATCHBUFFER    0x03
 156 #define DRM_I915_IRQ_EMIT       0x04
 157 #define DRM_I915_IRQ_WAIT       0x05
 158 #define DRM_I915_GETPARAM       0x06
 159 #define DRM_I915_SETPARAM       0x07
 160 #define DRM_I915_ALLOC          0x08
 161 #define DRM_I915_FREE           0x09
 162 #define DRM_I915_INIT_HEAP      0x0a
 163 #define DRM_I915_CMDBUFFER      0x0b
 164 #define DRM_I915_DESTROY_HEAP   0x0c
 165 #define DRM_I915_SET_VBLANK_PIPE        0x0d
 166 #define DRM_I915_GET_VBLANK_PIPE        0x0e
 167 #define DRM_I915_VBLANK_SWAP    0x0f
 168 #define DRM_I915_HWS_ADDR       0x11
 169 #define DRM_I915_GEM_INIT       0x13
 170 #define DRM_I915_GEM_EXECBUFFER 0x14
 171 #define DRM_I915_GEM_PIN        0x15
 172 #define DRM_I915_GEM_UNPIN      0x16
 173 #define DRM_I915_GEM_BUSY       0x17
 174 #define DRM_I915_GEM_THROTTLE   0x18
 175 #define DRM_I915_GEM_ENTERVT    0x19
 176 #define DRM_I915_GEM_LEAVEVT    0x1a
 177 #define DRM_I915_GEM_CREATE     0x1b
 178 #define DRM_I915_GEM_PREAD      0x1c
 179 #define DRM_I915_GEM_PWRITE     0x1d
 180 #define DRM_I915_GEM_MMAP       0x1e
 181 #define DRM_I915_GEM_SET_DOMAIN 0x1f
 182 #define DRM_I915_GEM_SW_FINISH  0x20
 183 #define DRM_I915_GEM_SET_TILING 0x21
 184 #define DRM_I915_GEM_GET_TILING 0x22
 185 #define DRM_I915_GEM_GET_APERTURE 0x23
 186 #define DRM_I915_GEM_MMAP_GTT   0x24
 187
 188 #define DRM_IOCTL_I915_INIT             DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
 189 #define DRM_IOCTL_I915_FLUSH            DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
 190 #define DRM_IOCTL_I915_FLIP             DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
 191 #define DRM_IOCTL_I915_BATCHBUFFER      DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
 192 #define DRM_IOCTL_I915_IRQ_EMIT         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
 193 #define DRM_IOCTL_I915_IRQ_WAIT         DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
 194 #define DRM_IOCTL_I915_GETPARAM         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
 195 #define DRM_IOCTL_I915_SETPARAM         DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
 196 #define DRM_IOCTL_I915_ALLOC            DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
 197 #define DRM_IOCTL_I915_FREE             DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
 198 #define DRM_IOCTL_I915_INIT_HEAP        DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
 199 #define DRM_IOCTL_I915_CMDBUFFER        DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
 200 #define DRM_IOCTL_I915_DESTROY_HEAP     DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
 201 #define DRM_IOCTL_I915_SET_VBLANK_PIPE  DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
 202 #define DRM_IOCTL_I915_GET_VBLANK_PIPE  DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
 203 #define DRM_IOCTL_I915_VBLANK_SWAP      DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
 204 #define DRM_IOCTL_I915_GEM_INIT         DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
 205 #define DRM_IOCTL_I915_GEM_EXECBUFFER   DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
 206 #define DRM_IOCTL_I915_GEM_PIN          DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
 207 #define DRM_IOCTL_I915_GEM_UNPIN        DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
 208 #define DRM_IOCTL_I915_GEM_BUSY         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
 209 #define DRM_IOCTL_I915_GEM_THROTTLE     DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
 210 #define DRM_IOCTL_I915_GEM_ENTERVT      DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
 211 #define DRM_IOCTL_I915_GEM_LEAVEVT      DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
 212 #define DRM_IOCTL_I915_GEM_CREATE       DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
 213 #define DRM_IOCTL_I915_GEM_PREAD        DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
 214 #define DRM_IOCTL_I915_GEM_PWRITE       DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
 215 #define DRM_IOCTL_I915_GEM_MMAP         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
 216 #define DRM_IOCTL_I915_GEM_MMAP_GTT     DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
 217 #define DRM_IOCTL_I915_GEM_SET_DOMAIN   DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
 218 #define DRM_IOCTL_I915_GEM_SW_FINISH    DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
 219 #define DRM_IOCTL_I915_GEM_SET_TILING   DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
 220 #define DRM_IOCTL_I915_GEM_GET_TILING   DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
 221 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR  (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
 222
 223 /* Allow drivers to submit batchbuffers directly to hardware, relying
 224  * on the security mechanisms provided by hardware.
 225  */
 226 typedef struct drm_i915_batchbuffer {
 227         int start;              /* agp offset */
 228         int used;               /* nr bytes in use */
 229         int DR1;                /* hw flags for GFX_OP_DRAWRECT_INFO */
 230         int DR4;                /* window origin for GFX_OP_DRAWRECT_INFO */
 231         int num_cliprects;      /* mulitpass with multiple cliprects? */
 232         struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
 233 } drm_i915_batchbuffer_t;
 234
 235 /* As above, but pass a pointer to userspace buffer which can be
 236  * validated by the kernel prior to sending to hardware.
 237  */
 238 typedef struct _drm_i915_cmdbuffer {
 239         char __user *buf;       /* pointer to userspace command buffer */
 240         int sz;                 /* nr bytes in buf */
 241         int DR1;                /* hw flags for GFX_OP_DRAWRECT_INFO */
 242         int DR4;                /* window origin for GFX_OP_DRAWRECT_INFO */
 243         int num_cliprects;      /* mulitpass with multiple cliprects? */
 244         struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
 245 } drm_i915_cmdbuffer_t;
 246
 247 /* Userspace can request & wait on irq's:
 248  */
 249 typedef struct drm_i915_irq_emit {
 250         int __user *irq_seq;
 251 } drm_i915_irq_emit_t;
 252
 253 typedef struct drm_i915_irq_wait {
 254         int irq_seq;
 255 } drm_i915_irq_wait_t;
 256
 257 /* Ioctl to query kernel params:
 258  */
 259 #define I915_PARAM_IRQ_ACTIVE            1
 260 #define I915_PARAM_ALLOW_BATCHBUFFER     2
 261 #define I915_PARAM_LAST_DISPATCH         3
 262 #define I915_PARAM_CHIPSET_ID            4
 263 #define I915_PARAM_HAS_GEM               5
 264 #define I915_PARAM_NUM_FENCES_AVAIL      6
 265
 266 typedef struct drm_i915_getparam {
 267         int param;
 268         int __user *value;
 269 } drm_i915_getparam_t;
 270
 271 /* Ioctl to set kernel params:
 272  */
 273 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START            1
 274 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY             2
 275 #define I915_SETPARAM_ALLOW_BATCHBUFFER                   3
 276 #define I915_SETPARAM_NUM_USED_FENCES                     4
 277
 278 typedef struct drm_i915_setparam {
 279         int param;
 280         int value;
 281 } drm_i915_setparam_t;
 282
 283 /* A memory manager for regions of shared memory:
 284  */
 285 #define I915_MEM_REGION_AGP 1
 286
 287 typedef struct drm_i915_mem_alloc {
 288         int region;
 289         int alignment;
 290         int size;
 291         int __user *region_offset;      /* offset from start of fb or agp */
 292 } drm_i915_mem_alloc_t;
 293
 294 typedef struct drm_i915_mem_free {
 295         int region;
 296         int region_offset;
 297 } drm_i915_mem_free_t;
 298
 299 typedef struct drm_i915_mem_init_heap {
 300         int region;
 301         int size;
 302         int start;
 303 } drm_i915_mem_init_heap_t;
 304
 305 /* Allow memory manager to be torn down and re-initialized (eg on
 306  * rotate):
 307  */
 308 typedef struct drm_i915_mem_destroy_heap {
 309         int region;
 310 } drm_i915_mem_destroy_heap_t;
 311
 312 /* Allow X server to configure which pipes to monitor for vblank signals
 313  */
 314 #define DRM_I915_VBLANK_PIPE_A  1
 315 #define DRM_I915_VBLANK_PIPE_B  2
 316
 317 typedef struct drm_i915_vblank_pipe {
 318         int pipe;
 319 } drm_i915_vblank_pipe_t;
 320
 321 /* Schedule buffer swap at given vertical blank:
 322  */
 323 typedef struct drm_i915_vblank_swap {
 324         drm_drawable_t drawable;
 325         enum drm_vblank_seq_type seqtype;
 326         unsigned int sequence;
 327 } drm_i915_vblank_swap_t;
 328
 329 typedef struct drm_i915_hws_addr {
 330         uint64_t addr;
 331 } drm_i915_hws_addr_t;
 332
 333 struct drm_i915_gem_init {
 334         /**
 335          * Beginning offset in the GTT to be managed by the DRM memory
 336          * manager.
 337          */
 338         uint64_t gtt_start;
 339         /**
 340          * Ending offset in the GTT to be managed by the DRM memory
 341          * manager.
 342          */
 343         uint64_t gtt_end;
 344 };
 345
 346 struct drm_i915_gem_create {
 347         /**
 348          * Requested size for the object.
 349          *
 350          * The (page-aligned) allocated size for the object will be returned.
 351          */
 352         uint64_t size;
 353         /**
 354          * Returned handle for the object.
 355          *
 356          * Object handles are nonzero.
 357          */
 358         uint32_t handle;
 359         uint32_t pad;
 360 };
 361
 362 struct drm_i915_gem_pread {
 363         /** Handle for the object being read. */
 364         uint32_t handle;
 365         uint32_t pad;
 366         /** Offset into the object to read from */
 367         uint64_t offset;
 368         /** Length of data to read */
 369         uint64_t size;
 370         /**
 371          * Pointer to write the data into.
 372          *
 373          * This is a fixed-size type for 32/64 compatibility.
 374          */
 375         uint64_t data_ptr;
 376 };
 377
 378 struct drm_i915_gem_pwrite {
 379         /** Handle for the object being written to. */
 380         uint32_t handle;
 381         uint32_t pad;
 382         /** Offset into the object to write to */
 383         uint64_t offset;
 384         /** Length of data to write */
 385         uint64_t size;
 386         /**
 387          * Pointer to read the data from.
 388          *
 389          * This is a fixed-size type for 32/64 compatibility.
 390          */
 391         uint64_t data_ptr;
 392 };
 393
 394 struct drm_i915_gem_mmap {
 395         /** Handle for the object being mapped. */
 396         uint32_t handle;
 397         uint32_t pad;
 398         /** Offset in the object to map. */
 399         uint64_t offset;
 400         /**
 401          * Length of data to map.
 402          *
 403          * The value will be page-aligned.
 404          */
 405         uint64_t size;
 406         /**
 407          * Returned pointer the data was mapped at.
 408          *
 409          * This is a fixed-size type for 32/64 compatibility.
 410          */
 411         uint64_t addr_ptr;
 412 };
 413
 414 struct drm_i915_gem_mmap_gtt {
 415         /** Handle for the object being mapped. */
 416         uint32_t handle;
 417         uint32_t pad;
 418         /**
 419          * Fake offset to use for subsequent mmap call
 420          *
 421          * This is a fixed-size type for 32/64 compatibility.
 422          */
 423         uint64_t offset;
 424 };
 425
 426 struct drm_i915_gem_set_domain {
 427         /** Handle for the object */
 428         uint32_t handle;
 429
 430         /** New read domains */
 431         uint32_t read_domains;
 432
 433         /** New write domain */
 434         uint32_t write_domain;
 435 };
 436
 437 struct drm_i915_gem_sw_finish {
 438         /** Handle for the object */
 439         uint32_t handle;
 440 };
 441
 442 struct drm_i915_gem_relocation_entry {
 443         /**
 444          * Handle of the buffer being pointed to by this relocation entry.
 445          *
 446          * It's appealing to make this be an index into the mm_validate_entry
 447          * list to refer to the buffer, but this allows the driver to create
 448          * a relocation list for state buffers and not re-write it per
 449          * exec using the buffer.
 450          */
 451         uint32_t target_handle;
 452
 453         /**
 454          * Value to be added to the offset of the target buffer to make up
 455          * the relocation entry.
 456          */
 457         uint32_t delta;
 458
 459         /** Offset in the buffer the relocation entry will be written into */
 460         uint64_t offset;
 461
 462         /**
 463          * Offset value of the target buffer that the relocation entry was last
 464          * written as.
 465          *
 466          * If the buffer has the same offset as last time, we can skip syncing
 467          * and writing the relocation.  This value is written back out by
 468          * the execbuffer ioctl when the relocation is written.
 469          */
 470         uint64_t presumed_offset;
 471
 472         /**
 473          * Target memory domains read by this operation.
 474          */
 475         uint32_t read_domains;
 476
 477         /**
 478          * Target memory domains written by this operation.
 479          *
 480          * Note that only one domain may be written by the whole
 481          * execbuffer operation, so that where there are conflicts,
 482          * the application will get -EINVAL back.
 483          */
 484         uint32_t write_domain;
 485 };
 486
 487 /** @{
 488  * Intel memory domains
 489  *
 490  * Most of these just align with the various caches in
 491  * the system and are used to flush and invalidate as
 492  * objects end up cached in different domains.
 493  */
 494 /** CPU cache */
 495 #define I915_GEM_DOMAIN_CPU             0x00000001
 496 /** Render cache, used by 2D and 3D drawing */
 497 #define I915_GEM_DOMAIN_RENDER          0x00000002
 498 /** Sampler cache, used by texture engine */
 499 #define I915_GEM_DOMAIN_SAMPLER         0x00000004
 500 /** Command queue, used to load batch buffers */
 501 #define I915_GEM_DOMAIN_COMMAND         0x00000008
 502 /** Instruction cache, used by shader programs */
 503 #define I915_GEM_DOMAIN_INSTRUCTION     0x00000010
 504 /** Vertex address cache */
 505 #define I915_GEM_DOMAIN_VERTEX          0x00000020
 506 /** GTT domain - aperture and scanout */
 507 #define I915_GEM_DOMAIN_GTT             0x00000040
 508 /** @} */
 509
 510 struct drm_i915_gem_exec_object {
 511         /**
 512          * User's handle for a buffer to be bound into the GTT for this
 513          * operation.
 514          */
 515         uint32_t handle;
 516
 517         /** Number of relocations to be performed on this buffer */
 518         uint32_t relocation_count;
 519         /**
 520          * Pointer to array of struct drm_i915_gem_relocation_entry containing
 521          * the relocations to be performed in this buffer.
 522          */
 523         uint64_t relocs_ptr;
 524
 525         /** Required alignment in graphics aperture */
 526         uint64_t alignment;
 527
 528         /**
 529          * Returned value of the updated offset of the object, for future
 530          * presumed_offset writes.
 531          */
 532         uint64_t offset;
 533 };
 534
 535 struct drm_i915_gem_execbuffer {
 536         /**
 537          * List of buffers to be validated with their relocations to be
 538          * performend on them.
 539          *
 540          * This is a pointer to an array of struct drm_i915_gem_validate_entry.
 541          *
 542          * These buffers must be listed in an order such that all relocations
 543          * a buffer is performing refer to buffers that have already appeared
 544          * in the validate list.
 545          */
 546         uint64_t buffers_ptr;
 547         uint32_t buffer_count;
 548
 549         /** Offset in the batchbuffer to start execution from. */
 550         uint32_t batch_start_offset;
 551         /** Bytes used in batchbuffer from batch_start_offset */
 552         uint32_t batch_len;
 553         uint32_t DR1;
 554         uint32_t DR4;
 555         uint32_t num_cliprects;
 556         /** This is a struct drm_clip_rect *cliprects */
 557         uint64_t cliprects_ptr;
 558 };
 559
 560 struct drm_i915_gem_pin {
 561         /** Handle of the buffer to be pinned. */
 562         uint32_t handle;
 563         uint32_t pad;
 564
 565         /** alignment required within the aperture */
 566         uint64_t alignment;
 567
 568         /** Returned GTT offset of the buffer. */
 569         uint64_t offset;
 570 };
 571
 572 struct drm_i915_gem_unpin {
 573         /** Handle of the buffer to be unpinned. */
 574         uint32_t handle;
 575         uint32_t pad;
 576 };
 577
 578 struct drm_i915_gem_busy {
 579         /** Handle of the buffer to check for busy */
 580         uint32_t handle;
 581
 582         /** Return busy status (1 if busy, 0 if idle) */
 583         uint32_t busy;
 584 };
 585
 586 #define I915_TILING_NONE        0
 587 #define I915_TILING_X           1
 588 #define I915_TILING_Y           2
 589
 590 #define I915_BIT_6_SWIZZLE_NONE         0
 591 #define I915_BIT_6_SWIZZLE_9            1
 592 #define I915_BIT_6_SWIZZLE_9_10         2
 593 #define I915_BIT_6_SWIZZLE_9_11         3
 594 #define I915_BIT_6_SWIZZLE_9_10_11      4
 595 /* Not seen by userland */
 596 #define I915_BIT_6_SWIZZLE_UNKNOWN      5
 597
 598 struct drm_i915_gem_set_tiling {
 599         /** Handle of the buffer to have its tiling state updated */
 600         uint32_t handle;
 601
 602         /**
 603          * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
 604          * I915_TILING_Y).
 605          *
 606          * This value is to be set on request, and will be updated by the
 607          * kernel on successful return with the actual chosen tiling layout.
 608          *
 609          * The tiling mode may be demoted to I915_TILING_NONE when the system
 610          * has bit 6 swizzling that can't be managed correctly by GEM.
 611          *
 612          * Buffer contents become undefined when changing tiling_mode.
 613          */
 614         uint32_t tiling_mode;
 615
 616         /**
 617          * Stride in bytes for the object when in I915_TILING_X or
 618          * I915_TILING_Y.
 619          */
 620         uint32_t stride;
 621
 622         /**
 623          * Returned address bit 6 swizzling required for CPU access through
 624          * mmap mapping.
 625          */
 626         uint32_t swizzle_mode;
 627 };
 628
 629 struct drm_i915_gem_get_tiling {
 630         /** Handle of the buffer to get tiling state for. */
 631         uint32_t handle;
 632
 633         /**
 634          * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
 635          * I915_TILING_Y).
 636          */
 637         uint32_t tiling_mode;
 638
 639         /**
 640          * Returned address bit 6 swizzling required for CPU access through
 641          * mmap mapping.
 642          */
 643         uint32_t swizzle_mode;
 644 };
 645
 646 struct drm_i915_gem_get_aperture {
 647         /** Total size of the aperture used by i915_gem_execbuffer, in bytes */
 648         uint64_t aper_size;
 649
 650         /**
 651          * Available space in the aperture used by i915_gem_execbuffer, in
 652          * bytes
 653          */
 654         uint64_t aper_available_size;
 655 };
 656
 657 #endif                          /* _I915_DRM_H_ */