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[ARM] 3266/1: S3C2400 - adds macro S3C24XX
[linux-2.6/mini2440.git] / drivers / serial / s3c2410.c
blob0a2dd6c5b95fdecc116e78a4090552e31be90eaa
1 /*
2 * linux/drivers/serial/s3c2410.c
3 *
4 * Driver for onboard UARTs on the Samsung S3C24XX
5 *
6 * Based on drivers/char/serial.c and drivers/char/21285.c
7 *
8 * Ben Dooks, (c) 2003-2005 Simtec Electronics
9 * http://www.simtec.co.uk/products/SWLINUX/
10 *
11 * Changelog:
12 *
13 * 22-Jul-2004 BJD Finished off device rewrite
14 *
15 * 21-Jul-2004 BJD Thanks to <herbet@13thfloor.at> for pointing out
16 * problems with baud rate and loss of IR settings. Update
17 * to add configuration via platform_device structure
18 *
19 * 28-Sep-2004 BJD Re-write for the following items
20 * - S3C2410 and S3C2440 serial support
21 * - Power Management support
22 * - Fix console via IrDA devices
23 * - SysReq (Herbert Pötzl)
24 * - Break character handling (Herbert Pötzl)
25 * - spin-lock initialisation (Dimitry Andric)
26 * - added clock control
27 * - updated init code to use platform_device info
28 *
29 * 06-Mar-2005 BJD Add s3c2440 fclk clock source
30 *
31 * 09-Mar-2005 BJD Add s3c2400 support
32 *
33 * 10-Mar-2005 LCVR Changed S3C2410_VA_UART to S3C24XX_VA_UART
34 */
35
36 /* Note on 2440 fclk clock source handling
37 *
38 * Whilst it is possible to use the fclk as clock source, the method
39 * of properly switching too/from this is currently un-implemented, so
40 * whichever way is configured at startup is the one that will be used.
41 */
42
43 /* Hote on 2410 error handling
44 *
45 * The s3c2410 manual has a love/hate affair with the contents of the
46 * UERSTAT register in the UART blocks, and keeps marking some of the
47 * error bits as reserved. Having checked with the s3c2410x01,
48 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
49 * feature from the latter versions of the manual.
50 *
51 * If it becomes aparrent that latter versions of the 2410 remove these
52 * bits, then action will have to be taken to differentiate the versions
53 * and change the policy on BREAK
54 *
55 * BJD, 04-Nov-2004
56 */
57
58 #include <linux/config.h>
59
60 #if defined(CONFIG_SERIAL_S3C2410_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
61 #define SUPPORT_SYSRQ
62 #endif
63
64 #include <linux/module.h>
65 #include <linux/ioport.h>
66 #include <linux/platform_device.h>
67 #include <linux/init.h>
68 #include <linux/sysrq.h>
69 #include <linux/console.h>
70 #include <linux/tty.h>
71 #include <linux/tty_flip.h>
72 #include <linux/serial_core.h>
73 #include <linux/serial.h>
74 #include <linux/delay.h>
75 #include <linux/clk.h>
76
77 #include <asm/io.h>
78 #include <asm/irq.h>
79
80 #include <asm/hardware.h>
81
82 #include <asm/arch/regs-serial.h>
83 #include <asm/arch/regs-gpio.h>
84
85 /* structures */
86
87 struct s3c24xx_uart_info {
88 char *name;
89 unsigned int type;
90 unsigned int fifosize;
91 unsigned long rx_fifomask;
92 unsigned long rx_fifoshift;
93 unsigned long rx_fifofull;
94 unsigned long tx_fifomask;
95 unsigned long tx_fifoshift;
96 unsigned long tx_fifofull;
97
98 /* clock source control */
99
100 int (*get_clksrc)(struct uart_port *, struct s3c24xx_uart_clksrc *clk);
101 int (*set_clksrc)(struct uart_port *, struct s3c24xx_uart_clksrc *clk);
102
103 /* uart controls */
104 int (*reset_port)(struct uart_port *, struct s3c2410_uartcfg *);
105 };
106
107 struct s3c24xx_uart_port {
108 unsigned char rx_claimed;
109 unsigned char tx_claimed;
110
111 struct s3c24xx_uart_info *info;
112 struct s3c24xx_uart_clksrc *clksrc;
113 struct clk *clk;
114 struct clk *baudclk;
115 struct uart_port port;
116 };
117
118
119 /* configuration defines */
120
121 #if 0
122 #if 1
123 /* send debug to the low-level output routines */
124
125 extern void printascii(const char *);
126
127 static void
128 s3c24xx_serial_dbg(const char *fmt, ...)
129 {
130 va_list va;
131 char buff[256];
132
133 va_start(va, fmt);
134 vsprintf(buff, fmt, va);
135 va_end(va);
136
137 printascii(buff);
138 }
139
140 #define dbg(x...) s3c24xx_serial_dbg(x)
141
142 #else
143 #define dbg(x...) printk(KERN_DEBUG "s3c24xx: ");
144 #endif
145 #else /* no debug */
146 #define dbg(x...) do {} while(0)
147 #endif
148
149 /* UART name and device definitions */
150
151 #define S3C24XX_SERIAL_NAME "ttySAC"
152 #define S3C24XX_SERIAL_DEVFS "tts/"
153 #define S3C24XX_SERIAL_MAJOR 204
154 #define S3C24XX_SERIAL_MINOR 64
155
156
157 /* conversion functions */
158
159 #define s3c24xx_dev_to_port(__dev) (struct uart_port *)dev_get_drvdata(__dev)
160 #define s3c24xx_dev_to_cfg(__dev) (struct s3c2410_uartcfg *)((__dev)->platform_data)
161
162 /* we can support 3 uarts, but not always use them */
163
164 #define NR_PORTS (3)
165
166 /* port irq numbers */
167
168 #define TX_IRQ(port) ((port)->irq + 1)
169 #define RX_IRQ(port) ((port)->irq)
170
171 /* register access controls */
172
173 #define portaddr(port, reg) ((port)->membase + (reg))
174
175 #define rd_regb(port, reg) (__raw_readb(portaddr(port, reg)))
176 #define rd_regl(port, reg) (__raw_readl(portaddr(port, reg)))
177
178 #define wr_regb(port, reg, val) \
179 do { __raw_writeb(val, portaddr(port, reg)); } while(0)
180
181 #define wr_regl(port, reg, val) \
182 do { __raw_writel(val, portaddr(port, reg)); } while(0)
183
184 /* macros to change one thing to another */
185
186 #define tx_enabled(port) ((port)->unused[0])
187 #define rx_enabled(port) ((port)->unused[1])
188
189 /* flag to ignore all characters comming in */
190 #define RXSTAT_DUMMY_READ (0x10000000)
191
192 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
193 {
194 return container_of(port, struct s3c24xx_uart_port, port);
195 }
196
197 /* translate a port to the device name */
198
199 static inline const char *s3c24xx_serial_portname(struct uart_port *port)
200 {
201 return to_platform_device(port->dev)->name;
202 }
203
204 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
205 {
206 return (rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE);
207 }
208
209 static void s3c24xx_serial_rx_enable(struct uart_port *port)
210 {
211 unsigned long flags;
212 unsigned int ucon, ufcon;
213 int count = 10000;
214
215 spin_lock_irqsave(&port->lock, flags);
216
217 while (--count && !s3c24xx_serial_txempty_nofifo(port))
218 udelay(100);
219
220 ufcon = rd_regl(port, S3C2410_UFCON);
221 ufcon |= S3C2410_UFCON_RESETRX;
222 wr_regl(port, S3C2410_UFCON, ufcon);
223
224 ucon = rd_regl(port, S3C2410_UCON);
225 ucon |= S3C2410_UCON_RXIRQMODE;
226 wr_regl(port, S3C2410_UCON, ucon);
227
228 rx_enabled(port) = 1;
229 spin_unlock_irqrestore(&port->lock, flags);
230 }
231
232 static void s3c24xx_serial_rx_disable(struct uart_port *port)
233 {
234 unsigned long flags;
235 unsigned int ucon;
236
237 spin_lock_irqsave(&port->lock, flags);
238
239 ucon = rd_regl(port, S3C2410_UCON);
240 ucon &= ~S3C2410_UCON_RXIRQMODE;
241 wr_regl(port, S3C2410_UCON, ucon);
242
243 rx_enabled(port) = 0;
244 spin_unlock_irqrestore(&port->lock, flags);
245 }
246
247 static void s3c24xx_serial_stop_tx(struct uart_port *port)
248 {
249 if (tx_enabled(port)) {
250 disable_irq(TX_IRQ(port));
251 tx_enabled(port) = 0;
252 if (port->flags & UPF_CONS_FLOW)
253 s3c24xx_serial_rx_enable(port);
254 }
255 }
256
257 static void s3c24xx_serial_start_tx(struct uart_port *port)
258 {
259 if (!tx_enabled(port)) {
260 if (port->flags & UPF_CONS_FLOW)
261 s3c24xx_serial_rx_disable(port);
262
263 enable_irq(TX_IRQ(port));
264 tx_enabled(port) = 1;
265 }
266 }
267
268
269 static void s3c24xx_serial_stop_rx(struct uart_port *port)
270 {
271 if (rx_enabled(port)) {
272 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
273 disable_irq(RX_IRQ(port));
274 rx_enabled(port) = 0;
275 }
276 }
277
278 static void s3c24xx_serial_enable_ms(struct uart_port *port)
279 {
280 }
281
282 static inline struct s3c24xx_uart_info *s3c24xx_port_to_info(struct uart_port *port)
283 {
284 return to_ourport(port)->info;
285 }
286
287 static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port *port)
288 {
289 if (port->dev == NULL)
290 return NULL;
291
292 return (struct s3c2410_uartcfg *)port->dev->platform_data;
293 }
294
295 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
296 unsigned long ufstat)
297 {
298 struct s3c24xx_uart_info *info = ourport->info;
299
300 if (ufstat & info->rx_fifofull)
301 return info->fifosize;
302
303 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
304 }
305
306
307 /* ? - where has parity gone?? */
308 #define S3C2410_UERSTAT_PARITY (0x1000)
309
310 static irqreturn_t
311 s3c24xx_serial_rx_chars(int irq, void *dev_id, struct pt_regs *regs)
312 {
313 struct s3c24xx_uart_port *ourport = dev_id;
314 struct uart_port *port = &ourport->port;
315 struct tty_struct *tty = port->info->tty;
316 unsigned int ufcon, ch, flag, ufstat, uerstat;
317 int max_count = 64;
318
319 while (max_count-- > 0) {
320 ufcon = rd_regl(port, S3C2410_UFCON);
321 ufstat = rd_regl(port, S3C2410_UFSTAT);
322
323 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
324 break;
325
326 uerstat = rd_regl(port, S3C2410_UERSTAT);
327 ch = rd_regb(port, S3C2410_URXH);
328
329 if (port->flags & UPF_CONS_FLOW) {
330 int txe = s3c24xx_serial_txempty_nofifo(port);
331
332 if (rx_enabled(port)) {
333 if (!txe) {
334 rx_enabled(port) = 0;
335 continue;
336 }
337 } else {
338 if (txe) {
339 ufcon |= S3C2410_UFCON_RESETRX;
340 wr_regl(port, S3C2410_UFCON, ufcon);
341 rx_enabled(port) = 1;
342 goto out;
343 }
344 continue;
345 }
346 }
347
348 /* insert the character into the buffer */
349
350 flag = TTY_NORMAL;
351 port->icount.rx++;
352
353 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
354 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
355 ch, uerstat);
356
357 /* check for break */
358 if (uerstat & S3C2410_UERSTAT_BREAK) {
359 dbg("break!\n");
360 port->icount.brk++;
361 if (uart_handle_break(port))
362 goto ignore_char;
363 }
364
365 if (uerstat & S3C2410_UERSTAT_FRAME)
366 port->icount.frame++;
367 if (uerstat & S3C2410_UERSTAT_OVERRUN)
368 port->icount.overrun++;
369
370 uerstat &= port->read_status_mask;
371
372 if (uerstat & S3C2410_UERSTAT_BREAK)
373 flag = TTY_BREAK;
374 else if (uerstat & S3C2410_UERSTAT_PARITY)
375 flag = TTY_PARITY;
376 else if (uerstat & ( S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_OVERRUN))
377 flag = TTY_FRAME;
378 }
379
380 if (uart_handle_sysrq_char(port, ch, regs))
381 goto ignore_char;
382
383 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN, ch, flag);
384
385 ignore_char:
386 continue;
387 }
388 tty_flip_buffer_push(tty);
389
390 out:
391 return IRQ_HANDLED;
392 }
393
394 static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id, struct pt_regs *regs)
395 {
396 struct s3c24xx_uart_port *ourport = id;
397 struct uart_port *port = &ourport->port;
398 struct circ_buf *xmit = &port->info->xmit;
399 int count = 256;
400
401 if (port->x_char) {
402 wr_regb(port, S3C2410_UTXH, port->x_char);
403 port->icount.tx++;
404 port->x_char = 0;
405 goto out;
406 }
407
408 /* if there isnt anything more to transmit, or the uart is now
409 * stopped, disable the uart and exit
410 */
411
412 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
413 s3c24xx_serial_stop_tx(port);
414 goto out;
415 }
416
417 /* try and drain the buffer... */
418
419 while (!uart_circ_empty(xmit) && count-- > 0) {
420 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
421 break;
422
423 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
424 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
425 port->icount.tx++;
426 }
427
428 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
429 uart_write_wakeup(port);
430
431 if (uart_circ_empty(xmit))
432 s3c24xx_serial_stop_tx(port);
433
434 out:
435 return IRQ_HANDLED;
436 }
437
438 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
439 {
440 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
441 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
442 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
443
444 if (ufcon & S3C2410_UFCON_FIFOMODE) {
445 if ((ufstat & info->tx_fifomask) != 0 ||
446 (ufstat & info->tx_fifofull))
447 return 0;
448
449 return 1;
450 }
451
452 return s3c24xx_serial_txempty_nofifo(port);
453 }
454
455 /* no modem control lines */
456 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
457 {
458 unsigned int umstat = rd_regb(port,S3C2410_UMSTAT);
459
460 if (umstat & S3C2410_UMSTAT_CTS)
461 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
462 else
463 return TIOCM_CAR | TIOCM_DSR;
464 }
465
466 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
467 {
468 /* todo - possibly remove AFC and do manual CTS */
469 }
470
471 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
472 {
473 unsigned long flags;
474 unsigned int ucon;
475
476 spin_lock_irqsave(&port->lock, flags);
477
478 ucon = rd_regl(port, S3C2410_UCON);
479
480 if (break_state)
481 ucon |= S3C2410_UCON_SBREAK;
482 else
483 ucon &= ~S3C2410_UCON_SBREAK;
484
485 wr_regl(port, S3C2410_UCON, ucon);
486
487 spin_unlock_irqrestore(&port->lock, flags);
488 }
489
490 static void s3c24xx_serial_shutdown(struct uart_port *port)
491 {
492 struct s3c24xx_uart_port *ourport = to_ourport(port);
493
494 if (ourport->tx_claimed) {
495 free_irq(TX_IRQ(port), ourport);
496 tx_enabled(port) = 0;
497 ourport->tx_claimed = 0;
498 }
499
500 if (ourport->rx_claimed) {
501 free_irq(RX_IRQ(port), ourport);
502 ourport->rx_claimed = 0;
503 rx_enabled(port) = 0;
504 }
505 }
506
507
508 static int s3c24xx_serial_startup(struct uart_port *port)
509 {
510 struct s3c24xx_uart_port *ourport = to_ourport(port);
511 int ret;
512
513 dbg("s3c24xx_serial_startup: port=%p (%08lx,%p)\n",
514 port->mapbase, port->membase);
515
516 rx_enabled(port) = 1;
517
518 ret = request_irq(RX_IRQ(port),
519 s3c24xx_serial_rx_chars, 0,
520 s3c24xx_serial_portname(port), ourport);
521
522 if (ret != 0) {
523 printk(KERN_ERR "cannot get irq %d\n", RX_IRQ(port));
524 return ret;
525 }
526
527 ourport->rx_claimed = 1;
528
529 dbg("requesting tx irq...\n");
530
531 tx_enabled(port) = 1;
532
533 ret = request_irq(TX_IRQ(port),
534 s3c24xx_serial_tx_chars, 0,
535 s3c24xx_serial_portname(port), ourport);
536
537 if (ret) {
538 printk(KERN_ERR "cannot get irq %d\n", TX_IRQ(port));
539 goto err;
540 }
541
542 ourport->tx_claimed = 1;
543
544 dbg("s3c24xx_serial_startup ok\n");
545
546 /* the port reset code should have done the correct
547 * register setup for the port controls */
548
549 return ret;
550
551 err:
552 s3c24xx_serial_shutdown(port);
553 return ret;
554 }
555
556 /* power power management control */
557
558 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
559 unsigned int old)
560 {
561 struct s3c24xx_uart_port *ourport = to_ourport(port);
562
563 switch (level) {
564 case 3:
565 if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
566 clk_disable(ourport->baudclk);
567
568 clk_disable(ourport->clk);
569 break;
570
571 case 0:
572 clk_enable(ourport->clk);
573
574 if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
575 clk_enable(ourport->baudclk);
576
577 break;
578 default:
579 printk(KERN_ERR "s3c24xx_serial: unknown pm %d\n", level);
580 }
581 }
582
583 /* baud rate calculation
584 *
585 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
586 * of different sources, including the peripheral clock ("pclk") and an
587 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
588 * with a programmable extra divisor.
589 *
590 * The following code goes through the clock sources, and calculates the
591 * baud clocks (and the resultant actual baud rates) and then tries to
592 * pick the closest one and select that.
593 *
594 */
595
596
597 #define MAX_CLKS (8)
598
599 static struct s3c24xx_uart_clksrc tmp_clksrc = {
600 .name = "pclk",
601 .min_baud = 0,
602 .max_baud = 0,
603 .divisor = 1,
604 };
605
606 static inline int
607 s3c24xx_serial_getsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
608 {
609 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
610
611 return (info->get_clksrc)(port, c);
612 }
613
614 static inline int
615 s3c24xx_serial_setsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
616 {
617 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
618
619 return (info->set_clksrc)(port, c);
620 }
621
622 struct baud_calc {
623 struct s3c24xx_uart_clksrc *clksrc;
624 unsigned int calc;
625 unsigned int quot;
626 struct clk *src;
627 };
628
629 static int s3c24xx_serial_calcbaud(struct baud_calc *calc,
630 struct uart_port *port,
631 struct s3c24xx_uart_clksrc *clksrc,
632 unsigned int baud)
633 {
634 unsigned long rate;
635
636 calc->src = clk_get(port->dev, clksrc->name);
637 if (calc->src == NULL || IS_ERR(calc->src))
638 return 0;
639
640 rate = clk_get_rate(calc->src);
641 rate /= clksrc->divisor;
642
643 calc->clksrc = clksrc;
644 calc->quot = (rate + (8 * baud)) / (16 * baud);
645 calc->calc = (rate / (calc->quot * 16));
646
647 calc->quot--;
648 return 1;
649 }
650
651 static unsigned int s3c24xx_serial_getclk(struct uart_port *port,
652 struct s3c24xx_uart_clksrc **clksrc,
653 struct clk **clk,
654 unsigned int baud)
655 {
656 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
657 struct s3c24xx_uart_clksrc *clkp;
658 struct baud_calc res[MAX_CLKS];
659 struct baud_calc *resptr, *best, *sptr;
660 int i;
661
662 clkp = cfg->clocks;
663 best = NULL;
664
665 if (cfg->clocks_size < 2) {
666 if (cfg->clocks_size == 0)
667 clkp = &tmp_clksrc;
668
669 /* check to see if we're sourcing fclk, and if so we're
670 * going to have to update the clock source
671 */
672
673 if (strcmp(clkp->name, "fclk") == 0) {
674 struct s3c24xx_uart_clksrc src;
675
676 s3c24xx_serial_getsource(port, &src);
677
678 /* check that the port already using fclk, and if
679 * not, then re-select fclk
680 */
681
682 if (strcmp(src.name, clkp->name) == 0) {
683 s3c24xx_serial_setsource(port, clkp);
684 s3c24xx_serial_getsource(port, &src);
685 }
686
687 clkp->divisor = src.divisor;
688 }
689
690 s3c24xx_serial_calcbaud(res, port, clkp, baud);
691 best = res;
692 resptr = best + 1;
693 } else {
694 resptr = res;
695
696 for (i = 0; i < cfg->clocks_size; i++, clkp++) {
697 if (s3c24xx_serial_calcbaud(resptr, port, clkp, baud))
698 resptr++;
699 }
700 }
701
702 /* ok, we now need to select the best clock we found */
703
704 if (!best) {
705 unsigned int deviation = (1<<30)|((1<<30)-1);
706 int calc_deviation;
707
708 for (sptr = res; sptr < resptr; sptr++) {
709 printk(KERN_DEBUG
710 "found clk %p (%s) quot %d, calc %d\n",
711 sptr->clksrc, sptr->clksrc->name,
712 sptr->quot, sptr->calc);
713
714 calc_deviation = baud - sptr->calc;
715 if (calc_deviation < 0)
716 calc_deviation = -calc_deviation;
717
718 if (calc_deviation < deviation) {
719 best = sptr;
720 deviation = calc_deviation;
721 }
722 }
723
724 printk(KERN_DEBUG "best %p (deviation %d)\n", best, deviation);
725 }
726
727 printk(KERN_DEBUG "selected clock %p (%s) quot %d, calc %d\n",
728 best->clksrc, best->clksrc->name, best->quot, best->calc);
729
730 /* store results to pass back */
731
732 *clksrc = best->clksrc;
733 *clk = best->src;
734
735 return best->quot;
736 }
737
738 static void s3c24xx_serial_set_termios(struct uart_port *port,
739 struct termios *termios,
740 struct termios *old)
741 {
742 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
743 struct s3c24xx_uart_port *ourport = to_ourport(port);
744 struct s3c24xx_uart_clksrc *clksrc = NULL;
745 struct clk *clk = NULL;
746 unsigned long flags;
747 unsigned int baud, quot;
748 unsigned int ulcon;
749 unsigned int umcon;
750
751 /*
752 * We don't support modem control lines.
753 */
754 termios->c_cflag &= ~(HUPCL | CMSPAR);
755 termios->c_cflag |= CLOCAL;
756
757 /*
758 * Ask the core to calculate the divisor for us.
759 */
760
761 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
762
763 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
764 quot = port->custom_divisor;
765 else
766 quot = s3c24xx_serial_getclk(port, &clksrc, &clk, baud);
767
768 /* check to see if we need to change clock source */
769
770 if (ourport->clksrc != clksrc || ourport->baudclk != clk) {
771 s3c24xx_serial_setsource(port, clksrc);
772
773 if (ourport->baudclk != NULL && !IS_ERR(ourport->baudclk)) {
774 clk_disable(ourport->baudclk);
775 ourport->baudclk = NULL;
776 }
777
778 clk_enable(clk);
779
780 ourport->clksrc = clksrc;
781 ourport->baudclk = clk;
782 }
783
784 switch (termios->c_cflag & CSIZE) {
785 case CS5:
786 dbg("config: 5bits/char\n");
787 ulcon = S3C2410_LCON_CS5;
788 break;
789 case CS6:
790 dbg("config: 6bits/char\n");
791 ulcon = S3C2410_LCON_CS6;
792 break;
793 case CS7:
794 dbg("config: 7bits/char\n");
795 ulcon = S3C2410_LCON_CS7;
796 break;
797 case CS8:
798 default:
799 dbg("config: 8bits/char\n");
800 ulcon = S3C2410_LCON_CS8;
801 break;
802 }
803
804 /* preserve original lcon IR settings */
805 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
806
807 if (termios->c_cflag & CSTOPB)
808 ulcon |= S3C2410_LCON_STOPB;
809
810 umcon = (termios->c_cflag & CRTSCTS) ? S3C2410_UMCOM_AFC : 0;
811
812 if (termios->c_cflag & PARENB) {
813 if (termios->c_cflag & PARODD)
814 ulcon |= S3C2410_LCON_PODD;
815 else
816 ulcon |= S3C2410_LCON_PEVEN;
817 } else {
818 ulcon |= S3C2410_LCON_PNONE;
819 }
820
821 spin_lock_irqsave(&port->lock, flags);
822
823 dbg("setting ulcon to %08x, brddiv to %d\n", ulcon, quot);
824
825 wr_regl(port, S3C2410_ULCON, ulcon);
826 wr_regl(port, S3C2410_UBRDIV, quot);
827 wr_regl(port, S3C2410_UMCON, umcon);
828
829 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
830 rd_regl(port, S3C2410_ULCON),
831 rd_regl(port, S3C2410_UCON),
832 rd_regl(port, S3C2410_UFCON));
833
834 /*
835 * Update the per-port timeout.
836 */
837 uart_update_timeout(port, termios->c_cflag, baud);
838
839 /*
840 * Which character status flags are we interested in?
841 */
842 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
843 if (termios->c_iflag & INPCK)
844 port->read_status_mask |= S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_PARITY;
845
846 /*
847 * Which character status flags should we ignore?
848 */
849 port->ignore_status_mask = 0;
850 if (termios->c_iflag & IGNPAR)
851 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
852 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
853 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
854
855 /*
856 * Ignore all characters if CREAD is not set.
857 */
858 if ((termios->c_cflag & CREAD) == 0)
859 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
860
861 spin_unlock_irqrestore(&port->lock, flags);
862 }
863
864 static const char *s3c24xx_serial_type(struct uart_port *port)
865 {
866 switch (port->type) {
867 case PORT_S3C2410:
868 return "S3C2410";
869 case PORT_S3C2440:
870 return "S3C2440";
871 default:
872 return NULL;
873 }
874 }
875
876 #define MAP_SIZE (0x100)
877
878 static void s3c24xx_serial_release_port(struct uart_port *port)
879 {
880 release_mem_region(port->mapbase, MAP_SIZE);
881 }
882
883 static int s3c24xx_serial_request_port(struct uart_port *port)
884 {
885 const char *name = s3c24xx_serial_portname(port);
886 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
887 }
888
889 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
890 {
891 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
892
893 if (flags & UART_CONFIG_TYPE &&
894 s3c24xx_serial_request_port(port) == 0)
895 port->type = info->type;
896 }
897
898 /*
899 * verify the new serial_struct (for TIOCSSERIAL).
900 */
901 static int
902 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
903 {
904 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
905
906 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
907 return -EINVAL;
908
909 return 0;
910 }
911
912
913 #ifdef CONFIG_SERIAL_S3C2410_CONSOLE
914
915 static struct console s3c24xx_serial_console;
916
917 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
918 #else
919 #define S3C24XX_SERIAL_CONSOLE NULL
920 #endif
921
922 static struct uart_ops s3c24xx_serial_ops = {
923 .pm = s3c24xx_serial_pm,
924 .tx_empty = s3c24xx_serial_tx_empty,
925 .get_mctrl = s3c24xx_serial_get_mctrl,
926 .set_mctrl = s3c24xx_serial_set_mctrl,
927 .stop_tx = s3c24xx_serial_stop_tx,
928 .start_tx = s3c24xx_serial_start_tx,
929 .stop_rx = s3c24xx_serial_stop_rx,
930 .enable_ms = s3c24xx_serial_enable_ms,
931 .break_ctl = s3c24xx_serial_break_ctl,
932 .startup = s3c24xx_serial_startup,
933 .shutdown = s3c24xx_serial_shutdown,
934 .set_termios = s3c24xx_serial_set_termios,
935 .type = s3c24xx_serial_type,
936 .release_port = s3c24xx_serial_release_port,
937 .request_port = s3c24xx_serial_request_port,
938 .config_port = s3c24xx_serial_config_port,
939 .verify_port = s3c24xx_serial_verify_port,
940 };
941
942
943 static struct uart_driver s3c24xx_uart_drv = {
944 .owner = THIS_MODULE,
945 .dev_name = "s3c2410_serial",
946 .nr = 3,
947 .cons = S3C24XX_SERIAL_CONSOLE,
948 .driver_name = S3C24XX_SERIAL_NAME,
949 .devfs_name = S3C24XX_SERIAL_DEVFS,
950 .major = S3C24XX_SERIAL_MAJOR,
951 .minor = S3C24XX_SERIAL_MINOR,
952 };
953
954 static struct s3c24xx_uart_port s3c24xx_serial_ports[NR_PORTS] = {
955 [0] = {
956 .port = {
957 .lock = SPIN_LOCK_UNLOCKED,
958 .iotype = UPIO_MEM,
959 .irq = IRQ_S3CUART_RX0,
960 .uartclk = 0,
961 .fifosize = 16,
962 .ops = &s3c24xx_serial_ops,
963 .flags = UPF_BOOT_AUTOCONF,
964 .line = 0,
965 }
966 },
967 [1] = {
968 .port = {
969 .lock = SPIN_LOCK_UNLOCKED,
970 .iotype = UPIO_MEM,
971 .irq = IRQ_S3CUART_RX1,
972 .uartclk = 0,
973 .fifosize = 16,
974 .ops = &s3c24xx_serial_ops,
975 .flags = UPF_BOOT_AUTOCONF,
976 .line = 1,
977 }
978 },
979 #if NR_PORTS > 2
980
981 [2] = {
982 .port = {
983 .lock = SPIN_LOCK_UNLOCKED,
984 .iotype = UPIO_MEM,
985 .irq = IRQ_S3CUART_RX2,
986 .uartclk = 0,
987 .fifosize = 16,
988 .ops = &s3c24xx_serial_ops,
989 .flags = UPF_BOOT_AUTOCONF,
990 .line = 2,
991 }
992 }
993 #endif
994 };
995
996 /* s3c24xx_serial_resetport
997 *
998 * wrapper to call the specific reset for this port (reset the fifos
999 * and the settings)
1000 */
1001
1002 static inline int s3c24xx_serial_resetport(struct uart_port * port,
1003 struct s3c2410_uartcfg *cfg)
1004 {
1005 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1006
1007 return (info->reset_port)(port, cfg);
1008 }
1009
1010 /* s3c24xx_serial_init_port
1011 *
1012 * initialise a single serial port from the platform device given
1013 */
1014
1015 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1016 struct s3c24xx_uart_info *info,
1017 struct platform_device *platdev)
1018 {
1019 struct uart_port *port = &ourport->port;
1020 struct s3c2410_uartcfg *cfg;
1021 struct resource *res;
1022
1023 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1024
1025 if (platdev == NULL)
1026 return -ENODEV;
1027
1028 cfg = s3c24xx_dev_to_cfg(&platdev->dev);
1029
1030 if (port->mapbase != 0)
1031 return 0;
1032
1033 if (cfg->hwport > 3)
1034 return -EINVAL;
1035
1036 /* setup info for port */
1037 port->dev = &platdev->dev;
1038 ourport->info = info;
1039
1040 /* copy the info in from provided structure */
1041 ourport->port.fifosize = info->fifosize;
1042
1043 dbg("s3c24xx_serial_init_port: %p (hw %d)...\n", port, cfg->hwport);
1044
1045 port->uartclk = 1;
1046
1047 if (cfg->uart_flags & UPF_CONS_FLOW) {
1048 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1049 port->flags |= UPF_CONS_FLOW;
1050 }
1051
1052 /* sort our the physical and virtual addresses for each UART */
1053
1054 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1055 if (res == NULL) {
1056 printk(KERN_ERR "failed to find memory resource for uart\n");
1057 return -EINVAL;
1058 }
1059
1060 dbg("resource %p (%lx..%lx)\n", res, res->start, res->end);
1061
1062 port->mapbase = res->start;
1063 port->membase = S3C24XX_VA_UART + (res->start - S3C24XX_PA_UART);
1064 port->irq = platform_get_irq(platdev, 0);
1065
1066 ourport->clk = clk_get(&platdev->dev, "uart");
1067
1068 dbg("port: map=%08x, mem=%08x, irq=%d, clock=%ld\n",
1069 port->mapbase, port->membase, port->irq, port->uartclk);
1070
1071 /* reset the fifos (and setup the uart) */
1072 s3c24xx_serial_resetport(port, cfg);
1073 return 0;
1074 }
1075
1076 /* Device driver serial port probe */
1077
1078 static int probe_index = 0;
1079
1080 static int s3c24xx_serial_probe(struct platform_device *dev,
1081 struct s3c24xx_uart_info *info)
1082 {
1083 struct s3c24xx_uart_port *ourport;
1084 int ret;
1085
1086 dbg("s3c24xx_serial_probe(%p, %p) %d\n", dev, info, probe_index);
1087
1088 ourport = &s3c24xx_serial_ports[probe_index];
1089 probe_index++;
1090
1091 dbg("%s: initialising port %p...\n", __FUNCTION__, ourport);
1092
1093 ret = s3c24xx_serial_init_port(ourport, info, dev);
1094 if (ret < 0)
1095 goto probe_err;
1096
1097 dbg("%s: adding port\n", __FUNCTION__);
1098 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1099 platform_set_drvdata(dev, &ourport->port);
1100
1101 return 0;
1102
1103 probe_err:
1104 return ret;
1105 }
1106
1107 static int s3c24xx_serial_remove(struct platform_device *dev)
1108 {
1109 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1110
1111 if (port)
1112 uart_remove_one_port(&s3c24xx_uart_drv, port);
1113
1114 return 0;
1115 }
1116
1117 /* UART power management code */
1118
1119 #ifdef CONFIG_PM
1120
1121 static int s3c24xx_serial_suspend(struct platform_device *dev, pm_message_t state)
1122 {
1123 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1124
1125 if (port)
1126 uart_suspend_port(&s3c24xx_uart_drv, port);
1127
1128 return 0;
1129 }
1130
1131 static int s3c24xx_serial_resume(struct platform_device *dev)
1132 {
1133 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1134 struct s3c24xx_uart_port *ourport = to_ourport(port);
1135
1136 if (port) {
1137 clk_enable(ourport->clk);
1138 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1139 clk_disable(ourport->clk);
1140
1141 uart_resume_port(&s3c24xx_uart_drv, port);
1142 }
1143
1144 return 0;
1145 }
1146
1147 #else
1148 #define s3c24xx_serial_suspend NULL
1149 #define s3c24xx_serial_resume NULL
1150 #endif
1151
1152 static int s3c24xx_serial_init(struct platform_driver *drv,
1153 struct s3c24xx_uart_info *info)
1154 {
1155 dbg("s3c24xx_serial_init(%p,%p)\n", drv, info);
1156 return platform_driver_register(drv);
1157 }
1158
1159
1160 /* now comes the code to initialise either the s3c2410 or s3c2440 serial
1161 * port information
1162 */
1163
1164 /* cpu specific variations on the serial port support */
1165
1166 #ifdef CONFIG_CPU_S3C2400
1167
1168 static int s3c2400_serial_getsource(struct uart_port *port,
1169 struct s3c24xx_uart_clksrc *clk)
1170 {
1171 clk->divisor = 1;
1172 clk->name = "pclk";
1173
1174 return 0;
1175 }
1176
1177 static int s3c2400_serial_setsource(struct uart_port *port,
1178 struct s3c24xx_uart_clksrc *clk)
1179 {
1180 return 0;
1181 }
1182
1183 static int s3c2400_serial_resetport(struct uart_port *port,
1184 struct s3c2410_uartcfg *cfg)
1185 {
1186 dbg("s3c2400_serial_resetport: port=%p (%08lx), cfg=%p\n",
1187 port, port->mapbase, cfg);
1188
1189 wr_regl(port, S3C2410_UCON, cfg->ucon);
1190 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
1191
1192 /* reset both fifos */
1193
1194 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1195 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1196
1197 return 0;
1198 }
1199
1200 static struct s3c24xx_uart_info s3c2400_uart_inf = {
1201 .name = "Samsung S3C2400 UART",
1202 .type = PORT_S3C2400,
1203 .fifosize = 16,
1204 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
1205 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
1206 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
1207 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
1208 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
1209 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
1210 .get_clksrc = s3c2400_serial_getsource,
1211 .set_clksrc = s3c2400_serial_setsource,
1212 .reset_port = s3c2400_serial_resetport,
1213 };
1214
1215 static int s3c2400_serial_probe(struct platform_device *dev)
1216 {
1217 return s3c24xx_serial_probe(dev, &s3c2400_uart_inf);
1218 }
1219
1220 static struct platform_driver s3c2400_serial_drv = {
1221 .probe = s3c2400_serial_probe,
1222 .remove = s3c24xx_serial_remove,
1223 .suspend = s3c24xx_serial_suspend,
1224 .resume = s3c24xx_serial_resume,
1225 .driver = {
1226 .name = "s3c2400-uart",
1227 .owner = THIS_MODULE,
1228 },
1229 };
1230
1231 static inline int s3c2400_serial_init(void)
1232 {
1233 return s3c24xx_serial_init(&s3c2400_serial_drv, &s3c2400_uart_inf);
1234 }
1235
1236 static inline void s3c2400_serial_exit(void)
1237 {
1238 platform_driver_unregister(&s3c2400_serial_drv);
1239 }
1240
1241 #define s3c2400_uart_inf_at &s3c2400_uart_inf
1242 #else
1243
1244 static inline int s3c2400_serial_init(void)
1245 {
1246 return 0;
1247 }
1248
1249 static inline void s3c2400_serial_exit(void)
1250 {
1251 }
1252
1253 #define s3c2400_uart_inf_at NULL
1254
1255 #endif /* CONFIG_CPU_S3C2400 */
1256
1257 /* S3C2410 support */
1258
1259 #ifdef CONFIG_CPU_S3C2410
1260
1261 static int s3c2410_serial_setsource(struct uart_port *port,
1262 struct s3c24xx_uart_clksrc *clk)
1263 {
1264 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1265
1266 if (strcmp(clk->name, "uclk") == 0)
1267 ucon |= S3C2410_UCON_UCLK;
1268 else
1269 ucon &= ~S3C2410_UCON_UCLK;
1270
1271 wr_regl(port, S3C2410_UCON, ucon);
1272 return 0;
1273 }
1274
1275 static int s3c2410_serial_getsource(struct uart_port *port,
1276 struct s3c24xx_uart_clksrc *clk)
1277 {
1278 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1279
1280 clk->divisor = 1;
1281 clk->name = (ucon & S3C2410_UCON_UCLK) ? "uclk" : "pclk";
1282
1283 return 0;
1284 }
1285
1286 static int s3c2410_serial_resetport(struct uart_port *port,
1287 struct s3c2410_uartcfg *cfg)
1288 {
1289 dbg("s3c2410_serial_resetport: port=%p (%08lx), cfg=%p\n",
1290 port, port->mapbase, cfg);
1291
1292 wr_regl(port, S3C2410_UCON, cfg->ucon);
1293 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
1294
1295 /* reset both fifos */
1296
1297 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1298 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1299
1300 return 0;
1301 }
1302
1303 static struct s3c24xx_uart_info s3c2410_uart_inf = {
1304 .name = "Samsung S3C2410 UART",
1305 .type = PORT_S3C2410,
1306 .fifosize = 16,
1307 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
1308 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
1309 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
1310 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
1311 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
1312 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
1313 .get_clksrc = s3c2410_serial_getsource,
1314 .set_clksrc = s3c2410_serial_setsource,
1315 .reset_port = s3c2410_serial_resetport,
1316 };
1317
1318 /* device management */
1319
1320 static int s3c2410_serial_probe(struct platform_device *dev)
1321 {
1322 return s3c24xx_serial_probe(dev, &s3c2410_uart_inf);
1323 }
1324
1325 static struct platform_driver s3c2410_serial_drv = {
1326 .probe = s3c2410_serial_probe,
1327 .remove = s3c24xx_serial_remove,
1328 .suspend = s3c24xx_serial_suspend,
1329 .resume = s3c24xx_serial_resume,
1330 .driver = {
1331 .name = "s3c2410-uart",
1332 .owner = THIS_MODULE,
1333 },
1334 };
1335
1336 static inline int s3c2410_serial_init(void)
1337 {
1338 return s3c24xx_serial_init(&s3c2410_serial_drv, &s3c2410_uart_inf);
1339 }
1340
1341 static inline void s3c2410_serial_exit(void)
1342 {
1343 platform_driver_unregister(&s3c2410_serial_drv);
1344 }
1345
1346 #define s3c2410_uart_inf_at &s3c2410_uart_inf
1347 #else
1348
1349 static inline int s3c2410_serial_init(void)
1350 {
1351 return 0;
1352 }
1353
1354 static inline void s3c2410_serial_exit(void)
1355 {
1356 }
1357
1358 #define s3c2410_uart_inf_at NULL
1359
1360 #endif /* CONFIG_CPU_S3C2410 */
1361
1362 #ifdef CONFIG_CPU_S3C2440
1363
1364 static int s3c2440_serial_setsource(struct uart_port *port,
1365 struct s3c24xx_uart_clksrc *clk)
1366 {
1367 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1368
1369 // todo - proper fclk<>nonfclk switch //
1370
1371 ucon &= ~S3C2440_UCON_CLKMASK;
1372
1373 if (strcmp(clk->name, "uclk") == 0)
1374 ucon |= S3C2440_UCON_UCLK;
1375 else if (strcmp(clk->name, "pclk") == 0)
1376 ucon |= S3C2440_UCON_PCLK;
1377 else if (strcmp(clk->name, "fclk") == 0)
1378 ucon |= S3C2440_UCON_FCLK;
1379 else {
1380 printk(KERN_ERR "unknown clock source %s\n", clk->name);
1381 return -EINVAL;
1382 }
1383
1384 wr_regl(port, S3C2410_UCON, ucon);
1385 return 0;
1386 }
1387
1388
1389 static int s3c2440_serial_getsource(struct uart_port *port,
1390 struct s3c24xx_uart_clksrc *clk)
1391 {
1392 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1393 unsigned long ucon0, ucon1, ucon2;
1394
1395 switch (ucon & S3C2440_UCON_CLKMASK) {
1396 case S3C2440_UCON_UCLK:
1397 clk->divisor = 1;
1398 clk->name = "uclk";
1399 break;
1400
1401 case S3C2440_UCON_PCLK:
1402 case S3C2440_UCON_PCLK2:
1403 clk->divisor = 1;
1404 clk->name = "pclk";
1405 break;
1406
1407 case S3C2440_UCON_FCLK:
1408 /* the fun of calculating the uart divisors on
1409 * the s3c2440 */
1410
1411 ucon0 = __raw_readl(S3C24XX_VA_UART0 + S3C2410_UCON);
1412 ucon1 = __raw_readl(S3C24XX_VA_UART1 + S3C2410_UCON);
1413 ucon2 = __raw_readl(S3C24XX_VA_UART2 + S3C2410_UCON);
1414
1415 printk("ucons: %08lx, %08lx, %08lx\n", ucon0, ucon1, ucon2);
1416
1417 ucon0 &= S3C2440_UCON0_DIVMASK;
1418 ucon1 &= S3C2440_UCON1_DIVMASK;
1419 ucon2 &= S3C2440_UCON2_DIVMASK;
1420
1421 if (ucon0 != 0) {
1422 clk->divisor = ucon0 >> S3C2440_UCON_DIVSHIFT;
1423 clk->divisor += 6;
1424 } else if (ucon1 != 0) {
1425 clk->divisor = ucon1 >> S3C2440_UCON_DIVSHIFT;
1426 clk->divisor += 21;
1427 } else if (ucon2 != 0) {
1428 clk->divisor = ucon2 >> S3C2440_UCON_DIVSHIFT;
1429 clk->divisor += 36;
1430 } else {
1431 /* manual calims 44, seems to be 9 */
1432 clk->divisor = 9;
1433 }
1434
1435 clk->name = "fclk";
1436 break;
1437 }
1438
1439 return 0;
1440 }
1441
1442 static int s3c2440_serial_resetport(struct uart_port *port,
1443 struct s3c2410_uartcfg *cfg)
1444 {
1445 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1446
1447 dbg("s3c2440_serial_resetport: port=%p (%08lx), cfg=%p\n",
1448 port, port->mapbase, cfg);
1449
1450 /* ensure we don't change the clock settings... */
1451
1452 ucon &= (S3C2440_UCON0_DIVMASK | (3<<10));
1453
1454 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1455 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
1456
1457 /* reset both fifos */
1458
1459 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1460 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1461
1462 return 0;
1463 }
1464
1465 static struct s3c24xx_uart_info s3c2440_uart_inf = {
1466 .name = "Samsung S3C2440 UART",
1467 .type = PORT_S3C2440,
1468 .fifosize = 64,
1469 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1470 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1471 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1472 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1473 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1474 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1475 .get_clksrc = s3c2440_serial_getsource,
1476 .set_clksrc = s3c2440_serial_setsource,
1477 .reset_port = s3c2440_serial_resetport,
1478 };
1479
1480 /* device management */
1481
1482 static int s3c2440_serial_probe(struct platform_device *dev)
1483 {
1484 dbg("s3c2440_serial_probe: dev=%p\n", dev);
1485 return s3c24xx_serial_probe(dev, &s3c2440_uart_inf);
1486 }
1487
1488 static struct platform_driver s3c2440_serial_drv = {
1489 .probe = s3c2440_serial_probe,
1490 .remove = s3c24xx_serial_remove,
1491 .suspend = s3c24xx_serial_suspend,
1492 .resume = s3c24xx_serial_resume,
1493 .driver = {
1494 .name = "s3c2440-uart",
1495 .owner = THIS_MODULE,
1496 },
1497 };
1498
1499
1500 static inline int s3c2440_serial_init(void)
1501 {
1502 return s3c24xx_serial_init(&s3c2440_serial_drv, &s3c2440_uart_inf);
1503 }
1504
1505 static inline void s3c2440_serial_exit(void)
1506 {
1507 platform_driver_unregister(&s3c2440_serial_drv);
1508 }
1509
1510 #define s3c2440_uart_inf_at &s3c2440_uart_inf
1511 #else
1512
1513 static inline int s3c2440_serial_init(void)
1514 {
1515 return 0;
1516 }
1517
1518 static inline void s3c2440_serial_exit(void)
1519 {
1520 }
1521
1522 #define s3c2440_uart_inf_at NULL
1523 #endif /* CONFIG_CPU_S3C2440 */
1524
1525 /* module initialisation code */
1526
1527 static int __init s3c24xx_serial_modinit(void)
1528 {
1529 int ret;
1530
1531 ret = uart_register_driver(&s3c24xx_uart_drv);
1532 if (ret < 0) {
1533 printk(KERN_ERR "failed to register UART driver\n");
1534 return -1;
1535 }
1536
1537 s3c2400_serial_init();
1538 s3c2410_serial_init();
1539 s3c2440_serial_init();
1540
1541 return 0;
1542 }
1543
1544 static void __exit s3c24xx_serial_modexit(void)
1545 {
1546 s3c2400_serial_exit();
1547 s3c2410_serial_exit();
1548 s3c2440_serial_exit();
1549
1550 uart_unregister_driver(&s3c24xx_uart_drv);
1551 }
1552
1553
1554 module_init(s3c24xx_serial_modinit);
1555 module_exit(s3c24xx_serial_modexit);
1556
1557 /* Console code */
1558
1559 #ifdef CONFIG_SERIAL_S3C2410_CONSOLE
1560
1561 static struct uart_port *cons_uart;
1562
1563 static int
1564 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1565 {
1566 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1567 unsigned long ufstat, utrstat;
1568
1569 if (ufcon & S3C2410_UFCON_FIFOMODE) {
1570 /* fifo mode - check ammount of data in fifo registers... */
1571
1572 ufstat = rd_regl(port, S3C2410_UFSTAT);
1573 return (ufstat & info->tx_fifofull) ? 0 : 1;
1574 }
1575
1576 /* in non-fifo mode, we go and use the tx buffer empty */
1577
1578 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1579 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1580 }
1581
1582 static void
1583 s3c24xx_serial_console_write(struct console *co, const char *s,
1584 unsigned int count)
1585 {
1586 int i;
1587 unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
1588
1589 for (i = 0; i < count; i++) {
1590 while (!s3c24xx_serial_console_txrdy(cons_uart, ufcon))
1591 barrier();
1592
1593 wr_regb(cons_uart, S3C2410_UTXH, s[i]);
1594
1595 if (s[i] == '\n') {
1596 while (!s3c24xx_serial_console_txrdy(cons_uart, ufcon))
1597 barrier();
1598
1599 wr_regb(cons_uart, S3C2410_UTXH, '\r');
1600 }
1601 }
1602 }
1603
1604 static void __init
1605 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
1606 int *parity, int *bits)
1607 {
1608 struct s3c24xx_uart_clksrc clksrc;
1609 struct clk *clk;
1610 unsigned int ulcon;
1611 unsigned int ucon;
1612 unsigned int ubrdiv;
1613 unsigned long rate;
1614
1615 ulcon = rd_regl(port, S3C2410_ULCON);
1616 ucon = rd_regl(port, S3C2410_UCON);
1617 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
1618
1619 dbg("s3c24xx_serial_get_options: port=%p\n"
1620 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
1621 port, ulcon, ucon, ubrdiv);
1622
1623 if ((ucon & 0xf) != 0) {
1624 /* consider the serial port configured if the tx/rx mode set */
1625
1626 switch (ulcon & S3C2410_LCON_CSMASK) {
1627 case S3C2410_LCON_CS5:
1628 *bits = 5;
1629 break;
1630 case S3C2410_LCON_CS6:
1631 *bits = 6;
1632 break;
1633 case S3C2410_LCON_CS7:
1634 *bits = 7;
1635 break;
1636 default:
1637 case S3C2410_LCON_CS8:
1638 *bits = 8;
1639 break;
1640 }
1641
1642 switch (ulcon & S3C2410_LCON_PMASK) {
1643 case S3C2410_LCON_PEVEN:
1644 *parity = 'e';
1645 break;
1646
1647 case S3C2410_LCON_PODD:
1648 *parity = 'o';
1649 break;
1650
1651 case S3C2410_LCON_PNONE:
1652 default:
1653 *parity = 'n';
1654 }
1655
1656 /* now calculate the baud rate */
1657
1658 s3c24xx_serial_getsource(port, &clksrc);
1659
1660 clk = clk_get(port->dev, clksrc.name);
1661 if (!IS_ERR(clk) && clk != NULL)
1662 rate = clk_get_rate(clk) / clksrc.divisor;
1663 else
1664 rate = 1;
1665
1666
1667 *baud = rate / ( 16 * (ubrdiv + 1));
1668 dbg("calculated baud %d\n", *baud);
1669 }
1670
1671 }
1672
1673 /* s3c24xx_serial_init_ports
1674 *
1675 * initialise the serial ports from the machine provided initialisation
1676 * data.
1677 */
1678
1679 static int s3c24xx_serial_init_ports(struct s3c24xx_uart_info *info)
1680 {
1681 struct s3c24xx_uart_port *ptr = s3c24xx_serial_ports;
1682 struct platform_device **platdev_ptr;
1683 int i;
1684
1685 dbg("s3c24xx_serial_init_ports: initialising ports...\n");
1686
1687 platdev_ptr = s3c24xx_uart_devs;
1688
1689 for (i = 0; i < NR_PORTS; i++, ptr++, platdev_ptr++) {
1690 s3c24xx_serial_init_port(ptr, info, *platdev_ptr);
1691 }
1692
1693 return 0;
1694 }
1695
1696 static int __init
1697 s3c24xx_serial_console_setup(struct console *co, char *options)
1698 {
1699 struct uart_port *port;
1700 int baud = 9600;
1701 int bits = 8;
1702 int parity = 'n';
1703 int flow = 'n';
1704
1705 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
1706 co, co->index, options);
1707
1708 /* is this a valid port */
1709
1710 if (co->index == -1 || co->index >= NR_PORTS)
1711 co->index = 0;
1712
1713 port = &s3c24xx_serial_ports[co->index].port;
1714
1715 /* is the port configured? */
1716
1717 if (port->mapbase == 0x0) {
1718 co->index = 0;
1719 port = &s3c24xx_serial_ports[co->index].port;
1720 }
1721
1722 cons_uart = port;
1723
1724 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
1725
1726 /*
1727 * Check whether an invalid uart number has been specified, and
1728 * if so, search for the first available port that does have
1729 * console support.
1730 */
1731 if (options)
1732 uart_parse_options(options, &baud, &parity, &bits, &flow);
1733 else
1734 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
1735
1736 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
1737
1738 return uart_set_options(port, co, baud, parity, bits, flow);
1739 }
1740
1741 /* s3c24xx_serial_initconsole
1742 *
1743 * initialise the console from one of the uart drivers
1744 */
1745
1746 static struct console s3c24xx_serial_console =
1747 {
1748 .name = S3C24XX_SERIAL_NAME,
1749 .device = uart_console_device,
1750 .flags = CON_PRINTBUFFER,
1751 .index = -1,
1752 .write = s3c24xx_serial_console_write,
1753 .setup = s3c24xx_serial_console_setup
1754 };
1755
1756 static int s3c24xx_serial_initconsole(void)
1757 {
1758 struct s3c24xx_uart_info *info;
1759 struct platform_device *dev = s3c24xx_uart_devs[0];
1760
1761 dbg("s3c24xx_serial_initconsole\n");
1762
1763 /* select driver based on the cpu */
1764
1765 if (dev == NULL) {
1766 printk(KERN_ERR "s3c24xx: no devices for console init\n");
1767 return 0;
1768 }
1769
1770 if (strcmp(dev->name, "s3c2400-uart") == 0) {
1771 info = s3c2400_uart_inf_at;
1772 } else if (strcmp(dev->name, "s3c2410-uart") == 0) {
1773 info = s3c2410_uart_inf_at;
1774 } else if (strcmp(dev->name, "s3c2440-uart") == 0) {
1775 info = s3c2440_uart_inf_at;
1776 } else {
1777 printk(KERN_ERR "s3c24xx: no driver for %s\n", dev->name);
1778 return 0;
1779 }
1780
1781 if (info == NULL) {
1782 printk(KERN_ERR "s3c24xx: no driver for console\n");
1783 return 0;
1784 }
1785
1786 s3c24xx_serial_console.data = &s3c24xx_uart_drv;
1787 s3c24xx_serial_init_ports(info);
1788
1789 register_console(&s3c24xx_serial_console);
1790 return 0;
1791 }
1792
1793 console_initcall(s3c24xx_serial_initconsole);
1794
1795 #endif /* CONFIG_SERIAL_S3C2410_CONSOLE */
1796
1797 MODULE_LICENSE("GPL");
1798 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1799 MODULE_DESCRIPTION("Samsung S3C2410/S3C2440 Serial port driver");
Support for the Chinese Samsung S3C2440 based development boards