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x86: Move paravirt pagetable_setup to x86_init_ops
[linux-2.6/mini2440.git] / arch / x86 / include / asm / paravirt.h
blob1caf25b91e6b81f56a943dae7475f0b22ce2a76b
1 #ifndef _ASM_X86_PARAVIRT_H
2 #define _ASM_X86_PARAVIRT_H
3 /* Various instructions on x86 need to be replaced for
4 * para-virtualization: those hooks are defined here. */
5
6 #ifdef CONFIG_PARAVIRT
7 #include <asm/pgtable_types.h>
8 #include <asm/asm.h>
9
10 #include <asm/paravirt_types.h>
11
12 #ifndef __ASSEMBLY__
13 #include <linux/types.h>
14 #include <linux/cpumask.h>
15
16 static inline int paravirt_enabled(void)
17 {
18 return pv_info.paravirt_enabled;
19 }
20
21 static inline void load_sp0(struct tss_struct *tss,
22 struct thread_struct *thread)
23 {
24 PVOP_VCALL2(pv_cpu_ops.load_sp0, tss, thread);
25 }
26
27 static inline unsigned long get_wallclock(void)
28 {
29 return PVOP_CALL0(unsigned long, pv_time_ops.get_wallclock);
30 }
31
32 static inline int set_wallclock(unsigned long nowtime)
33 {
34 return PVOP_CALL1(int, pv_time_ops.set_wallclock, nowtime);
35 }
36
37 static inline void (*choose_time_init(void))(void)
38 {
39 return pv_time_ops.time_init;
40 }
41
42 /* The paravirtualized CPUID instruction. */
43 static inline void __cpuid(unsigned int *eax, unsigned int *ebx,
44 unsigned int *ecx, unsigned int *edx)
45 {
46 PVOP_VCALL4(pv_cpu_ops.cpuid, eax, ebx, ecx, edx);
47 }
48
49 /*
50 * These special macros can be used to get or set a debugging register
51 */
52 static inline unsigned long paravirt_get_debugreg(int reg)
53 {
54 return PVOP_CALL1(unsigned long, pv_cpu_ops.get_debugreg, reg);
55 }
56 #define get_debugreg(var, reg) var = paravirt_get_debugreg(reg)
57 static inline void set_debugreg(unsigned long val, int reg)
58 {
59 PVOP_VCALL2(pv_cpu_ops.set_debugreg, reg, val);
60 }
61
62 static inline void clts(void)
63 {
64 PVOP_VCALL0(pv_cpu_ops.clts);
65 }
66
67 static inline unsigned long read_cr0(void)
68 {
69 return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr0);
70 }
71
72 static inline void write_cr0(unsigned long x)
73 {
74 PVOP_VCALL1(pv_cpu_ops.write_cr0, x);
75 }
76
77 static inline unsigned long read_cr2(void)
78 {
79 return PVOP_CALL0(unsigned long, pv_mmu_ops.read_cr2);
80 }
81
82 static inline void write_cr2(unsigned long x)
83 {
84 PVOP_VCALL1(pv_mmu_ops.write_cr2, x);
85 }
86
87 static inline unsigned long read_cr3(void)
88 {
89 return PVOP_CALL0(unsigned long, pv_mmu_ops.read_cr3);
90 }
91
92 static inline void write_cr3(unsigned long x)
93 {
94 PVOP_VCALL1(pv_mmu_ops.write_cr3, x);
95 }
96
97 static inline unsigned long read_cr4(void)
98 {
99 return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr4);
100 }
101 static inline unsigned long read_cr4_safe(void)
102 {
103 return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr4_safe);
104 }
105
106 static inline void write_cr4(unsigned long x)
107 {
108 PVOP_VCALL1(pv_cpu_ops.write_cr4, x);
109 }
110
111 #ifdef CONFIG_X86_64
112 static inline unsigned long read_cr8(void)
113 {
114 return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr8);
115 }
116
117 static inline void write_cr8(unsigned long x)
118 {
119 PVOP_VCALL1(pv_cpu_ops.write_cr8, x);
120 }
121 #endif
122
123 static inline void raw_safe_halt(void)
124 {
125 PVOP_VCALL0(pv_irq_ops.safe_halt);
126 }
127
128 static inline void halt(void)
129 {
130 PVOP_VCALL0(pv_irq_ops.safe_halt);
131 }
132
133 static inline void wbinvd(void)
134 {
135 PVOP_VCALL0(pv_cpu_ops.wbinvd);
136 }
137
138 #define get_kernel_rpl() (pv_info.kernel_rpl)
139
140 static inline u64 paravirt_read_msr(unsigned msr, int *err)
141 {
142 return PVOP_CALL2(u64, pv_cpu_ops.read_msr, msr, err);
143 }
144 static inline u64 paravirt_read_msr_amd(unsigned msr, int *err)
145 {
146 return PVOP_CALL2(u64, pv_cpu_ops.read_msr_amd, msr, err);
147 }
148 static inline int paravirt_write_msr(unsigned msr, unsigned low, unsigned high)
149 {
150 return PVOP_CALL3(int, pv_cpu_ops.write_msr, msr, low, high);
151 }
152
153 /* These should all do BUG_ON(_err), but our headers are too tangled. */
154 #define rdmsr(msr, val1, val2) \
155 do { \
156 int _err; \
157 u64 _l = paravirt_read_msr(msr, &_err); \
158 val1 = (u32)_l; \
159 val2 = _l >> 32; \
160 } while (0)
161
162 #define wrmsr(msr, val1, val2) \
163 do { \
164 paravirt_write_msr(msr, val1, val2); \
165 } while (0)
166
167 #define rdmsrl(msr, val) \
168 do { \
169 int _err; \
170 val = paravirt_read_msr(msr, &_err); \
171 } while (0)
172
173 #define wrmsrl(msr, val) wrmsr(msr, (u32)((u64)(val)), ((u64)(val))>>32)
174 #define wrmsr_safe(msr, a, b) paravirt_write_msr(msr, a, b)
175
176 /* rdmsr with exception handling */
177 #define rdmsr_safe(msr, a, b) \
178 ({ \
179 int _err; \
180 u64 _l = paravirt_read_msr(msr, &_err); \
181 (*a) = (u32)_l; \
182 (*b) = _l >> 32; \
183 _err; \
184 })
185
186 static inline int rdmsrl_safe(unsigned msr, unsigned long long *p)
187 {
188 int err;
189
190 *p = paravirt_read_msr(msr, &err);
191 return err;
192 }
193 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
194 {
195 int err;
196
197 *p = paravirt_read_msr_amd(msr, &err);
198 return err;
199 }
200
201 static inline u64 paravirt_read_tsc(void)
202 {
203 return PVOP_CALL0(u64, pv_cpu_ops.read_tsc);
204 }
205
206 #define rdtscl(low) \
207 do { \
208 u64 _l = paravirt_read_tsc(); \
209 low = (int)_l; \
210 } while (0)
211
212 #define rdtscll(val) (val = paravirt_read_tsc())
213
214 static inline unsigned long long paravirt_sched_clock(void)
215 {
216 return PVOP_CALL0(unsigned long long, pv_time_ops.sched_clock);
217 }
218 #define calibrate_tsc() (pv_time_ops.get_tsc_khz())
219
220 static inline unsigned long long paravirt_read_pmc(int counter)
221 {
222 return PVOP_CALL1(u64, pv_cpu_ops.read_pmc, counter);
223 }
224
225 #define rdpmc(counter, low, high) \
226 do { \
227 u64 _l = paravirt_read_pmc(counter); \
228 low = (u32)_l; \
229 high = _l >> 32; \
230 } while (0)
231
232 static inline unsigned long long paravirt_rdtscp(unsigned int *aux)
233 {
234 return PVOP_CALL1(u64, pv_cpu_ops.read_tscp, aux);
235 }
236
237 #define rdtscp(low, high, aux) \
238 do { \
239 int __aux; \
240 unsigned long __val = paravirt_rdtscp(&__aux); \
241 (low) = (u32)__val; \
242 (high) = (u32)(__val >> 32); \
243 (aux) = __aux; \
244 } while (0)
245
246 #define rdtscpll(val, aux) \
247 do { \
248 unsigned long __aux; \
249 val = paravirt_rdtscp(&__aux); \
250 (aux) = __aux; \
251 } while (0)
252
253 static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries)
254 {
255 PVOP_VCALL2(pv_cpu_ops.alloc_ldt, ldt, entries);
256 }
257
258 static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries)
259 {
260 PVOP_VCALL2(pv_cpu_ops.free_ldt, ldt, entries);
261 }
262
263 static inline void load_TR_desc(void)
264 {
265 PVOP_VCALL0(pv_cpu_ops.load_tr_desc);
266 }
267 static inline void load_gdt(const struct desc_ptr *dtr)
268 {
269 PVOP_VCALL1(pv_cpu_ops.load_gdt, dtr);
270 }
271 static inline void load_idt(const struct desc_ptr *dtr)
272 {
273 PVOP_VCALL1(pv_cpu_ops.load_idt, dtr);
274 }
275 static inline void set_ldt(const void *addr, unsigned entries)
276 {
277 PVOP_VCALL2(pv_cpu_ops.set_ldt, addr, entries);
278 }
279 static inline void store_gdt(struct desc_ptr *dtr)
280 {
281 PVOP_VCALL1(pv_cpu_ops.store_gdt, dtr);
282 }
283 static inline void store_idt(struct desc_ptr *dtr)
284 {
285 PVOP_VCALL1(pv_cpu_ops.store_idt, dtr);
286 }
287 static inline unsigned long paravirt_store_tr(void)
288 {
289 return PVOP_CALL0(unsigned long, pv_cpu_ops.store_tr);
290 }
291 #define store_tr(tr) ((tr) = paravirt_store_tr())
292 static inline void load_TLS(struct thread_struct *t, unsigned cpu)
293 {
294 PVOP_VCALL2(pv_cpu_ops.load_tls, t, cpu);
295 }
296
297 #ifdef CONFIG_X86_64
298 static inline void load_gs_index(unsigned int gs)
299 {
300 PVOP_VCALL1(pv_cpu_ops.load_gs_index, gs);
301 }
302 #endif
303
304 static inline void write_ldt_entry(struct desc_struct *dt, int entry,
305 const void *desc)
306 {
307 PVOP_VCALL3(pv_cpu_ops.write_ldt_entry, dt, entry, desc);
308 }
309
310 static inline void write_gdt_entry(struct desc_struct *dt, int entry,
311 void *desc, int type)
312 {
313 PVOP_VCALL4(pv_cpu_ops.write_gdt_entry, dt, entry, desc, type);
314 }
315
316 static inline void write_idt_entry(gate_desc *dt, int entry, const gate_desc *g)
317 {
318 PVOP_VCALL3(pv_cpu_ops.write_idt_entry, dt, entry, g);
319 }
320 static inline void set_iopl_mask(unsigned mask)
321 {
322 PVOP_VCALL1(pv_cpu_ops.set_iopl_mask, mask);
323 }
324
325 /* The paravirtualized I/O functions */
326 static inline void slow_down_io(void)
327 {
328 pv_cpu_ops.io_delay();
329 #ifdef REALLY_SLOW_IO
330 pv_cpu_ops.io_delay();
331 pv_cpu_ops.io_delay();
332 pv_cpu_ops.io_delay();
333 #endif
334 }
335
336 #ifdef CONFIG_X86_LOCAL_APIC
337 static inline void setup_boot_clock(void)
338 {
339 PVOP_VCALL0(pv_apic_ops.setup_boot_clock);
340 }
341
342 static inline void setup_secondary_clock(void)
343 {
344 PVOP_VCALL0(pv_apic_ops.setup_secondary_clock);
345 }
346 #endif
347
348 static inline void paravirt_post_allocator_init(void)
349 {
350 if (pv_init_ops.post_allocator_init)
351 (*pv_init_ops.post_allocator_init)();
352 }
353
354 #ifdef CONFIG_SMP
355 static inline void startup_ipi_hook(int phys_apicid, unsigned long start_eip,
356 unsigned long start_esp)
357 {
358 PVOP_VCALL3(pv_apic_ops.startup_ipi_hook,
359 phys_apicid, start_eip, start_esp);
360 }
361 #endif
362
363 static inline void paravirt_activate_mm(struct mm_struct *prev,
364 struct mm_struct *next)
365 {
366 PVOP_VCALL2(pv_mmu_ops.activate_mm, prev, next);
367 }
368
369 static inline void arch_dup_mmap(struct mm_struct *oldmm,
370 struct mm_struct *mm)
371 {
372 PVOP_VCALL2(pv_mmu_ops.dup_mmap, oldmm, mm);
373 }
374
375 static inline void arch_exit_mmap(struct mm_struct *mm)
376 {
377 PVOP_VCALL1(pv_mmu_ops.exit_mmap, mm);
378 }
379
380 static inline void __flush_tlb(void)
381 {
382 PVOP_VCALL0(pv_mmu_ops.flush_tlb_user);
383 }
384 static inline void __flush_tlb_global(void)
385 {
386 PVOP_VCALL0(pv_mmu_ops.flush_tlb_kernel);
387 }
388 static inline void __flush_tlb_single(unsigned long addr)
389 {
390 PVOP_VCALL1(pv_mmu_ops.flush_tlb_single, addr);
391 }
392
393 static inline void flush_tlb_others(const struct cpumask *cpumask,
394 struct mm_struct *mm,
395 unsigned long va)
396 {
397 PVOP_VCALL3(pv_mmu_ops.flush_tlb_others, cpumask, mm, va);
398 }
399
400 static inline int paravirt_pgd_alloc(struct mm_struct *mm)
401 {
402 return PVOP_CALL1(int, pv_mmu_ops.pgd_alloc, mm);
403 }
404
405 static inline void paravirt_pgd_free(struct mm_struct *mm, pgd_t *pgd)
406 {
407 PVOP_VCALL2(pv_mmu_ops.pgd_free, mm, pgd);
408 }
409
410 static inline void paravirt_alloc_pte(struct mm_struct *mm, unsigned long pfn)
411 {
412 PVOP_VCALL2(pv_mmu_ops.alloc_pte, mm, pfn);
413 }
414 static inline void paravirt_release_pte(unsigned long pfn)
415 {
416 PVOP_VCALL1(pv_mmu_ops.release_pte, pfn);
417 }
418
419 static inline void paravirt_alloc_pmd(struct mm_struct *mm, unsigned long pfn)
420 {
421 PVOP_VCALL2(pv_mmu_ops.alloc_pmd, mm, pfn);
422 }
423
424 static inline void paravirt_alloc_pmd_clone(unsigned long pfn, unsigned long clonepfn,
425 unsigned long start, unsigned long count)
426 {
427 PVOP_VCALL4(pv_mmu_ops.alloc_pmd_clone, pfn, clonepfn, start, count);
428 }
429 static inline void paravirt_release_pmd(unsigned long pfn)
430 {
431 PVOP_VCALL1(pv_mmu_ops.release_pmd, pfn);
432 }
433
434 static inline void paravirt_alloc_pud(struct mm_struct *mm, unsigned long pfn)
435 {
436 PVOP_VCALL2(pv_mmu_ops.alloc_pud, mm, pfn);
437 }
438 static inline void paravirt_release_pud(unsigned long pfn)
439 {
440 PVOP_VCALL1(pv_mmu_ops.release_pud, pfn);
441 }
442
443 #ifdef CONFIG_HIGHPTE
444 static inline void *kmap_atomic_pte(struct page *page, enum km_type type)
445 {
446 unsigned long ret;
447 ret = PVOP_CALL2(unsigned long, pv_mmu_ops.kmap_atomic_pte, page, type);
448 return (void *)ret;
449 }
450 #endif
451
452 static inline void pte_update(struct mm_struct *mm, unsigned long addr,
453 pte_t *ptep)
454 {
455 PVOP_VCALL3(pv_mmu_ops.pte_update, mm, addr, ptep);
456 }
457
458 static inline void pte_update_defer(struct mm_struct *mm, unsigned long addr,
459 pte_t *ptep)
460 {
461 PVOP_VCALL3(pv_mmu_ops.pte_update_defer, mm, addr, ptep);
462 }
463
464 static inline pte_t __pte(pteval_t val)
465 {
466 pteval_t ret;
467
468 if (sizeof(pteval_t) > sizeof(long))
469 ret = PVOP_CALLEE2(pteval_t,
470 pv_mmu_ops.make_pte,
471 val, (u64)val >> 32);
472 else
473 ret = PVOP_CALLEE1(pteval_t,
474 pv_mmu_ops.make_pte,
475 val);
476
477 return (pte_t) { .pte = ret };
478 }
479
480 static inline pteval_t pte_val(pte_t pte)
481 {
482 pteval_t ret;
483
484 if (sizeof(pteval_t) > sizeof(long))
485 ret = PVOP_CALLEE2(pteval_t, pv_mmu_ops.pte_val,
486 pte.pte, (u64)pte.pte >> 32);
487 else
488 ret = PVOP_CALLEE1(pteval_t, pv_mmu_ops.pte_val,
489 pte.pte);
490
491 return ret;
492 }
493
494 static inline pgd_t __pgd(pgdval_t val)
495 {
496 pgdval_t ret;
497
498 if (sizeof(pgdval_t) > sizeof(long))
499 ret = PVOP_CALLEE2(pgdval_t, pv_mmu_ops.make_pgd,
500 val, (u64)val >> 32);
501 else
502 ret = PVOP_CALLEE1(pgdval_t, pv_mmu_ops.make_pgd,
503 val);
504
505 return (pgd_t) { ret };
506 }
507
508 static inline pgdval_t pgd_val(pgd_t pgd)
509 {
510 pgdval_t ret;
511
512 if (sizeof(pgdval_t) > sizeof(long))
513 ret = PVOP_CALLEE2(pgdval_t, pv_mmu_ops.pgd_val,
514 pgd.pgd, (u64)pgd.pgd >> 32);
515 else
516 ret = PVOP_CALLEE1(pgdval_t, pv_mmu_ops.pgd_val,
517 pgd.pgd);
518
519 return ret;
520 }
521
522 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
523 static inline pte_t ptep_modify_prot_start(struct mm_struct *mm, unsigned long addr,
524 pte_t *ptep)
525 {
526 pteval_t ret;
527
528 ret = PVOP_CALL3(pteval_t, pv_mmu_ops.ptep_modify_prot_start,
529 mm, addr, ptep);
530
531 return (pte_t) { .pte = ret };
532 }
533
534 static inline void ptep_modify_prot_commit(struct mm_struct *mm, unsigned long addr,
535 pte_t *ptep, pte_t pte)
536 {
537 if (sizeof(pteval_t) > sizeof(long))
538 /* 5 arg words */
539 pv_mmu_ops.ptep_modify_prot_commit(mm, addr, ptep, pte);
540 else
541 PVOP_VCALL4(pv_mmu_ops.ptep_modify_prot_commit,
542 mm, addr, ptep, pte.pte);
543 }
544
545 static inline void set_pte(pte_t *ptep, pte_t pte)
546 {
547 if (sizeof(pteval_t) > sizeof(long))
548 PVOP_VCALL3(pv_mmu_ops.set_pte, ptep,
549 pte.pte, (u64)pte.pte >> 32);
550 else
551 PVOP_VCALL2(pv_mmu_ops.set_pte, ptep,
552 pte.pte);
553 }
554
555 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
556 pte_t *ptep, pte_t pte)
557 {
558 if (sizeof(pteval_t) > sizeof(long))
559 /* 5 arg words */
560 pv_mmu_ops.set_pte_at(mm, addr, ptep, pte);
561 else
562 PVOP_VCALL4(pv_mmu_ops.set_pte_at, mm, addr, ptep, pte.pte);
563 }
564
565 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
566 {
567 pmdval_t val = native_pmd_val(pmd);
568
569 if (sizeof(pmdval_t) > sizeof(long))
570 PVOP_VCALL3(pv_mmu_ops.set_pmd, pmdp, val, (u64)val >> 32);
571 else
572 PVOP_VCALL2(pv_mmu_ops.set_pmd, pmdp, val);
573 }
574
575 #if PAGETABLE_LEVELS >= 3
576 static inline pmd_t __pmd(pmdval_t val)
577 {
578 pmdval_t ret;
579
580 if (sizeof(pmdval_t) > sizeof(long))
581 ret = PVOP_CALLEE2(pmdval_t, pv_mmu_ops.make_pmd,
582 val, (u64)val >> 32);
583 else
584 ret = PVOP_CALLEE1(pmdval_t, pv_mmu_ops.make_pmd,
585 val);
586
587 return (pmd_t) { ret };
588 }
589
590 static inline pmdval_t pmd_val(pmd_t pmd)
591 {
592 pmdval_t ret;
593
594 if (sizeof(pmdval_t) > sizeof(long))
595 ret = PVOP_CALLEE2(pmdval_t, pv_mmu_ops.pmd_val,
596 pmd.pmd, (u64)pmd.pmd >> 32);
597 else
598 ret = PVOP_CALLEE1(pmdval_t, pv_mmu_ops.pmd_val,
599 pmd.pmd);
600
601 return ret;
602 }
603
604 static inline void set_pud(pud_t *pudp, pud_t pud)
605 {
606 pudval_t val = native_pud_val(pud);
607
608 if (sizeof(pudval_t) > sizeof(long))
609 PVOP_VCALL3(pv_mmu_ops.set_pud, pudp,
610 val, (u64)val >> 32);
611 else
612 PVOP_VCALL2(pv_mmu_ops.set_pud, pudp,
613 val);
614 }
615 #if PAGETABLE_LEVELS == 4
616 static inline pud_t __pud(pudval_t val)
617 {
618 pudval_t ret;
619
620 if (sizeof(pudval_t) > sizeof(long))
621 ret = PVOP_CALLEE2(pudval_t, pv_mmu_ops.make_pud,
622 val, (u64)val >> 32);
623 else
624 ret = PVOP_CALLEE1(pudval_t, pv_mmu_ops.make_pud,
625 val);
626
627 return (pud_t) { ret };
628 }
629
630 static inline pudval_t pud_val(pud_t pud)
631 {
632 pudval_t ret;
633
634 if (sizeof(pudval_t) > sizeof(long))
635 ret = PVOP_CALLEE2(pudval_t, pv_mmu_ops.pud_val,
636 pud.pud, (u64)pud.pud >> 32);
637 else
638 ret = PVOP_CALLEE1(pudval_t, pv_mmu_ops.pud_val,
639 pud.pud);
640
641 return ret;
642 }
643
644 static inline void set_pgd(pgd_t *pgdp, pgd_t pgd)
645 {
646 pgdval_t val = native_pgd_val(pgd);
647
648 if (sizeof(pgdval_t) > sizeof(long))
649 PVOP_VCALL3(pv_mmu_ops.set_pgd, pgdp,
650 val, (u64)val >> 32);
651 else
652 PVOP_VCALL2(pv_mmu_ops.set_pgd, pgdp,
653 val);
654 }
655
656 static inline void pgd_clear(pgd_t *pgdp)
657 {
658 set_pgd(pgdp, __pgd(0));
659 }
660
661 static inline void pud_clear(pud_t *pudp)
662 {
663 set_pud(pudp, __pud(0));
664 }
665
666 #endif /* PAGETABLE_LEVELS == 4 */
667
668 #endif /* PAGETABLE_LEVELS >= 3 */
669
670 #ifdef CONFIG_X86_PAE
671 /* Special-case pte-setting operations for PAE, which can't update a
672 64-bit pte atomically */
673 static inline void set_pte_atomic(pte_t *ptep, pte_t pte)
674 {
675 PVOP_VCALL3(pv_mmu_ops.set_pte_atomic, ptep,
676 pte.pte, pte.pte >> 32);
677 }
678
679 static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
680 pte_t *ptep)
681 {
682 PVOP_VCALL3(pv_mmu_ops.pte_clear, mm, addr, ptep);
683 }
684
685 static inline void pmd_clear(pmd_t *pmdp)
686 {
687 PVOP_VCALL1(pv_mmu_ops.pmd_clear, pmdp);
688 }
689 #else /* !CONFIG_X86_PAE */
690 static inline void set_pte_atomic(pte_t *ptep, pte_t pte)
691 {
692 set_pte(ptep, pte);
693 }
694
695 static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
696 pte_t *ptep)
697 {
698 set_pte_at(mm, addr, ptep, __pte(0));
699 }
700
701 static inline void pmd_clear(pmd_t *pmdp)
702 {
703 set_pmd(pmdp, __pmd(0));
704 }
705 #endif /* CONFIG_X86_PAE */
706
707 #define __HAVE_ARCH_START_CONTEXT_SWITCH
708 static inline void arch_start_context_switch(struct task_struct *prev)
709 {
710 PVOP_VCALL1(pv_cpu_ops.start_context_switch, prev);
711 }
712
713 static inline void arch_end_context_switch(struct task_struct *next)
714 {
715 PVOP_VCALL1(pv_cpu_ops.end_context_switch, next);
716 }
717
718 #define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
719 static inline void arch_enter_lazy_mmu_mode(void)
720 {
721 PVOP_VCALL0(pv_mmu_ops.lazy_mode.enter);
722 }
723
724 static inline void arch_leave_lazy_mmu_mode(void)
725 {
726 PVOP_VCALL0(pv_mmu_ops.lazy_mode.leave);
727 }
728
729 void arch_flush_lazy_mmu_mode(void);
730
731 static inline void __set_fixmap(unsigned /* enum fixed_addresses */ idx,
732 phys_addr_t phys, pgprot_t flags)
733 {
734 pv_mmu_ops.set_fixmap(idx, phys, flags);
735 }
736
737 #if defined(CONFIG_SMP) && defined(CONFIG_PARAVIRT_SPINLOCKS)
738
739 static inline int __raw_spin_is_locked(struct raw_spinlock *lock)
740 {
741 return PVOP_CALL1(int, pv_lock_ops.spin_is_locked, lock);
742 }
743
744 static inline int __raw_spin_is_contended(struct raw_spinlock *lock)
745 {
746 return PVOP_CALL1(int, pv_lock_ops.spin_is_contended, lock);
747 }
748 #define __raw_spin_is_contended __raw_spin_is_contended
749
750 static __always_inline void __raw_spin_lock(struct raw_spinlock *lock)
751 {
752 PVOP_VCALL1(pv_lock_ops.spin_lock, lock);
753 }
754
755 static __always_inline void __raw_spin_lock_flags(struct raw_spinlock *lock,
756 unsigned long flags)
757 {
758 PVOP_VCALL2(pv_lock_ops.spin_lock_flags, lock, flags);
759 }
760
761 static __always_inline int __raw_spin_trylock(struct raw_spinlock *lock)
762 {
763 return PVOP_CALL1(int, pv_lock_ops.spin_trylock, lock);
764 }
765
766 static __always_inline void __raw_spin_unlock(struct raw_spinlock *lock)
767 {
768 PVOP_VCALL1(pv_lock_ops.spin_unlock, lock);
769 }
770
771 #endif
772
773 #ifdef CONFIG_X86_32
774 #define PV_SAVE_REGS "pushl %ecx; pushl %edx;"
775 #define PV_RESTORE_REGS "popl %edx; popl %ecx;"
776
777 /* save and restore all caller-save registers, except return value */
778 #define PV_SAVE_ALL_CALLER_REGS "pushl %ecx;"
779 #define PV_RESTORE_ALL_CALLER_REGS "popl %ecx;"
780
781 #define PV_FLAGS_ARG "0"
782 #define PV_EXTRA_CLOBBERS
783 #define PV_VEXTRA_CLOBBERS
784 #else
785 /* save and restore all caller-save registers, except return value */
786 #define PV_SAVE_ALL_CALLER_REGS \
787 "push %rcx;" \
788 "push %rdx;" \
789 "push %rsi;" \
790 "push %rdi;" \
791 "push %r8;" \
792 "push %r9;" \
793 "push %r10;" \
794 "push %r11;"
795 #define PV_RESTORE_ALL_CALLER_REGS \
796 "pop %r11;" \
797 "pop %r10;" \
798 "pop %r9;" \
799 "pop %r8;" \
800 "pop %rdi;" \
801 "pop %rsi;" \
802 "pop %rdx;" \
803 "pop %rcx;"
804
805 /* We save some registers, but all of them, that's too much. We clobber all
806 * caller saved registers but the argument parameter */
807 #define PV_SAVE_REGS "pushq %%rdi;"
808 #define PV_RESTORE_REGS "popq %%rdi;"
809 #define PV_EXTRA_CLOBBERS EXTRA_CLOBBERS, "rcx" , "rdx", "rsi"
810 #define PV_VEXTRA_CLOBBERS EXTRA_CLOBBERS, "rdi", "rcx" , "rdx", "rsi"
811 #define PV_FLAGS_ARG "D"
812 #endif
813
814 /*
815 * Generate a thunk around a function which saves all caller-save
816 * registers except for the return value. This allows C functions to
817 * be called from assembler code where fewer than normal registers are
818 * available. It may also help code generation around calls from C
819 * code if the common case doesn't use many registers.
820 *
821 * When a callee is wrapped in a thunk, the caller can assume that all
822 * arg regs and all scratch registers are preserved across the
823 * call. The return value in rax/eax will not be saved, even for void
824 * functions.
825 */
826 #define PV_CALLEE_SAVE_REGS_THUNK(func) \
827 extern typeof(func) __raw_callee_save_##func; \
828 static void *__##func##__ __used = func; \
829 \
830 asm(".pushsection .text;" \
831 "__raw_callee_save_" #func ": " \
832 PV_SAVE_ALL_CALLER_REGS \
833 "call " #func ";" \
834 PV_RESTORE_ALL_CALLER_REGS \
835 "ret;" \
836 ".popsection")
837
838 /* Get a reference to a callee-save function */
839 #define PV_CALLEE_SAVE(func) \
840 ((struct paravirt_callee_save) { __raw_callee_save_##func })
841
842 /* Promise that "func" already uses the right calling convention */
843 #define __PV_IS_CALLEE_SAVE(func) \
844 ((struct paravirt_callee_save) { func })
845
846 static inline unsigned long __raw_local_save_flags(void)
847 {
848 unsigned long f;
849
850 asm volatile(paravirt_alt(PARAVIRT_CALL)
851 : "=a"(f)
852 : paravirt_type(pv_irq_ops.save_fl),
853 paravirt_clobber(CLBR_EAX)
854 : "memory", "cc");
855 return f;
856 }
857
858 static inline void raw_local_irq_restore(unsigned long f)
859 {
860 asm volatile(paravirt_alt(PARAVIRT_CALL)
861 : "=a"(f)
862 : PV_FLAGS_ARG(f),
863 paravirt_type(pv_irq_ops.restore_fl),
864 paravirt_clobber(CLBR_EAX)
865 : "memory", "cc");
866 }
867
868 static inline void raw_local_irq_disable(void)
869 {
870 asm volatile(paravirt_alt(PARAVIRT_CALL)
871 :
872 : paravirt_type(pv_irq_ops.irq_disable),
873 paravirt_clobber(CLBR_EAX)
874 : "memory", "eax", "cc");
875 }
876
877 static inline void raw_local_irq_enable(void)
878 {
879 asm volatile(paravirt_alt(PARAVIRT_CALL)
880 :
881 : paravirt_type(pv_irq_ops.irq_enable),
882 paravirt_clobber(CLBR_EAX)
883 : "memory", "eax", "cc");
884 }
885
886 static inline unsigned long __raw_local_irq_save(void)
887 {
888 unsigned long f;
889
890 f = __raw_local_save_flags();
891 raw_local_irq_disable();
892 return f;
893 }
894
895
896 /* Make sure as little as possible of this mess escapes. */
897 #undef PARAVIRT_CALL
898 #undef __PVOP_CALL
899 #undef __PVOP_VCALL
900 #undef PVOP_VCALL0
901 #undef PVOP_CALL0
902 #undef PVOP_VCALL1
903 #undef PVOP_CALL1
904 #undef PVOP_VCALL2
905 #undef PVOP_CALL2
906 #undef PVOP_VCALL3
907 #undef PVOP_CALL3
908 #undef PVOP_VCALL4
909 #undef PVOP_CALL4
910
911 extern void default_banner(void);
912
913 #else /* __ASSEMBLY__ */
914
915 #define _PVSITE(ptype, clobbers, ops, word, algn) \
916 771:; \
917 ops; \
918 772:; \
919 .pushsection .parainstructions,"a"; \
920 .align algn; \
921 word 771b; \
922 .byte ptype; \
923 .byte 772b-771b; \
924 .short clobbers; \
925 .popsection
926
927
928 #define COND_PUSH(set, mask, reg) \
929 .if ((~(set)) & mask); push %reg; .endif
930 #define COND_POP(set, mask, reg) \
931 .if ((~(set)) & mask); pop %reg; .endif
932
933 #ifdef CONFIG_X86_64
934
935 #define PV_SAVE_REGS(set) \
936 COND_PUSH(set, CLBR_RAX, rax); \
937 COND_PUSH(set, CLBR_RCX, rcx); \
938 COND_PUSH(set, CLBR_RDX, rdx); \
939 COND_PUSH(set, CLBR_RSI, rsi); \
940 COND_PUSH(set, CLBR_RDI, rdi); \
941 COND_PUSH(set, CLBR_R8, r8); \
942 COND_PUSH(set, CLBR_R9, r9); \
943 COND_PUSH(set, CLBR_R10, r10); \
944 COND_PUSH(set, CLBR_R11, r11)
945 #define PV_RESTORE_REGS(set) \
946 COND_POP(set, CLBR_R11, r11); \
947 COND_POP(set, CLBR_R10, r10); \
948 COND_POP(set, CLBR_R9, r9); \
949 COND_POP(set, CLBR_R8, r8); \
950 COND_POP(set, CLBR_RDI, rdi); \
951 COND_POP(set, CLBR_RSI, rsi); \
952 COND_POP(set, CLBR_RDX, rdx); \
953 COND_POP(set, CLBR_RCX, rcx); \
954 COND_POP(set, CLBR_RAX, rax)
955
956 #define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 8)
957 #define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .quad, 8)
958 #define PARA_INDIRECT(addr) *addr(%rip)
959 #else
960 #define PV_SAVE_REGS(set) \
961 COND_PUSH(set, CLBR_EAX, eax); \
962 COND_PUSH(set, CLBR_EDI, edi); \
963 COND_PUSH(set, CLBR_ECX, ecx); \
964 COND_PUSH(set, CLBR_EDX, edx)
965 #define PV_RESTORE_REGS(set) \
966 COND_POP(set, CLBR_EDX, edx); \
967 COND_POP(set, CLBR_ECX, ecx); \
968 COND_POP(set, CLBR_EDI, edi); \
969 COND_POP(set, CLBR_EAX, eax)
970
971 #define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 4)
972 #define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .long, 4)
973 #define PARA_INDIRECT(addr) *%cs:addr
974 #endif
975
976 #define INTERRUPT_RETURN \
977 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_iret), CLBR_NONE, \
978 jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_iret))
979
980 #define DISABLE_INTERRUPTS(clobbers) \
981 PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_disable), clobbers, \
982 PV_SAVE_REGS(clobbers | CLBR_CALLEE_SAVE); \
983 call PARA_INDIRECT(pv_irq_ops+PV_IRQ_irq_disable); \
984 PV_RESTORE_REGS(clobbers | CLBR_CALLEE_SAVE);)
985
986 #define ENABLE_INTERRUPTS(clobbers) \
987 PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_enable), clobbers, \
988 PV_SAVE_REGS(clobbers | CLBR_CALLEE_SAVE); \
989 call PARA_INDIRECT(pv_irq_ops+PV_IRQ_irq_enable); \
990 PV_RESTORE_REGS(clobbers | CLBR_CALLEE_SAVE);)
991
992 #define USERGS_SYSRET32 \
993 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_usergs_sysret32), \
994 CLBR_NONE, \
995 jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_usergs_sysret32))
996
997 #ifdef CONFIG_X86_32
998 #define GET_CR0_INTO_EAX \
999 push %ecx; push %edx; \
1000 call PARA_INDIRECT(pv_cpu_ops+PV_CPU_read_cr0); \
1001 pop %edx; pop %ecx
1002
1003 #define ENABLE_INTERRUPTS_SYSEXIT \
1004 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_irq_enable_sysexit), \
1005 CLBR_NONE, \
1006 jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_irq_enable_sysexit))
1007
1008
1009 #else /* !CONFIG_X86_32 */
1010
1011 /*
1012 * If swapgs is used while the userspace stack is still current,
1013 * there's no way to call a pvop. The PV replacement *must* be
1014 * inlined, or the swapgs instruction must be trapped and emulated.
1015 */
1016 #define SWAPGS_UNSAFE_STACK \
1017 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_swapgs), CLBR_NONE, \
1018 swapgs)
1019
1020 /*
1021 * Note: swapgs is very special, and in practise is either going to be
1022 * implemented with a single "swapgs" instruction or something very
1023 * special. Either way, we don't need to save any registers for
1024 * it.
1025 */
1026 #define SWAPGS \
1027 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_swapgs), CLBR_NONE, \
1028 call PARA_INDIRECT(pv_cpu_ops+PV_CPU_swapgs) \
1029 )
1030
1031 #define GET_CR2_INTO_RCX \
1032 call PARA_INDIRECT(pv_mmu_ops+PV_MMU_read_cr2); \
1033 movq %rax, %rcx; \
1034 xorq %rax, %rax;
1035
1036 #define PARAVIRT_ADJUST_EXCEPTION_FRAME \
1037 PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_adjust_exception_frame), \
1038 CLBR_NONE, \
1039 call PARA_INDIRECT(pv_irq_ops+PV_IRQ_adjust_exception_frame))
1040
1041 #define USERGS_SYSRET64 \
1042 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_usergs_sysret64), \
1043 CLBR_NONE, \
1044 jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_usergs_sysret64))
1045
1046 #define ENABLE_INTERRUPTS_SYSEXIT32 \
1047 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_irq_enable_sysexit), \
1048 CLBR_NONE, \
1049 jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_irq_enable_sysexit))
1050 #endif /* CONFIG_X86_32 */
1051
1052 #endif /* __ASSEMBLY__ */
1053 #else /* CONFIG_PARAVIRT */
1054 # define default_banner x86_init_noop
1055 #endif /* !CONFIG_PARAVIRT */
1056 #endif /* _ASM_X86_PARAVIRT_H */
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