include/asm-mips/bcache.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (c) 1997, 1999 by Ralf Baechle
   7  * Copyright (c) 1999 Silicon Graphics, Inc.
   8  */
   9 #ifndef _ASM_BCACHE_H
  10 #define _ASM_BCACHE_H
  11
  12
  13 /* Some R4000 / R4400 / R4600 / R5000 machines may have a non-dma-coherent,
  14    chipset implemented caches.  On machines with other CPUs the CPU does the
  15    cache thing itself. */
  16 struct bcache_ops {
  17         void (*bc_enable)(void);
  18         void (*bc_disable)(void);
  19         void (*bc_wback_inv)(unsigned long page, unsigned long size);
  20         void (*bc_inv)(unsigned long page, unsigned long size);
  21 };
  22
  23 extern void indy_sc_init(void);
  24 extern void sni_pcimt_sc_init(void);
  25
  26 #ifdef CONFIG_BOARD_SCACHE
  27
  28 extern struct bcache_ops *bcops;
  29
  30 static inline void bc_enable(void)
  31 {
  32         bcops->bc_enable();
  33 }
  34
  35 static inline void bc_disable(void)
  36 {
  37         bcops->bc_disable();
  38 }
  39
  40 static inline void bc_wback_inv(unsigned long page, unsigned long size)
  41 {
  42         bcops->bc_wback_inv(page, size);
  43 }
  44
  45 static inline void bc_inv(unsigned long page, unsigned long size)
  46 {
  47         bcops->bc_inv(page, size);
  48 }
  49
  50 #else /* !defined(CONFIG_BOARD_SCACHE) */
  51
  52 /* Not R4000 / R4400 / R4600 / R5000.  */
  53
  54 #define bc_enable() do { } while (0)
  55 #define bc_disable() do { } while (0)
  56 #define bc_wback_inv(page, size) do { } while (0)
  57 #define bc_inv(page, size) do { } while (0)
  58
  59 #endif /* !defined(CONFIG_BOARD_SCACHE) */
  60
  61 #endif /* _ASM_BCACHE_H */