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pnpacpi: fix potential corruption on "pnpacpi: exceeded the max number of IRQ resourc...
[linux-2.6/mini2440.git] / drivers / serial / sh-sci.c
blobc2ea5d4df44a07c5aab6ae01bb86b9a73cade4d0
1 /*
2 * drivers/serial/sh-sci.c
3 *
4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 *
6 * Copyright (C) 2002 - 2006 Paul Mundt
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
8 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16 * Removed SH7300 support (Jul 2007).
17 *
18 * This file is subject to the terms and conditions of the GNU General Public
19 * License. See the file "COPYING" in the main directory of this archive
20 * for more details.
21 */
22 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
23 #define SUPPORT_SYSRQ
24 #endif
25
26 #undef DEBUG
27
28 #include <linux/module.h>
29 #include <linux/errno.h>
30 #include <linux/timer.h>
31 #include <linux/interrupt.h>
32 #include <linux/tty.h>
33 #include <linux/tty_flip.h>
34 #include <linux/serial.h>
35 #include <linux/major.h>
36 #include <linux/string.h>
37 #include <linux/sysrq.h>
38 #include <linux/ioport.h>
39 #include <linux/mm.h>
40 #include <linux/init.h>
41 #include <linux/delay.h>
42 #include <linux/console.h>
43 #include <linux/platform_device.h>
44 #include <linux/serial_sci.h>
45
46 #ifdef CONFIG_CPU_FREQ
47 #include <linux/notifier.h>
48 #include <linux/cpufreq.h>
49 #endif
50
51 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
52 #include <linux/ctype.h>
53 #include <asm/clock.h>
54 #include <asm/sh_bios.h>
55 #include <asm/kgdb.h>
56 #endif
57
58 #include "sh-sci.h"
59
60 struct sci_port {
61 struct uart_port port;
62
63 /* Port type */
64 unsigned int type;
65
66 /* Port IRQs: ERI, RXI, TXI, BRI (optional) */
67 unsigned int irqs[SCIx_NR_IRQS];
68
69 /* Port pin configuration */
70 void (*init_pins)(struct uart_port *port,
71 unsigned int cflag);
72
73 /* Port enable callback */
74 void (*enable)(struct uart_port *port);
75
76 /* Port disable callback */
77 void (*disable)(struct uart_port *port);
78
79 /* Break timer */
80 struct timer_list break_timer;
81 int break_flag;
82
83 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
84 /* Port clock */
85 struct clk *clk;
86 #endif
87 };
88
89 #ifdef CONFIG_SH_KGDB
90 static struct sci_port *kgdb_sci_port;
91 #endif
92
93 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
94 static struct sci_port *serial_console_port;
95 #endif
96
97 /* Function prototypes */
98 static void sci_stop_tx(struct uart_port *port);
99
100 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
101
102 static struct sci_port sci_ports[SCI_NPORTS];
103 static struct uart_driver sci_uart_driver;
104
105 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && \
106 defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB)
107 static inline void handle_error(struct uart_port *port)
108 {
109 /* Clear error flags */
110 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
111 }
112
113 static int get_char(struct uart_port *port)
114 {
115 unsigned long flags;
116 unsigned short status;
117 int c;
118
119 spin_lock_irqsave(&port->lock, flags);
120 do {
121 status = sci_in(port, SCxSR);
122 if (status & SCxSR_ERRORS(port)) {
123 handle_error(port);
124 continue;
125 }
126 } while (!(status & SCxSR_RDxF(port)));
127 c = sci_in(port, SCxRDR);
128 sci_in(port, SCxSR); /* Dummy read */
129 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
130 spin_unlock_irqrestore(&port->lock, flags);
131
132 return c;
133 }
134 #endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */
135
136 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || defined(CONFIG_SH_KGDB)
137 static void put_char(struct uart_port *port, char c)
138 {
139 unsigned long flags;
140 unsigned short status;
141
142 spin_lock_irqsave(&port->lock, flags);
143
144 do {
145 status = sci_in(port, SCxSR);
146 } while (!(status & SCxSR_TDxE(port)));
147
148 sci_out(port, SCxTDR, c);
149 sci_in(port, SCxSR); /* Dummy read */
150 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
151
152 spin_unlock_irqrestore(&port->lock, flags);
153 }
154 #endif
155
156 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
157 static void put_string(struct sci_port *sci_port, const char *buffer, int count)
158 {
159 struct uart_port *port = &sci_port->port;
160 const unsigned char *p = buffer;
161 int i;
162
163 #if defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB)
164 int checksum;
165 int usegdb=0;
166
167 #ifdef CONFIG_SH_STANDARD_BIOS
168 /* This call only does a trap the first time it is
169 * called, and so is safe to do here unconditionally
170 */
171 usegdb |= sh_bios_in_gdb_mode();
172 #endif
173 #ifdef CONFIG_SH_KGDB
174 usegdb |= (kgdb_in_gdb_mode && (sci_port == kgdb_sci_port));
175 #endif
176
177 if (usegdb) {
178 /* $<packet info>#<checksum>. */
179 do {
180 unsigned char c;
181 put_char(port, '$');
182 put_char(port, 'O'); /* 'O'utput to console */
183 checksum = 'O';
184
185 for (i=0; i<count; i++) { /* Don't use run length encoding */
186 int h, l;
187
188 c = *p++;
189 h = highhex(c);
190 l = lowhex(c);
191 put_char(port, h);
192 put_char(port, l);
193 checksum += h + l;
194 }
195 put_char(port, '#');
196 put_char(port, highhex(checksum));
197 put_char(port, lowhex(checksum));
198 } while (get_char(port) != '+');
199 } else
200 #endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */
201 for (i=0; i<count; i++) {
202 if (*p == 10)
203 put_char(port, '\r');
204 put_char(port, *p++);
205 }
206 }
207 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
208
209 #ifdef CONFIG_SH_KGDB
210 static int kgdb_sci_getchar(void)
211 {
212 int c;
213
214 /* Keep trying to read a character, this could be neater */
215 while ((c = get_char(&kgdb_sci_port->port)) < 0)
216 cpu_relax();
217
218 return c;
219 }
220
221 static inline void kgdb_sci_putchar(int c)
222 {
223 put_char(&kgdb_sci_port->port, c);
224 }
225 #endif /* CONFIG_SH_KGDB */
226
227 #if defined(__H8300S__)
228 enum { sci_disable, sci_enable };
229
230 static void h8300_sci_config(struct uart_port* port, unsigned int ctrl)
231 {
232 volatile unsigned char *mstpcrl=(volatile unsigned char *)MSTPCRL;
233 int ch = (port->mapbase - SMR0) >> 3;
234 unsigned char mask = 1 << (ch+1);
235
236 if (ctrl == sci_disable) {
237 *mstpcrl |= mask;
238 } else {
239 *mstpcrl &= ~mask;
240 }
241 }
242
243 static inline void h8300_sci_enable(struct uart_port *port)
244 {
245 h8300_sci_config(port, sci_enable);
246 }
247
248 static inline void h8300_sci_disable(struct uart_port *port)
249 {
250 h8300_sci_config(port, sci_disable);
251 }
252 #endif
253
254 #if defined(SCI_ONLY) || defined(SCI_AND_SCIF) && \
255 defined(__H8300H__) || defined(__H8300S__)
256 static void sci_init_pins_sci(struct uart_port* port, unsigned int cflag)
257 {
258 int ch = (port->mapbase - SMR0) >> 3;
259
260 /* set DDR regs */
261 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
262 h8300_sci_pins[ch].rx,
263 H8300_GPIO_INPUT);
264 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
265 h8300_sci_pins[ch].tx,
266 H8300_GPIO_OUTPUT);
267
268 /* tx mark output*/
269 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
270 }
271 #else
272 #define sci_init_pins_sci NULL
273 #endif
274
275 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
276 static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag)
277 {
278 unsigned int fcr_val = 0;
279
280 if (cflag & CRTSCTS)
281 fcr_val |= SCFCR_MCE;
282
283 sci_out(port, SCFCR, fcr_val);
284 }
285 #else
286 #define sci_init_pins_irda NULL
287 #endif
288
289 #ifdef SCI_ONLY
290 #define sci_init_pins_scif NULL
291 #endif
292
293 #if defined(SCIF_ONLY) || defined(SCI_AND_SCIF)
294 #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
295 static void sci_init_pins_scif(struct uart_port* port, unsigned int cflag)
296 {
297 unsigned int fcr_val = 0;
298
299 set_sh771x_scif_pfc(port);
300 if (cflag & CRTSCTS) {
301 fcr_val |= SCFCR_MCE;
302 }
303 sci_out(port, SCFCR, fcr_val);
304 }
305 #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721)
306 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
307 {
308 unsigned int fcr_val = 0;
309 unsigned short data;
310
311 if (cflag & CRTSCTS) {
312 /* enable RTS/CTS */
313 if (port->mapbase == 0xa4430000) { /* SCIF0 */
314 /* Clear PTCR bit 9-2; enable all scif pins but sck */
315 data = ctrl_inw(PORT_PTCR);
316 ctrl_outw((data & 0xfc03), PORT_PTCR);
317 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
318 /* Clear PVCR bit 9-2 */
319 data = ctrl_inw(PORT_PVCR);
320 ctrl_outw((data & 0xfc03), PORT_PVCR);
321 }
322 fcr_val |= SCFCR_MCE;
323 } else {
324 if (port->mapbase == 0xa4430000) { /* SCIF0 */
325 /* Clear PTCR bit 5-2; enable only tx and rx */
326 data = ctrl_inw(PORT_PTCR);
327 ctrl_outw((data & 0xffc3), PORT_PTCR);
328 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
329 /* Clear PVCR bit 5-2 */
330 data = ctrl_inw(PORT_PVCR);
331 ctrl_outw((data & 0xffc3), PORT_PVCR);
332 }
333 }
334 sci_out(port, SCFCR, fcr_val);
335 }
336 #elif defined(CONFIG_CPU_SH3)
337 /* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
338 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
339 {
340 unsigned int fcr_val = 0;
341 unsigned short data;
342
343 /* We need to set SCPCR to enable RTS/CTS */
344 data = ctrl_inw(SCPCR);
345 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
346 ctrl_outw(data & 0x0fcf, SCPCR);
347
348 if (cflag & CRTSCTS)
349 fcr_val |= SCFCR_MCE;
350 else {
351 /* We need to set SCPCR to enable RTS/CTS */
352 data = ctrl_inw(SCPCR);
353 /* Clear out SCP7MD1,0, SCP4MD1,0,
354 Set SCP6MD1,0 = {01} (output) */
355 ctrl_outw((data & 0x0fcf) | 0x1000, SCPCR);
356
357 data = ctrl_inb(SCPDR);
358 /* Set /RTS2 (bit6) = 0 */
359 ctrl_outb(data & 0xbf, SCPDR);
360 }
361
362 sci_out(port, SCFCR, fcr_val);
363 }
364 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
365 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
366 {
367 unsigned int fcr_val = 0;
368
369 if (cflag & CRTSCTS) {
370 fcr_val |= SCFCR_MCE;
371
372 ctrl_outw(0x0000, PORT_PSCR);
373 } else {
374 unsigned short data;
375
376 data = ctrl_inw(PORT_PSCR);
377 data &= 0x033f;
378 data |= 0x0400;
379 ctrl_outw(data, PORT_PSCR);
380
381 ctrl_outw(ctrl_inw(SCSPTR0) & 0x17, SCSPTR0);
382 }
383
384 sci_out(port, SCFCR, fcr_val);
385 }
386 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)
387 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
388 {
389 /* Nothing to do here.. */
390 sci_out(port, SCFCR, 0);
391 }
392 #else
393 /* For SH7750 */
394 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
395 {
396 unsigned int fcr_val = 0;
397
398 if (cflag & CRTSCTS) {
399 fcr_val |= SCFCR_MCE;
400 } else {
401 #if defined(CONFIG_CPU_SUBTYPE_SH7343) || defined(CONFIG_CPU_SUBTYPE_SH7366)
402 /* Nothing */
403 #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
404 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
405 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
406 defined(CONFIG_CPU_SUBTYPE_SHX3)
407 ctrl_outw(0x0080, SCSPTR0); /* Set RTS = 1 */
408 #else
409 ctrl_outw(0x0080, SCSPTR2); /* Set RTS = 1 */
410 #endif
411 }
412 sci_out(port, SCFCR, fcr_val);
413 }
414 #endif
415
416 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
417 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
418 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
419 defined(CONFIG_CPU_SUBTYPE_SH7785)
420 static inline int scif_txroom(struct uart_port *port)
421 {
422 return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff);
423 }
424
425 static inline int scif_rxroom(struct uart_port *port)
426 {
427 return sci_in(port, SCRFDR) & 0xff;
428 }
429 #else
430 static inline int scif_txroom(struct uart_port *port)
431 {
432 return SCIF_TXROOM_MAX - (sci_in(port, SCFDR) >> 8);
433 }
434
435 static inline int scif_rxroom(struct uart_port *port)
436 {
437 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
438 }
439 #endif
440 #endif /* SCIF_ONLY || SCI_AND_SCIF */
441
442 static inline int sci_txroom(struct uart_port *port)
443 {
444 return ((sci_in(port, SCxSR) & SCI_TDRE) != 0);
445 }
446
447 static inline int sci_rxroom(struct uart_port *port)
448 {
449 return ((sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0);
450 }
451
452 /* ********************************************************************** *
453 * the interrupt related routines *
454 * ********************************************************************** */
455
456 static void sci_transmit_chars(struct uart_port *port)
457 {
458 struct circ_buf *xmit = &port->info->xmit;
459 unsigned int stopped = uart_tx_stopped(port);
460 unsigned short status;
461 unsigned short ctrl;
462 int count;
463
464 status = sci_in(port, SCxSR);
465 if (!(status & SCxSR_TDxE(port))) {
466 ctrl = sci_in(port, SCSCR);
467 if (uart_circ_empty(xmit)) {
468 ctrl &= ~SCI_CTRL_FLAGS_TIE;
469 } else {
470 ctrl |= SCI_CTRL_FLAGS_TIE;
471 }
472 sci_out(port, SCSCR, ctrl);
473 return;
474 }
475
476 #ifndef SCI_ONLY
477 if (port->type == PORT_SCIF)
478 count = scif_txroom(port);
479 else
480 #endif
481 count = sci_txroom(port);
482
483 do {
484 unsigned char c;
485
486 if (port->x_char) {
487 c = port->x_char;
488 port->x_char = 0;
489 } else if (!uart_circ_empty(xmit) && !stopped) {
490 c = xmit->buf[xmit->tail];
491 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
492 } else {
493 break;
494 }
495
496 sci_out(port, SCxTDR, c);
497
498 port->icount.tx++;
499 } while (--count > 0);
500
501 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
502
503 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
504 uart_write_wakeup(port);
505 if (uart_circ_empty(xmit)) {
506 sci_stop_tx(port);
507 } else {
508 ctrl = sci_in(port, SCSCR);
509
510 #if !defined(SCI_ONLY)
511 if (port->type == PORT_SCIF) {
512 sci_in(port, SCxSR); /* Dummy read */
513 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
514 }
515 #endif
516
517 ctrl |= SCI_CTRL_FLAGS_TIE;
518 sci_out(port, SCSCR, ctrl);
519 }
520 }
521
522 /* On SH3, SCIF may read end-of-break as a space->mark char */
523 #define STEPFN(c) ({int __c=(c); (((__c-1)|(__c)) == -1); })
524
525 static inline void sci_receive_chars(struct uart_port *port)
526 {
527 struct sci_port *sci_port = (struct sci_port *)port;
528 struct tty_struct *tty = port->info->tty;
529 int i, count, copied = 0;
530 unsigned short status;
531 unsigned char flag;
532
533 status = sci_in(port, SCxSR);
534 if (!(status & SCxSR_RDxF(port)))
535 return;
536
537 while (1) {
538 #if !defined(SCI_ONLY)
539 if (port->type == PORT_SCIF)
540 count = scif_rxroom(port);
541 else
542 #endif
543 count = sci_rxroom(port);
544
545 /* Don't copy more bytes than there is room for in the buffer */
546 count = tty_buffer_request_room(tty, count);
547
548 /* If for any reason we can't copy more data, we're done! */
549 if (count == 0)
550 break;
551
552 if (port->type == PORT_SCI) {
553 char c = sci_in(port, SCxRDR);
554 if (uart_handle_sysrq_char(port, c) || sci_port->break_flag)
555 count = 0;
556 else {
557 tty_insert_flip_char(tty, c, TTY_NORMAL);
558 }
559 } else {
560 for (i=0; i<count; i++) {
561 char c = sci_in(port, SCxRDR);
562 status = sci_in(port, SCxSR);
563 #if defined(CONFIG_CPU_SH3)
564 /* Skip "chars" during break */
565 if (sci_port->break_flag) {
566 if ((c == 0) &&
567 (status & SCxSR_FER(port))) {
568 count--; i--;
569 continue;
570 }
571
572 /* Nonzero => end-of-break */
573 pr_debug("scif: debounce<%02x>\n", c);
574 sci_port->break_flag = 0;
575
576 if (STEPFN(c)) {
577 count--; i--;
578 continue;
579 }
580 }
581 #endif /* CONFIG_CPU_SH3 */
582 if (uart_handle_sysrq_char(port, c)) {
583 count--; i--;
584 continue;
585 }
586
587 /* Store data and status */
588 if (status&SCxSR_FER(port)) {
589 flag = TTY_FRAME;
590 pr_debug("sci: frame error\n");
591 } else if (status&SCxSR_PER(port)) {
592 flag = TTY_PARITY;
593 pr_debug("sci: parity error\n");
594 } else
595 flag = TTY_NORMAL;
596 tty_insert_flip_char(tty, c, flag);
597 }
598 }
599
600 sci_in(port, SCxSR); /* dummy read */
601 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
602
603 copied += count;
604 port->icount.rx += count;
605 }
606
607 if (copied) {
608 /* Tell the rest of the system the news. New characters! */
609 tty_flip_buffer_push(tty);
610 } else {
611 sci_in(port, SCxSR); /* dummy read */
612 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
613 }
614 }
615
616 #define SCI_BREAK_JIFFIES (HZ/20)
617 /* The sci generates interrupts during the break,
618 * 1 per millisecond or so during the break period, for 9600 baud.
619 * So dont bother disabling interrupts.
620 * But dont want more than 1 break event.
621 * Use a kernel timer to periodically poll the rx line until
622 * the break is finished.
623 */
624 static void sci_schedule_break_timer(struct sci_port *port)
625 {
626 port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES;
627 add_timer(&port->break_timer);
628 }
629 /* Ensure that two consecutive samples find the break over. */
630 static void sci_break_timer(unsigned long data)
631 {
632 struct sci_port *port = (struct sci_port *)data;
633
634 if (sci_rxd_in(&port->port) == 0) {
635 port->break_flag = 1;
636 sci_schedule_break_timer(port);
637 } else if (port->break_flag == 1) {
638 /* break is over. */
639 port->break_flag = 2;
640 sci_schedule_break_timer(port);
641 } else
642 port->break_flag = 0;
643 }
644
645 static inline int sci_handle_errors(struct uart_port *port)
646 {
647 int copied = 0;
648 unsigned short status = sci_in(port, SCxSR);
649 struct tty_struct *tty = port->info->tty;
650
651 if (status & SCxSR_ORER(port)) {
652 /* overrun error */
653 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
654 copied++;
655 pr_debug("sci: overrun error\n");
656 }
657
658 if (status & SCxSR_FER(port)) {
659 if (sci_rxd_in(port) == 0) {
660 /* Notify of BREAK */
661 struct sci_port *sci_port = (struct sci_port *)port;
662
663 if (!sci_port->break_flag) {
664 sci_port->break_flag = 1;
665 sci_schedule_break_timer(sci_port);
666
667 /* Do sysrq handling. */
668 if (uart_handle_break(port))
669 return 0;
670 pr_debug("sci: BREAK detected\n");
671 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
672 copied++;
673 }
674 } else {
675 /* frame error */
676 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
677 copied++;
678 pr_debug("sci: frame error\n");
679 }
680 }
681
682 if (status & SCxSR_PER(port)) {
683 /* parity error */
684 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
685 copied++;
686 pr_debug("sci: parity error\n");
687 }
688
689 if (copied)
690 tty_flip_buffer_push(tty);
691
692 return copied;
693 }
694
695 static inline int sci_handle_breaks(struct uart_port *port)
696 {
697 int copied = 0;
698 unsigned short status = sci_in(port, SCxSR);
699 struct tty_struct *tty = port->info->tty;
700 struct sci_port *s = &sci_ports[port->line];
701
702 if (uart_handle_break(port))
703 return 0;
704
705 if (!s->break_flag && status & SCxSR_BRK(port)) {
706 #if defined(CONFIG_CPU_SH3)
707 /* Debounce break */
708 s->break_flag = 1;
709 #endif
710 /* Notify of BREAK */
711 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
712 copied++;
713 pr_debug("sci: BREAK detected\n");
714 }
715
716 #if defined(SCIF_ORER)
717 /* XXX: Handle SCIF overrun error */
718 if (port->type == PORT_SCIF && (sci_in(port, SCLSR) & SCIF_ORER) != 0) {
719 sci_out(port, SCLSR, 0);
720 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN)) {
721 copied++;
722 pr_debug("sci: overrun error\n");
723 }
724 }
725 #endif
726
727 if (copied)
728 tty_flip_buffer_push(tty);
729
730 return copied;
731 }
732
733 static irqreturn_t sci_rx_interrupt(int irq, void *port)
734 {
735 /* I think sci_receive_chars has to be called irrespective
736 * of whether the I_IXOFF is set, otherwise, how is the interrupt
737 * to be disabled?
738 */
739 sci_receive_chars(port);
740
741 return IRQ_HANDLED;
742 }
743
744 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
745 {
746 struct uart_port *port = ptr;
747
748 spin_lock_irq(&port->lock);
749 sci_transmit_chars(port);
750 spin_unlock_irq(&port->lock);
751
752 return IRQ_HANDLED;
753 }
754
755 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
756 {
757 struct uart_port *port = ptr;
758
759 /* Handle errors */
760 if (port->type == PORT_SCI) {
761 if (sci_handle_errors(port)) {
762 /* discard character in rx buffer */
763 sci_in(port, SCxSR);
764 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
765 }
766 } else {
767 #if defined(SCIF_ORER)
768 if((sci_in(port, SCLSR) & SCIF_ORER) != 0) {
769 struct tty_struct *tty = port->info->tty;
770
771 sci_out(port, SCLSR, 0);
772 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
773 tty_flip_buffer_push(tty);
774 pr_debug("scif: overrun error\n");
775 }
776 #endif
777 sci_rx_interrupt(irq, ptr);
778 }
779
780 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
781
782 /* Kick the transmission */
783 sci_tx_interrupt(irq, ptr);
784
785 return IRQ_HANDLED;
786 }
787
788 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
789 {
790 struct uart_port *port = ptr;
791
792 /* Handle BREAKs */
793 sci_handle_breaks(port);
794 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
795
796 return IRQ_HANDLED;
797 }
798
799 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
800 {
801 unsigned short ssr_status, scr_status;
802 struct uart_port *port = ptr;
803
804 ssr_status = sci_in(port,SCxSR);
805 scr_status = sci_in(port,SCSCR);
806
807 /* Tx Interrupt */
808 if ((ssr_status & 0x0020) && (scr_status & 0x0080))
809 sci_tx_interrupt(irq, ptr);
810 /* Rx Interrupt */
811 if ((ssr_status & 0x0002) && (scr_status & 0x0040))
812 sci_rx_interrupt(irq, ptr);
813 /* Error Interrupt */
814 if ((ssr_status & 0x0080) && (scr_status & 0x0400))
815 sci_er_interrupt(irq, ptr);
816 /* Break Interrupt */
817 if ((ssr_status & 0x0010) && (scr_status & 0x0200))
818 sci_br_interrupt(irq, ptr);
819
820 return IRQ_HANDLED;
821 }
822
823 #ifdef CONFIG_CPU_FREQ
824 /*
825 * Here we define a transistion notifier so that we can update all of our
826 * ports' baud rate when the peripheral clock changes.
827 */
828 static int sci_notifier(struct notifier_block *self,
829 unsigned long phase, void *p)
830 {
831 struct cpufreq_freqs *freqs = p;
832 int i;
833
834 if ((phase == CPUFREQ_POSTCHANGE) ||
835 (phase == CPUFREQ_RESUMECHANGE)){
836 for (i = 0; i < SCI_NPORTS; i++) {
837 struct uart_port *port = &sci_ports[i].port;
838 struct clk *clk;
839
840 /*
841 * Update the uartclk per-port if frequency has
842 * changed, since it will no longer necessarily be
843 * consistent with the old frequency.
844 *
845 * Really we want to be able to do something like
846 * uart_change_speed() or something along those lines
847 * here to implicitly reset the per-port baud rate..
848 *
849 * Clean this up later..
850 */
851 clk = clk_get(NULL, "module_clk");
852 port->uartclk = clk_get_rate(clk) * 16;
853 clk_put(clk);
854 }
855
856 printk(KERN_INFO "%s: got a postchange notification "
857 "for cpu %d (old %d, new %d)\n",
858 __FUNCTION__, freqs->cpu, freqs->old, freqs->new);
859 }
860
861 return NOTIFY_OK;
862 }
863
864 static struct notifier_block sci_nb = { &sci_notifier, NULL, 0 };
865 #endif /* CONFIG_CPU_FREQ */
866
867 static int sci_request_irq(struct sci_port *port)
868 {
869 int i;
870 irqreturn_t (*handlers[4])(int irq, void *ptr) = {
871 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt,
872 sci_br_interrupt,
873 };
874 const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full",
875 "SCI Transmit Data Empty", "SCI Break" };
876
877 if (port->irqs[0] == port->irqs[1]) {
878 if (!port->irqs[0]) {
879 printk(KERN_ERR "sci: Cannot allocate irq.(IRQ=0)\n");
880 return -ENODEV;
881 }
882
883 if (request_irq(port->irqs[0], sci_mpxed_interrupt,
884 IRQF_DISABLED, "sci", port)) {
885 printk(KERN_ERR "sci: Cannot allocate irq.\n");
886 return -ENODEV;
887 }
888 } else {
889 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
890 if (!port->irqs[i])
891 continue;
892 if (request_irq(port->irqs[i], handlers[i],
893 IRQF_DISABLED, desc[i], port)) {
894 printk(KERN_ERR "sci: Cannot allocate irq.\n");
895 return -ENODEV;
896 }
897 }
898 }
899
900 return 0;
901 }
902
903 static void sci_free_irq(struct sci_port *port)
904 {
905 int i;
906
907 if (port->irqs[0] == port->irqs[1]) {
908 if (!port->irqs[0])
909 printk("sci: sci_free_irq error\n");
910 else
911 free_irq(port->irqs[0], port);
912 } else {
913 for (i = 0; i < ARRAY_SIZE(port->irqs); i++) {
914 if (!port->irqs[i])
915 continue;
916
917 free_irq(port->irqs[i], port);
918 }
919 }
920 }
921
922 static unsigned int sci_tx_empty(struct uart_port *port)
923 {
924 /* Can't detect */
925 return TIOCSER_TEMT;
926 }
927
928 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
929 {
930 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
931 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
932 /* If you have signals for DTR and DCD, please implement here. */
933 }
934
935 static unsigned int sci_get_mctrl(struct uart_port *port)
936 {
937 /* This routine is used for geting signals of: DTR, DCD, DSR, RI,
938 and CTS/RTS */
939
940 return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
941 }
942
943 static void sci_start_tx(struct uart_port *port)
944 {
945 unsigned short ctrl;
946
947 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
948 ctrl = sci_in(port, SCSCR);
949 ctrl |= SCI_CTRL_FLAGS_TIE;
950 sci_out(port, SCSCR, ctrl);
951 }
952
953 static void sci_stop_tx(struct uart_port *port)
954 {
955 unsigned short ctrl;
956
957 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
958 ctrl = sci_in(port, SCSCR);
959 ctrl &= ~SCI_CTRL_FLAGS_TIE;
960 sci_out(port, SCSCR, ctrl);
961 }
962
963 static void sci_start_rx(struct uart_port *port, unsigned int tty_start)
964 {
965 unsigned short ctrl;
966
967 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */
968 ctrl = sci_in(port, SCSCR);
969 ctrl |= SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE;
970 sci_out(port, SCSCR, ctrl);
971 }
972
973 static void sci_stop_rx(struct uart_port *port)
974 {
975 unsigned short ctrl;
976
977 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
978 ctrl = sci_in(port, SCSCR);
979 ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE);
980 sci_out(port, SCSCR, ctrl);
981 }
982
983 static void sci_enable_ms(struct uart_port *port)
984 {
985 /* Nothing here yet .. */
986 }
987
988 static void sci_break_ctl(struct uart_port *port, int break_state)
989 {
990 /* Nothing here yet .. */
991 }
992
993 static int sci_startup(struct uart_port *port)
994 {
995 struct sci_port *s = &sci_ports[port->line];
996
997 if (s->enable)
998 s->enable(port);
999
1000 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
1001 s->clk = clk_get(NULL, "module_clk");
1002 #endif
1003
1004 sci_request_irq(s);
1005 sci_start_tx(port);
1006 sci_start_rx(port, 1);
1007
1008 return 0;
1009 }
1010
1011 static void sci_shutdown(struct uart_port *port)
1012 {
1013 struct sci_port *s = &sci_ports[port->line];
1014
1015 sci_stop_rx(port);
1016 sci_stop_tx(port);
1017 sci_free_irq(s);
1018
1019 if (s->disable)
1020 s->disable(port);
1021
1022 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
1023 clk_put(s->clk);
1024 s->clk = NULL;
1025 #endif
1026 }
1027
1028 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1029 struct ktermios *old)
1030 {
1031 struct sci_port *s = &sci_ports[port->line];
1032 unsigned int status, baud, smr_val;
1033 int t;
1034
1035 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
1036
1037 switch (baud) {
1038 case 0:
1039 t = -1;
1040 break;
1041 default:
1042 {
1043 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
1044 t = SCBRR_VALUE(baud, clk_get_rate(s->clk));
1045 #else
1046 t = SCBRR_VALUE(baud);
1047 #endif
1048 break;
1049 }
1050 }
1051
1052 do {
1053 status = sci_in(port, SCxSR);
1054 } while (!(status & SCxSR_TEND(port)));
1055
1056 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1057
1058 #if !defined(SCI_ONLY)
1059 if (port->type == PORT_SCIF)
1060 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1061 #endif
1062
1063 smr_val = sci_in(port, SCSMR) & 3;
1064 if ((termios->c_cflag & CSIZE) == CS7)
1065 smr_val |= 0x40;
1066 if (termios->c_cflag & PARENB)
1067 smr_val |= 0x20;
1068 if (termios->c_cflag & PARODD)
1069 smr_val |= 0x30;
1070 if (termios->c_cflag & CSTOPB)
1071 smr_val |= 0x08;
1072
1073 uart_update_timeout(port, termios->c_cflag, baud);
1074
1075 sci_out(port, SCSMR, smr_val);
1076
1077 if (t > 0) {
1078 if(t >= 256) {
1079 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
1080 t >>= 2;
1081 } else {
1082 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
1083 }
1084 sci_out(port, SCBRR, t);
1085 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1086 }
1087
1088 if (likely(s->init_pins))
1089 s->init_pins(port, termios->c_cflag);
1090
1091 sci_out(port, SCSCR, SCSCR_INIT(port));
1092
1093 if ((termios->c_cflag & CREAD) != 0)
1094 sci_start_rx(port,0);
1095 }
1096
1097 static const char *sci_type(struct uart_port *port)
1098 {
1099 switch (port->type) {
1100 case PORT_SCI: return "sci";
1101 case PORT_SCIF: return "scif";
1102 case PORT_IRDA: return "irda";
1103 }
1104
1105 return 0;
1106 }
1107
1108 static void sci_release_port(struct uart_port *port)
1109 {
1110 /* Nothing here yet .. */
1111 }
1112
1113 static int sci_request_port(struct uart_port *port)
1114 {
1115 /* Nothing here yet .. */
1116 return 0;
1117 }
1118
1119 static void sci_config_port(struct uart_port *port, int flags)
1120 {
1121 struct sci_port *s = &sci_ports[port->line];
1122
1123 port->type = s->type;
1124
1125 switch (port->type) {
1126 case PORT_SCI:
1127 s->init_pins = sci_init_pins_sci;
1128 break;
1129 case PORT_SCIF:
1130 s->init_pins = sci_init_pins_scif;
1131 break;
1132 case PORT_IRDA:
1133 s->init_pins = sci_init_pins_irda;
1134 break;
1135 }
1136
1137 #if defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
1138 if (port->mapbase == 0)
1139 port->mapbase = onchip_remap(SCIF_ADDR_SH5, 1024, "SCIF");
1140
1141 port->membase = (void __iomem *)port->mapbase;
1142 #endif
1143 }
1144
1145 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1146 {
1147 struct sci_port *s = &sci_ports[port->line];
1148
1149 if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > NR_IRQS)
1150 return -EINVAL;
1151 if (ser->baud_base < 2400)
1152 /* No paper tape reader for Mitch.. */
1153 return -EINVAL;
1154
1155 return 0;
1156 }
1157
1158 static struct uart_ops sci_uart_ops = {
1159 .tx_empty = sci_tx_empty,
1160 .set_mctrl = sci_set_mctrl,
1161 .get_mctrl = sci_get_mctrl,
1162 .start_tx = sci_start_tx,
1163 .stop_tx = sci_stop_tx,
1164 .stop_rx = sci_stop_rx,
1165 .enable_ms = sci_enable_ms,
1166 .break_ctl = sci_break_ctl,
1167 .startup = sci_startup,
1168 .shutdown = sci_shutdown,
1169 .set_termios = sci_set_termios,
1170 .type = sci_type,
1171 .release_port = sci_release_port,
1172 .request_port = sci_request_port,
1173 .config_port = sci_config_port,
1174 .verify_port = sci_verify_port,
1175 };
1176
1177 static void __init sci_init_ports(void)
1178 {
1179 static int first = 1;
1180 int i;
1181
1182 if (!first)
1183 return;
1184
1185 first = 0;
1186
1187 for (i = 0; i < SCI_NPORTS; i++) {
1188 sci_ports[i].port.ops = &sci_uart_ops;
1189 sci_ports[i].port.iotype = UPIO_MEM;
1190 sci_ports[i].port.line = i;
1191 sci_ports[i].port.fifosize = 1;
1192
1193 #if defined(__H8300H__) || defined(__H8300S__)
1194 #ifdef __H8300S__
1195 sci_ports[i].enable = h8300_sci_enable;
1196 sci_ports[i].disable = h8300_sci_disable;
1197 #endif
1198 sci_ports[i].port.uartclk = CONFIG_CPU_CLOCK;
1199 #elif defined(CONFIG_SUPERH64)
1200 sci_ports[i].port.uartclk = current_cpu_data.module_clock * 16;
1201 #else
1202 /*
1203 * XXX: We should use a proper SCI/SCIF clock
1204 */
1205 {
1206 struct clk *clk = clk_get(NULL, "module_clk");
1207 sci_ports[i].port.uartclk = clk_get_rate(clk) * 16;
1208 clk_put(clk);
1209 }
1210 #endif
1211
1212 sci_ports[i].break_timer.data = (unsigned long)&sci_ports[i];
1213 sci_ports[i].break_timer.function = sci_break_timer;
1214
1215 init_timer(&sci_ports[i].break_timer);
1216 }
1217 }
1218
1219 int __init early_sci_setup(struct uart_port *port)
1220 {
1221 if (unlikely(port->line > SCI_NPORTS))
1222 return -ENODEV;
1223
1224 sci_init_ports();
1225
1226 sci_ports[port->line].port.membase = port->membase;
1227 sci_ports[port->line].port.mapbase = port->mapbase;
1228 sci_ports[port->line].port.type = port->type;
1229
1230 return 0;
1231 }
1232
1233 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1234 /*
1235 * Print a string to the serial port trying not to disturb
1236 * any possible real use of the port...
1237 */
1238 static void serial_console_write(struct console *co, const char *s,
1239 unsigned count)
1240 {
1241 put_string(serial_console_port, s, count);
1242 }
1243
1244 static int __init serial_console_setup(struct console *co, char *options)
1245 {
1246 struct uart_port *port;
1247 int baud = 115200;
1248 int bits = 8;
1249 int parity = 'n';
1250 int flow = 'n';
1251 int ret;
1252
1253 /*
1254 * Check whether an invalid uart number has been specified, and
1255 * if so, search for the first available port that does have
1256 * console support.
1257 */
1258 if (co->index >= SCI_NPORTS)
1259 co->index = 0;
1260
1261 serial_console_port = &sci_ports[co->index];
1262 port = &serial_console_port->port;
1263
1264 /*
1265 * Also need to check port->type, we don't actually have any
1266 * UPIO_PORT ports, but uart_report_port() handily misreports
1267 * it anyways if we don't have a port available by the time this is
1268 * called.
1269 */
1270 if (!port->type)
1271 return -ENODEV;
1272 if (!port->membase || !port->mapbase)
1273 return -ENODEV;
1274
1275 port->type = serial_console_port->type;
1276
1277 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
1278 if (!serial_console_port->clk)
1279 serial_console_port->clk = clk_get(NULL, "module_clk");
1280 #endif
1281
1282 if (port->flags & UPF_IOREMAP)
1283 sci_config_port(port, 0);
1284
1285 if (serial_console_port->enable)
1286 serial_console_port->enable(port);
1287
1288 if (options)
1289 uart_parse_options(options, &baud, &parity, &bits, &flow);
1290
1291 ret = uart_set_options(port, co, baud, parity, bits, flow);
1292 #if defined(__H8300H__) || defined(__H8300S__)
1293 /* disable rx interrupt */
1294 if (ret == 0)
1295 sci_stop_rx(port);
1296 #endif
1297 return ret;
1298 }
1299
1300 static struct console serial_console = {
1301 .name = "ttySC",
1302 .device = uart_console_device,
1303 .write = serial_console_write,
1304 .setup = serial_console_setup,
1305 .flags = CON_PRINTBUFFER,
1306 .index = -1,
1307 .data = &sci_uart_driver,
1308 };
1309
1310 static int __init sci_console_init(void)
1311 {
1312 sci_init_ports();
1313 register_console(&serial_console);
1314 return 0;
1315 }
1316 console_initcall(sci_console_init);
1317 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1318
1319 #ifdef CONFIG_SH_KGDB_CONSOLE
1320 /*
1321 * FIXME: Most of this can go away.. at the moment, we rely on
1322 * arch/sh/kernel/setup.c to do the command line parsing for kgdb, though
1323 * most of that can easily be done here instead.
1324 *
1325 * For the time being, just accept the values that were parsed earlier..
1326 */
1327 static void __init kgdb_console_get_options(struct uart_port *port, int *baud,
1328 int *parity, int *bits)
1329 {
1330 *baud = kgdb_baud;
1331 *parity = tolower(kgdb_parity);
1332 *bits = kgdb_bits - '0';
1333 }
1334
1335 /*
1336 * The naming here is somewhat misleading, since kgdb_console_setup() takes
1337 * care of the early-on initialization for kgdb, regardless of whether we
1338 * actually use kgdb as a console or not.
1339 *
1340 * On the plus side, this lets us kill off the old kgdb_sci_setup() nonsense.
1341 */
1342 int __init kgdb_console_setup(struct console *co, char *options)
1343 {
1344 struct uart_port *port = &sci_ports[kgdb_portnum].port;
1345 int baud = 38400;
1346 int bits = 8;
1347 int parity = 'n';
1348 int flow = 'n';
1349
1350 if (co->index != kgdb_portnum)
1351 co->index = kgdb_portnum;
1352
1353 kgdb_sci_port = &sci_ports[co->index];
1354 port = &kgdb_sci_port->port;
1355
1356 /*
1357 * Also need to check port->type, we don't actually have any
1358 * UPIO_PORT ports, but uart_report_port() handily misreports
1359 * it anyways if we don't have a port available by the time this is
1360 * called.
1361 */
1362 if (!port->type)
1363 return -ENODEV;
1364 if (!port->membase || !port->mapbase)
1365 return -ENODEV;
1366
1367 if (options)
1368 uart_parse_options(options, &baud, &parity, &bits, &flow);
1369 else
1370 kgdb_console_get_options(port, &baud, &parity, &bits);
1371
1372 kgdb_getchar = kgdb_sci_getchar;
1373 kgdb_putchar = kgdb_sci_putchar;
1374
1375 return uart_set_options(port, co, baud, parity, bits, flow);
1376 }
1377
1378 static struct console kgdb_console = {
1379 .name = "ttySC",
1380 .device = uart_console_device,
1381 .write = kgdb_console_write,
1382 .setup = kgdb_console_setup,
1383 .flags = CON_PRINTBUFFER,
1384 .index = -1,
1385 .data = &sci_uart_driver,
1386 };
1387
1388 /* Register the KGDB console so we get messages (d'oh!) */
1389 static int __init kgdb_console_init(void)
1390 {
1391 sci_init_ports();
1392 register_console(&kgdb_console);
1393 return 0;
1394 }
1395 console_initcall(kgdb_console_init);
1396 #endif /* CONFIG_SH_KGDB_CONSOLE */
1397
1398 #if defined(CONFIG_SH_KGDB_CONSOLE)
1399 #define SCI_CONSOLE &kgdb_console
1400 #elif defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1401 #define SCI_CONSOLE &serial_console
1402 #else
1403 #define SCI_CONSOLE 0
1404 #endif
1405
1406 static char banner[] __initdata =
1407 KERN_INFO "SuperH SCI(F) driver initialized\n";
1408
1409 static struct uart_driver sci_uart_driver = {
1410 .owner = THIS_MODULE,
1411 .driver_name = "sci",
1412 .dev_name = "ttySC",
1413 .major = SCI_MAJOR,
1414 .minor = SCI_MINOR_START,
1415 .nr = SCI_NPORTS,
1416 .cons = SCI_CONSOLE,
1417 };
1418
1419 /*
1420 * Register a set of serial devices attached to a platform device. The
1421 * list is terminated with a zero flags entry, which means we expect
1422 * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need
1423 * remapping (such as sh64) should also set UPF_IOREMAP.
1424 */
1425 static int __devinit sci_probe(struct platform_device *dev)
1426 {
1427 struct plat_sci_port *p = dev->dev.platform_data;
1428 int i;
1429
1430 for (i = 0; p && p->flags != 0; p++, i++) {
1431 struct sci_port *sciport = &sci_ports[i];
1432
1433 /* Sanity check */
1434 if (unlikely(i == SCI_NPORTS)) {
1435 dev_notice(&dev->dev, "Attempting to register port "
1436 "%d when only %d are available.\n",
1437 i+1, SCI_NPORTS);
1438 dev_notice(&dev->dev, "Consider bumping "
1439 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
1440 break;
1441 }
1442
1443 sciport->port.mapbase = p->mapbase;
1444
1445 /*
1446 * For the simple (and majority of) cases where we don't need
1447 * to do any remapping, just cast the cookie directly.
1448 */
1449 if (p->mapbase && !p->membase && !(p->flags & UPF_IOREMAP))
1450 p->membase = (void __iomem *)p->mapbase;
1451
1452 sciport->port.membase = p->membase;
1453
1454 sciport->port.irq = p->irqs[SCIx_TXI_IRQ];
1455 sciport->port.flags = p->flags;
1456 sciport->port.dev = &dev->dev;
1457
1458 sciport->type = sciport->port.type = p->type;
1459
1460 memcpy(&sciport->irqs, &p->irqs, sizeof(p->irqs));
1461
1462 uart_add_one_port(&sci_uart_driver, &sciport->port);
1463 }
1464
1465 #if defined(CONFIG_SH_KGDB) && !defined(CONFIG_SH_KGDB_CONSOLE)
1466 kgdb_sci_port = &sci_ports[kgdb_portnum];
1467 kgdb_getchar = kgdb_sci_getchar;
1468 kgdb_putchar = kgdb_sci_putchar;
1469 #endif
1470
1471 #ifdef CONFIG_CPU_FREQ
1472 cpufreq_register_notifier(&sci_nb, CPUFREQ_TRANSITION_NOTIFIER);
1473 dev_info(&dev->dev, "CPU frequency notifier registered\n");
1474 #endif
1475
1476 #ifdef CONFIG_SH_STANDARD_BIOS
1477 sh_bios_gdb_detach();
1478 #endif
1479
1480 return 0;
1481 }
1482
1483 static int __devexit sci_remove(struct platform_device *dev)
1484 {
1485 int i;
1486
1487 for (i = 0; i < SCI_NPORTS; i++)
1488 uart_remove_one_port(&sci_uart_driver, &sci_ports[i].port);
1489
1490 return 0;
1491 }
1492
1493 static int sci_suspend(struct platform_device *dev, pm_message_t state)
1494 {
1495 int i;
1496
1497 for (i = 0; i < SCI_NPORTS; i++) {
1498 struct sci_port *p = &sci_ports[i];
1499
1500 if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev)
1501 uart_suspend_port(&sci_uart_driver, &p->port);
1502 }
1503
1504 return 0;
1505 }
1506
1507 static int sci_resume(struct platform_device *dev)
1508 {
1509 int i;
1510
1511 for (i = 0; i < SCI_NPORTS; i++) {
1512 struct sci_port *p = &sci_ports[i];
1513
1514 if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev)
1515 uart_resume_port(&sci_uart_driver, &p->port);
1516 }
1517
1518 return 0;
1519 }
1520
1521 static struct platform_driver sci_driver = {
1522 .probe = sci_probe,
1523 .remove = __devexit_p(sci_remove),
1524 .suspend = sci_suspend,
1525 .resume = sci_resume,
1526 .driver = {
1527 .name = "sh-sci",
1528 .owner = THIS_MODULE,
1529 },
1530 };
1531
1532 static int __init sci_init(void)
1533 {
1534 int ret;
1535
1536 printk(banner);
1537
1538 sci_init_ports();
1539
1540 ret = uart_register_driver(&sci_uart_driver);
1541 if (likely(ret == 0)) {
1542 ret = platform_driver_register(&sci_driver);
1543 if (unlikely(ret))
1544 uart_unregister_driver(&sci_uart_driver);
1545 }
1546
1547 return ret;
1548 }
1549
1550 static void __exit sci_exit(void)
1551 {
1552 platform_driver_unregister(&sci_driver);
1553 uart_unregister_driver(&sci_uart_driver);
1554 }
1555
1556 module_init(sci_init);
1557 module_exit(sci_exit);
1558
1559 MODULE_LICENSE("GPL");
1560 MODULE_ALIAS("platform:sh-sci");
Support for the Chinese Samsung S3C2440 based development boards