2 * adv7842 - Analog Devices ADV7842 video decoder driver
4 * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * References (c = chapter, p = page):
23 * REF_01 - Analog devices, ADV7842,
24 * Register Settings Recommendations, Rev. 1.9, April 2011
25 * REF_02 - Analog devices, Software User Guide, UG-206,
26 * ADV7842 I2C Register Maps, Rev. 0, November 2010
27 * REF_03 - Analog devices, Hardware User Guide, UG-214,
28 * ADV7842 Fast Switching 2:1 HDMI 1.4 Receiver with 3D-Comb
29 * Decoder and Digitizer , Rev. 0, January 2011
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/slab.h>
36 #include <linux/i2c.h>
37 #include <linux/delay.h>
38 #include <linux/videodev2.h>
39 #include <linux/workqueue.h>
40 #include <linux/v4l2-dv-timings.h>
41 #include <media/v4l2-device.h>
42 #include <media/v4l2-ctrls.h>
43 #include <media/v4l2-dv-timings.h>
44 #include <media/adv7842.h>
47 module_param(debug
, int, 0644);
48 MODULE_PARM_DESC(debug
, "debug level (0-2)");
50 MODULE_DESCRIPTION("Analog Devices ADV7842 video decoder driver");
51 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
52 MODULE_AUTHOR("Martin Bugge <marbugge@cisco.com>");
53 MODULE_LICENSE("GPL");
55 /* ADV7842 system clock frequency */
56 #define ADV7842_fsc (28636360)
59 **********************************************************************
61 * Arrays with configuration parameters for the ADV7842
63 **********************************************************************
66 struct adv7842_state
{
67 struct adv7842_platform_data pdata
;
68 struct v4l2_subdev sd
;
70 struct v4l2_ctrl_handler hdl
;
71 enum adv7842_mode mode
;
72 struct v4l2_dv_timings timings
;
73 enum adv7842_vid_std_select vid_std_select
;
83 struct v4l2_fract aspect_ratio
;
84 u32 rgb_quantization_range
;
86 struct workqueue_struct
*work_queues
;
87 struct delayed_work delayed_work_enable_hotplug
;
88 bool restart_stdi_once
;
92 struct i2c_client
*i2c_sdp_io
;
93 struct i2c_client
*i2c_sdp
;
94 struct i2c_client
*i2c_cp
;
95 struct i2c_client
*i2c_vdp
;
96 struct i2c_client
*i2c_afe
;
97 struct i2c_client
*i2c_hdmi
;
98 struct i2c_client
*i2c_repeater
;
99 struct i2c_client
*i2c_edid
;
100 struct i2c_client
*i2c_infoframe
;
101 struct i2c_client
*i2c_cec
;
102 struct i2c_client
*i2c_avlink
;
105 struct v4l2_ctrl
*detect_tx_5v_ctrl
;
106 struct v4l2_ctrl
*analog_sampling_phase_ctrl
;
107 struct v4l2_ctrl
*free_run_color_ctrl_manual
;
108 struct v4l2_ctrl
*free_run_color_ctrl
;
109 struct v4l2_ctrl
*rgb_quantization_range_ctrl
;
112 /* Unsupported timings. This device cannot support 720p30. */
113 static const struct v4l2_dv_timings adv7842_timings_exceptions
[] = {
114 V4L2_DV_BT_CEA_1280X720P30
,
118 static bool adv7842_check_dv_timings(const struct v4l2_dv_timings
*t
, void *hdl
)
122 for (i
= 0; adv7842_timings_exceptions
[i
].bt
.width
; i
++)
123 if (v4l2_match_dv_timings(t
, adv7842_timings_exceptions
+ i
, 0))
128 struct adv7842_video_standards
{
129 struct v4l2_dv_timings timings
;
134 /* sorted by number of lines */
135 static const struct adv7842_video_standards adv7842_prim_mode_comp
[] = {
136 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
137 { V4L2_DV_BT_CEA_720X576P50
, 0x0b, 0x00 },
138 { V4L2_DV_BT_CEA_1280X720P50
, 0x19, 0x01 },
139 { V4L2_DV_BT_CEA_1280X720P60
, 0x19, 0x00 },
140 { V4L2_DV_BT_CEA_1920X1080P24
, 0x1e, 0x04 },
141 { V4L2_DV_BT_CEA_1920X1080P25
, 0x1e, 0x03 },
142 { V4L2_DV_BT_CEA_1920X1080P30
, 0x1e, 0x02 },
143 { V4L2_DV_BT_CEA_1920X1080P50
, 0x1e, 0x01 },
144 { V4L2_DV_BT_CEA_1920X1080P60
, 0x1e, 0x00 },
145 /* TODO add 1920x1080P60_RB (CVT timing) */
149 /* sorted by number of lines */
150 static const struct adv7842_video_standards adv7842_prim_mode_gr
[] = {
151 { V4L2_DV_BT_DMT_640X480P60
, 0x08, 0x00 },
152 { V4L2_DV_BT_DMT_640X480P72
, 0x09, 0x00 },
153 { V4L2_DV_BT_DMT_640X480P75
, 0x0a, 0x00 },
154 { V4L2_DV_BT_DMT_640X480P85
, 0x0b, 0x00 },
155 { V4L2_DV_BT_DMT_800X600P56
, 0x00, 0x00 },
156 { V4L2_DV_BT_DMT_800X600P60
, 0x01, 0x00 },
157 { V4L2_DV_BT_DMT_800X600P72
, 0x02, 0x00 },
158 { V4L2_DV_BT_DMT_800X600P75
, 0x03, 0x00 },
159 { V4L2_DV_BT_DMT_800X600P85
, 0x04, 0x00 },
160 { V4L2_DV_BT_DMT_1024X768P60
, 0x0c, 0x00 },
161 { V4L2_DV_BT_DMT_1024X768P70
, 0x0d, 0x00 },
162 { V4L2_DV_BT_DMT_1024X768P75
, 0x0e, 0x00 },
163 { V4L2_DV_BT_DMT_1024X768P85
, 0x0f, 0x00 },
164 { V4L2_DV_BT_DMT_1280X1024P60
, 0x05, 0x00 },
165 { V4L2_DV_BT_DMT_1280X1024P75
, 0x06, 0x00 },
166 { V4L2_DV_BT_DMT_1360X768P60
, 0x12, 0x00 },
167 { V4L2_DV_BT_DMT_1366X768P60
, 0x13, 0x00 },
168 { V4L2_DV_BT_DMT_1400X1050P60
, 0x14, 0x00 },
169 { V4L2_DV_BT_DMT_1400X1050P75
, 0x15, 0x00 },
170 { V4L2_DV_BT_DMT_1600X1200P60
, 0x16, 0x00 }, /* TODO not tested */
171 /* TODO add 1600X1200P60_RB (not a DMT timing) */
172 { V4L2_DV_BT_DMT_1680X1050P60
, 0x18, 0x00 },
173 { V4L2_DV_BT_DMT_1920X1200P60_RB
, 0x19, 0x00 }, /* TODO not tested */
177 /* sorted by number of lines */
178 static const struct adv7842_video_standards adv7842_prim_mode_hdmi_comp
[] = {
179 { V4L2_DV_BT_CEA_720X480P59_94
, 0x0a, 0x00 },
180 { V4L2_DV_BT_CEA_720X576P50
, 0x0b, 0x00 },
181 { V4L2_DV_BT_CEA_1280X720P50
, 0x13, 0x01 },
182 { V4L2_DV_BT_CEA_1280X720P60
, 0x13, 0x00 },
183 { V4L2_DV_BT_CEA_1920X1080P24
, 0x1e, 0x04 },
184 { V4L2_DV_BT_CEA_1920X1080P25
, 0x1e, 0x03 },
185 { V4L2_DV_BT_CEA_1920X1080P30
, 0x1e, 0x02 },
186 { V4L2_DV_BT_CEA_1920X1080P50
, 0x1e, 0x01 },
187 { V4L2_DV_BT_CEA_1920X1080P60
, 0x1e, 0x00 },
191 /* sorted by number of lines */
192 static const struct adv7842_video_standards adv7842_prim_mode_hdmi_gr
[] = {
193 { V4L2_DV_BT_DMT_640X480P60
, 0x08, 0x00 },
194 { V4L2_DV_BT_DMT_640X480P72
, 0x09, 0x00 },
195 { V4L2_DV_BT_DMT_640X480P75
, 0x0a, 0x00 },
196 { V4L2_DV_BT_DMT_640X480P85
, 0x0b, 0x00 },
197 { V4L2_DV_BT_DMT_800X600P56
, 0x00, 0x00 },
198 { V4L2_DV_BT_DMT_800X600P60
, 0x01, 0x00 },
199 { V4L2_DV_BT_DMT_800X600P72
, 0x02, 0x00 },
200 { V4L2_DV_BT_DMT_800X600P75
, 0x03, 0x00 },
201 { V4L2_DV_BT_DMT_800X600P85
, 0x04, 0x00 },
202 { V4L2_DV_BT_DMT_1024X768P60
, 0x0c, 0x00 },
203 { V4L2_DV_BT_DMT_1024X768P70
, 0x0d, 0x00 },
204 { V4L2_DV_BT_DMT_1024X768P75
, 0x0e, 0x00 },
205 { V4L2_DV_BT_DMT_1024X768P85
, 0x0f, 0x00 },
206 { V4L2_DV_BT_DMT_1280X1024P60
, 0x05, 0x00 },
207 { V4L2_DV_BT_DMT_1280X1024P75
, 0x06, 0x00 },
211 /* ----------------------------------------------------------------------- */
213 static inline struct adv7842_state
*to_state(struct v4l2_subdev
*sd
)
215 return container_of(sd
, struct adv7842_state
, sd
);
218 static inline struct v4l2_subdev
*to_sd(struct v4l2_ctrl
*ctrl
)
220 return &container_of(ctrl
->handler
, struct adv7842_state
, hdl
)->sd
;
223 static inline unsigned hblanking(const struct v4l2_bt_timings
*t
)
225 return V4L2_DV_BT_BLANKING_WIDTH(t
);
228 static inline unsigned htotal(const struct v4l2_bt_timings
*t
)
230 return V4L2_DV_BT_FRAME_WIDTH(t
);
233 static inline unsigned vblanking(const struct v4l2_bt_timings
*t
)
235 return V4L2_DV_BT_BLANKING_HEIGHT(t
);
238 static inline unsigned vtotal(const struct v4l2_bt_timings
*t
)
240 return V4L2_DV_BT_FRAME_HEIGHT(t
);
244 /* ----------------------------------------------------------------------- */
246 static s32
adv_smbus_read_byte_data_check(struct i2c_client
*client
,
247 u8 command
, bool check
)
249 union i2c_smbus_data data
;
251 if (!i2c_smbus_xfer(client
->adapter
, client
->addr
, client
->flags
,
252 I2C_SMBUS_READ
, command
,
253 I2C_SMBUS_BYTE_DATA
, &data
))
256 v4l_err(client
, "error reading %02x, %02x\n",
257 client
->addr
, command
);
261 static s32
adv_smbus_read_byte_data(struct i2c_client
*client
, u8 command
)
265 for (i
= 0; i
< 3; i
++) {
266 int ret
= adv_smbus_read_byte_data_check(client
, command
, true);
270 v4l_err(client
, "read ok after %d retries\n", i
);
274 v4l_err(client
, "read failed\n");
278 static s32
adv_smbus_write_byte_data(struct i2c_client
*client
,
279 u8 command
, u8 value
)
281 union i2c_smbus_data data
;
286 for (i
= 0; i
< 3; i
++) {
287 err
= i2c_smbus_xfer(client
->adapter
, client
->addr
,
289 I2C_SMBUS_WRITE
, command
,
290 I2C_SMBUS_BYTE_DATA
, &data
);
295 v4l_err(client
, "error writing %02x, %02x, %02x\n",
296 client
->addr
, command
, value
);
300 static void adv_smbus_write_byte_no_check(struct i2c_client
*client
,
301 u8 command
, u8 value
)
303 union i2c_smbus_data data
;
306 i2c_smbus_xfer(client
->adapter
, client
->addr
,
308 I2C_SMBUS_WRITE
, command
,
309 I2C_SMBUS_BYTE_DATA
, &data
);
312 static s32
adv_smbus_write_i2c_block_data(struct i2c_client
*client
,
313 u8 command
, unsigned length
, const u8
*values
)
315 union i2c_smbus_data data
;
317 if (length
> I2C_SMBUS_BLOCK_MAX
)
318 length
= I2C_SMBUS_BLOCK_MAX
;
319 data
.block
[0] = length
;
320 memcpy(data
.block
+ 1, values
, length
);
321 return i2c_smbus_xfer(client
->adapter
, client
->addr
, client
->flags
,
322 I2C_SMBUS_WRITE
, command
,
323 I2C_SMBUS_I2C_BLOCK_DATA
, &data
);
326 /* ----------------------------------------------------------------------- */
328 static inline int io_read(struct v4l2_subdev
*sd
, u8 reg
)
330 struct i2c_client
*client
= v4l2_get_subdevdata(sd
);
332 return adv_smbus_read_byte_data(client
, reg
);
335 static inline int io_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
337 struct i2c_client
*client
= v4l2_get_subdevdata(sd
);
339 return adv_smbus_write_byte_data(client
, reg
, val
);
342 static inline int io_write_and_or(struct v4l2_subdev
*sd
, u8 reg
, u8 mask
, u8 val
)
344 return io_write(sd
, reg
, (io_read(sd
, reg
) & mask
) | val
);
347 static inline int avlink_read(struct v4l2_subdev
*sd
, u8 reg
)
349 struct adv7842_state
*state
= to_state(sd
);
351 return adv_smbus_read_byte_data(state
->i2c_avlink
, reg
);
354 static inline int avlink_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
356 struct adv7842_state
*state
= to_state(sd
);
358 return adv_smbus_write_byte_data(state
->i2c_avlink
, reg
, val
);
361 static inline int cec_read(struct v4l2_subdev
*sd
, u8 reg
)
363 struct adv7842_state
*state
= to_state(sd
);
365 return adv_smbus_read_byte_data(state
->i2c_cec
, reg
);
368 static inline int cec_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
370 struct adv7842_state
*state
= to_state(sd
);
372 return adv_smbus_write_byte_data(state
->i2c_cec
, reg
, val
);
375 static inline int cec_write_and_or(struct v4l2_subdev
*sd
, u8 reg
, u8 mask
, u8 val
)
377 return cec_write(sd
, reg
, (cec_read(sd
, reg
) & mask
) | val
);
380 static inline int infoframe_read(struct v4l2_subdev
*sd
, u8 reg
)
382 struct adv7842_state
*state
= to_state(sd
);
384 return adv_smbus_read_byte_data(state
->i2c_infoframe
, reg
);
387 static inline int infoframe_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
389 struct adv7842_state
*state
= to_state(sd
);
391 return adv_smbus_write_byte_data(state
->i2c_infoframe
, reg
, val
);
394 static inline int sdp_io_read(struct v4l2_subdev
*sd
, u8 reg
)
396 struct adv7842_state
*state
= to_state(sd
);
398 return adv_smbus_read_byte_data(state
->i2c_sdp_io
, reg
);
401 static inline int sdp_io_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
403 struct adv7842_state
*state
= to_state(sd
);
405 return adv_smbus_write_byte_data(state
->i2c_sdp_io
, reg
, val
);
408 static inline int sdp_io_write_and_or(struct v4l2_subdev
*sd
, u8 reg
, u8 mask
, u8 val
)
410 return sdp_io_write(sd
, reg
, (sdp_io_read(sd
, reg
) & mask
) | val
);
413 static inline int sdp_read(struct v4l2_subdev
*sd
, u8 reg
)
415 struct adv7842_state
*state
= to_state(sd
);
417 return adv_smbus_read_byte_data(state
->i2c_sdp
, reg
);
420 static inline int sdp_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
422 struct adv7842_state
*state
= to_state(sd
);
424 return adv_smbus_write_byte_data(state
->i2c_sdp
, reg
, val
);
427 static inline int sdp_write_and_or(struct v4l2_subdev
*sd
, u8 reg
, u8 mask
, u8 val
)
429 return sdp_write(sd
, reg
, (sdp_read(sd
, reg
) & mask
) | val
);
432 static inline int afe_read(struct v4l2_subdev
*sd
, u8 reg
)
434 struct adv7842_state
*state
= to_state(sd
);
436 return adv_smbus_read_byte_data(state
->i2c_afe
, reg
);
439 static inline int afe_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
441 struct adv7842_state
*state
= to_state(sd
);
443 return adv_smbus_write_byte_data(state
->i2c_afe
, reg
, val
);
446 static inline int afe_write_and_or(struct v4l2_subdev
*sd
, u8 reg
, u8 mask
, u8 val
)
448 return afe_write(sd
, reg
, (afe_read(sd
, reg
) & mask
) | val
);
451 static inline int rep_read(struct v4l2_subdev
*sd
, u8 reg
)
453 struct adv7842_state
*state
= to_state(sd
);
455 return adv_smbus_read_byte_data(state
->i2c_repeater
, reg
);
458 static inline int rep_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
460 struct adv7842_state
*state
= to_state(sd
);
462 return adv_smbus_write_byte_data(state
->i2c_repeater
, reg
, val
);
465 static inline int rep_write_and_or(struct v4l2_subdev
*sd
, u8 reg
, u8 mask
, u8 val
)
467 return rep_write(sd
, reg
, (rep_read(sd
, reg
) & mask
) | val
);
470 static inline int edid_read(struct v4l2_subdev
*sd
, u8 reg
)
472 struct adv7842_state
*state
= to_state(sd
);
474 return adv_smbus_read_byte_data(state
->i2c_edid
, reg
);
477 static inline int edid_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
479 struct adv7842_state
*state
= to_state(sd
);
481 return adv_smbus_write_byte_data(state
->i2c_edid
, reg
, val
);
484 static inline int hdmi_read(struct v4l2_subdev
*sd
, u8 reg
)
486 struct adv7842_state
*state
= to_state(sd
);
488 return adv_smbus_read_byte_data(state
->i2c_hdmi
, reg
);
491 static inline int hdmi_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
493 struct adv7842_state
*state
= to_state(sd
);
495 return adv_smbus_write_byte_data(state
->i2c_hdmi
, reg
, val
);
498 static inline int hdmi_write_and_or(struct v4l2_subdev
*sd
, u8 reg
, u8 mask
, u8 val
)
500 return hdmi_write(sd
, reg
, (hdmi_read(sd
, reg
) & mask
) | val
);
503 static inline int cp_read(struct v4l2_subdev
*sd
, u8 reg
)
505 struct adv7842_state
*state
= to_state(sd
);
507 return adv_smbus_read_byte_data(state
->i2c_cp
, reg
);
510 static inline int cp_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
512 struct adv7842_state
*state
= to_state(sd
);
514 return adv_smbus_write_byte_data(state
->i2c_cp
, reg
, val
);
517 static inline int cp_write_and_or(struct v4l2_subdev
*sd
, u8 reg
, u8 mask
, u8 val
)
519 return cp_write(sd
, reg
, (cp_read(sd
, reg
) & mask
) | val
);
522 static inline int vdp_read(struct v4l2_subdev
*sd
, u8 reg
)
524 struct adv7842_state
*state
= to_state(sd
);
526 return adv_smbus_read_byte_data(state
->i2c_vdp
, reg
);
529 static inline int vdp_write(struct v4l2_subdev
*sd
, u8 reg
, u8 val
)
531 struct adv7842_state
*state
= to_state(sd
);
533 return adv_smbus_write_byte_data(state
->i2c_vdp
, reg
, val
);
536 static void main_reset(struct v4l2_subdev
*sd
)
538 struct i2c_client
*client
= v4l2_get_subdevdata(sd
);
540 v4l2_dbg(1, debug
, sd
, "%s:\n", __func__
);
542 adv_smbus_write_byte_no_check(client
, 0xff, 0x80);
547 /* ----------------------------------------------------------------------- */
549 static inline bool is_analog_input(struct v4l2_subdev
*sd
)
551 struct adv7842_state
*state
= to_state(sd
);
553 return ((state
->mode
== ADV7842_MODE_RGB
) ||
554 (state
->mode
== ADV7842_MODE_COMP
));
557 static inline bool is_digital_input(struct v4l2_subdev
*sd
)
559 struct adv7842_state
*state
= to_state(sd
);
561 return state
->mode
== ADV7842_MODE_HDMI
;
564 static const struct v4l2_dv_timings_cap adv7842_timings_cap_analog
= {
565 .type
= V4L2_DV_BT_656_1120
,
566 /* keep this initialization for compatibility with GCC < 4.4.6 */
568 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 170000000,
569 V4L2_DV_BT_STD_CEA861
| V4L2_DV_BT_STD_DMT
|
570 V4L2_DV_BT_STD_GTF
| V4L2_DV_BT_STD_CVT
,
571 V4L2_DV_BT_CAP_PROGRESSIVE
| V4L2_DV_BT_CAP_REDUCED_BLANKING
|
572 V4L2_DV_BT_CAP_CUSTOM
)
575 static const struct v4l2_dv_timings_cap adv7842_timings_cap_digital
= {
576 .type
= V4L2_DV_BT_656_1120
,
577 /* keep this initialization for compatibility with GCC < 4.4.6 */
579 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 225000000,
580 V4L2_DV_BT_STD_CEA861
| V4L2_DV_BT_STD_DMT
|
581 V4L2_DV_BT_STD_GTF
| V4L2_DV_BT_STD_CVT
,
582 V4L2_DV_BT_CAP_PROGRESSIVE
| V4L2_DV_BT_CAP_REDUCED_BLANKING
|
583 V4L2_DV_BT_CAP_CUSTOM
)
586 static inline const struct v4l2_dv_timings_cap
*
587 adv7842_get_dv_timings_cap(struct v4l2_subdev
*sd
)
589 return is_digital_input(sd
) ? &adv7842_timings_cap_digital
:
590 &adv7842_timings_cap_analog
;
593 /* ----------------------------------------------------------------------- */
595 static void adv7842_delayed_work_enable_hotplug(struct work_struct
*work
)
597 struct delayed_work
*dwork
= to_delayed_work(work
);
598 struct adv7842_state
*state
= container_of(dwork
,
599 struct adv7842_state
, delayed_work_enable_hotplug
);
600 struct v4l2_subdev
*sd
= &state
->sd
;
601 int present
= state
->hdmi_edid
.present
;
604 v4l2_dbg(2, debug
, sd
, "%s: enable hotplug on ports: 0x%x\n",
607 if (present
& (0x04 << ADV7842_EDID_PORT_A
))
609 if (present
& (0x04 << ADV7842_EDID_PORT_B
))
611 io_write_and_or(sd
, 0x20, 0xcf, mask
);
614 static int edid_write_vga_segment(struct v4l2_subdev
*sd
)
616 struct i2c_client
*client
= v4l2_get_subdevdata(sd
);
617 struct adv7842_state
*state
= to_state(sd
);
618 const u8
*val
= state
->vga_edid
.edid
;
622 v4l2_dbg(2, debug
, sd
, "%s: write EDID on VGA port\n", __func__
);
624 /* HPA disable on port A and B */
625 io_write_and_or(sd
, 0x20, 0xcf, 0x00);
627 /* Disable I2C access to internal EDID ram from VGA DDC port */
628 rep_write_and_or(sd
, 0x7f, 0x7f, 0x00);
630 /* edid segment pointer '1' for VGA port */
631 rep_write_and_or(sd
, 0x77, 0xef, 0x10);
633 for (i
= 0; !err
&& i
< 256; i
+= I2C_SMBUS_BLOCK_MAX
)
634 err
= adv_smbus_write_i2c_block_data(state
->i2c_edid
, i
,
635 I2C_SMBUS_BLOCK_MAX
, val
+ i
);
639 /* Calculates the checksums and enables I2C access
640 * to internal EDID ram from VGA DDC port.
642 rep_write_and_or(sd
, 0x7f, 0x7f, 0x80);
644 for (i
= 0; i
< 1000; i
++) {
645 if (rep_read(sd
, 0x79) & 0x20)
650 v4l_err(client
, "error enabling edid on VGA port\n");
654 /* enable hotplug after 200 ms */
655 queue_delayed_work(state
->work_queues
,
656 &state
->delayed_work_enable_hotplug
, HZ
/ 5);
661 static int edid_spa_location(const u8
*edid
)
666 * TODO, improve and update for other CEA extensions
667 * currently only for 1 segment (256 bytes),
668 * i.e. 1 extension block and CEA revision 3.
670 if ((edid
[0x7e] != 1) ||
671 (edid
[0x80] != 0x02) ||
672 (edid
[0x81] != 0x03)) {
676 * search Vendor Specific Data Block (tag 3)
678 d
= edid
[0x82] & 0x7f;
684 u8 len
= edid
[i
] & 0x1f;
686 if ((tag
== 3) && (len
>= 5))
694 static int edid_write_hdmi_segment(struct v4l2_subdev
*sd
, u8 port
)
696 struct i2c_client
*client
= v4l2_get_subdevdata(sd
);
697 struct adv7842_state
*state
= to_state(sd
);
698 const u8
*val
= state
->hdmi_edid
.edid
;
699 int spa_loc
= edid_spa_location(val
);
703 v4l2_dbg(2, debug
, sd
, "%s: write EDID on port %c (spa at 0x%x)\n",
704 __func__
, (port
== ADV7842_EDID_PORT_A
) ? 'A' : 'B', spa_loc
);
706 /* HPA disable on port A and B */
707 io_write_and_or(sd
, 0x20, 0xcf, 0x00);
709 /* Disable I2C access to internal EDID ram from HDMI DDC ports */
710 rep_write_and_or(sd
, 0x77, 0xf3, 0x00);
712 if (!state
->hdmi_edid
.present
)
715 /* edid segment pointer '0' for HDMI ports */
716 rep_write_and_or(sd
, 0x77, 0xef, 0x00);
718 for (i
= 0; !err
&& i
< 256; i
+= I2C_SMBUS_BLOCK_MAX
)
719 err
= adv_smbus_write_i2c_block_data(state
->i2c_edid
, i
,
720 I2C_SMBUS_BLOCK_MAX
, val
+ i
);
725 spa_loc
= 0xc0; /* Default value [REF_02, p. 199] */
727 if (port
== ADV7842_EDID_PORT_A
) {
728 rep_write(sd
, 0x72, val
[spa_loc
]);
729 rep_write(sd
, 0x73, val
[spa_loc
+ 1]);
731 rep_write(sd
, 0x74, val
[spa_loc
]);
732 rep_write(sd
, 0x75, val
[spa_loc
+ 1]);
734 rep_write(sd
, 0x76, spa_loc
& 0xff);
735 rep_write_and_or(sd
, 0x77, 0xbf, (spa_loc
>> 2) & 0x40);
737 /* Calculates the checksums and enables I2C access to internal
738 * EDID ram from HDMI DDC ports
740 rep_write_and_or(sd
, 0x77, 0xf3, state
->hdmi_edid
.present
);
742 for (i
= 0; i
< 1000; i
++) {
743 if (rep_read(sd
, 0x7d) & state
->hdmi_edid
.present
)
748 v4l_err(client
, "error enabling edid on port %c\n",
749 (port
== ADV7842_EDID_PORT_A
) ? 'A' : 'B');
753 /* enable hotplug after 200 ms */
754 queue_delayed_work(state
->work_queues
,
755 &state
->delayed_work_enable_hotplug
, HZ
/ 5);
760 /* ----------------------------------------------------------------------- */
762 #ifdef CONFIG_VIDEO_ADV_DEBUG
763 static void adv7842_inv_register(struct v4l2_subdev
*sd
)
765 v4l2_info(sd
, "0x000-0x0ff: IO Map\n");
766 v4l2_info(sd
, "0x100-0x1ff: AVLink Map\n");
767 v4l2_info(sd
, "0x200-0x2ff: CEC Map\n");
768 v4l2_info(sd
, "0x300-0x3ff: InfoFrame Map\n");
769 v4l2_info(sd
, "0x400-0x4ff: SDP_IO Map\n");
770 v4l2_info(sd
, "0x500-0x5ff: SDP Map\n");
771 v4l2_info(sd
, "0x600-0x6ff: AFE Map\n");
772 v4l2_info(sd
, "0x700-0x7ff: Repeater Map\n");
773 v4l2_info(sd
, "0x800-0x8ff: EDID Map\n");
774 v4l2_info(sd
, "0x900-0x9ff: HDMI Map\n");
775 v4l2_info(sd
, "0xa00-0xaff: CP Map\n");
776 v4l2_info(sd
, "0xb00-0xbff: VDP Map\n");
779 static int adv7842_g_register(struct v4l2_subdev
*sd
,
780 struct v4l2_dbg_register
*reg
)
783 switch (reg
->reg
>> 8) {
785 reg
->val
= io_read(sd
, reg
->reg
& 0xff);
788 reg
->val
= avlink_read(sd
, reg
->reg
& 0xff);
791 reg
->val
= cec_read(sd
, reg
->reg
& 0xff);
794 reg
->val
= infoframe_read(sd
, reg
->reg
& 0xff);
797 reg
->val
= sdp_io_read(sd
, reg
->reg
& 0xff);
800 reg
->val
= sdp_read(sd
, reg
->reg
& 0xff);
803 reg
->val
= afe_read(sd
, reg
->reg
& 0xff);
806 reg
->val
= rep_read(sd
, reg
->reg
& 0xff);
809 reg
->val
= edid_read(sd
, reg
->reg
& 0xff);
812 reg
->val
= hdmi_read(sd
, reg
->reg
& 0xff);
815 reg
->val
= cp_read(sd
, reg
->reg
& 0xff);
818 reg
->val
= vdp_read(sd
, reg
->reg
& 0xff);
821 v4l2_info(sd
, "Register %03llx not supported\n", reg
->reg
);
822 adv7842_inv_register(sd
);
828 static int adv7842_s_register(struct v4l2_subdev
*sd
,
829 const struct v4l2_dbg_register
*reg
)
831 u8 val
= reg
->val
& 0xff;
833 switch (reg
->reg
>> 8) {
835 io_write(sd
, reg
->reg
& 0xff, val
);
838 avlink_write(sd
, reg
->reg
& 0xff, val
);
841 cec_write(sd
, reg
->reg
& 0xff, val
);
844 infoframe_write(sd
, reg
->reg
& 0xff, val
);
847 sdp_io_write(sd
, reg
->reg
& 0xff, val
);
850 sdp_write(sd
, reg
->reg
& 0xff, val
);
853 afe_write(sd
, reg
->reg
& 0xff, val
);
856 rep_write(sd
, reg
->reg
& 0xff, val
);
859 edid_write(sd
, reg
->reg
& 0xff, val
);
862 hdmi_write(sd
, reg
->reg
& 0xff, val
);
865 cp_write(sd
, reg
->reg
& 0xff, val
);
868 vdp_write(sd
, reg
->reg
& 0xff, val
);
871 v4l2_info(sd
, "Register %03llx not supported\n", reg
->reg
);
872 adv7842_inv_register(sd
);
879 static int adv7842_s_detect_tx_5v_ctrl(struct v4l2_subdev
*sd
)
881 struct adv7842_state
*state
= to_state(sd
);
882 int prev
= v4l2_ctrl_g_ctrl(state
->detect_tx_5v_ctrl
);
883 u8 reg_io_6f
= io_read(sd
, 0x6f);
886 if (reg_io_6f
& 0x02)
887 val
|= 1; /* port A */
888 if (reg_io_6f
& 0x01)
889 val
|= 2; /* port B */
891 v4l2_dbg(1, debug
, sd
, "%s: 0x%x -> 0x%x\n", __func__
, prev
, val
);
894 return v4l2_ctrl_s_ctrl(state
->detect_tx_5v_ctrl
, val
);
898 static int find_and_set_predefined_video_timings(struct v4l2_subdev
*sd
,
900 const struct adv7842_video_standards
*predef_vid_timings
,
901 const struct v4l2_dv_timings
*timings
)
905 for (i
= 0; predef_vid_timings
[i
].timings
.bt
.width
; i
++) {
906 if (!v4l2_match_dv_timings(timings
, &predef_vid_timings
[i
].timings
,
907 is_digital_input(sd
) ? 250000 : 1000000))
910 io_write(sd
, 0x00, predef_vid_timings
[i
].vid_std
);
911 /* v_freq and prim mode */
912 io_write(sd
, 0x01, (predef_vid_timings
[i
].v_freq
<< 4) + prim_mode
);
919 static int configure_predefined_video_timings(struct v4l2_subdev
*sd
,
920 struct v4l2_dv_timings
*timings
)
922 struct adv7842_state
*state
= to_state(sd
);
925 v4l2_dbg(1, debug
, sd
, "%s\n", __func__
);
927 /* reset to default values */
928 io_write(sd
, 0x16, 0x43);
929 io_write(sd
, 0x17, 0x5a);
930 /* disable embedded syncs for auto graphics mode */
931 cp_write_and_or(sd
, 0x81, 0xef, 0x00);
932 cp_write(sd
, 0x26, 0x00);
933 cp_write(sd
, 0x27, 0x00);
934 cp_write(sd
, 0x28, 0x00);
935 cp_write(sd
, 0x29, 0x00);
936 cp_write(sd
, 0x8f, 0x40);
937 cp_write(sd
, 0x90, 0x00);
938 cp_write(sd
, 0xa5, 0x00);
939 cp_write(sd
, 0xa6, 0x00);
940 cp_write(sd
, 0xa7, 0x00);
941 cp_write(sd
, 0xab, 0x00);
942 cp_write(sd
, 0xac, 0x00);
944 switch (state
->mode
) {
945 case ADV7842_MODE_COMP
:
946 case ADV7842_MODE_RGB
:
947 err
= find_and_set_predefined_video_timings(sd
,
948 0x01, adv7842_prim_mode_comp
, timings
);
950 err
= find_and_set_predefined_video_timings(sd
,
951 0x02, adv7842_prim_mode_gr
, timings
);
953 case ADV7842_MODE_HDMI
:
954 err
= find_and_set_predefined_video_timings(sd
,
955 0x05, adv7842_prim_mode_hdmi_comp
, timings
);
957 err
= find_and_set_predefined_video_timings(sd
,
958 0x06, adv7842_prim_mode_hdmi_gr
, timings
);
961 v4l2_dbg(2, debug
, sd
, "%s: Unknown mode %d\n",
962 __func__
, state
->mode
);
971 static void configure_custom_video_timings(struct v4l2_subdev
*sd
,
972 const struct v4l2_bt_timings
*bt
)
974 struct adv7842_state
*state
= to_state(sd
);
975 struct i2c_client
*client
= v4l2_get_subdevdata(sd
);
976 u32 width
= htotal(bt
);
977 u32 height
= vtotal(bt
);
978 u16 cp_start_sav
= bt
->hsync
+ bt
->hbackporch
- 4;
979 u16 cp_start_eav
= width
- bt
->hfrontporch
;
980 u16 cp_start_vbi
= height
- bt
->vfrontporch
+ 1;
981 u16 cp_end_vbi
= bt
->vsync
+ bt
->vbackporch
+ 1;
982 u16 ch1_fr_ll
= (((u32
)bt
->pixelclock
/ 100) > 0) ?
983 ((width
* (ADV7842_fsc
/ 100)) / ((u32
)bt
->pixelclock
/ 100)) : 0;
985 0xc0 | ((width
>> 8) & 0x1f),
989 v4l2_dbg(2, debug
, sd
, "%s\n", __func__
);
991 switch (state
->mode
) {
992 case ADV7842_MODE_COMP
:
993 case ADV7842_MODE_RGB
:
995 io_write(sd
, 0x00, 0x07); /* video std */
996 io_write(sd
, 0x01, 0x02); /* prim mode */
997 /* enable embedded syncs for auto graphics mode */
998 cp_write_and_or(sd
, 0x81, 0xef, 0x10);
1000 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
1001 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
1002 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
1003 if (adv_smbus_write_i2c_block_data(client
, 0x16, 2, pll
)) {
1004 v4l2_err(sd
, "writing to reg 0x16 and 0x17 failed\n");
1008 /* active video - horizontal timing */
1009 cp_write(sd
, 0x26, (cp_start_sav
>> 8) & 0xf);
1010 cp_write(sd
, 0x27, (cp_start_sav
& 0xff));
1011 cp_write(sd
, 0x28, (cp_start_eav
>> 8) & 0xf);
1012 cp_write(sd
, 0x29, (cp_start_eav
& 0xff));
1014 /* active video - vertical timing */
1015 cp_write(sd
, 0xa5, (cp_start_vbi
>> 4) & 0xff);
1016 cp_write(sd
, 0xa6, ((cp_start_vbi
& 0xf) << 4) |
1017 ((cp_end_vbi
>> 8) & 0xf));
1018 cp_write(sd
, 0xa7, cp_end_vbi
& 0xff);
1020 case ADV7842_MODE_HDMI
:
1021 /* set default prim_mode/vid_std for HDMI
1022 according to [REF_03, c. 4.2] */
1023 io_write(sd
, 0x00, 0x02); /* video std */
1024 io_write(sd
, 0x01, 0x06); /* prim mode */
1027 v4l2_dbg(2, debug
, sd
, "%s: Unknown mode %d\n",
1028 __func__
, state
->mode
);
1032 cp_write(sd
, 0x8f, (ch1_fr_ll
>> 8) & 0x7);
1033 cp_write(sd
, 0x90, ch1_fr_ll
& 0xff);
1034 cp_write(sd
, 0xab, (height
>> 4) & 0xff);
1035 cp_write(sd
, 0xac, (height
& 0x0f) << 4);
1038 static void adv7842_set_offset(struct v4l2_subdev
*sd
, bool auto_offset
, u16 offset_a
, u16 offset_b
, u16 offset_c
)
1040 struct adv7842_state
*state
= to_state(sd
);
1049 v4l2_dbg(2, debug
, sd
, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
1050 __func__
, auto_offset
? "Auto" : "Manual",
1051 offset_a
, offset_b
, offset_c
);
1053 offset_buf
[0]= (cp_read(sd
, 0x77) & 0xc0) | ((offset_a
& 0x3f0) >> 4);
1054 offset_buf
[1] = ((offset_a
& 0x00f) << 4) | ((offset_b
& 0x3c0) >> 6);
1055 offset_buf
[2] = ((offset_b
& 0x03f) << 2) | ((offset_c
& 0x300) >> 8);
1056 offset_buf
[3] = offset_c
& 0x0ff;
1058 /* Registers must be written in this order with no i2c access in between */
1059 if (adv_smbus_write_i2c_block_data(state
->i2c_cp
, 0x77, 4, offset_buf
))
1060 v4l2_err(sd
, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__
);
1063 static void adv7842_set_gain(struct v4l2_subdev
*sd
, bool auto_gain
, u16 gain_a
, u16 gain_b
, u16 gain_c
)
1065 struct adv7842_state
*state
= to_state(sd
);
1068 u8 agc_mode_man
= 1;
1078 v4l2_dbg(2, debug
, sd
, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
1079 __func__
, auto_gain
? "Auto" : "Manual",
1080 gain_a
, gain_b
, gain_c
);
1082 gain_buf
[0] = ((gain_man
<< 7) | (agc_mode_man
<< 6) | ((gain_a
& 0x3f0) >> 4));
1083 gain_buf
[1] = (((gain_a
& 0x00f) << 4) | ((gain_b
& 0x3c0) >> 6));
1084 gain_buf
[2] = (((gain_b
& 0x03f) << 2) | ((gain_c
& 0x300) >> 8));
1085 gain_buf
[3] = ((gain_c
& 0x0ff));
1087 /* Registers must be written in this order with no i2c access in between */
1088 if (adv_smbus_write_i2c_block_data(state
->i2c_cp
, 0x73, 4, gain_buf
))
1089 v4l2_err(sd
, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__
);
1092 static void set_rgb_quantization_range(struct v4l2_subdev
*sd
)
1094 struct adv7842_state
*state
= to_state(sd
);
1095 bool rgb_output
= io_read(sd
, 0x02) & 0x02;
1096 bool hdmi_signal
= hdmi_read(sd
, 0x05) & 0x80;
1098 v4l2_dbg(2, debug
, sd
, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
1099 __func__
, state
->rgb_quantization_range
,
1100 rgb_output
, hdmi_signal
);
1102 adv7842_set_gain(sd
, true, 0x0, 0x0, 0x0);
1103 adv7842_set_offset(sd
, true, 0x0, 0x0, 0x0);
1105 switch (state
->rgb_quantization_range
) {
1106 case V4L2_DV_RGB_RANGE_AUTO
:
1107 if (state
->mode
== ADV7842_MODE_RGB
) {
1108 /* Receiving analog RGB signal
1109 * Set RGB full range (0-255) */
1110 io_write_and_or(sd
, 0x02, 0x0f, 0x10);
1114 if (state
->mode
== ADV7842_MODE_COMP
) {
1115 /* Receiving analog YPbPr signal
1117 io_write_and_or(sd
, 0x02, 0x0f, 0xf0);
1122 /* Receiving HDMI signal
1124 io_write_and_or(sd
, 0x02, 0x0f, 0xf0);
1128 /* Receiving DVI-D signal
1129 * ADV7842 selects RGB limited range regardless of
1130 * input format (CE/IT) in automatic mode */
1131 if (state
->timings
.bt
.standards
& V4L2_DV_BT_STD_CEA861
) {
1132 /* RGB limited range (16-235) */
1133 io_write_and_or(sd
, 0x02, 0x0f, 0x00);
1135 /* RGB full range (0-255) */
1136 io_write_and_or(sd
, 0x02, 0x0f, 0x10);
1138 if (is_digital_input(sd
) && rgb_output
) {
1139 adv7842_set_offset(sd
, false, 0x40, 0x40, 0x40);
1141 adv7842_set_gain(sd
, false, 0xe0, 0xe0, 0xe0);
1142 adv7842_set_offset(sd
, false, 0x70, 0x70, 0x70);
1146 case V4L2_DV_RGB_RANGE_LIMITED
:
1147 if (state
->mode
== ADV7842_MODE_COMP
) {
1148 /* YCrCb limited range (16-235) */
1149 io_write_and_or(sd
, 0x02, 0x0f, 0x20);
1153 /* RGB limited range (16-235) */
1154 io_write_and_or(sd
, 0x02, 0x0f, 0x00);
1157 case V4L2_DV_RGB_RANGE_FULL
:
1158 if (state
->mode
== ADV7842_MODE_COMP
) {
1159 /* YCrCb full range (0-255) */
1160 io_write_and_or(sd
, 0x02, 0x0f, 0x60);
1164 /* RGB full range (0-255) */
1165 io_write_and_or(sd
, 0x02, 0x0f, 0x10);
1167 if (is_analog_input(sd
) || hdmi_signal
)
1170 /* Adjust gain/offset for DVI-D signals only */
1172 adv7842_set_offset(sd
, false, 0x40, 0x40, 0x40);
1174 adv7842_set_gain(sd
, false, 0xe0, 0xe0, 0xe0);
1175 adv7842_set_offset(sd
, false, 0x70, 0x70, 0x70);
1181 static int adv7842_s_ctrl(struct v4l2_ctrl
*ctrl
)
1183 struct v4l2_subdev
*sd
= to_sd(ctrl
);
1184 struct adv7842_state
*state
= to_state(sd
);
1187 contrast/brightness/hue/free run is acting a bit strange,
1188 not sure if sdp csc is correct.
1191 /* standard ctrls */
1192 case V4L2_CID_BRIGHTNESS
:
1193 cp_write(sd
, 0x3c, ctrl
->val
);
1194 sdp_write(sd
, 0x14, ctrl
->val
);
1195 /* ignore lsb sdp 0x17[3:2] */
1197 case V4L2_CID_CONTRAST
:
1198 cp_write(sd
, 0x3a, ctrl
->val
);
1199 sdp_write(sd
, 0x13, ctrl
->val
);
1200 /* ignore lsb sdp 0x17[1:0] */
1202 case V4L2_CID_SATURATION
:
1203 cp_write(sd
, 0x3b, ctrl
->val
);
1204 sdp_write(sd
, 0x15, ctrl
->val
);
1205 /* ignore lsb sdp 0x17[5:4] */
1208 cp_write(sd
, 0x3d, ctrl
->val
);
1209 sdp_write(sd
, 0x16, ctrl
->val
);
1210 /* ignore lsb sdp 0x17[7:6] */
1213 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE
:
1214 afe_write(sd
, 0xc8, ctrl
->val
);
1216 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL
:
1217 cp_write_and_or(sd
, 0xbf, ~0x04, (ctrl
->val
<< 2));
1218 sdp_write_and_or(sd
, 0xdd, ~0x04, (ctrl
->val
<< 2));
1220 case V4L2_CID_ADV_RX_FREE_RUN_COLOR
: {
1221 u8 R
= (ctrl
->val
& 0xff0000) >> 16;
1222 u8 G
= (ctrl
->val
& 0x00ff00) >> 8;
1223 u8 B
= (ctrl
->val
& 0x0000ff);
1224 /* RGB -> YUV, numerical approximation */
1225 int Y
= 66 * R
+ 129 * G
+ 25 * B
;
1226 int U
= -38 * R
- 74 * G
+ 112 * B
;
1227 int V
= 112 * R
- 94 * G
- 18 * B
;
1229 /* Scale down to 8 bits with rounding */
1233 /* make U,V positive */
1238 v4l2_dbg(1, debug
, sd
, "R %x, G %x, B %x\n", R
, G
, B
);
1239 v4l2_dbg(1, debug
, sd
, "Y %x, U %x, V %x\n", Y
, U
, V
);
1242 cp_write(sd
, 0xc1, R
);
1243 cp_write(sd
, 0xc0, G
);
1244 cp_write(sd
, 0xc2, B
);
1246 sdp_write(sd
, 0xde, Y
);
1247 sdp_write(sd
, 0xdf, (V
& 0xf0) | ((U
>> 4) & 0x0f));
1250 case V4L2_CID_DV_RX_RGB_RANGE
:
1251 state
->rgb_quantization_range
= ctrl
->val
;
1252 set_rgb_quantization_range(sd
);
1258 static inline bool no_power(struct v4l2_subdev
*sd
)
1260 return io_read(sd
, 0x0c) & 0x24;
1263 static inline bool no_cp_signal(struct v4l2_subdev
*sd
)
1265 return ((cp_read(sd
, 0xb5) & 0xd0) != 0xd0) || !(cp_read(sd
, 0xb1) & 0x80);
1268 static inline bool is_hdmi(struct v4l2_subdev
*sd
)
1270 return hdmi_read(sd
, 0x05) & 0x80;
1273 static int adv7842_g_input_status(struct v4l2_subdev
*sd
, u32
*status
)
1275 struct adv7842_state
*state
= to_state(sd
);
1279 if (io_read(sd
, 0x0c) & 0x24)
1280 *status
|= V4L2_IN_ST_NO_POWER
;
1282 if (state
->mode
== ADV7842_MODE_SDP
) {
1283 /* status from SDP block */
1284 if (!(sdp_read(sd
, 0x5A) & 0x01))
1285 *status
|= V4L2_IN_ST_NO_SIGNAL
;
1287 v4l2_dbg(1, debug
, sd
, "%s: SDP status = 0x%x\n",
1291 /* status from CP block */
1292 if ((cp_read(sd
, 0xb5) & 0xd0) != 0xd0 ||
1293 !(cp_read(sd
, 0xb1) & 0x80))
1294 /* TODO channel 2 */
1295 *status
|= V4L2_IN_ST_NO_SIGNAL
;
1297 if (is_digital_input(sd
) && ((io_read(sd
, 0x74) & 0x03) != 0x03))
1298 *status
|= V4L2_IN_ST_NO_SIGNAL
;
1300 v4l2_dbg(1, debug
, sd
, "%s: CP status = 0x%x\n",
1306 struct stdi_readback
{
1312 static int stdi2dv_timings(struct v4l2_subdev
*sd
,
1313 struct stdi_readback
*stdi
,
1314 struct v4l2_dv_timings
*timings
)
1316 struct adv7842_state
*state
= to_state(sd
);
1317 u32 hfreq
= (ADV7842_fsc
* 8) / stdi
->bl
;
1321 for (i
= 0; v4l2_dv_timings_presets
[i
].bt
.width
; i
++) {
1322 const struct v4l2_bt_timings
*bt
= &v4l2_dv_timings_presets
[i
].bt
;
1324 if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets
[i
],
1325 adv7842_get_dv_timings_cap(sd
),
1326 adv7842_check_dv_timings
, NULL
))
1328 if (vtotal(bt
) != stdi
->lcf
+ 1)
1330 if (bt
->vsync
!= stdi
->lcvs
)
1333 pix_clk
= hfreq
* htotal(bt
);
1335 if ((pix_clk
< bt
->pixelclock
+ 1000000) &&
1336 (pix_clk
> bt
->pixelclock
- 1000000)) {
1337 *timings
= v4l2_dv_timings_presets
[i
];
1342 if (v4l2_detect_cvt(stdi
->lcf
+ 1, hfreq
, stdi
->lcvs
,
1343 (stdi
->hs_pol
== '+' ? V4L2_DV_HSYNC_POS_POL
: 0) |
1344 (stdi
->vs_pol
== '+' ? V4L2_DV_VSYNC_POS_POL
: 0),
1347 if (v4l2_detect_gtf(stdi
->lcf
+ 1, hfreq
, stdi
->lcvs
,
1348 (stdi
->hs_pol
== '+' ? V4L2_DV_HSYNC_POS_POL
: 0) |
1349 (stdi
->vs_pol
== '+' ? V4L2_DV_VSYNC_POS_POL
: 0),
1350 state
->aspect_ratio
, timings
))
1353 v4l2_dbg(2, debug
, sd
,
1354 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1355 __func__
, stdi
->lcvs
, stdi
->lcf
, stdi
->bl
,
1356 stdi
->hs_pol
, stdi
->vs_pol
);
1360 static int read_stdi(struct v4l2_subdev
*sd
, struct stdi_readback
*stdi
)
1364 adv7842_g_input_status(sd
, &status
);
1365 if (status
& V4L2_IN_ST_NO_SIGNAL
) {
1366 v4l2_dbg(2, debug
, sd
, "%s: no signal\n", __func__
);
1370 stdi
->bl
= ((cp_read(sd
, 0xb1) & 0x3f) << 8) | cp_read(sd
, 0xb2);
1371 stdi
->lcf
= ((cp_read(sd
, 0xb3) & 0x7) << 8) | cp_read(sd
, 0xb4);
1372 stdi
->lcvs
= cp_read(sd
, 0xb3) >> 3;
1374 if ((cp_read(sd
, 0xb5) & 0x80) && ((cp_read(sd
, 0xb5) & 0x03) == 0x01)) {
1375 stdi
->hs_pol
= ((cp_read(sd
, 0xb5) & 0x10) ?
1376 ((cp_read(sd
, 0xb5) & 0x08) ? '+' : '-') : 'x');
1377 stdi
->vs_pol
= ((cp_read(sd
, 0xb5) & 0x40) ?
1378 ((cp_read(sd
, 0xb5) & 0x20) ? '+' : '-') : 'x');
1383 stdi
->interlaced
= (cp_read(sd
, 0xb1) & 0x40) ? true : false;
1385 if (stdi
->lcf
< 239 || stdi
->bl
< 8 || stdi
->bl
== 0x3fff) {
1386 v4l2_dbg(2, debug
, sd
, "%s: invalid signal\n", __func__
);
1390 v4l2_dbg(2, debug
, sd
,
1391 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1392 __func__
, stdi
->lcf
, stdi
->bl
, stdi
->lcvs
,
1393 stdi
->hs_pol
, stdi
->vs_pol
,
1394 stdi
->interlaced
? "interlaced" : "progressive");
1399 static int adv7842_enum_dv_timings(struct v4l2_subdev
*sd
,
1400 struct v4l2_enum_dv_timings
*timings
)
1402 if (timings
->pad
!= 0)
1405 return v4l2_enum_dv_timings_cap(timings
,
1406 adv7842_get_dv_timings_cap(sd
), adv7842_check_dv_timings
, NULL
);
1409 static int adv7842_dv_timings_cap(struct v4l2_subdev
*sd
,
1410 struct v4l2_dv_timings_cap
*cap
)
1415 *cap
= *adv7842_get_dv_timings_cap(sd
);
1419 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1420 if the format is listed in adv7842_timings[] */
1421 static void adv7842_fill_optional_dv_timings_fields(struct v4l2_subdev
*sd
,
1422 struct v4l2_dv_timings
*timings
)
1424 v4l2_find_dv_timings_cap(timings
, adv7842_get_dv_timings_cap(sd
),
1425 is_digital_input(sd
) ? 250000 : 1000000,
1426 adv7842_check_dv_timings
, NULL
);
1429 static int adv7842_query_dv_timings(struct v4l2_subdev
*sd
,
1430 struct v4l2_dv_timings
*timings
)
1432 struct adv7842_state
*state
= to_state(sd
);
1433 struct v4l2_bt_timings
*bt
= &timings
->bt
;
1434 struct stdi_readback stdi
= { 0 };
1436 v4l2_dbg(1, debug
, sd
, "%s:\n", __func__
);
1438 memset(timings
, 0, sizeof(struct v4l2_dv_timings
));
1441 if (state
->mode
== ADV7842_MODE_SDP
)
1445 if (read_stdi(sd
, &stdi
)) {
1446 state
->restart_stdi_once
= true;
1447 v4l2_dbg(1, debug
, sd
, "%s: no valid signal\n", __func__
);
1450 bt
->interlaced
= stdi
.interlaced
?
1451 V4L2_DV_INTERLACED
: V4L2_DV_PROGRESSIVE
;
1453 if (is_digital_input(sd
)) {
1456 timings
->type
= V4L2_DV_BT_656_1120
;
1458 bt
->width
= (hdmi_read(sd
, 0x07) & 0x0f) * 256 + hdmi_read(sd
, 0x08);
1459 bt
->height
= (hdmi_read(sd
, 0x09) & 0x0f) * 256 + hdmi_read(sd
, 0x0a);
1460 freq
= ((hdmi_read(sd
, 0x51) << 1) + (hdmi_read(sd
, 0x52) >> 7)) * 1000000;
1461 freq
+= ((hdmi_read(sd
, 0x52) & 0x7f) * 7813);
1463 /* adjust for deep color mode */
1464 freq
= freq
* 8 / (((hdmi_read(sd
, 0x0b) & 0xc0) >> 6) * 2 + 8);
1466 bt
->pixelclock
= freq
;
1467 bt
->hfrontporch
= (hdmi_read(sd
, 0x20) & 0x03) * 256 +
1468 hdmi_read(sd
, 0x21);
1469 bt
->hsync
= (hdmi_read(sd
, 0x22) & 0x03) * 256 +
1470 hdmi_read(sd
, 0x23);
1471 bt
->hbackporch
= (hdmi_read(sd
, 0x24) & 0x03) * 256 +
1472 hdmi_read(sd
, 0x25);
1473 bt
->vfrontporch
= ((hdmi_read(sd
, 0x2a) & 0x1f) * 256 +
1474 hdmi_read(sd
, 0x2b)) / 2;
1475 bt
->vsync
= ((hdmi_read(sd
, 0x2e) & 0x1f) * 256 +
1476 hdmi_read(sd
, 0x2f)) / 2;
1477 bt
->vbackporch
= ((hdmi_read(sd
, 0x32) & 0x1f) * 256 +
1478 hdmi_read(sd
, 0x33)) / 2;
1479 bt
->polarities
= ((hdmi_read(sd
, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL
: 0) |
1480 ((hdmi_read(sd
, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL
: 0);
1481 if (bt
->interlaced
== V4L2_DV_INTERLACED
) {
1482 bt
->height
+= (hdmi_read(sd
, 0x0b) & 0x0f) * 256 +
1483 hdmi_read(sd
, 0x0c);
1484 bt
->il_vfrontporch
= ((hdmi_read(sd
, 0x2c) & 0x1f) * 256 +
1485 hdmi_read(sd
, 0x2d)) / 2;
1486 bt
->il_vsync
= ((hdmi_read(sd
, 0x30) & 0x1f) * 256 +
1487 hdmi_read(sd
, 0x31)) / 2;
1488 bt
->il_vbackporch
= ((hdmi_read(sd
, 0x34) & 0x1f) * 256 +
1489 hdmi_read(sd
, 0x35)) / 2;
1491 adv7842_fill_optional_dv_timings_fields(sd
, timings
);
1494 * Since LCVS values are inaccurate [REF_03, p. 339-340],
1495 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1497 if (!stdi2dv_timings(sd
, &stdi
, timings
))
1500 v4l2_dbg(1, debug
, sd
, "%s: lcvs + 1 = %d\n", __func__
, stdi
.lcvs
);
1501 if (!stdi2dv_timings(sd
, &stdi
, timings
))
1504 v4l2_dbg(1, debug
, sd
, "%s: lcvs - 1 = %d\n", __func__
, stdi
.lcvs
);
1505 if (stdi2dv_timings(sd
, &stdi
, timings
)) {
1507 * The STDI block may measure wrong values, especially
1508 * for lcvs and lcf. If the driver can not find any
1509 * valid timing, the STDI block is restarted to measure
1510 * the video timings again. The function will return an
1511 * error, but the restart of STDI will generate a new
1512 * STDI interrupt and the format detection process will
1515 if (state
->restart_stdi_once
) {
1516 v4l2_dbg(1, debug
, sd
, "%s: restart STDI\n", __func__
);
1517 /* TODO restart STDI for Sync Channel 2 */
1518 /* enter one-shot mode */
1519 cp_write_and_or(sd
, 0x86, 0xf9, 0x00);
1520 /* trigger STDI restart */
1521 cp_write_and_or(sd
, 0x86, 0xf9, 0x04);
1522 /* reset to continuous mode */
1523 cp_write_and_or(sd
, 0x86, 0xf9, 0x02);
1524 state
->restart_stdi_once
= false;
1527 v4l2_dbg(1, debug
, sd
, "%s: format not supported\n", __func__
);
1530 state
->restart_stdi_once
= true;
1535 v4l2_print_dv_timings(sd
->name
, "adv7842_query_dv_timings:",
1540 static int adv7842_s_dv_timings(struct v4l2_subdev
*sd
,
1541 struct v4l2_dv_timings
*timings
)
1543 struct adv7842_state
*state
= to_state(sd
);
1544 struct v4l2_bt_timings
*bt
;
1547 v4l2_dbg(1, debug
, sd
, "%s:\n", __func__
);
1549 if (state
->mode
== ADV7842_MODE_SDP
)
1552 if (v4l2_match_dv_timings(&state
->timings
, timings
, 0)) {
1553 v4l2_dbg(1, debug
, sd
, "%s: no change\n", __func__
);
1559 if (!v4l2_valid_dv_timings(timings
, adv7842_get_dv_timings_cap(sd
),
1560 adv7842_check_dv_timings
, NULL
))
1563 adv7842_fill_optional_dv_timings_fields(sd
, timings
);
1565 state
->timings
= *timings
;
1567 cp_write(sd
, 0x91, bt
->interlaced
? 0x40 : 0x00);
1569 /* Use prim_mode and vid_std when available */
1570 err
= configure_predefined_video_timings(sd
, timings
);
1572 /* custom settings when the video format
1573 does not have prim_mode/vid_std */
1574 configure_custom_video_timings(sd
, bt
);
1577 set_rgb_quantization_range(sd
);
1581 v4l2_print_dv_timings(sd
->name
, "adv7842_s_dv_timings: ",
1586 static int adv7842_g_dv_timings(struct v4l2_subdev
*sd
,
1587 struct v4l2_dv_timings
*timings
)
1589 struct adv7842_state
*state
= to_state(sd
);
1591 if (state
->mode
== ADV7842_MODE_SDP
)
1593 *timings
= state
->timings
;
1597 static void enable_input(struct v4l2_subdev
*sd
)
1599 struct adv7842_state
*state
= to_state(sd
);
1601 set_rgb_quantization_range(sd
);
1602 switch (state
->mode
) {
1603 case ADV7842_MODE_SDP
:
1604 case ADV7842_MODE_COMP
:
1605 case ADV7842_MODE_RGB
:
1606 io_write(sd
, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
1608 case ADV7842_MODE_HDMI
:
1609 hdmi_write(sd
, 0x01, 0x00); /* Enable HDMI clock terminators */
1610 io_write(sd
, 0x15, 0xa0); /* Disable Tristate of Pins */
1611 hdmi_write_and_or(sd
, 0x1a, 0xef, 0x00); /* Unmute audio */
1614 v4l2_dbg(2, debug
, sd
, "%s: Unknown mode %d\n",
1615 __func__
, state
->mode
);
1620 static void disable_input(struct v4l2_subdev
*sd
)
1622 hdmi_write_and_or(sd
, 0x1a, 0xef, 0x10); /* Mute audio [REF_01, c. 2.2.2] */
1623 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 8.29] */
1624 io_write(sd
, 0x15, 0xbe); /* Tristate all outputs from video core */
1625 hdmi_write(sd
, 0x01, 0x78); /* Disable HDMI clock terminators */
1628 static void sdp_csc_coeff(struct v4l2_subdev
*sd
,
1629 const struct adv7842_sdp_csc_coeff
*c
)
1631 /* csc auto/manual */
1632 sdp_io_write_and_or(sd
, 0xe0, 0xbf, c
->manual
? 0x00 : 0x40);
1638 sdp_io_write_and_or(sd
, 0xe0, 0x7f, c
->scaling
== 2 ? 0x80 : 0x00);
1641 sdp_io_write_and_or(sd
, 0xe0, 0xe0, c
->A1
>> 8);
1642 sdp_io_write(sd
, 0xe1, c
->A1
);
1643 sdp_io_write_and_or(sd
, 0xe2, 0xe0, c
->A2
>> 8);
1644 sdp_io_write(sd
, 0xe3, c
->A2
);
1645 sdp_io_write_and_or(sd
, 0xe4, 0xe0, c
->A3
>> 8);
1646 sdp_io_write(sd
, 0xe5, c
->A3
);
1649 sdp_io_write_and_or(sd
, 0xe6, 0x80, c
->A4
>> 8);
1650 sdp_io_write(sd
, 0xe7, c
->A4
);
1653 sdp_io_write_and_or(sd
, 0xe8, 0xe0, c
->B1
>> 8);
1654 sdp_io_write(sd
, 0xe9, c
->B1
);
1655 sdp_io_write_and_or(sd
, 0xea, 0xe0, c
->B2
>> 8);
1656 sdp_io_write(sd
, 0xeb, c
->B2
);
1657 sdp_io_write_and_or(sd
, 0xec, 0xe0, c
->B3
>> 8);
1658 sdp_io_write(sd
, 0xed, c
->B3
);
1661 sdp_io_write_and_or(sd
, 0xee, 0x80, c
->B4
>> 8);
1662 sdp_io_write(sd
, 0xef, c
->B4
);
1665 sdp_io_write_and_or(sd
, 0xf0, 0xe0, c
->C1
>> 8);
1666 sdp_io_write(sd
, 0xf1, c
->C1
);
1667 sdp_io_write_and_or(sd
, 0xf2, 0xe0, c
->C2
>> 8);
1668 sdp_io_write(sd
, 0xf3, c
->C2
);
1669 sdp_io_write_and_or(sd
, 0xf4, 0xe0, c
->C3
>> 8);
1670 sdp_io_write(sd
, 0xf5, c
->C3
);
1673 sdp_io_write_and_or(sd
, 0xf6, 0x80, c
->C4
>> 8);
1674 sdp_io_write(sd
, 0xf7, c
->C4
);
1677 static void select_input(struct v4l2_subdev
*sd
,
1678 enum adv7842_vid_std_select vid_std_select
)
1680 struct adv7842_state
*state
= to_state(sd
);
1682 switch (state
->mode
) {
1683 case ADV7842_MODE_SDP
:
1684 io_write(sd
, 0x00, vid_std_select
); /* video std: CVBS or YC mode */
1685 io_write(sd
, 0x01, 0); /* prim mode */
1686 /* enable embedded syncs for auto graphics mode */
1687 cp_write_and_or(sd
, 0x81, 0xef, 0x10);
1689 afe_write(sd
, 0x00, 0x00); /* power up ADC */
1690 afe_write(sd
, 0xc8, 0x00); /* phase control */
1692 io_write(sd
, 0xdd, 0x90); /* Manual 2x output clock */
1693 /* script says register 0xde, which don't exist in manual */
1695 /* Manual analog input muxing mode, CVBS (6.4)*/
1696 afe_write_and_or(sd
, 0x02, 0x7f, 0x80);
1697 if (vid_std_select
== ADV7842_SDP_VID_STD_CVBS_SD_4x1
) {
1698 afe_write(sd
, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
1699 afe_write(sd
, 0x04, 0x00); /* ADC2 N/C,ADC3 N/C*/
1701 afe_write(sd
, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
1702 afe_write(sd
, 0x04, 0xc0); /* ADC2 to AIN12, ADC3 N/C*/
1704 afe_write(sd
, 0x0c, 0x1f); /* ADI recommend write */
1705 afe_write(sd
, 0x12, 0x63); /* ADI recommend write */
1707 sdp_io_write(sd
, 0xb2, 0x60); /* Disable AV codes */
1708 sdp_io_write(sd
, 0xc8, 0xe3); /* Disable Ancillary data */
1710 /* SDP recommended settings */
1711 sdp_write(sd
, 0x00, 0x3F); /* Autodetect PAL NTSC (not SECAM) */
1712 sdp_write(sd
, 0x01, 0x00); /* Pedestal Off */
1714 sdp_write(sd
, 0x03, 0xE4); /* Manual VCR Gain Luma 0x40B */
1715 sdp_write(sd
, 0x04, 0x0B); /* Manual Luma setting */
1716 sdp_write(sd
, 0x05, 0xC3); /* Manual Chroma setting 0x3FE */
1717 sdp_write(sd
, 0x06, 0xFE); /* Manual Chroma setting */
1718 sdp_write(sd
, 0x12, 0x0D); /* Frame TBC,I_P, 3D comb enabled */
1719 sdp_write(sd
, 0xA7, 0x00); /* ADI Recommended Write */
1720 sdp_io_write(sd
, 0xB0, 0x00); /* Disable H and v blanking */
1722 /* deinterlacer enabled and 3D comb */
1723 sdp_write_and_or(sd
, 0x12, 0xf6, 0x09);
1727 case ADV7842_MODE_COMP
:
1728 case ADV7842_MODE_RGB
:
1729 /* Automatic analog input muxing mode */
1730 afe_write_and_or(sd
, 0x02, 0x7f, 0x00);
1731 /* set mode and select free run resolution */
1732 io_write(sd
, 0x00, vid_std_select
); /* video std */
1733 io_write(sd
, 0x01, 0x02); /* prim mode */
1734 cp_write_and_or(sd
, 0x81, 0xef, 0x10); /* enable embedded syncs
1735 for auto graphics mode */
1737 afe_write(sd
, 0x00, 0x00); /* power up ADC */
1738 afe_write(sd
, 0xc8, 0x00); /* phase control */
1739 if (state
->mode
== ADV7842_MODE_COMP
) {
1740 /* force to YCrCb */
1741 io_write_and_or(sd
, 0x02, 0x0f, 0x60);
1744 io_write_and_or(sd
, 0x02, 0x0f, 0x10);
1747 /* set ADI recommended settings for digitizer */
1748 /* "ADV7842 Register Settings Recommendations
1749 * (rev. 1.8, November 2010)" p. 9. */
1750 afe_write(sd
, 0x0c, 0x1f); /* ADC Range improvement */
1751 afe_write(sd
, 0x12, 0x63); /* ADC Range improvement */
1753 /* set to default gain for RGB */
1754 cp_write(sd
, 0x73, 0x10);
1755 cp_write(sd
, 0x74, 0x04);
1756 cp_write(sd
, 0x75, 0x01);
1757 cp_write(sd
, 0x76, 0x00);
1759 cp_write(sd
, 0x3e, 0x04); /* CP core pre-gain control */
1760 cp_write(sd
, 0xc3, 0x39); /* CP coast control. Graphics mode */
1761 cp_write(sd
, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */
1764 case ADV7842_MODE_HDMI
:
1765 /* Automatic analog input muxing mode */
1766 afe_write_and_or(sd
, 0x02, 0x7f, 0x00);
1767 /* set mode and select free run resolution */
1768 if (state
->hdmi_port_a
)
1769 hdmi_write(sd
, 0x00, 0x02); /* select port A */
1771 hdmi_write(sd
, 0x00, 0x03); /* select port B */
1772 io_write(sd
, 0x00, vid_std_select
); /* video std */
1773 io_write(sd
, 0x01, 5); /* prim mode */
1774 cp_write_and_or(sd
, 0x81, 0xef, 0x00); /* disable embedded syncs
1775 for auto graphics mode */
1777 /* set ADI recommended settings for HDMI: */
1778 /* "ADV7842 Register Settings Recommendations
1779 * (rev. 1.8, November 2010)" p. 3. */
1780 hdmi_write(sd
, 0xc0, 0x00);
1781 hdmi_write(sd
, 0x0d, 0x34); /* ADI recommended write */
1782 hdmi_write(sd
, 0x3d, 0x10); /* ADI recommended write */
1783 hdmi_write(sd
, 0x44, 0x85); /* TMDS PLL optimization */
1784 hdmi_write(sd
, 0x46, 0x1f); /* ADI recommended write */
1785 hdmi_write(sd
, 0x57, 0xb6); /* TMDS PLL optimization */
1786 hdmi_write(sd
, 0x58, 0x03); /* TMDS PLL optimization */
1787 hdmi_write(sd
, 0x60, 0x88); /* TMDS PLL optimization */
1788 hdmi_write(sd
, 0x61, 0x88); /* TMDS PLL optimization */
1789 hdmi_write(sd
, 0x6c, 0x18); /* Disable ISRC clearing bit,
1790 Improve robustness */
1791 hdmi_write(sd
, 0x75, 0x10); /* DDC drive strength */
1792 hdmi_write(sd
, 0x85, 0x1f); /* equaliser */
1793 hdmi_write(sd
, 0x87, 0x70); /* ADI recommended write */
1794 hdmi_write(sd
, 0x89, 0x04); /* equaliser */
1795 hdmi_write(sd
, 0x8a, 0x1e); /* equaliser */
1796 hdmi_write(sd
, 0x93, 0x04); /* equaliser */
1797 hdmi_write(sd
, 0x94, 0x1e); /* equaliser */
1798 hdmi_write(sd
, 0x99, 0xa1); /* ADI recommended write */
1799 hdmi_write(sd
, 0x9b, 0x09); /* ADI recommended write */
1800 hdmi_write(sd
, 0x9d, 0x02); /* equaliser */
1802 afe_write(sd
, 0x00, 0xff); /* power down ADC */
1803 afe_write(sd
, 0xc8, 0x40); /* phase control */
1805 /* set to default gain for HDMI */
1806 cp_write(sd
, 0x73, 0x10);
1807 cp_write(sd
, 0x74, 0x04);
1808 cp_write(sd
, 0x75, 0x01);
1809 cp_write(sd
, 0x76, 0x00);
1811 /* reset ADI recommended settings for digitizer */
1812 /* "ADV7842 Register Settings Recommendations
1813 * (rev. 2.5, June 2010)" p. 17. */
1814 afe_write(sd
, 0x12, 0xfb); /* ADC noise shaping filter controls */
1815 afe_write(sd
, 0x0c, 0x0d); /* CP core gain controls */
1816 cp_write(sd
, 0x3e, 0x00); /* CP core pre-gain control */
1818 /* CP coast control */
1819 cp_write(sd
, 0xc3, 0x33); /* Component mode */
1821 /* color space conversion, autodetect color space */
1822 io_write_and_or(sd
, 0x02, 0x0f, 0xf0);
1826 v4l2_dbg(2, debug
, sd
, "%s: Unknown mode %d\n",
1827 __func__
, state
->mode
);
1832 static int adv7842_s_routing(struct v4l2_subdev
*sd
,
1833 u32 input
, u32 output
, u32 config
)
1835 struct adv7842_state
*state
= to_state(sd
);
1837 v4l2_dbg(2, debug
, sd
, "%s: input %d\n", __func__
, input
);
1840 case ADV7842_SELECT_HDMI_PORT_A
:
1841 state
->mode
= ADV7842_MODE_HDMI
;
1842 state
->vid_std_select
= ADV7842_HDMI_COMP_VID_STD_HD_1250P
;
1843 state
->hdmi_port_a
= true;
1845 case ADV7842_SELECT_HDMI_PORT_B
:
1846 state
->mode
= ADV7842_MODE_HDMI
;
1847 state
->vid_std_select
= ADV7842_HDMI_COMP_VID_STD_HD_1250P
;
1848 state
->hdmi_port_a
= false;
1850 case ADV7842_SELECT_VGA_COMP
:
1851 state
->mode
= ADV7842_MODE_COMP
;
1852 state
->vid_std_select
= ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE
;
1854 case ADV7842_SELECT_VGA_RGB
:
1855 state
->mode
= ADV7842_MODE_RGB
;
1856 state
->vid_std_select
= ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE
;
1858 case ADV7842_SELECT_SDP_CVBS
:
1859 state
->mode
= ADV7842_MODE_SDP
;
1860 state
->vid_std_select
= ADV7842_SDP_VID_STD_CVBS_SD_4x1
;
1862 case ADV7842_SELECT_SDP_YC
:
1863 state
->mode
= ADV7842_MODE_SDP
;
1864 state
->vid_std_select
= ADV7842_SDP_VID_STD_YC_SD4_x1
;
1871 select_input(sd
, state
->vid_std_select
);
1874 v4l2_subdev_notify(sd
, ADV7842_FMT_CHANGE
, NULL
);
1879 static int adv7842_enum_mbus_fmt(struct v4l2_subdev
*sd
, unsigned int index
,
1880 enum v4l2_mbus_pixelcode
*code
)
1884 /* Good enough for now */
1885 *code
= V4L2_MBUS_FMT_FIXED
;
1889 static int adv7842_g_mbus_fmt(struct v4l2_subdev
*sd
,
1890 struct v4l2_mbus_framefmt
*fmt
)
1892 struct adv7842_state
*state
= to_state(sd
);
1894 fmt
->width
= state
->timings
.bt
.width
;
1895 fmt
->height
= state
->timings
.bt
.height
;
1896 fmt
->code
= V4L2_MBUS_FMT_FIXED
;
1897 fmt
->field
= V4L2_FIELD_NONE
;
1899 if (state
->mode
== ADV7842_MODE_SDP
) {
1901 if (!(sdp_read(sd
, 0x5A) & 0x01))
1905 if (state
->norm
& V4L2_STD_525_60
)
1909 fmt
->colorspace
= V4L2_COLORSPACE_SMPTE170M
;
1913 if (state
->timings
.bt
.standards
& V4L2_DV_BT_STD_CEA861
) {
1914 fmt
->colorspace
= (state
->timings
.bt
.height
<= 576) ?
1915 V4L2_COLORSPACE_SMPTE170M
: V4L2_COLORSPACE_REC709
;
1920 static void adv7842_irq_enable(struct v4l2_subdev
*sd
, bool enable
)
1923 /* Enable SSPD, STDI and CP locked/unlocked interrupts */
1924 io_write(sd
, 0x46, 0x9c);
1925 /* ESDP_50HZ_DET interrupt */
1926 io_write(sd
, 0x5a, 0x10);
1927 /* Enable CABLE_DET_A/B_ST (+5v) interrupt */
1928 io_write(sd
, 0x73, 0x03);
1929 /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
1930 io_write(sd
, 0x78, 0x03);
1931 /* Enable SDP Standard Detection Change and SDP Video Detected */
1932 io_write(sd
, 0xa0, 0x09);
1933 /* Enable HDMI_MODE interrupt */
1934 io_write(sd
, 0x69, 0x08);
1936 io_write(sd
, 0x46, 0x0);
1937 io_write(sd
, 0x5a, 0x0);
1938 io_write(sd
, 0x73, 0x0);
1939 io_write(sd
, 0x78, 0x0);
1940 io_write(sd
, 0xa0, 0x0);
1941 io_write(sd
, 0x69, 0x0);
1945 static int adv7842_isr(struct v4l2_subdev
*sd
, u32 status
, bool *handled
)
1947 struct adv7842_state
*state
= to_state(sd
);
1948 u8 fmt_change_cp
, fmt_change_digital
, fmt_change_sdp
;
1951 adv7842_irq_enable(sd
, false);
1954 irq_status
[0] = io_read(sd
, 0x43);
1955 irq_status
[1] = io_read(sd
, 0x57);
1956 irq_status
[2] = io_read(sd
, 0x70);
1957 irq_status
[3] = io_read(sd
, 0x75);
1958 irq_status
[4] = io_read(sd
, 0x9d);
1959 irq_status
[5] = io_read(sd
, 0x66);
1963 io_write(sd
, 0x44, irq_status
[0]);
1965 io_write(sd
, 0x58, irq_status
[1]);
1967 io_write(sd
, 0x71, irq_status
[2]);
1969 io_write(sd
, 0x76, irq_status
[3]);
1971 io_write(sd
, 0x9e, irq_status
[4]);
1973 io_write(sd
, 0x67, irq_status
[5]);
1975 adv7842_irq_enable(sd
, true);
1977 v4l2_dbg(1, debug
, sd
, "%s: irq %x, %x, %x, %x, %x, %x\n", __func__
,
1978 irq_status
[0], irq_status
[1], irq_status
[2],
1979 irq_status
[3], irq_status
[4], irq_status
[5]);
1981 /* format change CP */
1982 fmt_change_cp
= irq_status
[0] & 0x9c;
1984 /* format change SDP */
1985 if (state
->mode
== ADV7842_MODE_SDP
)
1986 fmt_change_sdp
= (irq_status
[1] & 0x30) | (irq_status
[4] & 0x09);
1990 /* digital format CP */
1991 if (is_digital_input(sd
))
1992 fmt_change_digital
= irq_status
[3] & 0x03;
1994 fmt_change_digital
= 0;
1997 if (fmt_change_cp
|| fmt_change_digital
|| fmt_change_sdp
) {
1998 v4l2_dbg(1, debug
, sd
,
1999 "%s: fmt_change_cp = 0x%x, fmt_change_digital = 0x%x, fmt_change_sdp = 0x%x\n",
2000 __func__
, fmt_change_cp
, fmt_change_digital
,
2002 v4l2_subdev_notify(sd
, ADV7842_FMT_CHANGE
, NULL
);
2008 if (irq_status
[5] & 0x08) {
2009 v4l2_dbg(1, debug
, sd
, "%s: irq %s mode\n", __func__
,
2010 (io_read(sd
, 0x65) & 0x08) ? "HDMI" : "DVI");
2011 set_rgb_quantization_range(sd
);
2017 if (irq_status
[2] & 0x3) {
2018 v4l2_dbg(1, debug
, sd
, "%s: irq tx_5v\n", __func__
);
2019 adv7842_s_detect_tx_5v_ctrl(sd
);
2026 static int adv7842_get_edid(struct v4l2_subdev
*sd
, struct v4l2_edid
*edid
)
2028 struct adv7842_state
*state
= to_state(sd
);
2031 if (edid
->pad
> ADV7842_EDID_PORT_VGA
)
2033 if (edid
->blocks
== 0)
2035 if (edid
->blocks
> 2)
2037 if (edid
->start_block
> 1)
2039 if (edid
->start_block
== 1)
2042 switch (edid
->pad
) {
2043 case ADV7842_EDID_PORT_A
:
2044 case ADV7842_EDID_PORT_B
:
2045 if (state
->hdmi_edid
.present
& (0x04 << edid
->pad
))
2046 data
= state
->hdmi_edid
.edid
;
2048 case ADV7842_EDID_PORT_VGA
:
2049 if (state
->vga_edid
.present
)
2050 data
= state
->vga_edid
.edid
;
2059 data
+ edid
->start_block
* 128,
2060 edid
->blocks
* 128);
2064 static int adv7842_set_edid(struct v4l2_subdev
*sd
, struct v4l2_edid
*e
)
2066 struct adv7842_state
*state
= to_state(sd
);
2069 if (e
->pad
> ADV7842_EDID_PORT_VGA
)
2071 if (e
->start_block
!= 0)
2076 /* todo, per edid */
2077 state
->aspect_ratio
= v4l2_calc_aspect_ratio(e
->edid
[0x15],
2081 case ADV7842_EDID_PORT_VGA
:
2082 memset(&state
->vga_edid
.edid
, 0, 256);
2083 state
->vga_edid
.present
= e
->blocks
? 0x1 : 0x0;
2084 memcpy(&state
->vga_edid
.edid
, e
->edid
, 128 * e
->blocks
);
2085 err
= edid_write_vga_segment(sd
);
2087 case ADV7842_EDID_PORT_A
:
2088 case ADV7842_EDID_PORT_B
:
2089 memset(&state
->hdmi_edid
.edid
, 0, 256);
2091 state
->hdmi_edid
.present
|= 0x04 << e
->pad
;
2093 state
->hdmi_edid
.present
&= ~(0x04 << e
->pad
);
2094 memcpy(&state
->hdmi_edid
.edid
, e
->edid
, 128 * e
->blocks
);
2095 err
= edid_write_hdmi_segment(sd
, e
->pad
);
2101 v4l2_err(sd
, "error %d writing edid on port %d\n", err
, e
->pad
);
2105 /*********** avi info frame CEA-861-E **************/
2106 /* TODO move to common library */
2108 struct avi_info_frame
{
2132 static const char *y10_txt
[4] = {
2139 static const char *c10_txt
[4] = {
2143 "Extended Colorimetry information valied",
2146 static const char *itc_txt
[2] = {
2151 static const char *ec210_txt
[8] = {
2162 static const char *q10_txt
[4] = {
2169 static void parse_avi_infoframe(struct v4l2_subdev
*sd
, uint8_t *buf
,
2170 struct avi_info_frame
*avi
)
2172 avi
->f17
= (buf
[1] >> 7) & 0x1;
2173 avi
->y10
= (buf
[1] >> 5) & 0x3;
2174 avi
->a0
= (buf
[1] >> 4) & 0x1;
2175 avi
->b10
= (buf
[1] >> 2) & 0x3;
2176 avi
->s10
= buf
[1] & 0x3;
2177 avi
->c10
= (buf
[2] >> 6) & 0x3;
2178 avi
->m10
= (buf
[2] >> 4) & 0x3;
2179 avi
->r3210
= buf
[2] & 0xf;
2180 avi
->itc
= (buf
[3] >> 7) & 0x1;
2181 avi
->ec210
= (buf
[3] >> 4) & 0x7;
2182 avi
->q10
= (buf
[3] >> 2) & 0x3;
2183 avi
->sc10
= buf
[3] & 0x3;
2184 avi
->f47
= (buf
[4] >> 7) & 0x1;
2185 avi
->vic
= buf
[4] & 0x7f;
2186 avi
->yq10
= (buf
[5] >> 6) & 0x3;
2187 avi
->cn10
= (buf
[5] >> 4) & 0x3;
2188 avi
->pr3210
= buf
[5] & 0xf;
2189 avi
->etb
= buf
[6] + 256*buf
[7];
2190 avi
->sbb
= buf
[8] + 256*buf
[9];
2191 avi
->elb
= buf
[10] + 256*buf
[11];
2192 avi
->srb
= buf
[12] + 256*buf
[13];
2195 static void print_avi_infoframe(struct v4l2_subdev
*sd
)
2201 struct avi_info_frame avi
;
2203 if (!(hdmi_read(sd
, 0x05) & 0x80)) {
2204 v4l2_info(sd
, "receive DVI-D signal (AVI infoframe not supported)\n");
2207 if (!(io_read(sd
, 0x60) & 0x01)) {
2208 v4l2_info(sd
, "AVI infoframe not received\n");
2212 if (io_read(sd
, 0x88) & 0x10) {
2213 v4l2_info(sd
, "AVI infoframe checksum error has occurred earlier\n");
2214 io_write(sd
, 0x8a, 0x10); /* clear AVI_INF_CKS_ERR_RAW */
2215 if (io_read(sd
, 0x88) & 0x10) {
2216 v4l2_info(sd
, "AVI infoframe checksum error still present\n");
2217 io_write(sd
, 0x8a, 0x10); /* clear AVI_INF_CKS_ERR_RAW */
2221 avi_len
= infoframe_read(sd
, 0xe2);
2222 avi_ver
= infoframe_read(sd
, 0xe1);
2223 v4l2_info(sd
, "AVI infoframe version %d (%d byte)\n",
2226 if (avi_ver
!= 0x02)
2229 for (i
= 0; i
< 14; i
++)
2230 buf
[i
] = infoframe_read(sd
, i
);
2232 v4l2_info(sd
, "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
2233 buf
[0], buf
[1], buf
[2], buf
[3], buf
[4], buf
[5], buf
[6], buf
[7],
2234 buf
[8], buf
[9], buf
[10], buf
[11], buf
[12], buf
[13]);
2236 parse_avi_infoframe(sd
, buf
, &avi
);
2239 v4l2_info(sd
, "\tVIC: %d\n", avi
.vic
);
2241 v4l2_info(sd
, "\t%s\n", itc_txt
[avi
.itc
]);
2244 v4l2_info(sd
, "\t%s %s\n", y10_txt
[avi
.y10
], !avi
.c10
? "" :
2245 (avi
.c10
== 0x3 ? ec210_txt
[avi
.ec210
] : c10_txt
[avi
.c10
]));
2247 v4l2_info(sd
, "\t%s %s\n", y10_txt
[avi
.y10
], q10_txt
[avi
.q10
]);
2250 static const char * const prim_mode_txt
[] = {
2255 "CVBS & HDMI AUDIO",
2269 static int adv7842_sdp_log_status(struct v4l2_subdev
*sd
)
2271 /* SDP (Standard definition processor) block */
2272 uint8_t sdp_signal_detected
= sdp_read(sd
, 0x5A) & 0x01;
2274 v4l2_info(sd
, "Chip powered %s\n", no_power(sd
) ? "off" : "on");
2275 v4l2_info(sd
, "Prim-mode = 0x%x, video std = 0x%x\n",
2276 io_read(sd
, 0x01) & 0x0f, io_read(sd
, 0x00) & 0x3f);
2278 v4l2_info(sd
, "SDP: free run: %s\n",
2279 (sdp_read(sd
, 0x56) & 0x01) ? "on" : "off");
2280 v4l2_info(sd
, "SDP: %s\n", sdp_signal_detected
?
2281 "valid SD/PR signal detected" : "invalid/no signal");
2282 if (sdp_signal_detected
) {
2283 static const char * const sdp_std_txt
[] = {
2291 "7?", "8?", "9?", "a?", "b?",
2297 v4l2_info(sd
, "SDP: standard %s\n",
2298 sdp_std_txt
[sdp_read(sd
, 0x52) & 0x0f]);
2299 v4l2_info(sd
, "SDP: %s\n",
2300 (sdp_read(sd
, 0x59) & 0x08) ? "50Hz" : "60Hz");
2301 v4l2_info(sd
, "SDP: %s\n",
2302 (sdp_read(sd
, 0x57) & 0x08) ? "Interlaced" : "Progressive");
2303 v4l2_info(sd
, "SDP: deinterlacer %s\n",
2304 (sdp_read(sd
, 0x12) & 0x08) ? "enabled" : "disabled");
2305 v4l2_info(sd
, "SDP: csc %s mode\n",
2306 (sdp_io_read(sd
, 0xe0) & 0x40) ? "auto" : "manual");
2311 static int adv7842_cp_log_status(struct v4l2_subdev
*sd
)
2314 struct adv7842_state
*state
= to_state(sd
);
2315 struct v4l2_dv_timings timings
;
2316 uint8_t reg_io_0x02
= io_read(sd
, 0x02);
2317 uint8_t reg_io_0x21
= io_read(sd
, 0x21);
2318 uint8_t reg_rep_0x77
= rep_read(sd
, 0x77);
2319 uint8_t reg_rep_0x7d
= rep_read(sd
, 0x7d);
2320 bool audio_pll_locked
= hdmi_read(sd
, 0x04) & 0x01;
2321 bool audio_sample_packet_detect
= hdmi_read(sd
, 0x18) & 0x01;
2322 bool audio_mute
= io_read(sd
, 0x65) & 0x40;
2324 static const char * const csc_coeff_sel_rb
[16] = {
2325 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
2326 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
2327 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
2328 "reserved", "reserved", "reserved", "reserved", "manual"
2330 static const char * const input_color_space_txt
[16] = {
2331 "RGB limited range (16-235)", "RGB full range (0-255)",
2332 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
2333 "xvYCC Bt.601", "xvYCC Bt.709",
2334 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2335 "invalid", "invalid", "invalid", "invalid", "invalid",
2336 "invalid", "invalid", "automatic"
2338 static const char * const rgb_quantization_range_txt
[] = {
2340 "RGB limited range (16-235)",
2341 "RGB full range (0-255)",
2343 static const char * const deep_color_mode_txt
[4] = {
2344 "8-bits per channel",
2345 "10-bits per channel",
2346 "12-bits per channel",
2347 "16-bits per channel (not supported)"
2350 v4l2_info(sd
, "-----Chip status-----\n");
2351 v4l2_info(sd
, "Chip power: %s\n", no_power(sd
) ? "off" : "on");
2352 v4l2_info(sd
, "HDMI/DVI-D port selected: %s\n",
2353 state
->hdmi_port_a
? "A" : "B");
2354 v4l2_info(sd
, "EDID A %s, B %s\n",
2355 ((reg_rep_0x7d
& 0x04) && (reg_rep_0x77
& 0x04)) ?
2356 "enabled" : "disabled",
2357 ((reg_rep_0x7d
& 0x08) && (reg_rep_0x77
& 0x08)) ?
2358 "enabled" : "disabled");
2359 v4l2_info(sd
, "HPD A %s, B %s\n",
2360 reg_io_0x21
& 0x02 ? "enabled" : "disabled",
2361 reg_io_0x21
& 0x01 ? "enabled" : "disabled");
2362 v4l2_info(sd
, "CEC %s\n", !!(cec_read(sd
, 0x2a) & 0x01) ?
2363 "enabled" : "disabled");
2365 v4l2_info(sd
, "-----Signal status-----\n");
2366 if (state
->hdmi_port_a
) {
2367 v4l2_info(sd
, "Cable detected (+5V power): %s\n",
2368 io_read(sd
, 0x6f) & 0x02 ? "true" : "false");
2369 v4l2_info(sd
, "TMDS signal detected: %s\n",
2370 (io_read(sd
, 0x6a) & 0x02) ? "true" : "false");
2371 v4l2_info(sd
, "TMDS signal locked: %s\n",
2372 (io_read(sd
, 0x6a) & 0x20) ? "true" : "false");
2374 v4l2_info(sd
, "Cable detected (+5V power):%s\n",
2375 io_read(sd
, 0x6f) & 0x01 ? "true" : "false");
2376 v4l2_info(sd
, "TMDS signal detected: %s\n",
2377 (io_read(sd
, 0x6a) & 0x01) ? "true" : "false");
2378 v4l2_info(sd
, "TMDS signal locked: %s\n",
2379 (io_read(sd
, 0x6a) & 0x10) ? "true" : "false");
2381 v4l2_info(sd
, "CP free run: %s\n",
2382 (!!(cp_read(sd
, 0xff) & 0x10) ? "on" : "off"));
2383 v4l2_info(sd
, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2384 io_read(sd
, 0x01) & 0x0f, io_read(sd
, 0x00) & 0x3f,
2385 (io_read(sd
, 0x01) & 0x70) >> 4);
2387 v4l2_info(sd
, "-----Video Timings-----\n");
2388 if (no_cp_signal(sd
)) {
2389 v4l2_info(sd
, "STDI: not locked\n");
2391 uint32_t bl
= ((cp_read(sd
, 0xb1) & 0x3f) << 8) | cp_read(sd
, 0xb2);
2392 uint32_t lcf
= ((cp_read(sd
, 0xb3) & 0x7) << 8) | cp_read(sd
, 0xb4);
2393 uint32_t lcvs
= cp_read(sd
, 0xb3) >> 3;
2394 uint32_t fcl
= ((cp_read(sd
, 0xb8) & 0x1f) << 8) | cp_read(sd
, 0xb9);
2395 char hs_pol
= ((cp_read(sd
, 0xb5) & 0x10) ?
2396 ((cp_read(sd
, 0xb5) & 0x08) ? '+' : '-') : 'x');
2397 char vs_pol
= ((cp_read(sd
, 0xb5) & 0x40) ?
2398 ((cp_read(sd
, 0xb5) & 0x20) ? '+' : '-') : 'x');
2400 "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, fcl = %d, %s, %chsync, %cvsync\n",
2402 (cp_read(sd
, 0xb1) & 0x40) ?
2403 "interlaced" : "progressive",
2406 if (adv7842_query_dv_timings(sd
, &timings
))
2407 v4l2_info(sd
, "No video detected\n");
2409 v4l2_print_dv_timings(sd
->name
, "Detected format: ",
2411 v4l2_print_dv_timings(sd
->name
, "Configured format: ",
2412 &state
->timings
, true);
2414 if (no_cp_signal(sd
))
2417 v4l2_info(sd
, "-----Color space-----\n");
2418 v4l2_info(sd
, "RGB quantization range ctrl: %s\n",
2419 rgb_quantization_range_txt
[state
->rgb_quantization_range
]);
2420 v4l2_info(sd
, "Input color space: %s\n",
2421 input_color_space_txt
[reg_io_0x02
>> 4]);
2422 v4l2_info(sd
, "Output color space: %s %s, saturator %s\n",
2423 (reg_io_0x02
& 0x02) ? "RGB" : "YCbCr",
2424 (reg_io_0x02
& 0x04) ? "(16-235)" : "(0-255)",
2425 ((reg_io_0x02
& 0x04) ^ (reg_io_0x02
& 0x01)) ?
2426 "enabled" : "disabled");
2427 v4l2_info(sd
, "Color space conversion: %s\n",
2428 csc_coeff_sel_rb
[cp_read(sd
, 0xf4) >> 4]);
2430 if (!is_digital_input(sd
))
2433 v4l2_info(sd
, "-----%s status-----\n", is_hdmi(sd
) ? "HDMI" : "DVI-D");
2434 v4l2_info(sd
, "HDCP encrypted content: %s\n",
2435 (hdmi_read(sd
, 0x05) & 0x40) ? "true" : "false");
2436 v4l2_info(sd
, "HDCP keys read: %s%s\n",
2437 (hdmi_read(sd
, 0x04) & 0x20) ? "yes" : "no",
2438 (hdmi_read(sd
, 0x04) & 0x10) ? "ERROR" : "");
2442 v4l2_info(sd
, "Audio: pll %s, samples %s, %s\n",
2443 audio_pll_locked
? "locked" : "not locked",
2444 audio_sample_packet_detect
? "detected" : "not detected",
2445 audio_mute
? "muted" : "enabled");
2446 if (audio_pll_locked
&& audio_sample_packet_detect
) {
2447 v4l2_info(sd
, "Audio format: %s\n",
2448 (hdmi_read(sd
, 0x07) & 0x40) ? "multi-channel" : "stereo");
2450 v4l2_info(sd
, "Audio CTS: %u\n", (hdmi_read(sd
, 0x5b) << 12) +
2451 (hdmi_read(sd
, 0x5c) << 8) +
2452 (hdmi_read(sd
, 0x5d) & 0xf0));
2453 v4l2_info(sd
, "Audio N: %u\n", ((hdmi_read(sd
, 0x5d) & 0x0f) << 16) +
2454 (hdmi_read(sd
, 0x5e) << 8) +
2455 hdmi_read(sd
, 0x5f));
2456 v4l2_info(sd
, "AV Mute: %s\n",
2457 (hdmi_read(sd
, 0x04) & 0x40) ? "on" : "off");
2458 v4l2_info(sd
, "Deep color mode: %s\n",
2459 deep_color_mode_txt
[hdmi_read(sd
, 0x0b) >> 6]);
2461 print_avi_infoframe(sd
);
2465 static int adv7842_log_status(struct v4l2_subdev
*sd
)
2467 struct adv7842_state
*state
= to_state(sd
);
2469 if (state
->mode
== ADV7842_MODE_SDP
)
2470 return adv7842_sdp_log_status(sd
);
2471 return adv7842_cp_log_status(sd
);
2474 static int adv7842_querystd(struct v4l2_subdev
*sd
, v4l2_std_id
*std
)
2476 struct adv7842_state
*state
= to_state(sd
);
2478 v4l2_dbg(1, debug
, sd
, "%s:\n", __func__
);
2480 if (state
->mode
!= ADV7842_MODE_SDP
)
2483 if (!(sdp_read(sd
, 0x5A) & 0x01)) {
2485 v4l2_dbg(1, debug
, sd
, "%s: no valid signal\n", __func__
);
2489 switch (sdp_read(sd
, 0x52) & 0x0f) {
2492 *std
&= V4L2_STD_NTSC
;
2496 *std
&= V4L2_STD_NTSC_443
;
2500 *std
&= V4L2_STD_SECAM
;
2504 *std
&= V4L2_STD_PAL_M
;
2508 *std
&= V4L2_STD_PAL_60
;
2512 *std
&= V4L2_STD_PAL_Nc
;
2516 *std
&= V4L2_STD_PAL
;
2520 *std
&= V4L2_STD_SECAM
;
2523 *std
&= V4L2_STD_ALL
;
2529 static void adv7842_s_sdp_io(struct v4l2_subdev
*sd
, struct adv7842_sdp_io_sync_adjustment
*s
)
2531 if (s
&& s
->adjust
) {
2532 sdp_io_write(sd
, 0x94, (s
->hs_beg
>> 8) & 0xf);
2533 sdp_io_write(sd
, 0x95, s
->hs_beg
& 0xff);
2534 sdp_io_write(sd
, 0x96, (s
->hs_width
>> 8) & 0xf);
2535 sdp_io_write(sd
, 0x97, s
->hs_width
& 0xff);
2536 sdp_io_write(sd
, 0x98, (s
->de_beg
>> 8) & 0xf);
2537 sdp_io_write(sd
, 0x99, s
->de_beg
& 0xff);
2538 sdp_io_write(sd
, 0x9a, (s
->de_end
>> 8) & 0xf);
2539 sdp_io_write(sd
, 0x9b, s
->de_end
& 0xff);
2540 sdp_io_write(sd
, 0xa8, s
->vs_beg_o
);
2541 sdp_io_write(sd
, 0xa9, s
->vs_beg_e
);
2542 sdp_io_write(sd
, 0xaa, s
->vs_end_o
);
2543 sdp_io_write(sd
, 0xab, s
->vs_end_e
);
2544 sdp_io_write(sd
, 0xac, s
->de_v_beg_o
);
2545 sdp_io_write(sd
, 0xad, s
->de_v_beg_e
);
2546 sdp_io_write(sd
, 0xae, s
->de_v_end_o
);
2547 sdp_io_write(sd
, 0xaf, s
->de_v_end_e
);
2549 /* set to default */
2550 sdp_io_write(sd
, 0x94, 0x00);
2551 sdp_io_write(sd
, 0x95, 0x00);
2552 sdp_io_write(sd
, 0x96, 0x00);
2553 sdp_io_write(sd
, 0x97, 0x20);
2554 sdp_io_write(sd
, 0x98, 0x00);
2555 sdp_io_write(sd
, 0x99, 0x00);
2556 sdp_io_write(sd
, 0x9a, 0x00);
2557 sdp_io_write(sd
, 0x9b, 0x00);
2558 sdp_io_write(sd
, 0xa8, 0x04);
2559 sdp_io_write(sd
, 0xa9, 0x04);
2560 sdp_io_write(sd
, 0xaa, 0x04);
2561 sdp_io_write(sd
, 0xab, 0x04);
2562 sdp_io_write(sd
, 0xac, 0x04);
2563 sdp_io_write(sd
, 0xad, 0x04);
2564 sdp_io_write(sd
, 0xae, 0x04);
2565 sdp_io_write(sd
, 0xaf, 0x04);
2569 static int adv7842_s_std(struct v4l2_subdev
*sd
, v4l2_std_id norm
)
2571 struct adv7842_state
*state
= to_state(sd
);
2572 struct adv7842_platform_data
*pdata
= &state
->pdata
;
2574 v4l2_dbg(1, debug
, sd
, "%s:\n", __func__
);
2576 if (state
->mode
!= ADV7842_MODE_SDP
)
2579 if (norm
& V4L2_STD_625_50
)
2580 adv7842_s_sdp_io(sd
, &pdata
->sdp_io_sync_625
);
2581 else if (norm
& V4L2_STD_525_60
)
2582 adv7842_s_sdp_io(sd
, &pdata
->sdp_io_sync_525
);
2584 adv7842_s_sdp_io(sd
, NULL
);
2586 if (norm
& V4L2_STD_ALL
) {
2593 static int adv7842_g_std(struct v4l2_subdev
*sd
, v4l2_std_id
*norm
)
2595 struct adv7842_state
*state
= to_state(sd
);
2597 v4l2_dbg(1, debug
, sd
, "%s:\n", __func__
);
2599 if (state
->mode
!= ADV7842_MODE_SDP
)
2602 *norm
= state
->norm
;
2606 /* ----------------------------------------------------------------------- */
2608 static int adv7842_core_init(struct v4l2_subdev
*sd
)
2610 struct adv7842_state
*state
= to_state(sd
);
2611 struct adv7842_platform_data
*pdata
= &state
->pdata
;
2612 hdmi_write(sd
, 0x48,
2613 (pdata
->disable_pwrdnb
? 0x80 : 0) |
2614 (pdata
->disable_cable_det_rst
? 0x40 : 0));
2619 * Disable I2C access to internal EDID ram from HDMI DDC ports
2620 * Disable auto edid enable when leaving powerdown mode
2622 rep_write_and_or(sd
, 0x77, 0xd3, 0x20);
2625 io_write(sd
, 0x0c, 0x42); /* Power up part and power down VDP */
2626 io_write(sd
, 0x15, 0x80); /* Power up pads */
2631 pdata
->alt_gamma
<< 3 |
2632 pdata
->op_656_range
<< 2 |
2633 pdata
->rgb_out
<< 1 |
2634 pdata
->alt_data_sat
<< 0);
2635 io_write(sd
, 0x03, pdata
->op_format_sel
);
2636 io_write_and_or(sd
, 0x04, 0x1f, pdata
->op_ch_sel
<< 5);
2637 io_write_and_or(sd
, 0x05, 0xf0, pdata
->blank_data
<< 3 |
2638 pdata
->insert_av_codes
<< 2 |
2639 pdata
->replicate_av_codes
<< 1 |
2640 pdata
->invert_cbcr
<< 0);
2643 hdmi_write_and_or(sd
, 0x1a, 0xf1, 0x08); /* Wait 1 s before unmute */
2645 /* Drive strength */
2646 io_write_and_or(sd
, 0x14, 0xc0,
2647 pdata
->dr_str_data
<< 4 |
2648 pdata
->dr_str_clk
<< 2 |
2649 pdata
->dr_str_sync
);
2652 cp_write_and_or(sd
, 0xba, 0xfc, pdata
->hdmi_free_run_enable
|
2653 (pdata
->hdmi_free_run_mode
<< 1));
2656 sdp_write_and_or(sd
, 0xdd, 0xf0, pdata
->sdp_free_run_force
|
2657 (pdata
->sdp_free_run_cbar_en
<< 1) |
2658 (pdata
->sdp_free_run_man_col_en
<< 2) |
2659 (pdata
->sdp_free_run_auto
<< 3));
2661 /* TODO from platform data */
2662 cp_write(sd
, 0x69, 0x14); /* Enable CP CSC */
2663 io_write(sd
, 0x06, 0xa6); /* positive VS and HS and DE */
2664 cp_write(sd
, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
2665 afe_write(sd
, 0xb5, 0x01); /* Setting MCLK to 256Fs */
2667 afe_write(sd
, 0x02, pdata
->ain_sel
); /* Select analog input muxing mode */
2668 io_write_and_or(sd
, 0x30, ~(1 << 4), pdata
->output_bus_lsb_to_msb
<< 4);
2670 sdp_csc_coeff(sd
, &pdata
->sdp_csc_coeff
);
2672 /* todo, improve settings for sdram */
2673 if (pdata
->sd_ram_size
>= 128) {
2674 sdp_write(sd
, 0x12, 0x0d); /* Frame TBC,3D comb enabled */
2675 if (pdata
->sd_ram_ddr
) {
2676 /* SDP setup for the AD eval board */
2677 sdp_io_write(sd
, 0x6f, 0x00); /* DDR mode */
2678 sdp_io_write(sd
, 0x75, 0x0a); /* 128 MB memory size */
2679 sdp_io_write(sd
, 0x7a, 0xa5); /* Timing Adjustment */
2680 sdp_io_write(sd
, 0x7b, 0x8f); /* Timing Adjustment */
2681 sdp_io_write(sd
, 0x60, 0x01); /* SDRAM reset */
2683 sdp_io_write(sd
, 0x75, 0x0a); /* 64 MB memory size ?*/
2684 sdp_io_write(sd
, 0x74, 0x00); /* must be zero for sdr sdram */
2685 sdp_io_write(sd
, 0x79, 0x33); /* CAS latency to 3,
2686 depends on memory */
2687 sdp_io_write(sd
, 0x6f, 0x01); /* SDR mode */
2688 sdp_io_write(sd
, 0x7a, 0xa5); /* Timing Adjustment */
2689 sdp_io_write(sd
, 0x7b, 0x8f); /* Timing Adjustment */
2690 sdp_io_write(sd
, 0x60, 0x01); /* SDRAM reset */
2694 * Manual UG-214, rev 0 is bit confusing on this bit
2695 * but a '1' disables any signal if the Ram is active.
2697 sdp_io_write(sd
, 0x29, 0x10); /* Tristate memory interface */
2700 select_input(sd
, pdata
->vid_std_select
);
2704 if (pdata
->hpa_auto
) {
2705 /* HPA auto, HPA 0.5s after Edid set and Cable detect */
2706 hdmi_write(sd
, 0x69, 0x5c);
2709 hdmi_write(sd
, 0x69, 0xa3);
2710 /* HPA disable on port A and B */
2711 io_write_and_or(sd
, 0x20, 0xcf, 0x00);
2715 io_write(sd
, 0x19, 0x80 | pdata
->llc_dll_phase
);
2716 io_write(sd
, 0x33, 0x40);
2719 io_write(sd
, 0x40, 0xf2); /* Configure INT1 */
2721 adv7842_irq_enable(sd
, true);
2723 return v4l2_ctrl_handler_setup(sd
->ctrl_handler
);
2726 /* ----------------------------------------------------------------------- */
2728 static int adv7842_ddr_ram_test(struct v4l2_subdev
*sd
)
2731 * From ADV784x external Memory test.pdf
2733 * Reset must just been performed before running test.
2734 * Recommended to reset after test.
2741 io_write(sd
, 0x00, 0x01); /* Program SDP 4x1 */
2742 io_write(sd
, 0x01, 0x00); /* Program SDP mode */
2743 afe_write(sd
, 0x80, 0x92); /* SDP Recommeneded Write */
2744 afe_write(sd
, 0x9B, 0x01); /* SDP Recommeneded Write ADV7844ES1 */
2745 afe_write(sd
, 0x9C, 0x60); /* SDP Recommeneded Write ADV7844ES1 */
2746 afe_write(sd
, 0x9E, 0x02); /* SDP Recommeneded Write ADV7844ES1 */
2747 afe_write(sd
, 0xA0, 0x0B); /* SDP Recommeneded Write ADV7844ES1 */
2748 afe_write(sd
, 0xC3, 0x02); /* Memory BIST Initialisation */
2749 io_write(sd
, 0x0C, 0x40); /* Power up ADV7844 */
2750 io_write(sd
, 0x15, 0xBA); /* Enable outputs */
2751 sdp_write(sd
, 0x12, 0x00); /* Disable 3D comb, Frame TBC & 3DNR */
2752 io_write(sd
, 0xFF, 0x04); /* Reset memory controller */
2756 sdp_write(sd
, 0x12, 0x00); /* Disable 3D Comb, Frame TBC & 3DNR */
2757 sdp_io_write(sd
, 0x2A, 0x01); /* Memory BIST Initialisation */
2758 sdp_io_write(sd
, 0x7c, 0x19); /* Memory BIST Initialisation */
2759 sdp_io_write(sd
, 0x80, 0x87); /* Memory BIST Initialisation */
2760 sdp_io_write(sd
, 0x81, 0x4a); /* Memory BIST Initialisation */
2761 sdp_io_write(sd
, 0x82, 0x2c); /* Memory BIST Initialisation */
2762 sdp_io_write(sd
, 0x83, 0x0e); /* Memory BIST Initialisation */
2763 sdp_io_write(sd
, 0x84, 0x94); /* Memory BIST Initialisation */
2764 sdp_io_write(sd
, 0x85, 0x62); /* Memory BIST Initialisation */
2765 sdp_io_write(sd
, 0x7d, 0x00); /* Memory BIST Initialisation */
2766 sdp_io_write(sd
, 0x7e, 0x1a); /* Memory BIST Initialisation */
2770 sdp_io_write(sd
, 0xd9, 0xd5); /* Enable BIST Test */
2771 sdp_write(sd
, 0x12, 0x05); /* Enable FRAME TBC & 3D COMB */
2775 for (i
= 0; i
< 10; i
++) {
2776 u8 result
= sdp_io_read(sd
, 0xdb);
2777 if (result
& 0x10) {
2787 v4l2_dbg(1, debug
, sd
,
2788 "Ram Test: completed %d of %d: pass %d, fail %d\n",
2789 complete
, i
, pass
, fail
);
2791 if (!complete
|| fail
)
2796 static void adv7842_rewrite_i2c_addresses(struct v4l2_subdev
*sd
,
2797 struct adv7842_platform_data
*pdata
)
2799 io_write(sd
, 0xf1, pdata
->i2c_sdp
<< 1);
2800 io_write(sd
, 0xf2, pdata
->i2c_sdp_io
<< 1);
2801 io_write(sd
, 0xf3, pdata
->i2c_avlink
<< 1);
2802 io_write(sd
, 0xf4, pdata
->i2c_cec
<< 1);
2803 io_write(sd
, 0xf5, pdata
->i2c_infoframe
<< 1);
2805 io_write(sd
, 0xf8, pdata
->i2c_afe
<< 1);
2806 io_write(sd
, 0xf9, pdata
->i2c_repeater
<< 1);
2807 io_write(sd
, 0xfa, pdata
->i2c_edid
<< 1);
2808 io_write(sd
, 0xfb, pdata
->i2c_hdmi
<< 1);
2810 io_write(sd
, 0xfd, pdata
->i2c_cp
<< 1);
2811 io_write(sd
, 0xfe, pdata
->i2c_vdp
<< 1);
2814 static int adv7842_command_ram_test(struct v4l2_subdev
*sd
)
2816 struct i2c_client
*client
= v4l2_get_subdevdata(sd
);
2817 struct adv7842_state
*state
= to_state(sd
);
2818 struct adv7842_platform_data
*pdata
= client
->dev
.platform_data
;
2819 struct v4l2_dv_timings timings
;
2825 if (!pdata
->sd_ram_size
|| !pdata
->sd_ram_ddr
) {
2826 v4l2_info(sd
, "no sdram or no ddr sdram\n");
2832 adv7842_rewrite_i2c_addresses(sd
, pdata
);
2835 ret
= adv7842_ddr_ram_test(sd
);
2839 adv7842_rewrite_i2c_addresses(sd
, pdata
);
2841 /* and re-init chip and state */
2842 adv7842_core_init(sd
);
2846 select_input(sd
, state
->vid_std_select
);
2850 edid_write_vga_segment(sd
);
2851 edid_write_hdmi_segment(sd
, ADV7842_EDID_PORT_A
);
2852 edid_write_hdmi_segment(sd
, ADV7842_EDID_PORT_B
);
2854 timings
= state
->timings
;
2856 memset(&state
->timings
, 0, sizeof(struct v4l2_dv_timings
));
2858 adv7842_s_dv_timings(sd
, &timings
);
2863 static long adv7842_ioctl(struct v4l2_subdev
*sd
, unsigned int cmd
, void *arg
)
2866 case ADV7842_CMD_RAM_TEST
:
2867 return adv7842_command_ram_test(sd
);
2872 /* ----------------------------------------------------------------------- */
2874 static const struct v4l2_ctrl_ops adv7842_ctrl_ops
= {
2875 .s_ctrl
= adv7842_s_ctrl
,
2878 static const struct v4l2_subdev_core_ops adv7842_core_ops
= {
2879 .log_status
= adv7842_log_status
,
2880 .ioctl
= adv7842_ioctl
,
2881 .interrupt_service_routine
= adv7842_isr
,
2882 #ifdef CONFIG_VIDEO_ADV_DEBUG
2883 .g_register
= adv7842_g_register
,
2884 .s_register
= adv7842_s_register
,
2888 static const struct v4l2_subdev_video_ops adv7842_video_ops
= {
2889 .g_std
= adv7842_g_std
,
2890 .s_std
= adv7842_s_std
,
2891 .s_routing
= adv7842_s_routing
,
2892 .querystd
= adv7842_querystd
,
2893 .g_input_status
= adv7842_g_input_status
,
2894 .s_dv_timings
= adv7842_s_dv_timings
,
2895 .g_dv_timings
= adv7842_g_dv_timings
,
2896 .query_dv_timings
= adv7842_query_dv_timings
,
2897 .enum_mbus_fmt
= adv7842_enum_mbus_fmt
,
2898 .g_mbus_fmt
= adv7842_g_mbus_fmt
,
2899 .try_mbus_fmt
= adv7842_g_mbus_fmt
,
2900 .s_mbus_fmt
= adv7842_g_mbus_fmt
,
2903 static const struct v4l2_subdev_pad_ops adv7842_pad_ops
= {
2904 .get_edid
= adv7842_get_edid
,
2905 .set_edid
= adv7842_set_edid
,
2906 .enum_dv_timings
= adv7842_enum_dv_timings
,
2907 .dv_timings_cap
= adv7842_dv_timings_cap
,
2910 static const struct v4l2_subdev_ops adv7842_ops
= {
2911 .core
= &adv7842_core_ops
,
2912 .video
= &adv7842_video_ops
,
2913 .pad
= &adv7842_pad_ops
,
2916 /* -------------------------- custom ctrls ---------------------------------- */
2918 static const struct v4l2_ctrl_config adv7842_ctrl_analog_sampling_phase
= {
2919 .ops
= &adv7842_ctrl_ops
,
2920 .id
= V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE
,
2921 .name
= "Analog Sampling Phase",
2922 .type
= V4L2_CTRL_TYPE_INTEGER
,
2929 static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color_manual
= {
2930 .ops
= &adv7842_ctrl_ops
,
2931 .id
= V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL
,
2932 .name
= "Free Running Color, Manual",
2933 .type
= V4L2_CTRL_TYPE_BOOLEAN
,
2939 static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color
= {
2940 .ops
= &adv7842_ctrl_ops
,
2941 .id
= V4L2_CID_ADV_RX_FREE_RUN_COLOR
,
2942 .name
= "Free Running Color",
2943 .type
= V4L2_CTRL_TYPE_INTEGER
,
2949 static void adv7842_unregister_clients(struct v4l2_subdev
*sd
)
2951 struct adv7842_state
*state
= to_state(sd
);
2952 if (state
->i2c_avlink
)
2953 i2c_unregister_device(state
->i2c_avlink
);
2955 i2c_unregister_device(state
->i2c_cec
);
2956 if (state
->i2c_infoframe
)
2957 i2c_unregister_device(state
->i2c_infoframe
);
2958 if (state
->i2c_sdp_io
)
2959 i2c_unregister_device(state
->i2c_sdp_io
);
2961 i2c_unregister_device(state
->i2c_sdp
);
2963 i2c_unregister_device(state
->i2c_afe
);
2964 if (state
->i2c_repeater
)
2965 i2c_unregister_device(state
->i2c_repeater
);
2966 if (state
->i2c_edid
)
2967 i2c_unregister_device(state
->i2c_edid
);
2968 if (state
->i2c_hdmi
)
2969 i2c_unregister_device(state
->i2c_hdmi
);
2971 i2c_unregister_device(state
->i2c_cp
);
2973 i2c_unregister_device(state
->i2c_vdp
);
2975 state
->i2c_avlink
= NULL
;
2976 state
->i2c_cec
= NULL
;
2977 state
->i2c_infoframe
= NULL
;
2978 state
->i2c_sdp_io
= NULL
;
2979 state
->i2c_sdp
= NULL
;
2980 state
->i2c_afe
= NULL
;
2981 state
->i2c_repeater
= NULL
;
2982 state
->i2c_edid
= NULL
;
2983 state
->i2c_hdmi
= NULL
;
2984 state
->i2c_cp
= NULL
;
2985 state
->i2c_vdp
= NULL
;
2988 static struct i2c_client
*adv7842_dummy_client(struct v4l2_subdev
*sd
, const char *desc
,
2991 struct i2c_client
*client
= v4l2_get_subdevdata(sd
);
2992 struct i2c_client
*cp
;
2994 io_write(sd
, io_reg
, addr
<< 1);
2997 v4l2_err(sd
, "no %s i2c addr configured\n", desc
);
3001 cp
= i2c_new_dummy(client
->adapter
, io_read(sd
, io_reg
) >> 1);
3003 v4l2_err(sd
, "register %s on i2c addr 0x%x failed\n", desc
, addr
);
3008 static int adv7842_register_clients(struct v4l2_subdev
*sd
)
3010 struct adv7842_state
*state
= to_state(sd
);
3011 struct adv7842_platform_data
*pdata
= &state
->pdata
;
3013 state
->i2c_avlink
= adv7842_dummy_client(sd
, "avlink", pdata
->i2c_avlink
, 0xf3);
3014 state
->i2c_cec
= adv7842_dummy_client(sd
, "cec", pdata
->i2c_cec
, 0xf4);
3015 state
->i2c_infoframe
= adv7842_dummy_client(sd
, "infoframe", pdata
->i2c_infoframe
, 0xf5);
3016 state
->i2c_sdp_io
= adv7842_dummy_client(sd
, "sdp_io", pdata
->i2c_sdp_io
, 0xf2);
3017 state
->i2c_sdp
= adv7842_dummy_client(sd
, "sdp", pdata
->i2c_sdp
, 0xf1);
3018 state
->i2c_afe
= adv7842_dummy_client(sd
, "afe", pdata
->i2c_afe
, 0xf8);
3019 state
->i2c_repeater
= adv7842_dummy_client(sd
, "repeater", pdata
->i2c_repeater
, 0xf9);
3020 state
->i2c_edid
= adv7842_dummy_client(sd
, "edid", pdata
->i2c_edid
, 0xfa);
3021 state
->i2c_hdmi
= adv7842_dummy_client(sd
, "hdmi", pdata
->i2c_hdmi
, 0xfb);
3022 state
->i2c_cp
= adv7842_dummy_client(sd
, "cp", pdata
->i2c_cp
, 0xfd);
3023 state
->i2c_vdp
= adv7842_dummy_client(sd
, "vdp", pdata
->i2c_vdp
, 0xfe);
3025 if (!state
->i2c_avlink
||
3027 !state
->i2c_infoframe
||
3028 !state
->i2c_sdp_io
||
3031 !state
->i2c_repeater
||
3041 static int adv7842_probe(struct i2c_client
*client
,
3042 const struct i2c_device_id
*id
)
3044 struct adv7842_state
*state
;
3045 static const struct v4l2_dv_timings cea640x480
=
3046 V4L2_DV_BT_CEA_640X480P59_94
;
3047 struct adv7842_platform_data
*pdata
= client
->dev
.platform_data
;
3048 struct v4l2_ctrl_handler
*hdl
;
3049 struct v4l2_subdev
*sd
;
3053 /* Check if the adapter supports the needed features */
3054 if (!i2c_check_functionality(client
->adapter
, I2C_FUNC_SMBUS_BYTE_DATA
))
3057 v4l_dbg(1, debug
, client
, "detecting adv7842 client on address 0x%x\n",
3061 v4l_err(client
, "No platform data!\n");
3065 state
= devm_kzalloc(&client
->dev
, sizeof(struct adv7842_state
), GFP_KERNEL
);
3067 v4l_err(client
, "Could not allocate adv7842_state memory!\n");
3072 state
->pdata
= *pdata
;
3073 state
->timings
= cea640x480
;
3076 v4l2_i2c_subdev_init(sd
, client
, &adv7842_ops
);
3077 sd
->flags
|= V4L2_SUBDEV_FL_HAS_DEVNODE
;
3078 state
->mode
= pdata
->mode
;
3080 state
->hdmi_port_a
= pdata
->input
== ADV7842_SELECT_HDMI_PORT_A
;
3081 state
->restart_stdi_once
= true;
3083 /* i2c access to adv7842? */
3084 rev
= adv_smbus_read_byte_data_check(client
, 0xea, false) << 8 |
3085 adv_smbus_read_byte_data_check(client
, 0xeb, false);
3086 if (rev
!= 0x2012) {
3087 v4l2_info(sd
, "got rev=0x%04x on first read attempt\n", rev
);
3088 rev
= adv_smbus_read_byte_data_check(client
, 0xea, false) << 8 |
3089 adv_smbus_read_byte_data_check(client
, 0xeb, false);
3091 if (rev
!= 0x2012) {
3092 v4l2_info(sd
, "not an adv7842 on address 0x%x (rev=0x%04x)\n",
3093 client
->addr
<< 1, rev
);
3097 if (pdata
->chip_reset
)
3100 /* control handlers */
3102 v4l2_ctrl_handler_init(hdl
, 6);
3104 /* add in ascending ID order */
3105 v4l2_ctrl_new_std(hdl
, &adv7842_ctrl_ops
,
3106 V4L2_CID_BRIGHTNESS
, -128, 127, 1, 0);
3107 v4l2_ctrl_new_std(hdl
, &adv7842_ctrl_ops
,
3108 V4L2_CID_CONTRAST
, 0, 255, 1, 128);
3109 v4l2_ctrl_new_std(hdl
, &adv7842_ctrl_ops
,
3110 V4L2_CID_SATURATION
, 0, 255, 1, 128);
3111 v4l2_ctrl_new_std(hdl
, &adv7842_ctrl_ops
,
3112 V4L2_CID_HUE
, 0, 128, 1, 0);
3114 /* custom controls */
3115 state
->detect_tx_5v_ctrl
= v4l2_ctrl_new_std(hdl
, NULL
,
3116 V4L2_CID_DV_RX_POWER_PRESENT
, 0, 3, 0, 0);
3117 state
->analog_sampling_phase_ctrl
= v4l2_ctrl_new_custom(hdl
,
3118 &adv7842_ctrl_analog_sampling_phase
, NULL
);
3119 state
->free_run_color_ctrl_manual
= v4l2_ctrl_new_custom(hdl
,
3120 &adv7842_ctrl_free_run_color_manual
, NULL
);
3121 state
->free_run_color_ctrl
= v4l2_ctrl_new_custom(hdl
,
3122 &adv7842_ctrl_free_run_color
, NULL
);
3123 state
->rgb_quantization_range_ctrl
=
3124 v4l2_ctrl_new_std_menu(hdl
, &adv7842_ctrl_ops
,
3125 V4L2_CID_DV_RX_RGB_RANGE
, V4L2_DV_RGB_RANGE_FULL
,
3126 0, V4L2_DV_RGB_RANGE_AUTO
);
3127 sd
->ctrl_handler
= hdl
;
3132 state
->detect_tx_5v_ctrl
->is_private
= true;
3133 state
->rgb_quantization_range_ctrl
->is_private
= true;
3134 state
->analog_sampling_phase_ctrl
->is_private
= true;
3135 state
->free_run_color_ctrl_manual
->is_private
= true;
3136 state
->free_run_color_ctrl
->is_private
= true;
3138 if (adv7842_s_detect_tx_5v_ctrl(sd
)) {
3143 if (adv7842_register_clients(sd
) < 0) {
3145 v4l2_err(sd
, "failed to create all i2c clients\n");
3150 state
->work_queues
= create_singlethread_workqueue(client
->name
);
3151 if (!state
->work_queues
) {
3152 v4l2_err(sd
, "Could not create work queue\n");
3157 INIT_DELAYED_WORK(&state
->delayed_work_enable_hotplug
,
3158 adv7842_delayed_work_enable_hotplug
);
3160 state
->pad
.flags
= MEDIA_PAD_FL_SOURCE
;
3161 err
= media_entity_init(&sd
->entity
, 1, &state
->pad
, 0);
3163 goto err_work_queues
;
3165 err
= adv7842_core_init(sd
);
3169 v4l2_info(sd
, "%s found @ 0x%x (%s)\n", client
->name
,
3170 client
->addr
<< 1, client
->adapter
->name
);
3174 media_entity_cleanup(&sd
->entity
);
3176 cancel_delayed_work(&state
->delayed_work_enable_hotplug
);
3177 destroy_workqueue(state
->work_queues
);
3179 adv7842_unregister_clients(sd
);
3181 v4l2_ctrl_handler_free(hdl
);
3185 /* ----------------------------------------------------------------------- */
3187 static int adv7842_remove(struct i2c_client
*client
)
3189 struct v4l2_subdev
*sd
= i2c_get_clientdata(client
);
3190 struct adv7842_state
*state
= to_state(sd
);
3192 adv7842_irq_enable(sd
, false);
3194 cancel_delayed_work(&state
->delayed_work_enable_hotplug
);
3195 destroy_workqueue(state
->work_queues
);
3196 v4l2_device_unregister_subdev(sd
);
3197 media_entity_cleanup(&sd
->entity
);
3198 adv7842_unregister_clients(sd
);
3199 v4l2_ctrl_handler_free(sd
->ctrl_handler
);
3203 /* ----------------------------------------------------------------------- */
3205 static struct i2c_device_id adv7842_id
[] = {
3209 MODULE_DEVICE_TABLE(i2c
, adv7842_id
);
3211 /* ----------------------------------------------------------------------- */
3213 static struct i2c_driver adv7842_driver
= {
3215 .owner
= THIS_MODULE
,
3218 .probe
= adv7842_probe
,
3219 .remove
= adv7842_remove
,
3220 .id_table
= adv7842_id
,
3223 module_i2c_driver(adv7842_driver
);