2 * Address map functions for Marvell EBU SoCs (Kirkwood, Armada
3 * 370/XP, Dove, Orion5x and MV78xx0)
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
9 * The Marvell EBU SoCs have a configurable physical address space:
10 * the physical address at which certain devices (PCIe, NOR, NAND,
11 * etc.) sit can be configured. The configuration takes place through
12 * two sets of registers:
14 * - One to configure the access of the CPU to the devices. Depending
15 * on the families, there are between 8 and 20 configurable windows,
16 * each can be use to create a physical memory window that maps to a
17 * specific device. Devices are identified by a tuple (target,
20 * - One to configure the access to the CPU to the SDRAM. There are
21 * either 2 (for Dove) or 4 (for other families) windows to map the
22 * SDRAM into the physical address space.
26 * - Reads out the SDRAM address decoding windows at initialization
27 * time, and fills the mvebu_mbus_dram_info structure with these
28 * informations. The exported function mv_mbus_dram_info() allow
29 * device drivers to get those informations related to the SDRAM
30 * address decoding windows. This is because devices also have their
31 * own windows (configured through registers that are part of each
32 * device register space), and therefore the drivers for Marvell
33 * devices have to configure those device -> SDRAM windows to ensure
34 * that DMA works properly.
36 * - Provides an API for platform code or device drivers to
37 * dynamically add or remove address decoding windows for the CPU ->
38 * device accesses. This API is mvebu_mbus_add_window_by_id(),
39 * mvebu_mbus_add_window_remap_by_id() and
40 * mvebu_mbus_del_window().
42 * - Provides a debugfs interface in /sys/kernel/debug/mvebu-mbus/ to
43 * see the list of CPU -> SDRAM windows and their configuration
44 * (file 'sdram') and the list of CPU -> devices windows and their
45 * configuration (file 'devices').
48 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
50 #include <linux/kernel.h>
51 #include <linux/module.h>
52 #include <linux/init.h>
53 #include <linux/mbus.h>
55 #include <linux/ioport.h>
57 #include <linux/of_address.h>
58 #include <linux/debugfs.h>
59 #include <linux/log2.h>
62 * DDR target is the same on all platforms.
67 * CPU Address Decode Windows registers
69 #define WIN_CTRL_OFF 0x0000
70 #define WIN_CTRL_ENABLE BIT(0)
71 #define WIN_CTRL_TGT_MASK 0xf0
72 #define WIN_CTRL_TGT_SHIFT 4
73 #define WIN_CTRL_ATTR_MASK 0xff00
74 #define WIN_CTRL_ATTR_SHIFT 8
75 #define WIN_CTRL_SIZE_MASK 0xffff0000
76 #define WIN_CTRL_SIZE_SHIFT 16
77 #define WIN_BASE_OFF 0x0004
78 #define WIN_BASE_LOW 0xffff0000
79 #define WIN_BASE_HIGH 0xf
80 #define WIN_REMAP_LO_OFF 0x0008
81 #define WIN_REMAP_LOW 0xffff0000
82 #define WIN_REMAP_HI_OFF 0x000c
84 #define ATTR_HW_COHERENCY (0x1 << 4)
86 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
87 #define DDR_BASE_CS_HIGH_MASK 0xf
88 #define DDR_BASE_CS_LOW_MASK 0xff000000
89 #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
90 #define DDR_SIZE_ENABLED BIT(0)
91 #define DDR_SIZE_CS_MASK 0x1c
92 #define DDR_SIZE_CS_SHIFT 2
93 #define DDR_SIZE_MASK 0xff000000
95 #define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4)
97 struct mvebu_mbus_state
;
99 struct mvebu_mbus_soc_data
{
100 unsigned int num_wins
;
101 unsigned int num_remappable_wins
;
102 unsigned int (*win_cfg_offset
)(const int win
);
103 void (*setup_cpu_target
)(struct mvebu_mbus_state
*s
);
104 int (*show_cpu_target
)(struct mvebu_mbus_state
*s
,
105 struct seq_file
*seq
, void *v
);
108 struct mvebu_mbus_state
{
109 void __iomem
*mbuswins_base
;
110 void __iomem
*sdramwins_base
;
111 struct dentry
*debugfs_root
;
112 struct dentry
*debugfs_sdram
;
113 struct dentry
*debugfs_devs
;
114 struct resource pcie_mem_aperture
;
115 struct resource pcie_io_aperture
;
116 const struct mvebu_mbus_soc_data
*soc
;
120 static struct mvebu_mbus_state mbus_state
;
122 static struct mbus_dram_target_info mvebu_mbus_dram_info
;
123 const struct mbus_dram_target_info
*mv_mbus_dram_info(void)
125 return &mvebu_mbus_dram_info
;
127 EXPORT_SYMBOL_GPL(mv_mbus_dram_info
);
130 * Functions to manipulate the address decoding windows
133 static void mvebu_mbus_read_window(struct mvebu_mbus_state
*mbus
,
134 int win
, int *enabled
, u64
*base
,
135 u32
*size
, u8
*target
, u8
*attr
,
138 void __iomem
*addr
= mbus
->mbuswins_base
+
139 mbus
->soc
->win_cfg_offset(win
);
140 u32 basereg
= readl(addr
+ WIN_BASE_OFF
);
141 u32 ctrlreg
= readl(addr
+ WIN_CTRL_OFF
);
143 if (!(ctrlreg
& WIN_CTRL_ENABLE
)) {
149 *base
= ((u64
)basereg
& WIN_BASE_HIGH
) << 32;
150 *base
|= (basereg
& WIN_BASE_LOW
);
151 *size
= (ctrlreg
| ~WIN_CTRL_SIZE_MASK
) + 1;
154 *target
= (ctrlreg
& WIN_CTRL_TGT_MASK
) >> WIN_CTRL_TGT_SHIFT
;
157 *attr
= (ctrlreg
& WIN_CTRL_ATTR_MASK
) >> WIN_CTRL_ATTR_SHIFT
;
160 if (win
< mbus
->soc
->num_remappable_wins
) {
161 u32 remap_low
= readl(addr
+ WIN_REMAP_LO_OFF
);
162 u32 remap_hi
= readl(addr
+ WIN_REMAP_HI_OFF
);
163 *remap
= ((u64
)remap_hi
<< 32) | remap_low
;
169 static void mvebu_mbus_disable_window(struct mvebu_mbus_state
*mbus
,
174 addr
= mbus
->mbuswins_base
+ mbus
->soc
->win_cfg_offset(win
);
176 writel(0, addr
+ WIN_BASE_OFF
);
177 writel(0, addr
+ WIN_CTRL_OFF
);
178 if (win
< mbus
->soc
->num_remappable_wins
) {
179 writel(0, addr
+ WIN_REMAP_LO_OFF
);
180 writel(0, addr
+ WIN_REMAP_HI_OFF
);
184 /* Checks whether the given window number is available */
185 static int mvebu_mbus_window_is_free(struct mvebu_mbus_state
*mbus
,
188 void __iomem
*addr
= mbus
->mbuswins_base
+
189 mbus
->soc
->win_cfg_offset(win
);
190 u32 ctrl
= readl(addr
+ WIN_CTRL_OFF
);
191 return !(ctrl
& WIN_CTRL_ENABLE
);
195 * Checks whether the given (base, base+size) area doesn't overlap an
198 static int mvebu_mbus_window_conflicts(struct mvebu_mbus_state
*mbus
,
199 phys_addr_t base
, size_t size
,
202 u64 end
= (u64
)base
+ size
;
205 for (win
= 0; win
< mbus
->soc
->num_wins
; win
++) {
211 mvebu_mbus_read_window(mbus
, win
,
212 &enabled
, &wbase
, &wsize
,
213 &wtarget
, &wattr
, NULL
);
218 wend
= wbase
+ wsize
;
221 * Check if the current window overlaps with the
222 * proposed physical range
224 if ((u64
)base
< wend
&& end
> wbase
)
231 static int mvebu_mbus_find_window(struct mvebu_mbus_state
*mbus
,
232 phys_addr_t base
, size_t size
)
236 for (win
= 0; win
< mbus
->soc
->num_wins
; win
++) {
241 mvebu_mbus_read_window(mbus
, win
,
242 &enabled
, &wbase
, &wsize
,
248 if (base
== wbase
&& size
== wsize
)
255 static int mvebu_mbus_setup_window(struct mvebu_mbus_state
*mbus
,
256 int win
, phys_addr_t base
, size_t size
,
257 phys_addr_t remap
, u8 target
,
260 void __iomem
*addr
= mbus
->mbuswins_base
+
261 mbus
->soc
->win_cfg_offset(win
);
262 u32 ctrl
, remap_addr
;
264 if (!is_power_of_2(size
)) {
265 WARN(true, "Invalid MBus window size: 0x%zx\n", size
);
269 if ((base
& (phys_addr_t
)(size
- 1)) != 0) {
270 WARN(true, "Invalid MBus base/size: %pa len 0x%zx\n", &base
,
275 ctrl
= ((size
- 1) & WIN_CTRL_SIZE_MASK
) |
276 (attr
<< WIN_CTRL_ATTR_SHIFT
) |
277 (target
<< WIN_CTRL_TGT_SHIFT
) |
280 writel(base
& WIN_BASE_LOW
, addr
+ WIN_BASE_OFF
);
281 writel(ctrl
, addr
+ WIN_CTRL_OFF
);
282 if (win
< mbus
->soc
->num_remappable_wins
) {
283 if (remap
== MVEBU_MBUS_NO_REMAP
)
287 writel(remap_addr
& WIN_REMAP_LOW
, addr
+ WIN_REMAP_LO_OFF
);
288 writel(0, addr
+ WIN_REMAP_HI_OFF
);
294 static int mvebu_mbus_alloc_window(struct mvebu_mbus_state
*mbus
,
295 phys_addr_t base
, size_t size
,
296 phys_addr_t remap
, u8 target
,
301 if (remap
== MVEBU_MBUS_NO_REMAP
) {
302 for (win
= mbus
->soc
->num_remappable_wins
;
303 win
< mbus
->soc
->num_wins
; win
++)
304 if (mvebu_mbus_window_is_free(mbus
, win
))
305 return mvebu_mbus_setup_window(mbus
, win
, base
,
311 for (win
= 0; win
< mbus
->soc
->num_wins
; win
++)
312 if (mvebu_mbus_window_is_free(mbus
, win
))
313 return mvebu_mbus_setup_window(mbus
, win
, base
, size
,
314 remap
, target
, attr
);
323 /* Common function used for Dove, Kirkwood, Armada 370/XP and Orion 5x */
324 static int mvebu_sdram_debug_show_orion(struct mvebu_mbus_state
*mbus
,
325 struct seq_file
*seq
, void *v
)
329 for (i
= 0; i
< 4; i
++) {
330 u32 basereg
= readl(mbus
->sdramwins_base
+ DDR_BASE_CS_OFF(i
));
331 u32 sizereg
= readl(mbus
->sdramwins_base
+ DDR_SIZE_CS_OFF(i
));
335 if (!(sizereg
& DDR_SIZE_ENABLED
)) {
336 seq_printf(seq
, "[%d] disabled\n", i
);
340 base
= ((u64
)basereg
& DDR_BASE_CS_HIGH_MASK
) << 32;
341 base
|= basereg
& DDR_BASE_CS_LOW_MASK
;
342 size
= (sizereg
| ~DDR_SIZE_MASK
);
344 seq_printf(seq
, "[%d] %016llx - %016llx : cs%d\n",
345 i
, (unsigned long long)base
,
346 (unsigned long long)base
+ size
+ 1,
347 (sizereg
& DDR_SIZE_CS_MASK
) >> DDR_SIZE_CS_SHIFT
);
353 /* Special function for Dove */
354 static int mvebu_sdram_debug_show_dove(struct mvebu_mbus_state
*mbus
,
355 struct seq_file
*seq
, void *v
)
359 for (i
= 0; i
< 2; i
++) {
360 u32 map
= readl(mbus
->sdramwins_base
+ DOVE_DDR_BASE_CS_OFF(i
));
365 seq_printf(seq
, "[%d] disabled\n", i
);
369 base
= map
& 0xff800000;
370 size
= 0x100000 << (((map
& 0x000f0000) >> 16) - 4);
372 seq_printf(seq
, "[%d] %016llx - %016llx : cs%d\n",
373 i
, (unsigned long long)base
,
374 (unsigned long long)base
+ size
, i
);
380 static int mvebu_sdram_debug_show(struct seq_file
*seq
, void *v
)
382 struct mvebu_mbus_state
*mbus
= &mbus_state
;
383 return mbus
->soc
->show_cpu_target(mbus
, seq
, v
);
386 static int mvebu_sdram_debug_open(struct inode
*inode
, struct file
*file
)
388 return single_open(file
, mvebu_sdram_debug_show
, inode
->i_private
);
391 static const struct file_operations mvebu_sdram_debug_fops
= {
392 .open
= mvebu_sdram_debug_open
,
395 .release
= single_release
,
398 static int mvebu_devs_debug_show(struct seq_file
*seq
, void *v
)
400 struct mvebu_mbus_state
*mbus
= &mbus_state
;
403 for (win
= 0; win
< mbus
->soc
->num_wins
; win
++) {
409 mvebu_mbus_read_window(mbus
, win
,
410 &enabled
, &wbase
, &wsize
,
411 &wtarget
, &wattr
, &wremap
);
414 seq_printf(seq
, "[%02d] disabled\n", win
);
418 seq_printf(seq
, "[%02d] %016llx - %016llx : %04x:%04x",
419 win
, (unsigned long long)wbase
,
420 (unsigned long long)(wbase
+ wsize
), wtarget
, wattr
);
422 if (!is_power_of_2(wsize
) ||
423 ((wbase
& (u64
)(wsize
- 1)) != 0))
424 seq_puts(seq
, " (Invalid base/size!!)");
426 if (win
< mbus
->soc
->num_remappable_wins
) {
427 seq_printf(seq
, " (remap %016llx)\n",
428 (unsigned long long)wremap
);
430 seq_printf(seq
, "\n");
436 static int mvebu_devs_debug_open(struct inode
*inode
, struct file
*file
)
438 return single_open(file
, mvebu_devs_debug_show
, inode
->i_private
);
441 static const struct file_operations mvebu_devs_debug_fops
= {
442 .open
= mvebu_devs_debug_open
,
445 .release
= single_release
,
449 * SoC-specific functions and definitions
452 static unsigned int orion_mbus_win_offset(int win
)
457 static unsigned int armada_370_xp_mbus_win_offset(int win
)
459 /* The register layout is a bit annoying and the below code
460 * tries to cope with it.
461 * - At offset 0x0, there are the registers for the first 8
462 * windows, with 4 registers of 32 bits per window (ctrl,
463 * base, remap low, remap high)
464 * - Then at offset 0x80, there is a hole of 0x10 bytes for
465 * the internal registers base address and internal units
466 * sync barrier register.
467 * - Then at offset 0x90, there the registers for 12
468 * windows, with only 2 registers of 32 bits per window
474 return 0x90 + ((win
- 8) << 3);
477 static unsigned int mv78xx0_mbus_win_offset(int win
)
482 return 0x900 + ((win
- 8) << 4);
486 mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state
*mbus
)
491 mvebu_mbus_dram_info
.mbus_dram_target_id
= TARGET_DDR
;
493 for (i
= 0, cs
= 0; i
< 4; i
++) {
494 u32 base
= readl(mbus
->sdramwins_base
+ DDR_BASE_CS_OFF(i
));
495 u32 size
= readl(mbus
->sdramwins_base
+ DDR_SIZE_CS_OFF(i
));
498 * We only take care of entries for which the chip
499 * select is enabled, and that don't have high base
500 * address bits set (devices can only access the first
501 * 32 bits of the memory).
503 if ((size
& DDR_SIZE_ENABLED
) &&
504 !(base
& DDR_BASE_CS_HIGH_MASK
)) {
505 struct mbus_dram_window
*w
;
507 w
= &mvebu_mbus_dram_info
.cs
[cs
++];
509 w
->mbus_attr
= 0xf & ~(1 << i
);
510 if (mbus
->hw_io_coherency
)
511 w
->mbus_attr
|= ATTR_HW_COHERENCY
;
512 w
->base
= base
& DDR_BASE_CS_LOW_MASK
;
513 w
->size
= (size
| ~DDR_SIZE_MASK
) + 1;
516 mvebu_mbus_dram_info
.num_cs
= cs
;
520 mvebu_mbus_dove_setup_cpu_target(struct mvebu_mbus_state
*mbus
)
525 mvebu_mbus_dram_info
.mbus_dram_target_id
= TARGET_DDR
;
527 for (i
= 0, cs
= 0; i
< 2; i
++) {
528 u32 map
= readl(mbus
->sdramwins_base
+ DOVE_DDR_BASE_CS_OFF(i
));
531 * Chip select enabled?
534 struct mbus_dram_window
*w
;
536 w
= &mvebu_mbus_dram_info
.cs
[cs
++];
538 w
->mbus_attr
= 0; /* CS address decoding done inside */
539 /* the DDR controller, no need to */
540 /* provide attributes */
541 w
->base
= map
& 0xff800000;
542 w
->size
= 0x100000 << (((map
& 0x000f0000) >> 16) - 4);
546 mvebu_mbus_dram_info
.num_cs
= cs
;
549 static const struct mvebu_mbus_soc_data armada_370_xp_mbus_data
= {
551 .num_remappable_wins
= 8,
552 .win_cfg_offset
= armada_370_xp_mbus_win_offset
,
553 .setup_cpu_target
= mvebu_mbus_default_setup_cpu_target
,
554 .show_cpu_target
= mvebu_sdram_debug_show_orion
,
557 static const struct mvebu_mbus_soc_data kirkwood_mbus_data
= {
559 .num_remappable_wins
= 4,
560 .win_cfg_offset
= orion_mbus_win_offset
,
561 .setup_cpu_target
= mvebu_mbus_default_setup_cpu_target
,
562 .show_cpu_target
= mvebu_sdram_debug_show_orion
,
565 static const struct mvebu_mbus_soc_data dove_mbus_data
= {
567 .num_remappable_wins
= 4,
568 .win_cfg_offset
= orion_mbus_win_offset
,
569 .setup_cpu_target
= mvebu_mbus_dove_setup_cpu_target
,
570 .show_cpu_target
= mvebu_sdram_debug_show_dove
,
574 * Some variants of Orion5x have 4 remappable windows, some other have
577 static const struct mvebu_mbus_soc_data orion5x_4win_mbus_data
= {
579 .num_remappable_wins
= 4,
580 .win_cfg_offset
= orion_mbus_win_offset
,
581 .setup_cpu_target
= mvebu_mbus_default_setup_cpu_target
,
582 .show_cpu_target
= mvebu_sdram_debug_show_orion
,
585 static const struct mvebu_mbus_soc_data orion5x_2win_mbus_data
= {
587 .num_remappable_wins
= 2,
588 .win_cfg_offset
= orion_mbus_win_offset
,
589 .setup_cpu_target
= mvebu_mbus_default_setup_cpu_target
,
590 .show_cpu_target
= mvebu_sdram_debug_show_orion
,
593 static const struct mvebu_mbus_soc_data mv78xx0_mbus_data
= {
595 .num_remappable_wins
= 8,
596 .win_cfg_offset
= mv78xx0_mbus_win_offset
,
597 .setup_cpu_target
= mvebu_mbus_default_setup_cpu_target
,
598 .show_cpu_target
= mvebu_sdram_debug_show_orion
,
601 static const struct of_device_id of_mvebu_mbus_ids
[] = {
602 { .compatible
= "marvell,armada370-mbus",
603 .data
= &armada_370_xp_mbus_data
, },
604 { .compatible
= "marvell,armadaxp-mbus",
605 .data
= &armada_370_xp_mbus_data
, },
606 { .compatible
= "marvell,kirkwood-mbus",
607 .data
= &kirkwood_mbus_data
, },
608 { .compatible
= "marvell,dove-mbus",
609 .data
= &dove_mbus_data
, },
610 { .compatible
= "marvell,orion5x-88f5281-mbus",
611 .data
= &orion5x_4win_mbus_data
, },
612 { .compatible
= "marvell,orion5x-88f5182-mbus",
613 .data
= &orion5x_2win_mbus_data
, },
614 { .compatible
= "marvell,orion5x-88f5181-mbus",
615 .data
= &orion5x_2win_mbus_data
, },
616 { .compatible
= "marvell,orion5x-88f6183-mbus",
617 .data
= &orion5x_4win_mbus_data
, },
618 { .compatible
= "marvell,mv78xx0-mbus",
619 .data
= &mv78xx0_mbus_data
, },
624 * Public API of the driver
626 int mvebu_mbus_add_window_remap_by_id(unsigned int target
,
627 unsigned int attribute
,
628 phys_addr_t base
, size_t size
,
631 struct mvebu_mbus_state
*s
= &mbus_state
;
633 if (!mvebu_mbus_window_conflicts(s
, base
, size
, target
, attribute
)) {
634 pr_err("cannot add window '%x:%x', conflicts with another window\n",
639 return mvebu_mbus_alloc_window(s
, base
, size
, remap
, target
, attribute
);
642 int mvebu_mbus_add_window_by_id(unsigned int target
, unsigned int attribute
,
643 phys_addr_t base
, size_t size
)
645 return mvebu_mbus_add_window_remap_by_id(target
, attribute
, base
,
646 size
, MVEBU_MBUS_NO_REMAP
);
649 int mvebu_mbus_del_window(phys_addr_t base
, size_t size
)
653 win
= mvebu_mbus_find_window(&mbus_state
, base
, size
);
657 mvebu_mbus_disable_window(&mbus_state
, win
);
661 void mvebu_mbus_get_pcie_mem_aperture(struct resource
*res
)
665 *res
= mbus_state
.pcie_mem_aperture
;
668 void mvebu_mbus_get_pcie_io_aperture(struct resource
*res
)
672 *res
= mbus_state
.pcie_io_aperture
;
675 static __init
int mvebu_mbus_debugfs_init(void)
677 struct mvebu_mbus_state
*s
= &mbus_state
;
680 * If no base has been initialized, doesn't make sense to
681 * register the debugfs entries. We may be on a multiplatform
682 * kernel that isn't running a Marvell EBU SoC.
684 if (!s
->mbuswins_base
)
687 s
->debugfs_root
= debugfs_create_dir("mvebu-mbus", NULL
);
688 if (s
->debugfs_root
) {
689 s
->debugfs_sdram
= debugfs_create_file("sdram", S_IRUGO
,
690 s
->debugfs_root
, NULL
,
691 &mvebu_sdram_debug_fops
);
692 s
->debugfs_devs
= debugfs_create_file("devices", S_IRUGO
,
693 s
->debugfs_root
, NULL
,
694 &mvebu_devs_debug_fops
);
699 fs_initcall(mvebu_mbus_debugfs_init
);
701 static int __init
mvebu_mbus_common_init(struct mvebu_mbus_state
*mbus
,
702 phys_addr_t mbuswins_phys_base
,
703 size_t mbuswins_size
,
704 phys_addr_t sdramwins_phys_base
,
705 size_t sdramwins_size
)
709 mbus
->mbuswins_base
= ioremap(mbuswins_phys_base
, mbuswins_size
);
710 if (!mbus
->mbuswins_base
)
713 mbus
->sdramwins_base
= ioremap(sdramwins_phys_base
, sdramwins_size
);
714 if (!mbus
->sdramwins_base
) {
715 iounmap(mbus_state
.mbuswins_base
);
719 for (win
= 0; win
< mbus
->soc
->num_wins
; win
++)
720 mvebu_mbus_disable_window(mbus
, win
);
722 mbus
->soc
->setup_cpu_target(mbus
);
727 int __init
mvebu_mbus_init(const char *soc
, phys_addr_t mbuswins_phys_base
,
728 size_t mbuswins_size
,
729 phys_addr_t sdramwins_phys_base
,
730 size_t sdramwins_size
)
732 const struct of_device_id
*of_id
;
734 for (of_id
= of_mvebu_mbus_ids
; of_id
->compatible
[0]; of_id
++)
735 if (!strcmp(of_id
->compatible
, soc
))
738 if (!of_id
->compatible
[0]) {
739 pr_err("could not find a matching SoC family\n");
743 mbus_state
.soc
= of_id
->data
;
745 return mvebu_mbus_common_init(&mbus_state
,
754 * The window IDs in the ranges DT property have the following format:
755 * - bits 28 to 31: MBus custom field
756 * - bits 24 to 27: window target ID
757 * - bits 16 to 23: window attribute ID
758 * - bits 0 to 15: unused
760 #define CUSTOM(id) (((id) & 0xF0000000) >> 24)
761 #define TARGET(id) (((id) & 0x0F000000) >> 24)
762 #define ATTR(id) (((id) & 0x00FF0000) >> 16)
764 static int __init
mbus_dt_setup_win(struct mvebu_mbus_state
*mbus
,
768 if (!mvebu_mbus_window_conflicts(mbus
, base
, size
, target
, attr
)) {
769 pr_err("cannot add window '%04x:%04x', conflicts with another window\n",
774 if (mvebu_mbus_alloc_window(mbus
, base
, size
, MVEBU_MBUS_NO_REMAP
,
776 pr_err("cannot add window '%04x:%04x', too many windows\n",
784 mbus_parse_ranges(struct device_node
*node
,
785 int *addr_cells
, int *c_addr_cells
, int *c_size_cells
,
786 int *cell_count
, const __be32
**ranges_start
,
787 const __be32
**ranges_end
)
790 int ranges_len
, tuple_len
;
792 /* Allow a node with no 'ranges' property */
793 *ranges_start
= of_get_property(node
, "ranges", &ranges_len
);
794 if (*ranges_start
== NULL
) {
795 *addr_cells
= *c_addr_cells
= *c_size_cells
= *cell_count
= 0;
796 *ranges_start
= *ranges_end
= NULL
;
799 *ranges_end
= *ranges_start
+ ranges_len
/ sizeof(__be32
);
801 *addr_cells
= of_n_addr_cells(node
);
803 prop
= of_get_property(node
, "#address-cells", NULL
);
804 *c_addr_cells
= be32_to_cpup(prop
);
806 prop
= of_get_property(node
, "#size-cells", NULL
);
807 *c_size_cells
= be32_to_cpup(prop
);
809 *cell_count
= *addr_cells
+ *c_addr_cells
+ *c_size_cells
;
810 tuple_len
= (*cell_count
) * sizeof(__be32
);
812 if (ranges_len
% tuple_len
) {
813 pr_warn("malformed ranges entry '%s'\n", node
->name
);
819 static int __init
mbus_dt_setup(struct mvebu_mbus_state
*mbus
,
820 struct device_node
*np
)
822 int addr_cells
, c_addr_cells
, c_size_cells
;
823 int i
, ret
, cell_count
;
824 const __be32
*r
, *ranges_start
, *ranges_end
;
826 ret
= mbus_parse_ranges(np
, &addr_cells
, &c_addr_cells
,
827 &c_size_cells
, &cell_count
,
828 &ranges_start
, &ranges_end
);
832 for (i
= 0, r
= ranges_start
; r
< ranges_end
; r
+= cell_count
, i
++) {
833 u32 windowid
, base
, size
;
837 * An entry with a non-zero custom field do not
838 * correspond to a static window, so skip it.
840 windowid
= of_read_number(r
, 1);
841 if (CUSTOM(windowid
))
844 target
= TARGET(windowid
);
845 attr
= ATTR(windowid
);
847 base
= of_read_number(r
+ c_addr_cells
, addr_cells
);
848 size
= of_read_number(r
+ c_addr_cells
+ addr_cells
,
850 ret
= mbus_dt_setup_win(mbus
, base
, size
, target
, attr
);
857 static void __init
mvebu_mbus_get_pcie_resources(struct device_node
*np
,
858 struct resource
*mem
,
865 * These are optional, so we make sure that resource_size(x) will
868 memset(mem
, 0, sizeof(struct resource
));
870 memset(io
, 0, sizeof(struct resource
));
873 ret
= of_property_read_u32_array(np
, "pcie-mem-aperture", reg
, ARRAY_SIZE(reg
));
876 mem
->end
= mem
->start
+ reg
[1] - 1;
877 mem
->flags
= IORESOURCE_MEM
;
880 ret
= of_property_read_u32_array(np
, "pcie-io-aperture", reg
, ARRAY_SIZE(reg
));
883 io
->end
= io
->start
+ reg
[1] - 1;
884 io
->flags
= IORESOURCE_IO
;
888 int __init
mvebu_mbus_dt_init(bool is_coherent
)
890 struct resource mbuswins_res
, sdramwins_res
;
891 struct device_node
*np
, *controller
;
892 const struct of_device_id
*of_id
;
896 np
= of_find_matching_node_and_match(NULL
, of_mvebu_mbus_ids
, &of_id
);
898 pr_err("could not find a matching SoC family\n");
902 mbus_state
.soc
= of_id
->data
;
904 prop
= of_get_property(np
, "controller", NULL
);
906 pr_err("required 'controller' property missing\n");
910 controller
= of_find_node_by_phandle(be32_to_cpup(prop
));
912 pr_err("could not find an 'mbus-controller' node\n");
916 if (of_address_to_resource(controller
, 0, &mbuswins_res
)) {
917 pr_err("cannot get MBUS register address\n");
921 if (of_address_to_resource(controller
, 1, &sdramwins_res
)) {
922 pr_err("cannot get SDRAM register address\n");
926 mbus_state
.hw_io_coherency
= is_coherent
;
928 /* Get optional pcie-{mem,io}-aperture properties */
929 mvebu_mbus_get_pcie_resources(np
, &mbus_state
.pcie_mem_aperture
,
930 &mbus_state
.pcie_io_aperture
);
932 ret
= mvebu_mbus_common_init(&mbus_state
,
934 resource_size(&mbuswins_res
),
936 resource_size(&sdramwins_res
));
940 /* Setup statically declared windows in the DT */
941 return mbus_dt_setup(&mbus_state
, np
);