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[WAN]: Converted synclink drivers to use netif_carrier_*()
[linux-2.6/linux-mips.git] / drivers / char / synclink.c
blob78b1b1a2732b3e9216556c3caa2b77354a0457d6
1 /*
2 * linux/drivers/char/synclink.c
3 *
4 * $Id: synclink.c,v 4.38 2005/11/07 16:30:34 paulkf Exp $
5 *
6 * Device driver for Microgate SyncLink ISA and PCI
7 * high speed multiprotocol serial adapters.
8 *
9 * written by Paul Fulghum for Microgate Corporation
10 * paulkf@microgate.com
11 *
12 * Microgate and SyncLink are trademarks of Microgate Corporation
13 *
14 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
15 *
16 * Original release 01/11/99
17 *
18 * This code is released under the GNU General Public License (GPL)
19 *
20 * This driver is primarily intended for use in synchronous
21 * HDLC mode. Asynchronous mode is also provided.
22 *
23 * When operating in synchronous mode, each call to mgsl_write()
24 * contains exactly one complete HDLC frame. Calling mgsl_put_char
25 * will start assembling an HDLC frame that will not be sent until
26 * mgsl_flush_chars or mgsl_write is called.
27 *
28 * Synchronous receive data is reported as complete frames. To accomplish
29 * this, the TTY flip buffer is bypassed (too small to hold largest
30 * frame and may fragment frames) and the line discipline
31 * receive entry point is called directly.
32 *
33 * This driver has been tested with a slightly modified ppp.c driver
34 * for synchronous PPP.
35 *
36 * 2000/02/16
37 * Added interface for syncppp.c driver (an alternate synchronous PPP
38 * implementation that also supports Cisco HDLC). Each device instance
39 * registers as a tty device AND a network device (if dosyncppp option
40 * is set for the device). The functionality is determined by which
41 * device interface is opened.
42 *
43 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
44 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
45 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
46 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
47 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
48 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
49 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
50 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
51 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
53 * OF THE POSSIBILITY OF SUCH DAMAGE.
54 */
55
56 #if defined(__i386__)
57 # define BREAKPOINT() asm(" int $3");
58 #else
59 # define BREAKPOINT() { }
60 #endif
61
62 #define MAX_ISA_DEVICES 10
63 #define MAX_PCI_DEVICES 10
64 #define MAX_TOTAL_DEVICES 20
65
66 #include <linux/config.h>
67 #include <linux/module.h>
68 #include <linux/errno.h>
69 #include <linux/signal.h>
70 #include <linux/sched.h>
71 #include <linux/timer.h>
72 #include <linux/interrupt.h>
73 #include <linux/pci.h>
74 #include <linux/tty.h>
75 #include <linux/tty_flip.h>
76 #include <linux/serial.h>
77 #include <linux/major.h>
78 #include <linux/string.h>
79 #include <linux/fcntl.h>
80 #include <linux/ptrace.h>
81 #include <linux/ioport.h>
82 #include <linux/mm.h>
83 #include <linux/slab.h>
84 #include <linux/delay.h>
85
86 #include <linux/netdevice.h>
87
88 #include <linux/vmalloc.h>
89 #include <linux/init.h>
90 #include <asm/serial.h>
91
92 #include <linux/delay.h>
93 #include <linux/ioctl.h>
94
95 #include <asm/system.h>
96 #include <asm/io.h>
97 #include <asm/irq.h>
98 #include <asm/dma.h>
99 #include <linux/bitops.h>
100 #include <asm/types.h>
101 #include <linux/termios.h>
102 #include <linux/workqueue.h>
103 #include <linux/hdlc.h>
104 #include <linux/dma-mapping.h>
105
106 #ifdef CONFIG_HDLC_MODULE
107 #define CONFIG_HDLC 1
108 #endif
109
110 #define GET_USER(error,value,addr) error = get_user(value,addr)
111 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
112 #define PUT_USER(error,value,addr) error = put_user(value,addr)
113 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
114
115 #include <asm/uaccess.h>
116
117 #include "linux/synclink.h"
118
119 #define RCLRVALUE 0xffff
120
121 static MGSL_PARAMS default_params = {
122 MGSL_MODE_HDLC, /* unsigned long mode */
123 0, /* unsigned char loopback; */
124 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
125 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
126 0, /* unsigned long clock_speed; */
127 0xff, /* unsigned char addr_filter; */
128 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
129 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
130 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
131 9600, /* unsigned long data_rate; */
132 8, /* unsigned char data_bits; */
133 1, /* unsigned char stop_bits; */
134 ASYNC_PARITY_NONE /* unsigned char parity; */
135 };
136
137 #define SHARED_MEM_ADDRESS_SIZE 0x40000
138 #define BUFFERLISTSIZE (PAGE_SIZE)
139 #define DMABUFFERSIZE (PAGE_SIZE)
140 #define MAXRXFRAMES 7
141
142 typedef struct _DMABUFFERENTRY
143 {
144 u32 phys_addr; /* 32-bit flat physical address of data buffer */
145 volatile u16 count; /* buffer size/data count */
146 volatile u16 status; /* Control/status field */
147 volatile u16 rcc; /* character count field */
148 u16 reserved; /* padding required by 16C32 */
149 u32 link; /* 32-bit flat link to next buffer entry */
150 char *virt_addr; /* virtual address of data buffer */
151 u32 phys_entry; /* physical address of this buffer entry */
152 dma_addr_t dma_addr;
153 } DMABUFFERENTRY, *DMAPBUFFERENTRY;
154
155 /* The queue of BH actions to be performed */
156
157 #define BH_RECEIVE 1
158 #define BH_TRANSMIT 2
159 #define BH_STATUS 4
160
161 #define IO_PIN_SHUTDOWN_LIMIT 100
162
163 #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
164
165 struct _input_signal_events {
166 int ri_up;
167 int ri_down;
168 int dsr_up;
169 int dsr_down;
170 int dcd_up;
171 int dcd_down;
172 int cts_up;
173 int cts_down;
174 };
175
176 /* transmit holding buffer definitions*/
177 #define MAX_TX_HOLDING_BUFFERS 5
178 struct tx_holding_buffer {
179 int buffer_size;
180 unsigned char * buffer;
181 };
182
183
184 /*
185 * Device instance data structure
186 */
187
188 struct mgsl_struct {
189 int magic;
190 int flags;
191 int count; /* count of opens */
192 int line;
193 int hw_version;
194 unsigned short close_delay;
195 unsigned short closing_wait; /* time to wait before closing */
196
197 struct mgsl_icount icount;
198
199 struct tty_struct *tty;
200 int timeout;
201 int x_char; /* xon/xoff character */
202 int blocked_open; /* # of blocked opens */
203 u16 read_status_mask;
204 u16 ignore_status_mask;
205 unsigned char *xmit_buf;
206 int xmit_head;
207 int xmit_tail;
208 int xmit_cnt;
209
210 wait_queue_head_t open_wait;
211 wait_queue_head_t close_wait;
212
213 wait_queue_head_t status_event_wait_q;
214 wait_queue_head_t event_wait_q;
215 struct timer_list tx_timer; /* HDLC transmit timeout timer */
216 struct mgsl_struct *next_device; /* device list link */
217
218 spinlock_t irq_spinlock; /* spinlock for synchronizing with ISR */
219 struct work_struct task; /* task structure for scheduling bh */
220
221 u32 EventMask; /* event trigger mask */
222 u32 RecordedEvents; /* pending events */
223
224 u32 max_frame_size; /* as set by device config */
225
226 u32 pending_bh;
227
228 int bh_running; /* Protection from multiple */
229 int isr_overflow;
230 int bh_requested;
231
232 int dcd_chkcount; /* check counts to prevent */
233 int cts_chkcount; /* too many IRQs if a signal */
234 int dsr_chkcount; /* is floating */
235 int ri_chkcount;
236
237 char *buffer_list; /* virtual address of Rx & Tx buffer lists */
238 u32 buffer_list_phys;
239 dma_addr_t buffer_list_dma_addr;
240
241 unsigned int rx_buffer_count; /* count of total allocated Rx buffers */
242 DMABUFFERENTRY *rx_buffer_list; /* list of receive buffer entries */
243 unsigned int current_rx_buffer;
244
245 int num_tx_dma_buffers; /* number of tx dma frames required */
246 int tx_dma_buffers_used;
247 unsigned int tx_buffer_count; /* count of total allocated Tx buffers */
248 DMABUFFERENTRY *tx_buffer_list; /* list of transmit buffer entries */
249 int start_tx_dma_buffer; /* tx dma buffer to start tx dma operation */
250 int current_tx_buffer; /* next tx dma buffer to be loaded */
251
252 unsigned char *intermediate_rxbuffer;
253
254 int num_tx_holding_buffers; /* number of tx holding buffer allocated */
255 int get_tx_holding_index; /* next tx holding buffer for adapter to load */
256 int put_tx_holding_index; /* next tx holding buffer to store user request */
257 int tx_holding_count; /* number of tx holding buffers waiting */
258 struct tx_holding_buffer tx_holding_buffers[MAX_TX_HOLDING_BUFFERS];
259
260 int rx_enabled;
261 int rx_overflow;
262 int rx_rcc_underrun;
263
264 int tx_enabled;
265 int tx_active;
266 u32 idle_mode;
267
268 u16 cmr_value;
269 u16 tcsr_value;
270
271 char device_name[25]; /* device instance name */
272
273 unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
274 unsigned char bus; /* expansion bus number (zero based) */
275 unsigned char function; /* PCI device number */
276
277 unsigned int io_base; /* base I/O address of adapter */
278 unsigned int io_addr_size; /* size of the I/O address range */
279 int io_addr_requested; /* nonzero if I/O address requested */
280
281 unsigned int irq_level; /* interrupt level */
282 unsigned long irq_flags;
283 int irq_requested; /* nonzero if IRQ requested */
284
285 unsigned int dma_level; /* DMA channel */
286 int dma_requested; /* nonzero if dma channel requested */
287
288 u16 mbre_bit;
289 u16 loopback_bits;
290 u16 usc_idle_mode;
291
292 MGSL_PARAMS params; /* communications parameters */
293
294 unsigned char serial_signals; /* current serial signal states */
295
296 int irq_occurred; /* for diagnostics use */
297 unsigned int init_error; /* Initialization startup error (DIAGS) */
298 int fDiagnosticsmode; /* Driver in Diagnostic mode? (DIAGS) */
299
300 u32 last_mem_alloc;
301 unsigned char* memory_base; /* shared memory address (PCI only) */
302 u32 phys_memory_base;
303 int shared_mem_requested;
304
305 unsigned char* lcr_base; /* local config registers (PCI only) */
306 u32 phys_lcr_base;
307 u32 lcr_offset;
308 int lcr_mem_requested;
309
310 u32 misc_ctrl_value;
311 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
312 char char_buf[MAX_ASYNC_BUFFER_SIZE];
313 BOOLEAN drop_rts_on_tx_done;
314
315 BOOLEAN loopmode_insert_requested;
316 BOOLEAN loopmode_send_done_requested;
317
318 struct _input_signal_events input_signal_events;
319
320 /* generic HDLC device parts */
321 int netcount;
322 int dosyncppp;
323 spinlock_t netlock;
324
325 #ifdef CONFIG_HDLC
326 struct net_device *netdev;
327 #endif
328 };
329
330 #define MGSL_MAGIC 0x5401
331
332 /*
333 * The size of the serial xmit buffer is 1 page, or 4096 bytes
334 */
335 #ifndef SERIAL_XMIT_SIZE
336 #define SERIAL_XMIT_SIZE 4096
337 #endif
338
339 /*
340 * These macros define the offsets used in calculating the
341 * I/O address of the specified USC registers.
342 */
343
344
345 #define DCPIN 2 /* Bit 1 of I/O address */
346 #define SDPIN 4 /* Bit 2 of I/O address */
347
348 #define DCAR 0 /* DMA command/address register */
349 #define CCAR SDPIN /* channel command/address register */
350 #define DATAREG DCPIN + SDPIN /* serial data register */
351 #define MSBONLY 0x41
352 #define LSBONLY 0x40
353
354 /*
355 * These macros define the register address (ordinal number)
356 * used for writing address/value pairs to the USC.
357 */
358
359 #define CMR 0x02 /* Channel mode Register */
360 #define CCSR 0x04 /* Channel Command/status Register */
361 #define CCR 0x06 /* Channel Control Register */
362 #define PSR 0x08 /* Port status Register */
363 #define PCR 0x0a /* Port Control Register */
364 #define TMDR 0x0c /* Test mode Data Register */
365 #define TMCR 0x0e /* Test mode Control Register */
366 #define CMCR 0x10 /* Clock mode Control Register */
367 #define HCR 0x12 /* Hardware Configuration Register */
368 #define IVR 0x14 /* Interrupt Vector Register */
369 #define IOCR 0x16 /* Input/Output Control Register */
370 #define ICR 0x18 /* Interrupt Control Register */
371 #define DCCR 0x1a /* Daisy Chain Control Register */
372 #define MISR 0x1c /* Misc Interrupt status Register */
373 #define SICR 0x1e /* status Interrupt Control Register */
374 #define RDR 0x20 /* Receive Data Register */
375 #define RMR 0x22 /* Receive mode Register */
376 #define RCSR 0x24 /* Receive Command/status Register */
377 #define RICR 0x26 /* Receive Interrupt Control Register */
378 #define RSR 0x28 /* Receive Sync Register */
379 #define RCLR 0x2a /* Receive count Limit Register */
380 #define RCCR 0x2c /* Receive Character count Register */
381 #define TC0R 0x2e /* Time Constant 0 Register */
382 #define TDR 0x30 /* Transmit Data Register */
383 #define TMR 0x32 /* Transmit mode Register */
384 #define TCSR 0x34 /* Transmit Command/status Register */
385 #define TICR 0x36 /* Transmit Interrupt Control Register */
386 #define TSR 0x38 /* Transmit Sync Register */
387 #define TCLR 0x3a /* Transmit count Limit Register */
388 #define TCCR 0x3c /* Transmit Character count Register */
389 #define TC1R 0x3e /* Time Constant 1 Register */
390
391
392 /*
393 * MACRO DEFINITIONS FOR DMA REGISTERS
394 */
395
396 #define DCR 0x06 /* DMA Control Register (shared) */
397 #define DACR 0x08 /* DMA Array count Register (shared) */
398 #define BDCR 0x12 /* Burst/Dwell Control Register (shared) */
399 #define DIVR 0x14 /* DMA Interrupt Vector Register (shared) */
400 #define DICR 0x18 /* DMA Interrupt Control Register (shared) */
401 #define CDIR 0x1a /* Clear DMA Interrupt Register (shared) */
402 #define SDIR 0x1c /* Set DMA Interrupt Register (shared) */
403
404 #define TDMR 0x02 /* Transmit DMA mode Register */
405 #define TDIAR 0x1e /* Transmit DMA Interrupt Arm Register */
406 #define TBCR 0x2a /* Transmit Byte count Register */
407 #define TARL 0x2c /* Transmit Address Register (low) */
408 #define TARU 0x2e /* Transmit Address Register (high) */
409 #define NTBCR 0x3a /* Next Transmit Byte count Register */
410 #define NTARL 0x3c /* Next Transmit Address Register (low) */
411 #define NTARU 0x3e /* Next Transmit Address Register (high) */
412
413 #define RDMR 0x82 /* Receive DMA mode Register (non-shared) */
414 #define RDIAR 0x9e /* Receive DMA Interrupt Arm Register */
415 #define RBCR 0xaa /* Receive Byte count Register */
416 #define RARL 0xac /* Receive Address Register (low) */
417 #define RARU 0xae /* Receive Address Register (high) */
418 #define NRBCR 0xba /* Next Receive Byte count Register */
419 #define NRARL 0xbc /* Next Receive Address Register (low) */
420 #define NRARU 0xbe /* Next Receive Address Register (high) */
421
422
423 /*
424 * MACRO DEFINITIONS FOR MODEM STATUS BITS
425 */
426
427 #define MODEMSTATUS_DTR 0x80
428 #define MODEMSTATUS_DSR 0x40
429 #define MODEMSTATUS_RTS 0x20
430 #define MODEMSTATUS_CTS 0x10
431 #define MODEMSTATUS_RI 0x04
432 #define MODEMSTATUS_DCD 0x01
433
434
435 /*
436 * Channel Command/Address Register (CCAR) Command Codes
437 */
438
439 #define RTCmd_Null 0x0000
440 #define RTCmd_ResetHighestIus 0x1000
441 #define RTCmd_TriggerChannelLoadDma 0x2000
442 #define RTCmd_TriggerRxDma 0x2800
443 #define RTCmd_TriggerTxDma 0x3000
444 #define RTCmd_TriggerRxAndTxDma 0x3800
445 #define RTCmd_PurgeRxFifo 0x4800
446 #define RTCmd_PurgeTxFifo 0x5000
447 #define RTCmd_PurgeRxAndTxFifo 0x5800
448 #define RTCmd_LoadRcc 0x6800
449 #define RTCmd_LoadTcc 0x7000
450 #define RTCmd_LoadRccAndTcc 0x7800
451 #define RTCmd_LoadTC0 0x8800
452 #define RTCmd_LoadTC1 0x9000
453 #define RTCmd_LoadTC0AndTC1 0x9800
454 #define RTCmd_SerialDataLSBFirst 0xa000
455 #define RTCmd_SerialDataMSBFirst 0xa800
456 #define RTCmd_SelectBigEndian 0xb000
457 #define RTCmd_SelectLittleEndian 0xb800
458
459
460 /*
461 * DMA Command/Address Register (DCAR) Command Codes
462 */
463
464 #define DmaCmd_Null 0x0000
465 #define DmaCmd_ResetTxChannel 0x1000
466 #define DmaCmd_ResetRxChannel 0x1200
467 #define DmaCmd_StartTxChannel 0x2000
468 #define DmaCmd_StartRxChannel 0x2200
469 #define DmaCmd_ContinueTxChannel 0x3000
470 #define DmaCmd_ContinueRxChannel 0x3200
471 #define DmaCmd_PauseTxChannel 0x4000
472 #define DmaCmd_PauseRxChannel 0x4200
473 #define DmaCmd_AbortTxChannel 0x5000
474 #define DmaCmd_AbortRxChannel 0x5200
475 #define DmaCmd_InitTxChannel 0x7000
476 #define DmaCmd_InitRxChannel 0x7200
477 #define DmaCmd_ResetHighestDmaIus 0x8000
478 #define DmaCmd_ResetAllChannels 0x9000
479 #define DmaCmd_StartAllChannels 0xa000
480 #define DmaCmd_ContinueAllChannels 0xb000
481 #define DmaCmd_PauseAllChannels 0xc000
482 #define DmaCmd_AbortAllChannels 0xd000
483 #define DmaCmd_InitAllChannels 0xf000
484
485 #define TCmd_Null 0x0000
486 #define TCmd_ClearTxCRC 0x2000
487 #define TCmd_SelectTicrTtsaData 0x4000
488 #define TCmd_SelectTicrTxFifostatus 0x5000
489 #define TCmd_SelectTicrIntLevel 0x6000
490 #define TCmd_SelectTicrdma_level 0x7000
491 #define TCmd_SendFrame 0x8000
492 #define TCmd_SendAbort 0x9000
493 #define TCmd_EnableDleInsertion 0xc000
494 #define TCmd_DisableDleInsertion 0xd000
495 #define TCmd_ClearEofEom 0xe000
496 #define TCmd_SetEofEom 0xf000
497
498 #define RCmd_Null 0x0000
499 #define RCmd_ClearRxCRC 0x2000
500 #define RCmd_EnterHuntmode 0x3000
501 #define RCmd_SelectRicrRtsaData 0x4000
502 #define RCmd_SelectRicrRxFifostatus 0x5000
503 #define RCmd_SelectRicrIntLevel 0x6000
504 #define RCmd_SelectRicrdma_level 0x7000
505
506 /*
507 * Bits for enabling and disabling IRQs in Interrupt Control Register (ICR)
508 */
509
510 #define RECEIVE_STATUS BIT5
511 #define RECEIVE_DATA BIT4
512 #define TRANSMIT_STATUS BIT3
513 #define TRANSMIT_DATA BIT2
514 #define IO_PIN BIT1
515 #define MISC BIT0
516
517
518 /*
519 * Receive status Bits in Receive Command/status Register RCSR
520 */
521
522 #define RXSTATUS_SHORT_FRAME BIT8
523 #define RXSTATUS_CODE_VIOLATION BIT8
524 #define RXSTATUS_EXITED_HUNT BIT7
525 #define RXSTATUS_IDLE_RECEIVED BIT6
526 #define RXSTATUS_BREAK_RECEIVED BIT5
527 #define RXSTATUS_ABORT_RECEIVED BIT5
528 #define RXSTATUS_RXBOUND BIT4
529 #define RXSTATUS_CRC_ERROR BIT3
530 #define RXSTATUS_FRAMING_ERROR BIT3
531 #define RXSTATUS_ABORT BIT2
532 #define RXSTATUS_PARITY_ERROR BIT2
533 #define RXSTATUS_OVERRUN BIT1
534 #define RXSTATUS_DATA_AVAILABLE BIT0
535 #define RXSTATUS_ALL 0x01f6
536 #define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )
537
538 /*
539 * Values for setting transmit idle mode in
540 * Transmit Control/status Register (TCSR)
541 */
542 #define IDLEMODE_FLAGS 0x0000
543 #define IDLEMODE_ALT_ONE_ZERO 0x0100
544 #define IDLEMODE_ZERO 0x0200
545 #define IDLEMODE_ONE 0x0300
546 #define IDLEMODE_ALT_MARK_SPACE 0x0500
547 #define IDLEMODE_SPACE 0x0600
548 #define IDLEMODE_MARK 0x0700
549 #define IDLEMODE_MASK 0x0700
550
551 /*
552 * IUSC revision identifiers
553 */
554 #define IUSC_SL1660 0x4d44
555 #define IUSC_PRE_SL1660 0x4553
556
557 /*
558 * Transmit status Bits in Transmit Command/status Register (TCSR)
559 */
560
561 #define TCSR_PRESERVE 0x0F00
562
563 #define TCSR_UNDERWAIT BIT11
564 #define TXSTATUS_PREAMBLE_SENT BIT7
565 #define TXSTATUS_IDLE_SENT BIT6
566 #define TXSTATUS_ABORT_SENT BIT5
567 #define TXSTATUS_EOF_SENT BIT4
568 #define TXSTATUS_EOM_SENT BIT4
569 #define TXSTATUS_CRC_SENT BIT3
570 #define TXSTATUS_ALL_SENT BIT2
571 #define TXSTATUS_UNDERRUN BIT1
572 #define TXSTATUS_FIFO_EMPTY BIT0
573 #define TXSTATUS_ALL 0x00fa
574 #define usc_UnlatchTxstatusBits(a,b) usc_OutReg( (a), TCSR, (u16)((a)->tcsr_value + ((b) & 0x00FF)) )
575
576
577 #define MISCSTATUS_RXC_LATCHED BIT15
578 #define MISCSTATUS_RXC BIT14
579 #define MISCSTATUS_TXC_LATCHED BIT13
580 #define MISCSTATUS_TXC BIT12
581 #define MISCSTATUS_RI_LATCHED BIT11
582 #define MISCSTATUS_RI BIT10
583 #define MISCSTATUS_DSR_LATCHED BIT9
584 #define MISCSTATUS_DSR BIT8
585 #define MISCSTATUS_DCD_LATCHED BIT7
586 #define MISCSTATUS_DCD BIT6
587 #define MISCSTATUS_CTS_LATCHED BIT5
588 #define MISCSTATUS_CTS BIT4
589 #define MISCSTATUS_RCC_UNDERRUN BIT3
590 #define MISCSTATUS_DPLL_NO_SYNC BIT2
591 #define MISCSTATUS_BRG1_ZERO BIT1
592 #define MISCSTATUS_BRG0_ZERO BIT0
593
594 #define usc_UnlatchIostatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0xaaa0))
595 #define usc_UnlatchMiscstatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0x000f))
596
597 #define SICR_RXC_ACTIVE BIT15
598 #define SICR_RXC_INACTIVE BIT14
599 #define SICR_RXC (BIT15+BIT14)
600 #define SICR_TXC_ACTIVE BIT13
601 #define SICR_TXC_INACTIVE BIT12
602 #define SICR_TXC (BIT13+BIT12)
603 #define SICR_RI_ACTIVE BIT11
604 #define SICR_RI_INACTIVE BIT10
605 #define SICR_RI (BIT11+BIT10)
606 #define SICR_DSR_ACTIVE BIT9
607 #define SICR_DSR_INACTIVE BIT8
608 #define SICR_DSR (BIT9+BIT8)
609 #define SICR_DCD_ACTIVE BIT7
610 #define SICR_DCD_INACTIVE BIT6
611 #define SICR_DCD (BIT7+BIT6)
612 #define SICR_CTS_ACTIVE BIT5
613 #define SICR_CTS_INACTIVE BIT4
614 #define SICR_CTS (BIT5+BIT4)
615 #define SICR_RCC_UNDERFLOW BIT3
616 #define SICR_DPLL_NO_SYNC BIT2
617 #define SICR_BRG1_ZERO BIT1
618 #define SICR_BRG0_ZERO BIT0
619
620 void usc_DisableMasterIrqBit( struct mgsl_struct *info );
621 void usc_EnableMasterIrqBit( struct mgsl_struct *info );
622 void usc_EnableInterrupts( struct mgsl_struct *info, u16 IrqMask );
623 void usc_DisableInterrupts( struct mgsl_struct *info, u16 IrqMask );
624 void usc_ClearIrqPendingBits( struct mgsl_struct *info, u16 IrqMask );
625
626 #define usc_EnableInterrupts( a, b ) \
627 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )
628
629 #define usc_DisableInterrupts( a, b ) \
630 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )
631
632 #define usc_EnableMasterIrqBit(a) \
633 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )
634
635 #define usc_DisableMasterIrqBit(a) \
636 usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )
637
638 #define usc_ClearIrqPendingBits( a, b ) usc_OutReg( (a), DCCR, 0x40 + (b) )
639
640 /*
641 * Transmit status Bits in Transmit Control status Register (TCSR)
642 * and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0)
643 */
644
645 #define TXSTATUS_PREAMBLE_SENT BIT7
646 #define TXSTATUS_IDLE_SENT BIT6
647 #define TXSTATUS_ABORT_SENT BIT5
648 #define TXSTATUS_EOF BIT4
649 #define TXSTATUS_CRC_SENT BIT3
650 #define TXSTATUS_ALL_SENT BIT2
651 #define TXSTATUS_UNDERRUN BIT1
652 #define TXSTATUS_FIFO_EMPTY BIT0
653
654 #define DICR_MASTER BIT15
655 #define DICR_TRANSMIT BIT0
656 #define DICR_RECEIVE BIT1
657
658 #define usc_EnableDmaInterrupts(a,b) \
659 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) | (b)) )
660
661 #define usc_DisableDmaInterrupts(a,b) \
662 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) )
663
664 #define usc_EnableStatusIrqs(a,b) \
665 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) )
666
667 #define usc_DisablestatusIrqs(a,b) \
668 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )
669
670 /* Transmit status Bits in Transmit Control status Register (TCSR) */
671 /* and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) */
672
673
674 #define DISABLE_UNCONDITIONAL 0
675 #define DISABLE_END_OF_FRAME 1
676 #define ENABLE_UNCONDITIONAL 2
677 #define ENABLE_AUTO_CTS 3
678 #define ENABLE_AUTO_DCD 3
679 #define usc_EnableTransmitter(a,b) \
680 usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) )
681 #define usc_EnableReceiver(a,b) \
682 usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) )
683
684 static u16 usc_InDmaReg( struct mgsl_struct *info, u16 Port );
685 static void usc_OutDmaReg( struct mgsl_struct *info, u16 Port, u16 Value );
686 static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd );
687
688 static u16 usc_InReg( struct mgsl_struct *info, u16 Port );
689 static void usc_OutReg( struct mgsl_struct *info, u16 Port, u16 Value );
690 static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd );
691 void usc_RCmd( struct mgsl_struct *info, u16 Cmd );
692 void usc_TCmd( struct mgsl_struct *info, u16 Cmd );
693
694 #define usc_TCmd(a,b) usc_OutReg((a), TCSR, (u16)((a)->tcsr_value + (b)))
695 #define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b))
696
697 #define usc_SetTransmitSyncChars(a,s0,s1) usc_OutReg((a), TSR, (u16)(((u16)s0<<8)|(u16)s1))
698
699 static void usc_process_rxoverrun_sync( struct mgsl_struct *info );
700 static void usc_start_receiver( struct mgsl_struct *info );
701 static void usc_stop_receiver( struct mgsl_struct *info );
702
703 static void usc_start_transmitter( struct mgsl_struct *info );
704 static void usc_stop_transmitter( struct mgsl_struct *info );
705 static void usc_set_txidle( struct mgsl_struct *info );
706 static void usc_load_txfifo( struct mgsl_struct *info );
707
708 static void usc_enable_aux_clock( struct mgsl_struct *info, u32 DataRate );
709 static void usc_enable_loopback( struct mgsl_struct *info, int enable );
710
711 static void usc_get_serial_signals( struct mgsl_struct *info );
712 static void usc_set_serial_signals( struct mgsl_struct *info );
713
714 static void usc_reset( struct mgsl_struct *info );
715
716 static void usc_set_sync_mode( struct mgsl_struct *info );
717 static void usc_set_sdlc_mode( struct mgsl_struct *info );
718 static void usc_set_async_mode( struct mgsl_struct *info );
719 static void usc_enable_async_clock( struct mgsl_struct *info, u32 DataRate );
720
721 static void usc_loopback_frame( struct mgsl_struct *info );
722
723 static void mgsl_tx_timeout(unsigned long context);
724
725
726 static void usc_loopmode_cancel_transmit( struct mgsl_struct * info );
727 static void usc_loopmode_insert_request( struct mgsl_struct * info );
728 static int usc_loopmode_active( struct mgsl_struct * info);
729 static void usc_loopmode_send_done( struct mgsl_struct * info );
730
731 static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg);
732
733 #ifdef CONFIG_HDLC
734 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
735 static void hdlcdev_tx_done(struct mgsl_struct *info);
736 static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size);
737 static int hdlcdev_init(struct mgsl_struct *info);
738 static void hdlcdev_exit(struct mgsl_struct *info);
739 #endif
740
741 /*
742 * Defines a BUS descriptor value for the PCI adapter
743 * local bus address ranges.
744 */
745
746 #define BUS_DESCRIPTOR( WrHold, WrDly, RdDly, Nwdd, Nwad, Nxda, Nrdd, Nrad ) \
747 (0x00400020 + \
748 ((WrHold) << 30) + \
749 ((WrDly) << 28) + \
750 ((RdDly) << 26) + \
751 ((Nwdd) << 20) + \
752 ((Nwad) << 15) + \
753 ((Nxda) << 13) + \
754 ((Nrdd) << 11) + \
755 ((Nrad) << 6) )
756
757 static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit);
758
759 /*
760 * Adapter diagnostic routines
761 */
762 static BOOLEAN mgsl_register_test( struct mgsl_struct *info );
763 static BOOLEAN mgsl_irq_test( struct mgsl_struct *info );
764 static BOOLEAN mgsl_dma_test( struct mgsl_struct *info );
765 static BOOLEAN mgsl_memory_test( struct mgsl_struct *info );
766 static int mgsl_adapter_test( struct mgsl_struct *info );
767
768 /*
769 * device and resource management routines
770 */
771 static int mgsl_claim_resources(struct mgsl_struct *info);
772 static void mgsl_release_resources(struct mgsl_struct *info);
773 static void mgsl_add_device(struct mgsl_struct *info);
774 static struct mgsl_struct* mgsl_allocate_device(void);
775
776 /*
777 * DMA buffer manupulation functions.
778 */
779 static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex );
780 static int mgsl_get_rx_frame( struct mgsl_struct *info );
781 static int mgsl_get_raw_rx_frame( struct mgsl_struct *info );
782 static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info );
783 static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info );
784 static int num_free_tx_dma_buffers(struct mgsl_struct *info);
785 static void mgsl_load_tx_dma_buffer( struct mgsl_struct *info, const char *Buffer, unsigned int BufferSize);
786 static void mgsl_load_pci_memory(char* TargetPtr, const char* SourcePtr, unsigned short count);
787
788 /*
789 * DMA and Shared Memory buffer allocation and formatting
790 */
791 static int mgsl_allocate_dma_buffers(struct mgsl_struct *info);
792 static void mgsl_free_dma_buffers(struct mgsl_struct *info);
793 static int mgsl_alloc_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
794 static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
795 static int mgsl_alloc_buffer_list_memory(struct mgsl_struct *info);
796 static void mgsl_free_buffer_list_memory(struct mgsl_struct *info);
797 static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info);
798 static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info);
799 static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info);
800 static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info);
801 static int load_next_tx_holding_buffer(struct mgsl_struct *info);
802 static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize);
803
804 /*
805 * Bottom half interrupt handlers
806 */
807 static void mgsl_bh_handler(void* Context);
808 static void mgsl_bh_receive(struct mgsl_struct *info);
809 static void mgsl_bh_transmit(struct mgsl_struct *info);
810 static void mgsl_bh_status(struct mgsl_struct *info);
811
812 /*
813 * Interrupt handler routines and dispatch table.
814 */
815 static void mgsl_isr_null( struct mgsl_struct *info );
816 static void mgsl_isr_transmit_data( struct mgsl_struct *info );
817 static void mgsl_isr_receive_data( struct mgsl_struct *info );
818 static void mgsl_isr_receive_status( struct mgsl_struct *info );
819 static void mgsl_isr_transmit_status( struct mgsl_struct *info );
820 static void mgsl_isr_io_pin( struct mgsl_struct *info );
821 static void mgsl_isr_misc( struct mgsl_struct *info );
822 static void mgsl_isr_receive_dma( struct mgsl_struct *info );
823 static void mgsl_isr_transmit_dma( struct mgsl_struct *info );
824
825 typedef void (*isr_dispatch_func)(struct mgsl_struct *);
826
827 static isr_dispatch_func UscIsrTable[7] =
828 {
829 mgsl_isr_null,
830 mgsl_isr_misc,
831 mgsl_isr_io_pin,
832 mgsl_isr_transmit_data,
833 mgsl_isr_transmit_status,
834 mgsl_isr_receive_data,
835 mgsl_isr_receive_status
836 };
837
838 /*
839 * ioctl call handlers
840 */
841 static int tiocmget(struct tty_struct *tty, struct file *file);
842 static int tiocmset(struct tty_struct *tty, struct file *file,
843 unsigned int set, unsigned int clear);
844 static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount
845 __user *user_icount);
846 static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params);
847 static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params);
848 static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode);
849 static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode);
850 static int mgsl_txenable(struct mgsl_struct * info, int enable);
851 static int mgsl_txabort(struct mgsl_struct * info);
852 static int mgsl_rxenable(struct mgsl_struct * info, int enable);
853 static int mgsl_wait_event(struct mgsl_struct * info, int __user *mask);
854 static int mgsl_loopmode_send_done( struct mgsl_struct * info );
855
856 /* set non-zero on successful registration with PCI subsystem */
857 static int pci_registered;
858
859 /*
860 * Global linked list of SyncLink devices
861 */
862 static struct mgsl_struct *mgsl_device_list;
863 static int mgsl_device_count;
864
865 /*
866 * Set this param to non-zero to load eax with the
867 * .text section address and breakpoint on module load.
868 * This is useful for use with gdb and add-symbol-file command.
869 */
870 static int break_on_load;
871
872 /*
873 * Driver major number, defaults to zero to get auto
874 * assigned major number. May be forced as module parameter.
875 */
876 static int ttymajor;
877
878 /*
879 * Array of user specified options for ISA adapters.
880 */
881 static int io[MAX_ISA_DEVICES];
882 static int irq[MAX_ISA_DEVICES];
883 static int dma[MAX_ISA_DEVICES];
884 static int debug_level;
885 static int maxframe[MAX_TOTAL_DEVICES];
886 static int dosyncppp[MAX_TOTAL_DEVICES];
887 static int txdmabufs[MAX_TOTAL_DEVICES];
888 static int txholdbufs[MAX_TOTAL_DEVICES];
889
890 module_param(break_on_load, bool, 0);
891 module_param(ttymajor, int, 0);
892 module_param_array(io, int, NULL, 0);
893 module_param_array(irq, int, NULL, 0);
894 module_param_array(dma, int, NULL, 0);
895 module_param(debug_level, int, 0);
896 module_param_array(maxframe, int, NULL, 0);
897 module_param_array(dosyncppp, int, NULL, 0);
898 module_param_array(txdmabufs, int, NULL, 0);
899 module_param_array(txholdbufs, int, NULL, 0);
900
901 static char *driver_name = "SyncLink serial driver";
902 static char *driver_version = "$Revision: 4.38 $";
903
904 static int synclink_init_one (struct pci_dev *dev,
905 const struct pci_device_id *ent);
906 static void synclink_remove_one (struct pci_dev *dev);
907
908 static struct pci_device_id synclink_pci_tbl[] = {
909 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_USC, PCI_ANY_ID, PCI_ANY_ID, },
910 { PCI_VENDOR_ID_MICROGATE, 0x0210, PCI_ANY_ID, PCI_ANY_ID, },
911 { 0, }, /* terminate list */
912 };
913 MODULE_DEVICE_TABLE(pci, synclink_pci_tbl);
914
915 MODULE_LICENSE("GPL");
916
917 static struct pci_driver synclink_pci_driver = {
918 .name = "synclink",
919 .id_table = synclink_pci_tbl,
920 .probe = synclink_init_one,
921 .remove = __devexit_p(synclink_remove_one),
922 };
923
924 static struct tty_driver *serial_driver;
925
926 /* number of characters left in xmit buffer before we ask for more */
927 #define WAKEUP_CHARS 256
928
929
930 static void mgsl_change_params(struct mgsl_struct *info);
931 static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout);
932
933 /*
934 * 1st function defined in .text section. Calling this function in
935 * init_module() followed by a breakpoint allows a remote debugger
936 * (gdb) to get the .text address for the add-symbol-file command.
937 * This allows remote debugging of dynamically loadable modules.
938 */
939 static void* mgsl_get_text_ptr(void)
940 {
941 return mgsl_get_text_ptr;
942 }
943
944 static inline int mgsl_paranoia_check(struct mgsl_struct *info,
945 char *name, const char *routine)
946 {
947 #ifdef MGSL_PARANOIA_CHECK
948 static const char *badmagic =
949 "Warning: bad magic number for mgsl struct (%s) in %s\n";
950 static const char *badinfo =
951 "Warning: null mgsl_struct for (%s) in %s\n";
952
953 if (!info) {
954 printk(badinfo, name, routine);
955 return 1;
956 }
957 if (info->magic != MGSL_MAGIC) {
958 printk(badmagic, name, routine);
959 return 1;
960 }
961 #else
962 if (!info)
963 return 1;
964 #endif
965 return 0;
966 }
967
968 /**
969 * line discipline callback wrappers
970 *
971 * The wrappers maintain line discipline references
972 * while calling into the line discipline.
973 *
974 * ldisc_receive_buf - pass receive data to line discipline
975 */
976
977 static void ldisc_receive_buf(struct tty_struct *tty,
978 const __u8 *data, char *flags, int count)
979 {
980 struct tty_ldisc *ld;
981 if (!tty)
982 return;
983 ld = tty_ldisc_ref(tty);
984 if (ld) {
985 if (ld->receive_buf)
986 ld->receive_buf(tty, data, flags, count);
987 tty_ldisc_deref(ld);
988 }
989 }
990
991 /* mgsl_stop() throttle (stop) transmitter
992 *
993 * Arguments: tty pointer to tty info structure
994 * Return Value: None
995 */
996 static void mgsl_stop(struct tty_struct *tty)
997 {
998 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
999 unsigned long flags;
1000
1001 if (mgsl_paranoia_check(info, tty->name, "mgsl_stop"))
1002 return;
1003
1004 if ( debug_level >= DEBUG_LEVEL_INFO )
1005 printk("mgsl_stop(%s)\n",info->device_name);
1006
1007 spin_lock_irqsave(&info->irq_spinlock,flags);
1008 if (info->tx_enabled)
1009 usc_stop_transmitter(info);
1010 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1011
1012 } /* end of mgsl_stop() */
1013
1014 /* mgsl_start() release (start) transmitter
1015 *
1016 * Arguments: tty pointer to tty info structure
1017 * Return Value: None
1018 */
1019 static void mgsl_start(struct tty_struct *tty)
1020 {
1021 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
1022 unsigned long flags;
1023
1024 if (mgsl_paranoia_check(info, tty->name, "mgsl_start"))
1025 return;
1026
1027 if ( debug_level >= DEBUG_LEVEL_INFO )
1028 printk("mgsl_start(%s)\n",info->device_name);
1029
1030 spin_lock_irqsave(&info->irq_spinlock,flags);
1031 if (!info->tx_enabled)
1032 usc_start_transmitter(info);
1033 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1034
1035 } /* end of mgsl_start() */
1036
1037 /*
1038 * Bottom half work queue access functions
1039 */
1040
1041 /* mgsl_bh_action() Return next bottom half action to perform.
1042 * Return Value: BH action code or 0 if nothing to do.
1043 */
1044 static int mgsl_bh_action(struct mgsl_struct *info)
1045 {
1046 unsigned long flags;
1047 int rc = 0;
1048
1049 spin_lock_irqsave(&info->irq_spinlock,flags);
1050
1051 if (info->pending_bh & BH_RECEIVE) {
1052 info->pending_bh &= ~BH_RECEIVE;
1053 rc = BH_RECEIVE;
1054 } else if (info->pending_bh & BH_TRANSMIT) {
1055 info->pending_bh &= ~BH_TRANSMIT;
1056 rc = BH_TRANSMIT;
1057 } else if (info->pending_bh & BH_STATUS) {
1058 info->pending_bh &= ~BH_STATUS;
1059 rc = BH_STATUS;
1060 }
1061
1062 if (!rc) {
1063 /* Mark BH routine as complete */
1064 info->bh_running = 0;
1065 info->bh_requested = 0;
1066 }
1067
1068 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1069
1070 return rc;
1071 }
1072
1073 /*
1074 * Perform bottom half processing of work items queued by ISR.
1075 */
1076 static void mgsl_bh_handler(void* Context)
1077 {
1078 struct mgsl_struct *info = (struct mgsl_struct*)Context;
1079 int action;
1080
1081 if (!info)
1082 return;
1083
1084 if ( debug_level >= DEBUG_LEVEL_BH )
1085 printk( "%s(%d):mgsl_bh_handler(%s) entry\n",
1086 __FILE__,__LINE__,info->device_name);
1087
1088 info->bh_running = 1;
1089
1090 while((action = mgsl_bh_action(info)) != 0) {
1091
1092 /* Process work item */
1093 if ( debug_level >= DEBUG_LEVEL_BH )
1094 printk( "%s(%d):mgsl_bh_handler() work item action=%d\n",
1095 __FILE__,__LINE__,action);
1096
1097 switch (action) {
1098
1099 case BH_RECEIVE:
1100 mgsl_bh_receive(info);
1101 break;
1102 case BH_TRANSMIT:
1103 mgsl_bh_transmit(info);
1104 break;
1105 case BH_STATUS:
1106 mgsl_bh_status(info);
1107 break;
1108 default:
1109 /* unknown work item ID */
1110 printk("Unknown work item ID=%08X!\n", action);
1111 break;
1112 }
1113 }
1114
1115 if ( debug_level >= DEBUG_LEVEL_BH )
1116 printk( "%s(%d):mgsl_bh_handler(%s) exit\n",
1117 __FILE__,__LINE__,info->device_name);
1118 }
1119
1120 static void mgsl_bh_receive(struct mgsl_struct *info)
1121 {
1122 int (*get_rx_frame)(struct mgsl_struct *info) =
1123 (info->params.mode == MGSL_MODE_HDLC ? mgsl_get_rx_frame : mgsl_get_raw_rx_frame);
1124
1125 if ( debug_level >= DEBUG_LEVEL_BH )
1126 printk( "%s(%d):mgsl_bh_receive(%s)\n",
1127 __FILE__,__LINE__,info->device_name);
1128
1129 do
1130 {
1131 if (info->rx_rcc_underrun) {
1132 unsigned long flags;
1133 spin_lock_irqsave(&info->irq_spinlock,flags);
1134 usc_start_receiver(info);
1135 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1136 return;
1137 }
1138 } while(get_rx_frame(info));
1139 }
1140
1141 static void mgsl_bh_transmit(struct mgsl_struct *info)
1142 {
1143 struct tty_struct *tty = info->tty;
1144 unsigned long flags;
1145
1146 if ( debug_level >= DEBUG_LEVEL_BH )
1147 printk( "%s(%d):mgsl_bh_transmit() entry on %s\n",
1148 __FILE__,__LINE__,info->device_name);
1149
1150 if (tty) {
1151 tty_wakeup(tty);
1152 wake_up_interruptible(&tty->write_wait);
1153 }
1154
1155 /* if transmitter idle and loopmode_send_done_requested
1156 * then start echoing RxD to TxD
1157 */
1158 spin_lock_irqsave(&info->irq_spinlock,flags);
1159 if ( !info->tx_active && info->loopmode_send_done_requested )
1160 usc_loopmode_send_done( info );
1161 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1162 }
1163
1164 static void mgsl_bh_status(struct mgsl_struct *info)
1165 {
1166 if ( debug_level >= DEBUG_LEVEL_BH )
1167 printk( "%s(%d):mgsl_bh_status() entry on %s\n",
1168 __FILE__,__LINE__,info->device_name);
1169
1170 info->ri_chkcount = 0;
1171 info->dsr_chkcount = 0;
1172 info->dcd_chkcount = 0;
1173 info->cts_chkcount = 0;
1174 }
1175
1176 /* mgsl_isr_receive_status()
1177 *
1178 * Service a receive status interrupt. The type of status
1179 * interrupt is indicated by the state of the RCSR.
1180 * This is only used for HDLC mode.
1181 *
1182 * Arguments: info pointer to device instance data
1183 * Return Value: None
1184 */
1185 static void mgsl_isr_receive_status( struct mgsl_struct *info )
1186 {
1187 u16 status = usc_InReg( info, RCSR );
1188
1189 if ( debug_level >= DEBUG_LEVEL_ISR )
1190 printk("%s(%d):mgsl_isr_receive_status status=%04X\n",
1191 __FILE__,__LINE__,status);
1192
1193 if ( (status & RXSTATUS_ABORT_RECEIVED) &&
1194 info->loopmode_insert_requested &&
1195 usc_loopmode_active(info) )
1196 {
1197 ++info->icount.rxabort;
1198 info->loopmode_insert_requested = FALSE;
1199
1200 /* clear CMR:13 to start echoing RxD to TxD */
1201 info->cmr_value &= ~BIT13;
1202 usc_OutReg(info, CMR, info->cmr_value);
1203
1204 /* disable received abort irq (no longer required) */
1205 usc_OutReg(info, RICR,
1206 (usc_InReg(info, RICR) & ~RXSTATUS_ABORT_RECEIVED));
1207 }
1208
1209 if (status & (RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED)) {
1210 if (status & RXSTATUS_EXITED_HUNT)
1211 info->icount.exithunt++;
1212 if (status & RXSTATUS_IDLE_RECEIVED)
1213 info->icount.rxidle++;
1214 wake_up_interruptible(&info->event_wait_q);
1215 }
1216
1217 if (status & RXSTATUS_OVERRUN){
1218 info->icount.rxover++;
1219 usc_process_rxoverrun_sync( info );
1220 }
1221
1222 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
1223 usc_UnlatchRxstatusBits( info, status );
1224
1225 } /* end of mgsl_isr_receive_status() */
1226
1227 /* mgsl_isr_transmit_status()
1228 *
1229 * Service a transmit status interrupt
1230 * HDLC mode :end of transmit frame
1231 * Async mode:all data is sent
1232 * transmit status is indicated by bits in the TCSR.
1233 *
1234 * Arguments: info pointer to device instance data
1235 * Return Value: None
1236 */
1237 static void mgsl_isr_transmit_status( struct mgsl_struct *info )
1238 {
1239 u16 status = usc_InReg( info, TCSR );
1240
1241 if ( debug_level >= DEBUG_LEVEL_ISR )
1242 printk("%s(%d):mgsl_isr_transmit_status status=%04X\n",
1243 __FILE__,__LINE__,status);
1244
1245 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
1246 usc_UnlatchTxstatusBits( info, status );
1247
1248 if ( status & (TXSTATUS_UNDERRUN | TXSTATUS_ABORT_SENT) )
1249 {
1250 /* finished sending HDLC abort. This may leave */
1251 /* the TxFifo with data from the aborted frame */
1252 /* so purge the TxFifo. Also shutdown the DMA */
1253 /* channel in case there is data remaining in */
1254 /* the DMA buffer */
1255 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
1256 usc_RTCmd( info, RTCmd_PurgeTxFifo );
1257 }
1258
1259 if ( status & TXSTATUS_EOF_SENT )
1260 info->icount.txok++;
1261 else if ( status & TXSTATUS_UNDERRUN )
1262 info->icount.txunder++;
1263 else if ( status & TXSTATUS_ABORT_SENT )
1264 info->icount.txabort++;
1265 else
1266 info->icount.txunder++;
1267
1268 info->tx_active = 0;
1269 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1270 del_timer(&info->tx_timer);
1271
1272 if ( info->drop_rts_on_tx_done ) {
1273 usc_get_serial_signals( info );
1274 if ( info->serial_signals & SerialSignal_RTS ) {
1275 info->serial_signals &= ~SerialSignal_RTS;
1276 usc_set_serial_signals( info );
1277 }
1278 info->drop_rts_on_tx_done = 0;
1279 }
1280
1281 #ifdef CONFIG_HDLC
1282 if (info->netcount)
1283 hdlcdev_tx_done(info);
1284 else
1285 #endif
1286 {
1287 if (info->tty->stopped || info->tty->hw_stopped) {
1288 usc_stop_transmitter(info);
1289 return;
1290 }
1291 info->pending_bh |= BH_TRANSMIT;
1292 }
1293
1294 } /* end of mgsl_isr_transmit_status() */
1295
1296 /* mgsl_isr_io_pin()
1297 *
1298 * Service an Input/Output pin interrupt. The type of
1299 * interrupt is indicated by bits in the MISR
1300 *
1301 * Arguments: info pointer to device instance data
1302 * Return Value: None
1303 */
1304 static void mgsl_isr_io_pin( struct mgsl_struct *info )
1305 {
1306 struct mgsl_icount *icount;
1307 u16 status = usc_InReg( info, MISR );
1308
1309 if ( debug_level >= DEBUG_LEVEL_ISR )
1310 printk("%s(%d):mgsl_isr_io_pin status=%04X\n",
1311 __FILE__,__LINE__,status);
1312
1313 usc_ClearIrqPendingBits( info, IO_PIN );
1314 usc_UnlatchIostatusBits( info, status );
1315
1316 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
1317 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
1318 icount = &info->icount;
1319 /* update input line counters */
1320 if (status & MISCSTATUS_RI_LATCHED) {
1321 if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1322 usc_DisablestatusIrqs(info,SICR_RI);
1323 icount->rng++;
1324 if ( status & MISCSTATUS_RI )
1325 info->input_signal_events.ri_up++;
1326 else
1327 info->input_signal_events.ri_down++;
1328 }
1329 if (status & MISCSTATUS_DSR_LATCHED) {
1330 if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1331 usc_DisablestatusIrqs(info,SICR_DSR);
1332 icount->dsr++;
1333 if ( status & MISCSTATUS_DSR )
1334 info->input_signal_events.dsr_up++;
1335 else
1336 info->input_signal_events.dsr_down++;
1337 }
1338 if (status & MISCSTATUS_DCD_LATCHED) {
1339 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1340 usc_DisablestatusIrqs(info,SICR_DCD);
1341 icount->dcd++;
1342 if (status & MISCSTATUS_DCD) {
1343 info->input_signal_events.dcd_up++;
1344 } else
1345 info->input_signal_events.dcd_down++;
1346 #ifdef CONFIG_HDLC
1347 if (info->netcount) {
1348 if (status & MISCSTATUS_DCD)
1349 netif_carrier_on(info->netdev);
1350 else
1351 netif_carrier_off(info->netdev);
1352 }
1353 #endif
1354 }
1355 if (status & MISCSTATUS_CTS_LATCHED)
1356 {
1357 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1358 usc_DisablestatusIrqs(info,SICR_CTS);
1359 icount->cts++;
1360 if ( status & MISCSTATUS_CTS )
1361 info->input_signal_events.cts_up++;
1362 else
1363 info->input_signal_events.cts_down++;
1364 }
1365 wake_up_interruptible(&info->status_event_wait_q);
1366 wake_up_interruptible(&info->event_wait_q);
1367
1368 if ( (info->flags & ASYNC_CHECK_CD) &&
1369 (status & MISCSTATUS_DCD_LATCHED) ) {
1370 if ( debug_level >= DEBUG_LEVEL_ISR )
1371 printk("%s CD now %s...", info->device_name,
1372 (status & MISCSTATUS_DCD) ? "on" : "off");
1373 if (status & MISCSTATUS_DCD)
1374 wake_up_interruptible(&info->open_wait);
1375 else {
1376 if ( debug_level >= DEBUG_LEVEL_ISR )
1377 printk("doing serial hangup...");
1378 if (info->tty)
1379 tty_hangup(info->tty);
1380 }
1381 }
1382
1383 if ( (info->flags & ASYNC_CTS_FLOW) &&
1384 (status & MISCSTATUS_CTS_LATCHED) ) {
1385 if (info->tty->hw_stopped) {
1386 if (status & MISCSTATUS_CTS) {
1387 if ( debug_level >= DEBUG_LEVEL_ISR )
1388 printk("CTS tx start...");
1389 if (info->tty)
1390 info->tty->hw_stopped = 0;
1391 usc_start_transmitter(info);
1392 info->pending_bh |= BH_TRANSMIT;
1393 return;
1394 }
1395 } else {
1396 if (!(status & MISCSTATUS_CTS)) {
1397 if ( debug_level >= DEBUG_LEVEL_ISR )
1398 printk("CTS tx stop...");
1399 if (info->tty)
1400 info->tty->hw_stopped = 1;
1401 usc_stop_transmitter(info);
1402 }
1403 }
1404 }
1405 }
1406
1407 info->pending_bh |= BH_STATUS;
1408
1409 /* for diagnostics set IRQ flag */
1410 if ( status & MISCSTATUS_TXC_LATCHED ){
1411 usc_OutReg( info, SICR,
1412 (unsigned short)(usc_InReg(info,SICR) & ~(SICR_TXC_ACTIVE+SICR_TXC_INACTIVE)) );
1413 usc_UnlatchIostatusBits( info, MISCSTATUS_TXC_LATCHED );
1414 info->irq_occurred = 1;
1415 }
1416
1417 } /* end of mgsl_isr_io_pin() */
1418
1419 /* mgsl_isr_transmit_data()
1420 *
1421 * Service a transmit data interrupt (async mode only).
1422 *
1423 * Arguments: info pointer to device instance data
1424 * Return Value: None
1425 */
1426 static void mgsl_isr_transmit_data( struct mgsl_struct *info )
1427 {
1428 if ( debug_level >= DEBUG_LEVEL_ISR )
1429 printk("%s(%d):mgsl_isr_transmit_data xmit_cnt=%d\n",
1430 __FILE__,__LINE__,info->xmit_cnt);
1431
1432 usc_ClearIrqPendingBits( info, TRANSMIT_DATA );
1433
1434 if (info->tty->stopped || info->tty->hw_stopped) {
1435 usc_stop_transmitter(info);
1436 return;
1437 }
1438
1439 if ( info->xmit_cnt )
1440 usc_load_txfifo( info );
1441 else
1442 info->tx_active = 0;
1443
1444 if (info->xmit_cnt < WAKEUP_CHARS)
1445 info->pending_bh |= BH_TRANSMIT;
1446
1447 } /* end of mgsl_isr_transmit_data() */
1448
1449 /* mgsl_isr_receive_data()
1450 *
1451 * Service a receive data interrupt. This occurs
1452 * when operating in asynchronous interrupt transfer mode.
1453 * The receive data FIFO is flushed to the receive data buffers.
1454 *
1455 * Arguments: info pointer to device instance data
1456 * Return Value: None
1457 */
1458 static void mgsl_isr_receive_data( struct mgsl_struct *info )
1459 {
1460 int Fifocount;
1461 u16 status;
1462 int work = 0;
1463 unsigned char DataByte;
1464 struct tty_struct *tty = info->tty;
1465 struct mgsl_icount *icount = &info->icount;
1466
1467 if ( debug_level >= DEBUG_LEVEL_ISR )
1468 printk("%s(%d):mgsl_isr_receive_data\n",
1469 __FILE__,__LINE__);
1470
1471 usc_ClearIrqPendingBits( info, RECEIVE_DATA );
1472
1473 /* select FIFO status for RICR readback */
1474 usc_RCmd( info, RCmd_SelectRicrRxFifostatus );
1475
1476 /* clear the Wordstatus bit so that status readback */
1477 /* only reflects the status of this byte */
1478 usc_OutReg( info, RICR+LSBONLY, (u16)(usc_InReg(info, RICR+LSBONLY) & ~BIT3 ));
1479
1480 /* flush the receive FIFO */
1481
1482 while( (Fifocount = (usc_InReg(info,RICR) >> 8)) ) {
1483 int flag;
1484
1485 /* read one byte from RxFIFO */
1486 outw( (inw(info->io_base + CCAR) & 0x0780) | (RDR+LSBONLY),
1487 info->io_base + CCAR );
1488 DataByte = inb( info->io_base + CCAR );
1489
1490 /* get the status of the received byte */
1491 status = usc_InReg(info, RCSR);
1492 if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
1493 RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) )
1494 usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
1495
1496 icount->rx++;
1497
1498 flag = 0;
1499 if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
1500 RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) ) {
1501 printk("rxerr=%04X\n",status);
1502 /* update error statistics */
1503 if ( status & RXSTATUS_BREAK_RECEIVED ) {
1504 status &= ~(RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR);
1505 icount->brk++;
1506 } else if (status & RXSTATUS_PARITY_ERROR)
1507 icount->parity++;
1508 else if (status & RXSTATUS_FRAMING_ERROR)
1509 icount->frame++;
1510 else if (status & RXSTATUS_OVERRUN) {
1511 /* must issue purge fifo cmd before */
1512 /* 16C32 accepts more receive chars */
1513 usc_RTCmd(info,RTCmd_PurgeRxFifo);
1514 icount->overrun++;
1515 }
1516
1517 /* discard char if tty control flags say so */
1518 if (status & info->ignore_status_mask)
1519 continue;
1520
1521 status &= info->read_status_mask;
1522
1523 if (status & RXSTATUS_BREAK_RECEIVED) {
1524 flag = TTY_BREAK;
1525 if (info->flags & ASYNC_SAK)
1526 do_SAK(tty);
1527 } else if (status & RXSTATUS_PARITY_ERROR)
1528 flag = TTY_PARITY;
1529 else if (status & RXSTATUS_FRAMING_ERROR)
1530 flag = TTY_FRAME;
1531 } /* end of if (error) */
1532 tty_insert_flip_char(tty, DataByte, flag);
1533 if (status & RXSTATUS_OVERRUN) {
1534 /* Overrun is special, since it's
1535 * reported immediately, and doesn't
1536 * affect the current character
1537 */
1538 work += tty_insert_flip_char(tty, 0, TTY_OVERRUN);
1539 }
1540 }
1541
1542 if ( debug_level >= DEBUG_LEVEL_ISR ) {
1543 printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
1544 __FILE__,__LINE__,icount->rx,icount->brk,
1545 icount->parity,icount->frame,icount->overrun);
1546 }
1547
1548 if(work)
1549 tty_flip_buffer_push(tty);
1550 }
1551
1552 /* mgsl_isr_misc()
1553 *
1554 * Service a miscellaneos interrupt source.
1555 *
1556 * Arguments: info pointer to device extension (instance data)
1557 * Return Value: None
1558 */
1559 static void mgsl_isr_misc( struct mgsl_struct *info )
1560 {
1561 u16 status = usc_InReg( info, MISR );
1562
1563 if ( debug_level >= DEBUG_LEVEL_ISR )
1564 printk("%s(%d):mgsl_isr_misc status=%04X\n",
1565 __FILE__,__LINE__,status);
1566
1567 if ((status & MISCSTATUS_RCC_UNDERRUN) &&
1568 (info->params.mode == MGSL_MODE_HDLC)) {
1569
1570 /* turn off receiver and rx DMA */
1571 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
1572 usc_DmaCmd(info, DmaCmd_ResetRxChannel);
1573 usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
1574 usc_ClearIrqPendingBits(info, RECEIVE_DATA + RECEIVE_STATUS);
1575 usc_DisableInterrupts(info, RECEIVE_DATA + RECEIVE_STATUS);
1576
1577 /* schedule BH handler to restart receiver */
1578 info->pending_bh |= BH_RECEIVE;
1579 info->rx_rcc_underrun = 1;
1580 }
1581
1582 usc_ClearIrqPendingBits( info, MISC );
1583 usc_UnlatchMiscstatusBits( info, status );
1584
1585 } /* end of mgsl_isr_misc() */
1586
1587 /* mgsl_isr_null()
1588 *
1589 * Services undefined interrupt vectors from the
1590 * USC. (hence this function SHOULD never be called)
1591 *
1592 * Arguments: info pointer to device extension (instance data)
1593 * Return Value: None
1594 */
1595 static void mgsl_isr_null( struct mgsl_struct *info )
1596 {
1597
1598 } /* end of mgsl_isr_null() */
1599
1600 /* mgsl_isr_receive_dma()
1601 *
1602 * Service a receive DMA channel interrupt.
1603 * For this driver there are two sources of receive DMA interrupts
1604 * as identified in the Receive DMA mode Register (RDMR):
1605 *
1606 * BIT3 EOA/EOL End of List, all receive buffers in receive
1607 * buffer list have been filled (no more free buffers
1608 * available). The DMA controller has shut down.
1609 *
1610 * BIT2 EOB End of Buffer. This interrupt occurs when a receive
1611 * DMA buffer is terminated in response to completion
1612 * of a good frame or a frame with errors. The status
1613 * of the frame is stored in the buffer entry in the
1614 * list of receive buffer entries.
1615 *
1616 * Arguments: info pointer to device instance data
1617 * Return Value: None
1618 */
1619 static void mgsl_isr_receive_dma( struct mgsl_struct *info )
1620 {
1621 u16 status;
1622
1623 /* clear interrupt pending and IUS bit for Rx DMA IRQ */
1624 usc_OutDmaReg( info, CDIR, BIT9+BIT1 );
1625
1626 /* Read the receive DMA status to identify interrupt type. */
1627 /* This also clears the status bits. */
1628 status = usc_InDmaReg( info, RDMR );
1629
1630 if ( debug_level >= DEBUG_LEVEL_ISR )
1631 printk("%s(%d):mgsl_isr_receive_dma(%s) status=%04X\n",
1632 __FILE__,__LINE__,info->device_name,status);
1633
1634 info->pending_bh |= BH_RECEIVE;
1635
1636 if ( status & BIT3 ) {
1637 info->rx_overflow = 1;
1638 info->icount.buf_overrun++;
1639 }
1640
1641 } /* end of mgsl_isr_receive_dma() */
1642
1643 /* mgsl_isr_transmit_dma()
1644 *
1645 * This function services a transmit DMA channel interrupt.
1646 *
1647 * For this driver there is one source of transmit DMA interrupts
1648 * as identified in the Transmit DMA Mode Register (TDMR):
1649 *
1650 * BIT2 EOB End of Buffer. This interrupt occurs when a
1651 * transmit DMA buffer has been emptied.
1652 *
1653 * The driver maintains enough transmit DMA buffers to hold at least
1654 * one max frame size transmit frame. When operating in a buffered
1655 * transmit mode, there may be enough transmit DMA buffers to hold at
1656 * least two or more max frame size frames. On an EOB condition,
1657 * determine if there are any queued transmit buffers and copy into
1658 * transmit DMA buffers if we have room.
1659 *
1660 * Arguments: info pointer to device instance data
1661 * Return Value: None
1662 */
1663 static void mgsl_isr_transmit_dma( struct mgsl_struct *info )
1664 {
1665 u16 status;
1666
1667 /* clear interrupt pending and IUS bit for Tx DMA IRQ */
1668 usc_OutDmaReg(info, CDIR, BIT8+BIT0 );
1669
1670 /* Read the transmit DMA status to identify interrupt type. */
1671 /* This also clears the status bits. */
1672
1673 status = usc_InDmaReg( info, TDMR );
1674
1675 if ( debug_level >= DEBUG_LEVEL_ISR )
1676 printk("%s(%d):mgsl_isr_transmit_dma(%s) status=%04X\n",
1677 __FILE__,__LINE__,info->device_name,status);
1678
1679 if ( status & BIT2 ) {
1680 --info->tx_dma_buffers_used;
1681
1682 /* if there are transmit frames queued,
1683 * try to load the next one
1684 */
1685 if ( load_next_tx_holding_buffer(info) ) {
1686 /* if call returns non-zero value, we have
1687 * at least one free tx holding buffer
1688 */
1689 info->pending_bh |= BH_TRANSMIT;
1690 }
1691 }
1692
1693 } /* end of mgsl_isr_transmit_dma() */
1694
1695 /* mgsl_interrupt()
1696 *
1697 * Interrupt service routine entry point.
1698 *
1699 * Arguments:
1700 *
1701 * irq interrupt number that caused interrupt
1702 * dev_id device ID supplied during interrupt registration
1703 * regs interrupted processor context
1704 *
1705 * Return Value: None
1706 */
1707 static irqreturn_t mgsl_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1708 {
1709 struct mgsl_struct * info;
1710 u16 UscVector;
1711 u16 DmaVector;
1712
1713 if ( debug_level >= DEBUG_LEVEL_ISR )
1714 printk("%s(%d):mgsl_interrupt(%d)entry.\n",
1715 __FILE__,__LINE__,irq);
1716
1717 info = (struct mgsl_struct *)dev_id;
1718 if (!info)
1719 return IRQ_NONE;
1720
1721 spin_lock(&info->irq_spinlock);
1722
1723 for(;;) {
1724 /* Read the interrupt vectors from hardware. */
1725 UscVector = usc_InReg(info, IVR) >> 9;
1726 DmaVector = usc_InDmaReg(info, DIVR);
1727
1728 if ( debug_level >= DEBUG_LEVEL_ISR )
1729 printk("%s(%d):%s UscVector=%08X DmaVector=%08X\n",
1730 __FILE__,__LINE__,info->device_name,UscVector,DmaVector);
1731
1732 if ( !UscVector && !DmaVector )
1733 break;
1734
1735 /* Dispatch interrupt vector */
1736 if ( UscVector )
1737 (*UscIsrTable[UscVector])(info);
1738 else if ( (DmaVector&(BIT10|BIT9)) == BIT10)
1739 mgsl_isr_transmit_dma(info);
1740 else
1741 mgsl_isr_receive_dma(info);
1742
1743 if ( info->isr_overflow ) {
1744 printk(KERN_ERR"%s(%d):%s isr overflow irq=%d\n",
1745 __FILE__,__LINE__,info->device_name, irq);
1746 usc_DisableMasterIrqBit(info);
1747 usc_DisableDmaInterrupts(info,DICR_MASTER);
1748 break;
1749 }
1750 }
1751
1752 /* Request bottom half processing if there's something
1753 * for it to do and the bh is not already running
1754 */
1755
1756 if ( info->pending_bh && !info->bh_running && !info->bh_requested ) {
1757 if ( debug_level >= DEBUG_LEVEL_ISR )
1758 printk("%s(%d):%s queueing bh task.\n",
1759 __FILE__,__LINE__,info->device_name);
1760 schedule_work(&info->task);
1761 info->bh_requested = 1;
1762 }
1763
1764 spin_unlock(&info->irq_spinlock);
1765
1766 if ( debug_level >= DEBUG_LEVEL_ISR )
1767 printk("%s(%d):mgsl_interrupt(%d)exit.\n",
1768 __FILE__,__LINE__,irq);
1769 return IRQ_HANDLED;
1770 } /* end of mgsl_interrupt() */
1771
1772 /* startup()
1773 *
1774 * Initialize and start device.
1775 *
1776 * Arguments: info pointer to device instance data
1777 * Return Value: 0 if success, otherwise error code
1778 */
1779 static int startup(struct mgsl_struct * info)
1780 {
1781 int retval = 0;
1782
1783 if ( debug_level >= DEBUG_LEVEL_INFO )
1784 printk("%s(%d):mgsl_startup(%s)\n",__FILE__,__LINE__,info->device_name);
1785
1786 if (info->flags & ASYNC_INITIALIZED)
1787 return 0;
1788
1789 if (!info->xmit_buf) {
1790 /* allocate a page of memory for a transmit buffer */
1791 info->xmit_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL);
1792 if (!info->xmit_buf) {
1793 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
1794 __FILE__,__LINE__,info->device_name);
1795 return -ENOMEM;
1796 }
1797 }
1798
1799 info->pending_bh = 0;
1800
1801 memset(&info->icount, 0, sizeof(info->icount));
1802
1803 init_timer(&info->tx_timer);
1804 info->tx_timer.data = (unsigned long)info;
1805 info->tx_timer.function = mgsl_tx_timeout;
1806
1807 /* Allocate and claim adapter resources */
1808 retval = mgsl_claim_resources(info);
1809
1810 /* perform existence check and diagnostics */
1811 if ( !retval )
1812 retval = mgsl_adapter_test(info);
1813
1814 if ( retval ) {
1815 if (capable(CAP_SYS_ADMIN) && info->tty)
1816 set_bit(TTY_IO_ERROR, &info->tty->flags);
1817 mgsl_release_resources(info);
1818 return retval;
1819 }
1820
1821 /* program hardware for current parameters */
1822 mgsl_change_params(info);
1823
1824 if (info->tty)
1825 clear_bit(TTY_IO_ERROR, &info->tty->flags);
1826
1827 info->flags |= ASYNC_INITIALIZED;
1828
1829 return 0;
1830
1831 } /* end of startup() */
1832
1833 /* shutdown()
1834 *
1835 * Called by mgsl_close() and mgsl_hangup() to shutdown hardware
1836 *
1837 * Arguments: info pointer to device instance data
1838 * Return Value: None
1839 */
1840 static void shutdown(struct mgsl_struct * info)
1841 {
1842 unsigned long flags;
1843
1844 if (!(info->flags & ASYNC_INITIALIZED))
1845 return;
1846
1847 if (debug_level >= DEBUG_LEVEL_INFO)
1848 printk("%s(%d):mgsl_shutdown(%s)\n",
1849 __FILE__,__LINE__, info->device_name );
1850
1851 /* clear status wait queue because status changes */
1852 /* can't happen after shutting down the hardware */
1853 wake_up_interruptible(&info->status_event_wait_q);
1854 wake_up_interruptible(&info->event_wait_q);
1855
1856 del_timer(&info->tx_timer);
1857
1858 if (info->xmit_buf) {
1859 free_page((unsigned long) info->xmit_buf);
1860 info->xmit_buf = NULL;
1861 }
1862
1863 spin_lock_irqsave(&info->irq_spinlock,flags);
1864 usc_DisableMasterIrqBit(info);
1865 usc_stop_receiver(info);
1866 usc_stop_transmitter(info);
1867 usc_DisableInterrupts(info,RECEIVE_DATA + RECEIVE_STATUS +
1868 TRANSMIT_DATA + TRANSMIT_STATUS + IO_PIN + MISC );
1869 usc_DisableDmaInterrupts(info,DICR_MASTER + DICR_TRANSMIT + DICR_RECEIVE);
1870
1871 /* Disable DMAEN (Port 7, Bit 14) */
1872 /* This disconnects the DMA request signal from the ISA bus */
1873 /* on the ISA adapter. This has no effect for the PCI adapter */
1874 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) | BIT14));
1875
1876 /* Disable INTEN (Port 6, Bit12) */
1877 /* This disconnects the IRQ request signal to the ISA bus */
1878 /* on the ISA adapter. This has no effect for the PCI adapter */
1879 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) | BIT12));
1880
1881 if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
1882 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
1883 usc_set_serial_signals(info);
1884 }
1885
1886 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1887
1888 mgsl_release_resources(info);
1889
1890 if (info->tty)
1891 set_bit(TTY_IO_ERROR, &info->tty->flags);
1892
1893 info->flags &= ~ASYNC_INITIALIZED;
1894
1895 } /* end of shutdown() */
1896
1897 static void mgsl_program_hw(struct mgsl_struct *info)
1898 {
1899 unsigned long flags;
1900
1901 spin_lock_irqsave(&info->irq_spinlock,flags);
1902
1903 usc_stop_receiver(info);
1904 usc_stop_transmitter(info);
1905 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1906
1907 if (info->params.mode == MGSL_MODE_HDLC ||
1908 info->params.mode == MGSL_MODE_RAW ||
1909 info->netcount)
1910 usc_set_sync_mode(info);
1911 else
1912 usc_set_async_mode(info);
1913
1914 usc_set_serial_signals(info);
1915
1916 info->dcd_chkcount = 0;
1917 info->cts_chkcount = 0;
1918 info->ri_chkcount = 0;
1919 info->dsr_chkcount = 0;
1920
1921 usc_EnableStatusIrqs(info,SICR_CTS+SICR_DSR+SICR_DCD+SICR_RI);
1922 usc_EnableInterrupts(info, IO_PIN);
1923 usc_get_serial_signals(info);
1924
1925 if (info->netcount || info->tty->termios->c_cflag & CREAD)
1926 usc_start_receiver(info);
1927
1928 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1929 }
1930
1931 /* Reconfigure adapter based on new parameters
1932 */
1933 static void mgsl_change_params(struct mgsl_struct *info)
1934 {
1935 unsigned cflag;
1936 int bits_per_char;
1937
1938 if (!info->tty || !info->tty->termios)
1939 return;
1940
1941 if (debug_level >= DEBUG_LEVEL_INFO)
1942 printk("%s(%d):mgsl_change_params(%s)\n",
1943 __FILE__,__LINE__, info->device_name );
1944
1945 cflag = info->tty->termios->c_cflag;
1946
1947 /* if B0 rate (hangup) specified then negate DTR and RTS */
1948 /* otherwise assert DTR and RTS */
1949 if (cflag & CBAUD)
1950 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1951 else
1952 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
1953
1954 /* byte size and parity */
1955
1956 switch (cflag & CSIZE) {
1957 case CS5: info->params.data_bits = 5; break;
1958 case CS6: info->params.data_bits = 6; break;
1959 case CS7: info->params.data_bits = 7; break;
1960 case CS8: info->params.data_bits = 8; break;
1961 /* Never happens, but GCC is too dumb to figure it out */
1962 default: info->params.data_bits = 7; break;
1963 }
1964
1965 if (cflag & CSTOPB)
1966 info->params.stop_bits = 2;
1967 else
1968 info->params.stop_bits = 1;
1969
1970 info->params.parity = ASYNC_PARITY_NONE;
1971 if (cflag & PARENB) {
1972 if (cflag & PARODD)
1973 info->params.parity = ASYNC_PARITY_ODD;
1974 else
1975 info->params.parity = ASYNC_PARITY_EVEN;
1976 #ifdef CMSPAR
1977 if (cflag & CMSPAR)
1978 info->params.parity = ASYNC_PARITY_SPACE;
1979 #endif
1980 }
1981
1982 /* calculate number of jiffies to transmit a full
1983 * FIFO (32 bytes) at specified data rate
1984 */
1985 bits_per_char = info->params.data_bits +
1986 info->params.stop_bits + 1;
1987
1988 /* if port data rate is set to 460800 or less then
1989 * allow tty settings to override, otherwise keep the
1990 * current data rate.
1991 */
1992 if (info->params.data_rate <= 460800)
1993 info->params.data_rate = tty_get_baud_rate(info->tty);
1994
1995 if ( info->params.data_rate ) {
1996 info->timeout = (32*HZ*bits_per_char) /
1997 info->params.data_rate;
1998 }
1999 info->timeout += HZ/50; /* Add .02 seconds of slop */
2000
2001 if (cflag & CRTSCTS)
2002 info->flags |= ASYNC_CTS_FLOW;
2003 else
2004 info->flags &= ~ASYNC_CTS_FLOW;
2005
2006 if (cflag & CLOCAL)
2007 info->flags &= ~ASYNC_CHECK_CD;
2008 else
2009 info->flags |= ASYNC_CHECK_CD;
2010
2011 /* process tty input control flags */
2012
2013 info->read_status_mask = RXSTATUS_OVERRUN;
2014 if (I_INPCK(info->tty))
2015 info->read_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
2016 if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
2017 info->read_status_mask |= RXSTATUS_BREAK_RECEIVED;
2018
2019 if (I_IGNPAR(info->tty))
2020 info->ignore_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
2021 if (I_IGNBRK(info->tty)) {
2022 info->ignore_status_mask |= RXSTATUS_BREAK_RECEIVED;
2023 /* If ignoring parity and break indicators, ignore
2024 * overruns too. (For real raw support).
2025 */
2026 if (I_IGNPAR(info->tty))
2027 info->ignore_status_mask |= RXSTATUS_OVERRUN;
2028 }
2029
2030 mgsl_program_hw(info);
2031
2032 } /* end of mgsl_change_params() */
2033
2034 /* mgsl_put_char()
2035 *
2036 * Add a character to the transmit buffer.
2037 *
2038 * Arguments: tty pointer to tty information structure
2039 * ch character to add to transmit buffer
2040 *
2041 * Return Value: None
2042 */
2043 static void mgsl_put_char(struct tty_struct *tty, unsigned char ch)
2044 {
2045 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2046 unsigned long flags;
2047
2048 if ( debug_level >= DEBUG_LEVEL_INFO ) {
2049 printk( "%s(%d):mgsl_put_char(%d) on %s\n",
2050 __FILE__,__LINE__,ch,info->device_name);
2051 }
2052
2053 if (mgsl_paranoia_check(info, tty->name, "mgsl_put_char"))
2054 return;
2055
2056 if (!tty || !info->xmit_buf)
2057 return;
2058
2059 spin_lock_irqsave(&info->irq_spinlock,flags);
2060
2061 if ( (info->params.mode == MGSL_MODE_ASYNC ) || !info->tx_active ) {
2062
2063 if (info->xmit_cnt < SERIAL_XMIT_SIZE - 1) {
2064 info->xmit_buf[info->xmit_head++] = ch;
2065 info->xmit_head &= SERIAL_XMIT_SIZE-1;
2066 info->xmit_cnt++;
2067 }
2068 }
2069
2070 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2071
2072 } /* end of mgsl_put_char() */
2073
2074 /* mgsl_flush_chars()
2075 *
2076 * Enable transmitter so remaining characters in the
2077 * transmit buffer are sent.
2078 *
2079 * Arguments: tty pointer to tty information structure
2080 * Return Value: None
2081 */
2082 static void mgsl_flush_chars(struct tty_struct *tty)
2083 {
2084 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2085 unsigned long flags;
2086
2087 if ( debug_level >= DEBUG_LEVEL_INFO )
2088 printk( "%s(%d):mgsl_flush_chars() entry on %s xmit_cnt=%d\n",
2089 __FILE__,__LINE__,info->device_name,info->xmit_cnt);
2090
2091 if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_chars"))
2092 return;
2093
2094 if (info->xmit_cnt <= 0 || tty->stopped || tty->hw_stopped ||
2095 !info->xmit_buf)
2096 return;
2097
2098 if ( debug_level >= DEBUG_LEVEL_INFO )
2099 printk( "%s(%d):mgsl_flush_chars() entry on %s starting transmitter\n",
2100 __FILE__,__LINE__,info->device_name );
2101
2102 spin_lock_irqsave(&info->irq_spinlock,flags);
2103
2104 if (!info->tx_active) {
2105 if ( (info->params.mode == MGSL_MODE_HDLC ||
2106 info->params.mode == MGSL_MODE_RAW) && info->xmit_cnt ) {
2107 /* operating in synchronous (frame oriented) mode */
2108 /* copy data from circular xmit_buf to */
2109 /* transmit DMA buffer. */
2110 mgsl_load_tx_dma_buffer(info,
2111 info->xmit_buf,info->xmit_cnt);
2112 }
2113 usc_start_transmitter(info);
2114 }
2115
2116 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2117
2118 } /* end of mgsl_flush_chars() */
2119
2120 /* mgsl_write()
2121 *
2122 * Send a block of data
2123 *
2124 * Arguments:
2125 *
2126 * tty pointer to tty information structure
2127 * buf pointer to buffer containing send data
2128 * count size of send data in bytes
2129 *
2130 * Return Value: number of characters written
2131 */
2132 static int mgsl_write(struct tty_struct * tty,
2133 const unsigned char *buf, int count)
2134 {
2135 int c, ret = 0;
2136 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2137 unsigned long flags;
2138
2139 if ( debug_level >= DEBUG_LEVEL_INFO )
2140 printk( "%s(%d):mgsl_write(%s) count=%d\n",
2141 __FILE__,__LINE__,info->device_name,count);
2142
2143 if (mgsl_paranoia_check(info, tty->name, "mgsl_write"))
2144 goto cleanup;
2145
2146 if (!tty || !info->xmit_buf)
2147 goto cleanup;
2148
2149 if ( info->params.mode == MGSL_MODE_HDLC ||
2150 info->params.mode == MGSL_MODE_RAW ) {
2151 /* operating in synchronous (frame oriented) mode */
2152 /* operating in synchronous (frame oriented) mode */
2153 if (info->tx_active) {
2154
2155 if ( info->params.mode == MGSL_MODE_HDLC ) {
2156 ret = 0;
2157 goto cleanup;
2158 }
2159 /* transmitter is actively sending data -
2160 * if we have multiple transmit dma and
2161 * holding buffers, attempt to queue this
2162 * frame for transmission at a later time.
2163 */
2164 if (info->tx_holding_count >= info->num_tx_holding_buffers ) {
2165 /* no tx holding buffers available */
2166 ret = 0;
2167 goto cleanup;
2168 }
2169
2170 /* queue transmit frame request */
2171 ret = count;
2172 save_tx_buffer_request(info,buf,count);
2173
2174 /* if we have sufficient tx dma buffers,
2175 * load the next buffered tx request
2176 */
2177 spin_lock_irqsave(&info->irq_spinlock,flags);
2178 load_next_tx_holding_buffer(info);
2179 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2180 goto cleanup;
2181 }
2182
2183 /* if operating in HDLC LoopMode and the adapter */
2184 /* has yet to be inserted into the loop, we can't */
2185 /* transmit */
2186
2187 if ( (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) &&
2188 !usc_loopmode_active(info) )
2189 {
2190 ret = 0;
2191 goto cleanup;
2192 }
2193
2194 if ( info->xmit_cnt ) {
2195 /* Send accumulated from send_char() calls */
2196 /* as frame and wait before accepting more data. */
2197 ret = 0;
2198
2199 /* copy data from circular xmit_buf to */
2200 /* transmit DMA buffer. */
2201 mgsl_load_tx_dma_buffer(info,
2202 info->xmit_buf,info->xmit_cnt);
2203 if ( debug_level >= DEBUG_LEVEL_INFO )
2204 printk( "%s(%d):mgsl_write(%s) sync xmit_cnt flushing\n",
2205 __FILE__,__LINE__,info->device_name);
2206 } else {
2207 if ( debug_level >= DEBUG_LEVEL_INFO )
2208 printk( "%s(%d):mgsl_write(%s) sync transmit accepted\n",
2209 __FILE__,__LINE__,info->device_name);
2210 ret = count;
2211 info->xmit_cnt = count;
2212 mgsl_load_tx_dma_buffer(info,buf,count);
2213 }
2214 } else {
2215 while (1) {
2216 spin_lock_irqsave(&info->irq_spinlock,flags);
2217 c = min_t(int, count,
2218 min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
2219 SERIAL_XMIT_SIZE - info->xmit_head));
2220 if (c <= 0) {
2221 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2222 break;
2223 }
2224 memcpy(info->xmit_buf + info->xmit_head, buf, c);
2225 info->xmit_head = ((info->xmit_head + c) &
2226 (SERIAL_XMIT_SIZE-1));
2227 info->xmit_cnt += c;
2228 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2229 buf += c;
2230 count -= c;
2231 ret += c;
2232 }
2233 }
2234
2235 if (info->xmit_cnt && !tty->stopped && !tty->hw_stopped) {
2236 spin_lock_irqsave(&info->irq_spinlock,flags);
2237 if (!info->tx_active)
2238 usc_start_transmitter(info);
2239 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2240 }
2241 cleanup:
2242 if ( debug_level >= DEBUG_LEVEL_INFO )
2243 printk( "%s(%d):mgsl_write(%s) returning=%d\n",
2244 __FILE__,__LINE__,info->device_name,ret);
2245
2246 return ret;
2247
2248 } /* end of mgsl_write() */
2249
2250 /* mgsl_write_room()
2251 *
2252 * Return the count of free bytes in transmit buffer
2253 *
2254 * Arguments: tty pointer to tty info structure
2255 * Return Value: None
2256 */
2257 static int mgsl_write_room(struct tty_struct *tty)
2258 {
2259 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2260 int ret;
2261
2262 if (mgsl_paranoia_check(info, tty->name, "mgsl_write_room"))
2263 return 0;
2264 ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1;
2265 if (ret < 0)
2266 ret = 0;
2267
2268 if (debug_level >= DEBUG_LEVEL_INFO)
2269 printk("%s(%d):mgsl_write_room(%s)=%d\n",
2270 __FILE__,__LINE__, info->device_name,ret );
2271
2272 if ( info->params.mode == MGSL_MODE_HDLC ||
2273 info->params.mode == MGSL_MODE_RAW ) {
2274 /* operating in synchronous (frame oriented) mode */
2275 if ( info->tx_active )
2276 return 0;
2277 else
2278 return HDLC_MAX_FRAME_SIZE;
2279 }
2280
2281 return ret;
2282
2283 } /* end of mgsl_write_room() */
2284
2285 /* mgsl_chars_in_buffer()
2286 *
2287 * Return the count of bytes in transmit buffer
2288 *
2289 * Arguments: tty pointer to tty info structure
2290 * Return Value: None
2291 */
2292 static int mgsl_chars_in_buffer(struct tty_struct *tty)
2293 {
2294 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2295
2296 if (debug_level >= DEBUG_LEVEL_INFO)
2297 printk("%s(%d):mgsl_chars_in_buffer(%s)\n",
2298 __FILE__,__LINE__, info->device_name );
2299
2300 if (mgsl_paranoia_check(info, tty->name, "mgsl_chars_in_buffer"))
2301 return 0;
2302
2303 if (debug_level >= DEBUG_LEVEL_INFO)
2304 printk("%s(%d):mgsl_chars_in_buffer(%s)=%d\n",
2305 __FILE__,__LINE__, info->device_name,info->xmit_cnt );
2306
2307 if ( info->params.mode == MGSL_MODE_HDLC ||
2308 info->params.mode == MGSL_MODE_RAW ) {
2309 /* operating in synchronous (frame oriented) mode */
2310 if ( info->tx_active )
2311 return info->max_frame_size;
2312 else
2313 return 0;
2314 }
2315
2316 return info->xmit_cnt;
2317 } /* end of mgsl_chars_in_buffer() */
2318
2319 /* mgsl_flush_buffer()
2320 *
2321 * Discard all data in the send buffer
2322 *
2323 * Arguments: tty pointer to tty info structure
2324 * Return Value: None
2325 */
2326 static void mgsl_flush_buffer(struct tty_struct *tty)
2327 {
2328 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2329 unsigned long flags;
2330
2331 if (debug_level >= DEBUG_LEVEL_INFO)
2332 printk("%s(%d):mgsl_flush_buffer(%s) entry\n",
2333 __FILE__,__LINE__, info->device_name );
2334
2335 if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_buffer"))
2336 return;
2337
2338 spin_lock_irqsave(&info->irq_spinlock,flags);
2339 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
2340 del_timer(&info->tx_timer);
2341 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2342
2343 wake_up_interruptible(&tty->write_wait);
2344 tty_wakeup(tty);
2345 }
2346
2347 /* mgsl_send_xchar()
2348 *
2349 * Send a high-priority XON/XOFF character
2350 *
2351 * Arguments: tty pointer to tty info structure
2352 * ch character to send
2353 * Return Value: None
2354 */
2355 static void mgsl_send_xchar(struct tty_struct *tty, char ch)
2356 {
2357 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2358 unsigned long flags;
2359
2360 if (debug_level >= DEBUG_LEVEL_INFO)
2361 printk("%s(%d):mgsl_send_xchar(%s,%d)\n",
2362 __FILE__,__LINE__, info->device_name, ch );
2363
2364 if (mgsl_paranoia_check(info, tty->name, "mgsl_send_xchar"))
2365 return;
2366
2367 info->x_char = ch;
2368 if (ch) {
2369 /* Make sure transmit interrupts are on */
2370 spin_lock_irqsave(&info->irq_spinlock,flags);
2371 if (!info->tx_enabled)
2372 usc_start_transmitter(info);
2373 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2374 }
2375 } /* end of mgsl_send_xchar() */
2376
2377 /* mgsl_throttle()
2378 *
2379 * Signal remote device to throttle send data (our receive data)
2380 *
2381 * Arguments: tty pointer to tty info structure
2382 * Return Value: None
2383 */
2384 static void mgsl_throttle(struct tty_struct * tty)
2385 {
2386 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2387 unsigned long flags;
2388
2389 if (debug_level >= DEBUG_LEVEL_INFO)
2390 printk("%s(%d):mgsl_throttle(%s) entry\n",
2391 __FILE__,__LINE__, info->device_name );
2392
2393 if (mgsl_paranoia_check(info, tty->name, "mgsl_throttle"))
2394 return;
2395
2396 if (I_IXOFF(tty))
2397 mgsl_send_xchar(tty, STOP_CHAR(tty));
2398
2399 if (tty->termios->c_cflag & CRTSCTS) {
2400 spin_lock_irqsave(&info->irq_spinlock,flags);
2401 info->serial_signals &= ~SerialSignal_RTS;
2402 usc_set_serial_signals(info);
2403 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2404 }
2405 } /* end of mgsl_throttle() */
2406
2407 /* mgsl_unthrottle()
2408 *
2409 * Signal remote device to stop throttling send data (our receive data)
2410 *
2411 * Arguments: tty pointer to tty info structure
2412 * Return Value: None
2413 */
2414 static void mgsl_unthrottle(struct tty_struct * tty)
2415 {
2416 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2417 unsigned long flags;
2418
2419 if (debug_level >= DEBUG_LEVEL_INFO)
2420 printk("%s(%d):mgsl_unthrottle(%s) entry\n",
2421 __FILE__,__LINE__, info->device_name );
2422
2423 if (mgsl_paranoia_check(info, tty->name, "mgsl_unthrottle"))
2424 return;
2425
2426 if (I_IXOFF(tty)) {
2427 if (info->x_char)
2428 info->x_char = 0;
2429 else
2430 mgsl_send_xchar(tty, START_CHAR(tty));
2431 }
2432
2433 if (tty->termios->c_cflag & CRTSCTS) {
2434 spin_lock_irqsave(&info->irq_spinlock,flags);
2435 info->serial_signals |= SerialSignal_RTS;
2436 usc_set_serial_signals(info);
2437 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2438 }
2439
2440 } /* end of mgsl_unthrottle() */
2441
2442 /* mgsl_get_stats()
2443 *
2444 * get the current serial parameters information
2445 *
2446 * Arguments: info pointer to device instance data
2447 * user_icount pointer to buffer to hold returned stats
2448 *
2449 * Return Value: 0 if success, otherwise error code
2450 */
2451 static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount __user *user_icount)
2452 {
2453 int err;
2454
2455 if (debug_level >= DEBUG_LEVEL_INFO)
2456 printk("%s(%d):mgsl_get_params(%s)\n",
2457 __FILE__,__LINE__, info->device_name);
2458
2459 if (!user_icount) {
2460 memset(&info->icount, 0, sizeof(info->icount));
2461 } else {
2462 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2463 if (err)
2464 return -EFAULT;
2465 }
2466
2467 return 0;
2468
2469 } /* end of mgsl_get_stats() */
2470
2471 /* mgsl_get_params()
2472 *
2473 * get the current serial parameters information
2474 *
2475 * Arguments: info pointer to device instance data
2476 * user_params pointer to buffer to hold returned params
2477 *
2478 * Return Value: 0 if success, otherwise error code
2479 */
2480 static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params)
2481 {
2482 int err;
2483 if (debug_level >= DEBUG_LEVEL_INFO)
2484 printk("%s(%d):mgsl_get_params(%s)\n",
2485 __FILE__,__LINE__, info->device_name);
2486
2487 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2488 if (err) {
2489 if ( debug_level >= DEBUG_LEVEL_INFO )
2490 printk( "%s(%d):mgsl_get_params(%s) user buffer copy failed\n",
2491 __FILE__,__LINE__,info->device_name);
2492 return -EFAULT;
2493 }
2494
2495 return 0;
2496
2497 } /* end of mgsl_get_params() */
2498
2499 /* mgsl_set_params()
2500 *
2501 * set the serial parameters
2502 *
2503 * Arguments:
2504 *
2505 * info pointer to device instance data
2506 * new_params user buffer containing new serial params
2507 *
2508 * Return Value: 0 if success, otherwise error code
2509 */
2510 static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params)
2511 {
2512 unsigned long flags;
2513 MGSL_PARAMS tmp_params;
2514 int err;
2515
2516 if (debug_level >= DEBUG_LEVEL_INFO)
2517 printk("%s(%d):mgsl_set_params %s\n", __FILE__,__LINE__,
2518 info->device_name );
2519 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2520 if (err) {
2521 if ( debug_level >= DEBUG_LEVEL_INFO )
2522 printk( "%s(%d):mgsl_set_params(%s) user buffer copy failed\n",
2523 __FILE__,__LINE__,info->device_name);
2524 return -EFAULT;
2525 }
2526
2527 spin_lock_irqsave(&info->irq_spinlock,flags);
2528 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2529 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2530
2531 mgsl_change_params(info);
2532
2533 return 0;
2534
2535 } /* end of mgsl_set_params() */
2536
2537 /* mgsl_get_txidle()
2538 *
2539 * get the current transmit idle mode
2540 *
2541 * Arguments: info pointer to device instance data
2542 * idle_mode pointer to buffer to hold returned idle mode
2543 *
2544 * Return Value: 0 if success, otherwise error code
2545 */
2546 static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode)
2547 {
2548 int err;
2549
2550 if (debug_level >= DEBUG_LEVEL_INFO)
2551 printk("%s(%d):mgsl_get_txidle(%s)=%d\n",
2552 __FILE__,__LINE__, info->device_name, info->idle_mode);
2553
2554 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2555 if (err) {
2556 if ( debug_level >= DEBUG_LEVEL_INFO )
2557 printk( "%s(%d):mgsl_get_txidle(%s) user buffer copy failed\n",
2558 __FILE__,__LINE__,info->device_name);
2559 return -EFAULT;
2560 }
2561
2562 return 0;
2563
2564 } /* end of mgsl_get_txidle() */
2565
2566 /* mgsl_set_txidle() service ioctl to set transmit idle mode
2567 *
2568 * Arguments: info pointer to device instance data
2569 * idle_mode new idle mode
2570 *
2571 * Return Value: 0 if success, otherwise error code
2572 */
2573 static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode)
2574 {
2575 unsigned long flags;
2576
2577 if (debug_level >= DEBUG_LEVEL_INFO)
2578 printk("%s(%d):mgsl_set_txidle(%s,%d)\n", __FILE__,__LINE__,
2579 info->device_name, idle_mode );
2580
2581 spin_lock_irqsave(&info->irq_spinlock,flags);
2582 info->idle_mode = idle_mode;
2583 usc_set_txidle( info );
2584 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2585 return 0;
2586
2587 } /* end of mgsl_set_txidle() */
2588
2589 /* mgsl_txenable()
2590 *
2591 * enable or disable the transmitter
2592 *
2593 * Arguments:
2594 *
2595 * info pointer to device instance data
2596 * enable 1 = enable, 0 = disable
2597 *
2598 * Return Value: 0 if success, otherwise error code
2599 */
2600 static int mgsl_txenable(struct mgsl_struct * info, int enable)
2601 {
2602 unsigned long flags;
2603
2604 if (debug_level >= DEBUG_LEVEL_INFO)
2605 printk("%s(%d):mgsl_txenable(%s,%d)\n", __FILE__,__LINE__,
2606 info->device_name, enable);
2607
2608 spin_lock_irqsave(&info->irq_spinlock,flags);
2609 if ( enable ) {
2610 if ( !info->tx_enabled ) {
2611
2612 usc_start_transmitter(info);
2613 /*--------------------------------------------------
2614 * if HDLC/SDLC Loop mode, attempt to insert the
2615 * station in the 'loop' by setting CMR:13. Upon
2616 * receipt of the next GoAhead (RxAbort) sequence,
2617 * the OnLoop indicator (CCSR:7) should go active
2618 * to indicate that we are on the loop
2619 *--------------------------------------------------*/
2620 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2621 usc_loopmode_insert_request( info );
2622 }
2623 } else {
2624 if ( info->tx_enabled )
2625 usc_stop_transmitter(info);
2626 }
2627 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2628 return 0;
2629
2630 } /* end of mgsl_txenable() */
2631
2632 /* mgsl_txabort() abort send HDLC frame
2633 *
2634 * Arguments: info pointer to device instance data
2635 * Return Value: 0 if success, otherwise error code
2636 */
2637 static int mgsl_txabort(struct mgsl_struct * info)
2638 {
2639 unsigned long flags;
2640
2641 if (debug_level >= DEBUG_LEVEL_INFO)
2642 printk("%s(%d):mgsl_txabort(%s)\n", __FILE__,__LINE__,
2643 info->device_name);
2644
2645 spin_lock_irqsave(&info->irq_spinlock,flags);
2646 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC )
2647 {
2648 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2649 usc_loopmode_cancel_transmit( info );
2650 else
2651 usc_TCmd(info,TCmd_SendAbort);
2652 }
2653 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2654 return 0;
2655
2656 } /* end of mgsl_txabort() */
2657
2658 /* mgsl_rxenable() enable or disable the receiver
2659 *
2660 * Arguments: info pointer to device instance data
2661 * enable 1 = enable, 0 = disable
2662 * Return Value: 0 if success, otherwise error code
2663 */
2664 static int mgsl_rxenable(struct mgsl_struct * info, int enable)
2665 {
2666 unsigned long flags;
2667
2668 if (debug_level >= DEBUG_LEVEL_INFO)
2669 printk("%s(%d):mgsl_rxenable(%s,%d)\n", __FILE__,__LINE__,
2670 info->device_name, enable);
2671
2672 spin_lock_irqsave(&info->irq_spinlock,flags);
2673 if ( enable ) {
2674 if ( !info->rx_enabled )
2675 usc_start_receiver(info);
2676 } else {
2677 if ( info->rx_enabled )
2678 usc_stop_receiver(info);
2679 }
2680 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2681 return 0;
2682
2683 } /* end of mgsl_rxenable() */
2684
2685 /* mgsl_wait_event() wait for specified event to occur
2686 *
2687 * Arguments: info pointer to device instance data
2688 * mask pointer to bitmask of events to wait for
2689 * Return Value: 0 if successful and bit mask updated with
2690 * of events triggerred,
2691 * otherwise error code
2692 */
2693 static int mgsl_wait_event(struct mgsl_struct * info, int __user * mask_ptr)
2694 {
2695 unsigned long flags;
2696 int s;
2697 int rc=0;
2698 struct mgsl_icount cprev, cnow;
2699 int events;
2700 int mask;
2701 struct _input_signal_events oldsigs, newsigs;
2702 DECLARE_WAITQUEUE(wait, current);
2703
2704 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
2705 if (rc) {
2706 return -EFAULT;
2707 }
2708
2709 if (debug_level >= DEBUG_LEVEL_INFO)
2710 printk("%s(%d):mgsl_wait_event(%s,%d)\n", __FILE__,__LINE__,
2711 info->device_name, mask);
2712
2713 spin_lock_irqsave(&info->irq_spinlock,flags);
2714
2715 /* return immediately if state matches requested events */
2716 usc_get_serial_signals(info);
2717 s = info->serial_signals;
2718 events = mask &
2719 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2720 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2721 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2722 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2723 if (events) {
2724 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2725 goto exit;
2726 }
2727
2728 /* save current irq counts */
2729 cprev = info->icount;
2730 oldsigs = info->input_signal_events;
2731
2732 /* enable hunt and idle irqs if needed */
2733 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2734 u16 oldreg = usc_InReg(info,RICR);
2735 u16 newreg = oldreg +
2736 (mask & MgslEvent_ExitHuntMode ? RXSTATUS_EXITED_HUNT:0) +
2737 (mask & MgslEvent_IdleReceived ? RXSTATUS_IDLE_RECEIVED:0);
2738 if (oldreg != newreg)
2739 usc_OutReg(info, RICR, newreg);
2740 }
2741
2742 set_current_state(TASK_INTERRUPTIBLE);
2743 add_wait_queue(&info->event_wait_q, &wait);
2744
2745 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2746
2747
2748 for(;;) {
2749 schedule();
2750 if (signal_pending(current)) {
2751 rc = -ERESTARTSYS;
2752 break;
2753 }
2754
2755 /* get current irq counts */
2756 spin_lock_irqsave(&info->irq_spinlock,flags);
2757 cnow = info->icount;
2758 newsigs = info->input_signal_events;
2759 set_current_state(TASK_INTERRUPTIBLE);
2760 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2761
2762 /* if no change, wait aborted for some reason */
2763 if (newsigs.dsr_up == oldsigs.dsr_up &&
2764 newsigs.dsr_down == oldsigs.dsr_down &&
2765 newsigs.dcd_up == oldsigs.dcd_up &&
2766 newsigs.dcd_down == oldsigs.dcd_down &&
2767 newsigs.cts_up == oldsigs.cts_up &&
2768 newsigs.cts_down == oldsigs.cts_down &&
2769 newsigs.ri_up == oldsigs.ri_up &&
2770 newsigs.ri_down == oldsigs.ri_down &&
2771 cnow.exithunt == cprev.exithunt &&
2772 cnow.rxidle == cprev.rxidle) {
2773 rc = -EIO;
2774 break;
2775 }
2776
2777 events = mask &
2778 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2779 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2780 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2781 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2782 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2783 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2784 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2785 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2786 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2787 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2788 if (events)
2789 break;
2790
2791 cprev = cnow;
2792 oldsigs = newsigs;
2793 }
2794
2795 remove_wait_queue(&info->event_wait_q, &wait);
2796 set_current_state(TASK_RUNNING);
2797
2798 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2799 spin_lock_irqsave(&info->irq_spinlock,flags);
2800 if (!waitqueue_active(&info->event_wait_q)) {
2801 /* disable enable exit hunt mode/idle rcvd IRQs */
2802 usc_OutReg(info, RICR, usc_InReg(info,RICR) &
2803 ~(RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED));
2804 }
2805 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2806 }
2807 exit:
2808 if ( rc == 0 )
2809 PUT_USER(rc, events, mask_ptr);
2810
2811 return rc;
2812
2813 } /* end of mgsl_wait_event() */
2814
2815 static int modem_input_wait(struct mgsl_struct *info,int arg)
2816 {
2817 unsigned long flags;
2818 int rc;
2819 struct mgsl_icount cprev, cnow;
2820 DECLARE_WAITQUEUE(wait, current);
2821
2822 /* save current irq counts */
2823 spin_lock_irqsave(&info->irq_spinlock,flags);
2824 cprev = info->icount;
2825 add_wait_queue(&info->status_event_wait_q, &wait);
2826 set_current_state(TASK_INTERRUPTIBLE);
2827 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2828
2829 for(;;) {
2830 schedule();
2831 if (signal_pending(current)) {
2832 rc = -ERESTARTSYS;
2833 break;
2834 }
2835
2836 /* get new irq counts */
2837 spin_lock_irqsave(&info->irq_spinlock,flags);
2838 cnow = info->icount;
2839 set_current_state(TASK_INTERRUPTIBLE);
2840 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2841
2842 /* if no change, wait aborted for some reason */
2843 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
2844 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
2845 rc = -EIO;
2846 break;
2847 }
2848
2849 /* check for change in caller specified modem input */
2850 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
2851 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
2852 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
2853 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
2854 rc = 0;
2855 break;
2856 }
2857
2858 cprev = cnow;
2859 }
2860 remove_wait_queue(&info->status_event_wait_q, &wait);
2861 set_current_state(TASK_RUNNING);
2862 return rc;
2863 }
2864
2865 /* return the state of the serial control and status signals
2866 */
2867 static int tiocmget(struct tty_struct *tty, struct file *file)
2868 {
2869 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2870 unsigned int result;
2871 unsigned long flags;
2872
2873 spin_lock_irqsave(&info->irq_spinlock,flags);
2874 usc_get_serial_signals(info);
2875 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2876
2877 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
2878 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
2879 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
2880 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
2881 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
2882 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
2883
2884 if (debug_level >= DEBUG_LEVEL_INFO)
2885 printk("%s(%d):%s tiocmget() value=%08X\n",
2886 __FILE__,__LINE__, info->device_name, result );
2887 return result;
2888 }
2889
2890 /* set modem control signals (DTR/RTS)
2891 */
2892 static int tiocmset(struct tty_struct *tty, struct file *file,
2893 unsigned int set, unsigned int clear)
2894 {
2895 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2896 unsigned long flags;
2897
2898 if (debug_level >= DEBUG_LEVEL_INFO)
2899 printk("%s(%d):%s tiocmset(%x,%x)\n",
2900 __FILE__,__LINE__,info->device_name, set, clear);
2901
2902 if (set & TIOCM_RTS)
2903 info->serial_signals |= SerialSignal_RTS;
2904 if (set & TIOCM_DTR)
2905 info->serial_signals |= SerialSignal_DTR;
2906 if (clear & TIOCM_RTS)
2907 info->serial_signals &= ~SerialSignal_RTS;
2908 if (clear & TIOCM_DTR)
2909 info->serial_signals &= ~SerialSignal_DTR;
2910
2911 spin_lock_irqsave(&info->irq_spinlock,flags);
2912 usc_set_serial_signals(info);
2913 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2914
2915 return 0;
2916 }
2917
2918 /* mgsl_break() Set or clear transmit break condition
2919 *
2920 * Arguments: tty pointer to tty instance data
2921 * break_state -1=set break condition, 0=clear
2922 * Return Value: None
2923 */
2924 static void mgsl_break(struct tty_struct *tty, int break_state)
2925 {
2926 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
2927 unsigned long flags;
2928
2929 if (debug_level >= DEBUG_LEVEL_INFO)
2930 printk("%s(%d):mgsl_break(%s,%d)\n",
2931 __FILE__,__LINE__, info->device_name, break_state);
2932
2933 if (mgsl_paranoia_check(info, tty->name, "mgsl_break"))
2934 return;
2935
2936 spin_lock_irqsave(&info->irq_spinlock,flags);
2937 if (break_state == -1)
2938 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) | BIT7));
2939 else
2940 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) & ~BIT7));
2941 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2942
2943 } /* end of mgsl_break() */
2944
2945 /* mgsl_ioctl() Service an IOCTL request
2946 *
2947 * Arguments:
2948 *
2949 * tty pointer to tty instance data
2950 * file pointer to associated file object for device
2951 * cmd IOCTL command code
2952 * arg command argument/context
2953 *
2954 * Return Value: 0 if success, otherwise error code
2955 */
2956 static int mgsl_ioctl(struct tty_struct *tty, struct file * file,
2957 unsigned int cmd, unsigned long arg)
2958 {
2959 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
2960
2961 if (debug_level >= DEBUG_LEVEL_INFO)
2962 printk("%s(%d):mgsl_ioctl %s cmd=%08X\n", __FILE__,__LINE__,
2963 info->device_name, cmd );
2964
2965 if (mgsl_paranoia_check(info, tty->name, "mgsl_ioctl"))
2966 return -ENODEV;
2967
2968 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
2969 (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
2970 if (tty->flags & (1 << TTY_IO_ERROR))
2971 return -EIO;
2972 }
2973
2974 return mgsl_ioctl_common(info, cmd, arg);
2975 }
2976
2977 static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg)
2978 {
2979 int error;
2980 struct mgsl_icount cnow; /* kernel counter temps */
2981 void __user *argp = (void __user *)arg;
2982 struct serial_icounter_struct __user *p_cuser; /* user space */
2983 unsigned long flags;
2984
2985 switch (cmd) {
2986 case MGSL_IOCGPARAMS:
2987 return mgsl_get_params(info, argp);
2988 case MGSL_IOCSPARAMS:
2989 return mgsl_set_params(info, argp);
2990 case MGSL_IOCGTXIDLE:
2991 return mgsl_get_txidle(info, argp);
2992 case MGSL_IOCSTXIDLE:
2993 return mgsl_set_txidle(info,(int)arg);
2994 case MGSL_IOCTXENABLE:
2995 return mgsl_txenable(info,(int)arg);
2996 case MGSL_IOCRXENABLE:
2997 return mgsl_rxenable(info,(int)arg);
2998 case MGSL_IOCTXABORT:
2999 return mgsl_txabort(info);
3000 case MGSL_IOCGSTATS:
3001 return mgsl_get_stats(info, argp);
3002 case MGSL_IOCWAITEVENT:
3003 return mgsl_wait_event(info, argp);
3004 case MGSL_IOCLOOPTXDONE:
3005 return mgsl_loopmode_send_done(info);
3006 /* Wait for modem input (DCD,RI,DSR,CTS) change
3007 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
3008 */
3009 case TIOCMIWAIT:
3010 return modem_input_wait(info,(int)arg);
3011
3012 /*
3013 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
3014 * Return: write counters to the user passed counter struct
3015 * NB: both 1->0 and 0->1 transitions are counted except for
3016 * RI where only 0->1 is counted.
3017 */
3018 case TIOCGICOUNT:
3019 spin_lock_irqsave(&info->irq_spinlock,flags);
3020 cnow = info->icount;
3021 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3022 p_cuser = argp;
3023 PUT_USER(error,cnow.cts, &p_cuser->cts);
3024 if (error) return error;
3025 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
3026 if (error) return error;
3027 PUT_USER(error,cnow.rng, &p_cuser->rng);
3028 if (error) return error;
3029 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
3030 if (error) return error;
3031 PUT_USER(error,cnow.rx, &p_cuser->rx);
3032 if (error) return error;
3033 PUT_USER(error,cnow.tx, &p_cuser->tx);
3034 if (error) return error;
3035 PUT_USER(error,cnow.frame, &p_cuser->frame);
3036 if (error) return error;
3037 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
3038 if (error) return error;
3039 PUT_USER(error,cnow.parity, &p_cuser->parity);
3040 if (error) return error;
3041 PUT_USER(error,cnow.brk, &p_cuser->brk);
3042 if (error) return error;
3043 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
3044 if (error) return error;
3045 return 0;
3046 default:
3047 return -ENOIOCTLCMD;
3048 }
3049 return 0;
3050 }
3051
3052 /* mgsl_set_termios()
3053 *
3054 * Set new termios settings
3055 *
3056 * Arguments:
3057 *
3058 * tty pointer to tty structure
3059 * termios pointer to buffer to hold returned old termios
3060 *
3061 * Return Value: None
3062 */
3063 static void mgsl_set_termios(struct tty_struct *tty, struct termios *old_termios)
3064 {
3065 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
3066 unsigned long flags;
3067
3068 if (debug_level >= DEBUG_LEVEL_INFO)
3069 printk("%s(%d):mgsl_set_termios %s\n", __FILE__,__LINE__,
3070 tty->driver->name );
3071
3072 /* just return if nothing has changed */
3073 if ((tty->termios->c_cflag == old_termios->c_cflag)
3074 && (RELEVANT_IFLAG(tty->termios->c_iflag)
3075 == RELEVANT_IFLAG(old_termios->c_iflag)))
3076 return;
3077
3078 mgsl_change_params(info);
3079
3080 /* Handle transition to B0 status */
3081 if (old_termios->c_cflag & CBAUD &&
3082 !(tty->termios->c_cflag & CBAUD)) {
3083 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
3084 spin_lock_irqsave(&info->irq_spinlock,flags);
3085 usc_set_serial_signals(info);
3086 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3087 }
3088
3089 /* Handle transition away from B0 status */
3090 if (!(old_termios->c_cflag & CBAUD) &&
3091 tty->termios->c_cflag & CBAUD) {
3092 info->serial_signals |= SerialSignal_DTR;
3093 if (!(tty->termios->c_cflag & CRTSCTS) ||
3094 !test_bit(TTY_THROTTLED, &tty->flags)) {
3095 info->serial_signals |= SerialSignal_RTS;
3096 }
3097 spin_lock_irqsave(&info->irq_spinlock,flags);
3098 usc_set_serial_signals(info);
3099 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3100 }
3101
3102 /* Handle turning off CRTSCTS */
3103 if (old_termios->c_cflag & CRTSCTS &&
3104 !(tty->termios->c_cflag & CRTSCTS)) {
3105 tty->hw_stopped = 0;
3106 mgsl_start(tty);
3107 }
3108
3109 } /* end of mgsl_set_termios() */
3110
3111 /* mgsl_close()
3112 *
3113 * Called when port is closed. Wait for remaining data to be
3114 * sent. Disable port and free resources.
3115 *
3116 * Arguments:
3117 *
3118 * tty pointer to open tty structure
3119 * filp pointer to open file object
3120 *
3121 * Return Value: None
3122 */
3123 static void mgsl_close(struct tty_struct *tty, struct file * filp)
3124 {
3125 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
3126
3127 if (mgsl_paranoia_check(info, tty->name, "mgsl_close"))
3128 return;
3129
3130 if (debug_level >= DEBUG_LEVEL_INFO)
3131 printk("%s(%d):mgsl_close(%s) entry, count=%d\n",
3132 __FILE__,__LINE__, info->device_name, info->count);
3133
3134 if (!info->count)
3135 return;
3136
3137 if (tty_hung_up_p(filp))
3138 goto cleanup;
3139
3140 if ((tty->count == 1) && (info->count != 1)) {
3141 /*
3142 * tty->count is 1 and the tty structure will be freed.
3143 * info->count should be one in this case.
3144 * if it's not, correct it so that the port is shutdown.
3145 */
3146 printk("mgsl_close: bad refcount; tty->count is 1, "
3147 "info->count is %d\n", info->count);
3148 info->count = 1;
3149 }
3150
3151 info->count--;
3152
3153 /* if at least one open remaining, leave hardware active */
3154 if (info->count)
3155 goto cleanup;
3156
3157 info->flags |= ASYNC_CLOSING;
3158
3159 /* set tty->closing to notify line discipline to
3160 * only process XON/XOFF characters. Only the N_TTY
3161 * discipline appears to use this (ppp does not).
3162 */
3163 tty->closing = 1;
3164
3165 /* wait for transmit data to clear all layers */
3166
3167 if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
3168 if (debug_level >= DEBUG_LEVEL_INFO)
3169 printk("%s(%d):mgsl_close(%s) calling tty_wait_until_sent\n",
3170 __FILE__,__LINE__, info->device_name );
3171 tty_wait_until_sent(tty, info->closing_wait);
3172 }
3173
3174 if (info->flags & ASYNC_INITIALIZED)
3175 mgsl_wait_until_sent(tty, info->timeout);
3176
3177 if (tty->driver->flush_buffer)
3178 tty->driver->flush_buffer(tty);
3179
3180 tty_ldisc_flush(tty);
3181
3182 shutdown(info);
3183
3184 tty->closing = 0;
3185 info->tty = NULL;
3186
3187 if (info->blocked_open) {
3188 if (info->close_delay) {
3189 msleep_interruptible(jiffies_to_msecs(info->close_delay));
3190 }
3191 wake_up_interruptible(&info->open_wait);
3192 }
3193
3194 info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
3195
3196 wake_up_interruptible(&info->close_wait);
3197
3198 cleanup:
3199 if (debug_level >= DEBUG_LEVEL_INFO)
3200 printk("%s(%d):mgsl_close(%s) exit, count=%d\n", __FILE__,__LINE__,
3201 tty->driver->name, info->count);
3202
3203 } /* end of mgsl_close() */
3204
3205 /* mgsl_wait_until_sent()
3206 *
3207 * Wait until the transmitter is empty.
3208 *
3209 * Arguments:
3210 *
3211 * tty pointer to tty info structure
3212 * timeout time to wait for send completion
3213 *
3214 * Return Value: None
3215 */
3216 static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout)
3217 {
3218 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
3219 unsigned long orig_jiffies, char_time;
3220
3221 if (!info )
3222 return;
3223
3224 if (debug_level >= DEBUG_LEVEL_INFO)
3225 printk("%s(%d):mgsl_wait_until_sent(%s) entry\n",
3226 __FILE__,__LINE__, info->device_name );
3227
3228 if (mgsl_paranoia_check(info, tty->name, "mgsl_wait_until_sent"))
3229 return;
3230
3231 if (!(info->flags & ASYNC_INITIALIZED))
3232 goto exit;
3233
3234 orig_jiffies = jiffies;
3235
3236 /* Set check interval to 1/5 of estimated time to
3237 * send a character, and make it at least 1. The check
3238 * interval should also be less than the timeout.
3239 * Note: use tight timings here to satisfy the NIST-PCTS.
3240 */
3241
3242 if ( info->params.data_rate ) {
3243 char_time = info->timeout/(32 * 5);
3244 if (!char_time)
3245 char_time++;
3246 } else
3247 char_time = 1;
3248
3249 if (timeout)
3250 char_time = min_t(unsigned long, char_time, timeout);
3251
3252 if ( info->params.mode == MGSL_MODE_HDLC ||
3253 info->params.mode == MGSL_MODE_RAW ) {
3254 while (info->tx_active) {
3255 msleep_interruptible(jiffies_to_msecs(char_time));
3256 if (signal_pending(current))
3257 break;
3258 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3259 break;
3260 }
3261 } else {
3262 while (!(usc_InReg(info,TCSR) & TXSTATUS_ALL_SENT) &&
3263 info->tx_enabled) {
3264 msleep_interruptible(jiffies_to_msecs(char_time));
3265 if (signal_pending(current))
3266 break;
3267 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3268 break;
3269 }
3270 }
3271
3272 exit:
3273 if (debug_level >= DEBUG_LEVEL_INFO)
3274 printk("%s(%d):mgsl_wait_until_sent(%s) exit\n",
3275 __FILE__,__LINE__, info->device_name );
3276
3277 } /* end of mgsl_wait_until_sent() */
3278
3279 /* mgsl_hangup()
3280 *
3281 * Called by tty_hangup() when a hangup is signaled.
3282 * This is the same as to closing all open files for the port.
3283 *
3284 * Arguments: tty pointer to associated tty object
3285 * Return Value: None
3286 */
3287 static void mgsl_hangup(struct tty_struct *tty)
3288 {
3289 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
3290
3291 if (debug_level >= DEBUG_LEVEL_INFO)
3292 printk("%s(%d):mgsl_hangup(%s)\n",
3293 __FILE__,__LINE__, info->device_name );
3294
3295 if (mgsl_paranoia_check(info, tty->name, "mgsl_hangup"))
3296 return;
3297
3298 mgsl_flush_buffer(tty);
3299 shutdown(info);
3300
3301 info->count = 0;
3302 info->flags &= ~ASYNC_NORMAL_ACTIVE;
3303 info->tty = NULL;
3304
3305 wake_up_interruptible(&info->open_wait);
3306
3307 } /* end of mgsl_hangup() */
3308
3309 /* block_til_ready()
3310 *
3311 * Block the current process until the specified port
3312 * is ready to be opened.
3313 *
3314 * Arguments:
3315 *
3316 * tty pointer to tty info structure
3317 * filp pointer to open file object
3318 * info pointer to device instance data
3319 *
3320 * Return Value: 0 if success, otherwise error code
3321 */
3322 static int block_til_ready(struct tty_struct *tty, struct file * filp,
3323 struct mgsl_struct *info)
3324 {
3325 DECLARE_WAITQUEUE(wait, current);
3326 int retval;
3327 int do_clocal = 0, extra_count = 0;
3328 unsigned long flags;
3329
3330 if (debug_level >= DEBUG_LEVEL_INFO)
3331 printk("%s(%d):block_til_ready on %s\n",
3332 __FILE__,__LINE__, tty->driver->name );
3333
3334 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3335 /* nonblock mode is set or port is not enabled */
3336 info->flags |= ASYNC_NORMAL_ACTIVE;
3337 return 0;
3338 }
3339
3340 if (tty->termios->c_cflag & CLOCAL)
3341 do_clocal = 1;
3342
3343 /* Wait for carrier detect and the line to become
3344 * free (i.e., not in use by the callout). While we are in
3345 * this loop, info->count is dropped by one, so that
3346 * mgsl_close() knows when to free things. We restore it upon
3347 * exit, either normal or abnormal.
3348 */
3349
3350 retval = 0;
3351 add_wait_queue(&info->open_wait, &wait);
3352
3353 if (debug_level >= DEBUG_LEVEL_INFO)
3354 printk("%s(%d):block_til_ready before block on %s count=%d\n",
3355 __FILE__,__LINE__, tty->driver->name, info->count );
3356
3357 spin_lock_irqsave(&info->irq_spinlock, flags);
3358 if (!tty_hung_up_p(filp)) {
3359 extra_count = 1;
3360 info->count--;
3361 }
3362 spin_unlock_irqrestore(&info->irq_spinlock, flags);
3363 info->blocked_open++;
3364
3365 while (1) {
3366 if (tty->termios->c_cflag & CBAUD) {
3367 spin_lock_irqsave(&info->irq_spinlock,flags);
3368 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3369 usc_set_serial_signals(info);
3370 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3371 }
3372
3373 set_current_state(TASK_INTERRUPTIBLE);
3374
3375 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
3376 retval = (info->flags & ASYNC_HUP_NOTIFY) ?
3377 -EAGAIN : -ERESTARTSYS;
3378 break;
3379 }
3380
3381 spin_lock_irqsave(&info->irq_spinlock,flags);
3382 usc_get_serial_signals(info);
3383 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3384
3385 if (!(info->flags & ASYNC_CLOSING) &&
3386 (do_clocal || (info->serial_signals & SerialSignal_DCD)) ) {
3387 break;
3388 }
3389
3390 if (signal_pending(current)) {
3391 retval = -ERESTARTSYS;
3392 break;
3393 }
3394
3395 if (debug_level >= DEBUG_LEVEL_INFO)
3396 printk("%s(%d):block_til_ready blocking on %s count=%d\n",
3397 __FILE__,__LINE__, tty->driver->name, info->count );
3398
3399 schedule();
3400 }
3401
3402 set_current_state(TASK_RUNNING);
3403 remove_wait_queue(&info->open_wait, &wait);
3404
3405 if (extra_count)
3406 info->count++;
3407 info->blocked_open--;
3408
3409 if (debug_level >= DEBUG_LEVEL_INFO)
3410 printk("%s(%d):block_til_ready after blocking on %s count=%d\n",
3411 __FILE__,__LINE__, tty->driver->name, info->count );
3412
3413 if (!retval)
3414 info->flags |= ASYNC_NORMAL_ACTIVE;
3415
3416 return retval;
3417
3418 } /* end of block_til_ready() */
3419
3420 /* mgsl_open()
3421 *
3422 * Called when a port is opened. Init and enable port.
3423 * Perform serial-specific initialization for the tty structure.
3424 *
3425 * Arguments: tty pointer to tty info structure
3426 * filp associated file pointer
3427 *
3428 * Return Value: 0 if success, otherwise error code
3429 */
3430 static int mgsl_open(struct tty_struct *tty, struct file * filp)
3431 {
3432 struct mgsl_struct *info;
3433 int retval, line;
3434 unsigned long flags;
3435
3436 /* verify range of specified line number */
3437 line = tty->index;
3438 if ((line < 0) || (line >= mgsl_device_count)) {
3439 printk("%s(%d):mgsl_open with invalid line #%d.\n",
3440 __FILE__,__LINE__,line);
3441 return -ENODEV;
3442 }
3443
3444 /* find the info structure for the specified line */
3445 info = mgsl_device_list;
3446 while(info && info->line != line)
3447 info = info->next_device;
3448 if (mgsl_paranoia_check(info, tty->name, "mgsl_open"))
3449 return -ENODEV;
3450
3451 tty->driver_data = info;
3452 info->tty = tty;
3453
3454 if (debug_level >= DEBUG_LEVEL_INFO)
3455 printk("%s(%d):mgsl_open(%s), old ref count = %d\n",
3456 __FILE__,__LINE__,tty->driver->name, info->count);
3457
3458 /* If port is closing, signal caller to try again */
3459 if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
3460 if (info->flags & ASYNC_CLOSING)
3461 interruptible_sleep_on(&info->close_wait);
3462 retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
3463 -EAGAIN : -ERESTARTSYS);
3464 goto cleanup;
3465 }
3466
3467 info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
3468
3469 spin_lock_irqsave(&info->netlock, flags);
3470 if (info->netcount) {
3471 retval = -EBUSY;
3472 spin_unlock_irqrestore(&info->netlock, flags);
3473 goto cleanup;
3474 }
3475 info->count++;
3476 spin_unlock_irqrestore(&info->netlock, flags);
3477
3478 if (info->count == 1) {
3479 /* 1st open on this device, init hardware */
3480 retval = startup(info);
3481 if (retval < 0)
3482 goto cleanup;
3483 }
3484
3485 retval = block_til_ready(tty, filp, info);
3486 if (retval) {
3487 if (debug_level >= DEBUG_LEVEL_INFO)
3488 printk("%s(%d):block_til_ready(%s) returned %d\n",
3489 __FILE__,__LINE__, info->device_name, retval);
3490 goto cleanup;
3491 }
3492
3493 if (debug_level >= DEBUG_LEVEL_INFO)
3494 printk("%s(%d):mgsl_open(%s) success\n",
3495 __FILE__,__LINE__, info->device_name);
3496 retval = 0;
3497
3498 cleanup:
3499 if (retval) {
3500 if (tty->count == 1)
3501 info->tty = NULL; /* tty layer will release tty struct */
3502 if(info->count)
3503 info->count--;
3504 }
3505
3506 return retval;
3507
3508 } /* end of mgsl_open() */
3509
3510 /*
3511 * /proc fs routines....
3512 */
3513
3514 static inline int line_info(char *buf, struct mgsl_struct *info)
3515 {
3516 char stat_buf[30];
3517 int ret;
3518 unsigned long flags;
3519
3520 if (info->bus_type == MGSL_BUS_TYPE_PCI) {
3521 ret = sprintf(buf, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X",
3522 info->device_name, info->io_base, info->irq_level,
3523 info->phys_memory_base, info->phys_lcr_base);
3524 } else {
3525 ret = sprintf(buf, "%s:(E)ISA io:%04X irq:%d dma:%d",
3526 info->device_name, info->io_base,
3527 info->irq_level, info->dma_level);
3528 }
3529
3530 /* output current serial signal states */
3531 spin_lock_irqsave(&info->irq_spinlock,flags);
3532 usc_get_serial_signals(info);
3533 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3534
3535 stat_buf[0] = 0;
3536 stat_buf[1] = 0;
3537 if (info->serial_signals & SerialSignal_RTS)
3538 strcat(stat_buf, "|RTS");
3539 if (info->serial_signals & SerialSignal_CTS)
3540 strcat(stat_buf, "|CTS");
3541 if (info->serial_signals & SerialSignal_DTR)
3542 strcat(stat_buf, "|DTR");
3543 if (info->serial_signals & SerialSignal_DSR)
3544 strcat(stat_buf, "|DSR");
3545 if (info->serial_signals & SerialSignal_DCD)
3546 strcat(stat_buf, "|CD");
3547 if (info->serial_signals & SerialSignal_RI)
3548 strcat(stat_buf, "|RI");
3549
3550 if (info->params.mode == MGSL_MODE_HDLC ||
3551 info->params.mode == MGSL_MODE_RAW ) {
3552 ret += sprintf(buf+ret, " HDLC txok:%d rxok:%d",
3553 info->icount.txok, info->icount.rxok);
3554 if (info->icount.txunder)
3555 ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
3556 if (info->icount.txabort)
3557 ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
3558 if (info->icount.rxshort)
3559 ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
3560 if (info->icount.rxlong)
3561 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
3562 if (info->icount.rxover)
3563 ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
3564 if (info->icount.rxcrc)
3565 ret += sprintf(buf+ret, " rxcrc:%d", info->icount.rxcrc);
3566 } else {
3567 ret += sprintf(buf+ret, " ASYNC tx:%d rx:%d",
3568 info->icount.tx, info->icount.rx);
3569 if (info->icount.frame)
3570 ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
3571 if (info->icount.parity)
3572 ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
3573 if (info->icount.brk)
3574 ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
3575 if (info->icount.overrun)
3576 ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
3577 }
3578
3579 /* Append serial signal status to end */
3580 ret += sprintf(buf+ret, " %s\n", stat_buf+1);
3581
3582 ret += sprintf(buf+ret, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
3583 info->tx_active,info->bh_requested,info->bh_running,
3584 info->pending_bh);
3585
3586 spin_lock_irqsave(&info->irq_spinlock,flags);
3587 {
3588 u16 Tcsr = usc_InReg( info, TCSR );
3589 u16 Tdmr = usc_InDmaReg( info, TDMR );
3590 u16 Ticr = usc_InReg( info, TICR );
3591 u16 Rscr = usc_InReg( info, RCSR );
3592 u16 Rdmr = usc_InDmaReg( info, RDMR );
3593 u16 Ricr = usc_InReg( info, RICR );
3594 u16 Icr = usc_InReg( info, ICR );
3595 u16 Dccr = usc_InReg( info, DCCR );
3596 u16 Tmr = usc_InReg( info, TMR );
3597 u16 Tccr = usc_InReg( info, TCCR );
3598 u16 Ccar = inw( info->io_base + CCAR );
3599 ret += sprintf(buf+ret, "tcsr=%04X tdmr=%04X ticr=%04X rcsr=%04X rdmr=%04X\n"
3600 "ricr=%04X icr =%04X dccr=%04X tmr=%04X tccr=%04X ccar=%04X\n",
3601 Tcsr,Tdmr,Ticr,Rscr,Rdmr,Ricr,Icr,Dccr,Tmr,Tccr,Ccar );
3602 }
3603 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3604
3605 return ret;
3606
3607 } /* end of line_info() */
3608
3609 /* mgsl_read_proc()
3610 *
3611 * Called to print information about devices
3612 *
3613 * Arguments:
3614 * page page of memory to hold returned info
3615 * start
3616 * off
3617 * count
3618 * eof
3619 * data
3620 *
3621 * Return Value:
3622 */
3623 static int mgsl_read_proc(char *page, char **start, off_t off, int count,
3624 int *eof, void *data)
3625 {
3626 int len = 0, l;
3627 off_t begin = 0;
3628 struct mgsl_struct *info;
3629
3630 len += sprintf(page, "synclink driver:%s\n", driver_version);
3631
3632 info = mgsl_device_list;
3633 while( info ) {
3634 l = line_info(page + len, info);
3635 len += l;
3636 if (len+begin > off+count)
3637 goto done;
3638 if (len+begin < off) {
3639 begin += len;
3640 len = 0;
3641 }
3642 info = info->next_device;
3643 }
3644
3645 *eof = 1;
3646 done:
3647 if (off >= len+begin)
3648 return 0;
3649 *start = page + (off-begin);
3650 return ((count < begin+len-off) ? count : begin+len-off);
3651
3652 } /* end of mgsl_read_proc() */
3653
3654 /* mgsl_allocate_dma_buffers()
3655 *
3656 * Allocate and format DMA buffers (ISA adapter)
3657 * or format shared memory buffers (PCI adapter).
3658 *
3659 * Arguments: info pointer to device instance data
3660 * Return Value: 0 if success, otherwise error
3661 */
3662 static int mgsl_allocate_dma_buffers(struct mgsl_struct *info)
3663 {
3664 unsigned short BuffersPerFrame;
3665
3666 info->last_mem_alloc = 0;
3667
3668 /* Calculate the number of DMA buffers necessary to hold the */
3669 /* largest allowable frame size. Note: If the max frame size is */
3670 /* not an even multiple of the DMA buffer size then we need to */
3671 /* round the buffer count per frame up one. */
3672
3673 BuffersPerFrame = (unsigned short)(info->max_frame_size/DMABUFFERSIZE);
3674 if ( info->max_frame_size % DMABUFFERSIZE )
3675 BuffersPerFrame++;
3676
3677 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3678 /*
3679 * The PCI adapter has 256KBytes of shared memory to use.
3680 * This is 64 PAGE_SIZE buffers.
3681 *
3682 * The first page is used for padding at this time so the
3683 * buffer list does not begin at offset 0 of the PCI
3684 * adapter's shared memory.
3685 *
3686 * The 2nd page is used for the buffer list. A 4K buffer
3687 * list can hold 128 DMA_BUFFER structures at 32 bytes
3688 * each.
3689 *
3690 * This leaves 62 4K pages.
3691 *
3692 * The next N pages are used for transmit frame(s). We
3693 * reserve enough 4K page blocks to hold the required
3694 * number of transmit dma buffers (num_tx_dma_buffers),
3695 * each of MaxFrameSize size.
3696 *
3697 * Of the remaining pages (62-N), determine how many can
3698 * be used to receive full MaxFrameSize inbound frames
3699 */
3700 info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3701 info->rx_buffer_count = 62 - info->tx_buffer_count;
3702 } else {
3703 /* Calculate the number of PAGE_SIZE buffers needed for */
3704 /* receive and transmit DMA buffers. */
3705
3706
3707 /* Calculate the number of DMA buffers necessary to */
3708 /* hold 7 max size receive frames and one max size transmit frame. */
3709 /* The receive buffer count is bumped by one so we avoid an */
3710 /* End of List condition if all receive buffers are used when */
3711 /* using linked list DMA buffers. */
3712
3713 info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3714 info->rx_buffer_count = (BuffersPerFrame * MAXRXFRAMES) + 6;
3715
3716 /*
3717 * limit total TxBuffers & RxBuffers to 62 4K total
3718 * (ala PCI Allocation)
3719 */
3720
3721 if ( (info->tx_buffer_count + info->rx_buffer_count) > 62 )
3722 info->rx_buffer_count = 62 - info->tx_buffer_count;
3723
3724 }
3725
3726 if ( debug_level >= DEBUG_LEVEL_INFO )
3727 printk("%s(%d):Allocating %d TX and %d RX DMA buffers.\n",
3728 __FILE__,__LINE__, info->tx_buffer_count,info->rx_buffer_count);
3729
3730 if ( mgsl_alloc_buffer_list_memory( info ) < 0 ||
3731 mgsl_alloc_frame_memory(info, info->rx_buffer_list, info->rx_buffer_count) < 0 ||
3732 mgsl_alloc_frame_memory(info, info->tx_buffer_list, info->tx_buffer_count) < 0 ||
3733 mgsl_alloc_intermediate_rxbuffer_memory(info) < 0 ||
3734 mgsl_alloc_intermediate_txbuffer_memory(info) < 0 ) {
3735 printk("%s(%d):Can't allocate DMA buffer memory\n",__FILE__,__LINE__);
3736 return -ENOMEM;
3737 }
3738
3739 mgsl_reset_rx_dma_buffers( info );
3740 mgsl_reset_tx_dma_buffers( info );
3741
3742 return 0;
3743
3744 } /* end of mgsl_allocate_dma_buffers() */
3745
3746 /*
3747 * mgsl_alloc_buffer_list_memory()
3748 *
3749 * Allocate a common DMA buffer for use as the
3750 * receive and transmit buffer lists.
3751 *
3752 * A buffer list is a set of buffer entries where each entry contains
3753 * a pointer to an actual buffer and a pointer to the next buffer entry
3754 * (plus some other info about the buffer).
3755 *
3756 * The buffer entries for a list are built to form a circular list so
3757 * that when the entire list has been traversed you start back at the
3758 * beginning.
3759 *
3760 * This function allocates memory for just the buffer entries.
3761 * The links (pointer to next entry) are filled in with the physical
3762 * address of the next entry so the adapter can navigate the list
3763 * using bus master DMA. The pointers to the actual buffers are filled
3764 * out later when the actual buffers are allocated.
3765 *
3766 * Arguments: info pointer to device instance data
3767 * Return Value: 0 if success, otherwise error
3768 */
3769 static int mgsl_alloc_buffer_list_memory( struct mgsl_struct *info )
3770 {
3771 unsigned int i;
3772
3773 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3774 /* PCI adapter uses shared memory. */
3775 info->buffer_list = info->memory_base + info->last_mem_alloc;
3776 info->buffer_list_phys = info->last_mem_alloc;
3777 info->last_mem_alloc += BUFFERLISTSIZE;
3778 } else {
3779 /* ISA adapter uses system memory. */
3780 /* The buffer lists are allocated as a common buffer that both */
3781 /* the processor and adapter can access. This allows the driver to */
3782 /* inspect portions of the buffer while other portions are being */
3783 /* updated by the adapter using Bus Master DMA. */
3784
3785 info->buffer_list = dma_alloc_coherent(NULL, BUFFERLISTSIZE, &info->buffer_list_dma_addr, GFP_KERNEL);
3786 if (info->buffer_list == NULL)
3787 return -ENOMEM;
3788 info->buffer_list_phys = (u32)(info->buffer_list_dma_addr);
3789 }
3790
3791 /* We got the memory for the buffer entry lists. */
3792 /* Initialize the memory block to all zeros. */
3793 memset( info->buffer_list, 0, BUFFERLISTSIZE );
3794
3795 /* Save virtual address pointers to the receive and */
3796 /* transmit buffer lists. (Receive 1st). These pointers will */
3797 /* be used by the processor to access the lists. */
3798 info->rx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3799 info->tx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3800 info->tx_buffer_list += info->rx_buffer_count;
3801
3802 /*
3803 * Build the links for the buffer entry lists such that
3804 * two circular lists are built. (Transmit and Receive).
3805 *
3806 * Note: the links are physical addresses
3807 * which are read by the adapter to determine the next
3808 * buffer entry to use.
3809 */
3810
3811 for ( i = 0; i < info->rx_buffer_count; i++ ) {
3812 /* calculate and store physical address of this buffer entry */
3813 info->rx_buffer_list[i].phys_entry =
3814 info->buffer_list_phys + (i * sizeof(DMABUFFERENTRY));
3815
3816 /* calculate and store physical address of */
3817 /* next entry in cirular list of entries */
3818
3819 info->rx_buffer_list[i].link = info->buffer_list_phys;
3820
3821 if ( i < info->rx_buffer_count - 1 )
3822 info->rx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3823 }
3824
3825 for ( i = 0; i < info->tx_buffer_count; i++ ) {
3826 /* calculate and store physical address of this buffer entry */
3827 info->tx_buffer_list[i].phys_entry = info->buffer_list_phys +
3828 ((info->rx_buffer_count + i) * sizeof(DMABUFFERENTRY));
3829
3830 /* calculate and store physical address of */
3831 /* next entry in cirular list of entries */
3832
3833 info->tx_buffer_list[i].link = info->buffer_list_phys +
3834 info->rx_buffer_count * sizeof(DMABUFFERENTRY);
3835
3836 if ( i < info->tx_buffer_count - 1 )
3837 info->tx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3838 }
3839
3840 return 0;
3841
3842 } /* end of mgsl_alloc_buffer_list_memory() */
3843
3844 /* Free DMA buffers allocated for use as the
3845 * receive and transmit buffer lists.
3846 * Warning:
3847 *
3848 * The data transfer buffers associated with the buffer list
3849 * MUST be freed before freeing the buffer list itself because
3850 * the buffer list contains the information necessary to free
3851 * the individual buffers!
3852 */
3853 static void mgsl_free_buffer_list_memory( struct mgsl_struct *info )
3854 {
3855 if (info->buffer_list && info->bus_type != MGSL_BUS_TYPE_PCI)
3856 dma_free_coherent(NULL, BUFFERLISTSIZE, info->buffer_list, info->buffer_list_dma_addr);
3857
3858 info->buffer_list = NULL;
3859 info->rx_buffer_list = NULL;
3860 info->tx_buffer_list = NULL;
3861
3862 } /* end of mgsl_free_buffer_list_memory() */
3863
3864 /*
3865 * mgsl_alloc_frame_memory()
3866 *
3867 * Allocate the frame DMA buffers used by the specified buffer list.
3868 * Each DMA buffer will be one memory page in size. This is necessary
3869 * because memory can fragment enough that it may be impossible
3870 * contiguous pages.
3871 *
3872 * Arguments:
3873 *
3874 * info pointer to device instance data
3875 * BufferList pointer to list of buffer entries
3876 * Buffercount count of buffer entries in buffer list
3877 *
3878 * Return Value: 0 if success, otherwise -ENOMEM
3879 */
3880 static int mgsl_alloc_frame_memory(struct mgsl_struct *info,DMABUFFERENTRY *BufferList,int Buffercount)
3881 {
3882 int i;
3883 u32 phys_addr;
3884
3885 /* Allocate page sized buffers for the receive buffer list */
3886
3887 for ( i = 0; i < Buffercount; i++ ) {
3888 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3889 /* PCI adapter uses shared memory buffers. */
3890 BufferList[i].virt_addr = info->memory_base + info->last_mem_alloc;
3891 phys_addr = info->last_mem_alloc;
3892 info->last_mem_alloc += DMABUFFERSIZE;
3893 } else {
3894 /* ISA adapter uses system memory. */
3895 BufferList[i].virt_addr = dma_alloc_coherent(NULL, DMABUFFERSIZE, &BufferList[i].dma_addr, GFP_KERNEL);
3896 if (BufferList[i].virt_addr == NULL)
3897 return -ENOMEM;
3898 phys_addr = (u32)(BufferList[i].dma_addr);
3899 }
3900 BufferList[i].phys_addr = phys_addr;
3901 }
3902
3903 return 0;
3904
3905 } /* end of mgsl_alloc_frame_memory() */
3906
3907 /*
3908 * mgsl_free_frame_memory()
3909 *
3910 * Free the buffers associated with
3911 * each buffer entry of a buffer list.
3912 *
3913 * Arguments:
3914 *
3915 * info pointer to device instance data
3916 * BufferList pointer to list of buffer entries
3917 * Buffercount count of buffer entries in buffer list
3918 *
3919 * Return Value: None
3920 */
3921 static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList, int Buffercount)
3922 {
3923 int i;
3924
3925 if ( BufferList ) {
3926 for ( i = 0 ; i < Buffercount ; i++ ) {
3927 if ( BufferList[i].virt_addr ) {
3928 if ( info->bus_type != MGSL_BUS_TYPE_PCI )
3929 dma_free_coherent(NULL, DMABUFFERSIZE, BufferList[i].virt_addr, BufferList[i].dma_addr);
3930 BufferList[i].virt_addr = NULL;
3931 }
3932 }
3933 }
3934
3935 } /* end of mgsl_free_frame_memory() */
3936
3937 /* mgsl_free_dma_buffers()
3938 *
3939 * Free DMA buffers
3940 *
3941 * Arguments: info pointer to device instance data
3942 * Return Value: None
3943 */
3944 static void mgsl_free_dma_buffers( struct mgsl_struct *info )
3945 {
3946 mgsl_free_frame_memory( info, info->rx_buffer_list, info->rx_buffer_count );
3947 mgsl_free_frame_memory( info, info->tx_buffer_list, info->tx_buffer_count );
3948 mgsl_free_buffer_list_memory( info );
3949
3950 } /* end of mgsl_free_dma_buffers() */
3951
3952
3953 /*
3954 * mgsl_alloc_intermediate_rxbuffer_memory()
3955 *
3956 * Allocate a buffer large enough to hold max_frame_size. This buffer
3957 * is used to pass an assembled frame to the line discipline.
3958 *
3959 * Arguments:
3960 *
3961 * info pointer to device instance data
3962 *
3963 * Return Value: 0 if success, otherwise -ENOMEM
3964 */
3965 static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info)
3966 {
3967 info->intermediate_rxbuffer = kmalloc(info->max_frame_size, GFP_KERNEL | GFP_DMA);
3968 if ( info->intermediate_rxbuffer == NULL )
3969 return -ENOMEM;
3970
3971 return 0;
3972
3973 } /* end of mgsl_alloc_intermediate_rxbuffer_memory() */
3974
3975 /*
3976 * mgsl_free_intermediate_rxbuffer_memory()
3977 *
3978 *
3979 * Arguments:
3980 *
3981 * info pointer to device instance data
3982 *
3983 * Return Value: None
3984 */
3985 static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info)
3986 {
3987 kfree(info->intermediate_rxbuffer);
3988 info->intermediate_rxbuffer = NULL;
3989
3990 } /* end of mgsl_free_intermediate_rxbuffer_memory() */
3991
3992 /*
3993 * mgsl_alloc_intermediate_txbuffer_memory()
3994 *
3995 * Allocate intermdiate transmit buffer(s) large enough to hold max_frame_size.
3996 * This buffer is used to load transmit frames into the adapter's dma transfer
3997 * buffers when there is sufficient space.
3998 *
3999 * Arguments:
4000 *
4001 * info pointer to device instance data
4002 *
4003 * Return Value: 0 if success, otherwise -ENOMEM
4004 */
4005 static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info)
4006 {
4007 int i;
4008
4009 if ( debug_level >= DEBUG_LEVEL_INFO )
4010 printk("%s %s(%d) allocating %d tx holding buffers\n",
4011 info->device_name, __FILE__,__LINE__,info->num_tx_holding_buffers);
4012
4013 memset(info->tx_holding_buffers,0,sizeof(info->tx_holding_buffers));
4014
4015 for ( i=0; i<info->num_tx_holding_buffers; ++i) {
4016 info->tx_holding_buffers[i].buffer =
4017 kmalloc(info->max_frame_size, GFP_KERNEL);
4018 if ( info->tx_holding_buffers[i].buffer == NULL )
4019 return -ENOMEM;
4020 }
4021
4022 return 0;
4023
4024 } /* end of mgsl_alloc_intermediate_txbuffer_memory() */
4025
4026 /*
4027 * mgsl_free_intermediate_txbuffer_memory()
4028 *
4029 *
4030 * Arguments:
4031 *
4032 * info pointer to device instance data
4033 *
4034 * Return Value: None
4035 */
4036 static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info)
4037 {
4038 int i;
4039
4040 for ( i=0; i<info->num_tx_holding_buffers; ++i ) {
4041 kfree(info->tx_holding_buffers[i].buffer);
4042 info->tx_holding_buffers[i].buffer = NULL;
4043 }
4044
4045 info->get_tx_holding_index = 0;
4046 info->put_tx_holding_index = 0;
4047 info->tx_holding_count = 0;
4048
4049 } /* end of mgsl_free_intermediate_txbuffer_memory() */
4050
4051
4052 /*
4053 * load_next_tx_holding_buffer()
4054 *
4055 * attempts to load the next buffered tx request into the
4056 * tx dma buffers
4057 *
4058 * Arguments:
4059 *
4060 * info pointer to device instance data
4061 *
4062 * Return Value: 1 if next buffered tx request loaded
4063 * into adapter's tx dma buffer,
4064 * 0 otherwise
4065 */
4066 static int load_next_tx_holding_buffer(struct mgsl_struct *info)
4067 {
4068 int ret = 0;
4069
4070 if ( info->tx_holding_count ) {
4071 /* determine if we have enough tx dma buffers
4072 * to accommodate the next tx frame
4073 */
4074 struct tx_holding_buffer *ptx =
4075 &info->tx_holding_buffers[info->get_tx_holding_index];
4076 int num_free = num_free_tx_dma_buffers(info);
4077 int num_needed = ptx->buffer_size / DMABUFFERSIZE;
4078 if ( ptx->buffer_size % DMABUFFERSIZE )
4079 ++num_needed;
4080
4081 if (num_needed <= num_free) {
4082 info->xmit_cnt = ptx->buffer_size;
4083 mgsl_load_tx_dma_buffer(info,ptx->buffer,ptx->buffer_size);
4084
4085 --info->tx_holding_count;
4086 if ( ++info->get_tx_holding_index >= info->num_tx_holding_buffers)
4087 info->get_tx_holding_index=0;
4088
4089 /* restart transmit timer */
4090 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(5000));
4091
4092 ret = 1;
4093 }
4094 }
4095
4096 return ret;
4097 }
4098
4099 /*
4100 * save_tx_buffer_request()
4101 *
4102 * attempt to store transmit frame request for later transmission
4103 *
4104 * Arguments:
4105 *
4106 * info pointer to device instance data
4107 * Buffer pointer to buffer containing frame to load
4108 * BufferSize size in bytes of frame in Buffer
4109 *
4110 * Return Value: 1 if able to store, 0 otherwise
4111 */
4112 static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize)
4113 {
4114 struct tx_holding_buffer *ptx;
4115
4116 if ( info->tx_holding_count >= info->num_tx_holding_buffers ) {
4117 return 0; /* all buffers in use */
4118 }
4119
4120 ptx = &info->tx_holding_buffers[info->put_tx_holding_index];
4121 ptx->buffer_size = BufferSize;
4122 memcpy( ptx->buffer, Buffer, BufferSize);
4123
4124 ++info->tx_holding_count;
4125 if ( ++info->put_tx_holding_index >= info->num_tx_holding_buffers)
4126 info->put_tx_holding_index=0;
4127
4128 return 1;
4129 }
4130
4131 static int mgsl_claim_resources(struct mgsl_struct *info)
4132 {
4133 if (request_region(info->io_base,info->io_addr_size,"synclink") == NULL) {
4134 printk( "%s(%d):I/O address conflict on device %s Addr=%08X\n",
4135 __FILE__,__LINE__,info->device_name, info->io_base);
4136 return -ENODEV;
4137 }
4138 info->io_addr_requested = 1;
4139
4140 if ( request_irq(info->irq_level,mgsl_interrupt,info->irq_flags,
4141 info->device_name, info ) < 0 ) {
4142 printk( "%s(%d):Cant request interrupt on device %s IRQ=%d\n",
4143 __FILE__,__LINE__,info->device_name, info->irq_level );
4144 goto errout;
4145 }
4146 info->irq_requested = 1;
4147
4148 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4149 if (request_mem_region(info->phys_memory_base,0x40000,"synclink") == NULL) {
4150 printk( "%s(%d):mem addr conflict device %s Addr=%08X\n",
4151 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
4152 goto errout;
4153 }
4154 info->shared_mem_requested = 1;
4155 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclink") == NULL) {
4156 printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n",
4157 __FILE__,__LINE__,info->device_name, info->phys_lcr_base + info->lcr_offset);
4158 goto errout;
4159 }
4160 info->lcr_mem_requested = 1;
4161
4162 info->memory_base = ioremap(info->phys_memory_base,0x40000);
4163 if (!info->memory_base) {
4164 printk( "%s(%d):Cant map shared memory on device %s MemAddr=%08X\n",
4165 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4166 goto errout;
4167 }
4168
4169 if ( !mgsl_memory_test(info) ) {
4170 printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n",
4171 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4172 goto errout;
4173 }
4174
4175 info->lcr_base = ioremap(info->phys_lcr_base,PAGE_SIZE) + info->lcr_offset;
4176 if (!info->lcr_base) {
4177 printk( "%s(%d):Cant map LCR memory on device %s MemAddr=%08X\n",
4178 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
4179 goto errout;
4180 }
4181
4182 } else {
4183 /* claim DMA channel */
4184
4185 if (request_dma(info->dma_level,info->device_name) < 0){
4186 printk( "%s(%d):Cant request DMA channel on device %s DMA=%d\n",
4187 __FILE__,__LINE__,info->device_name, info->dma_level );
4188 mgsl_release_resources( info );
4189 return -ENODEV;
4190 }
4191 info->dma_requested = 1;
4192
4193 /* ISA adapter uses bus master DMA */
4194 set_dma_mode(info->dma_level,DMA_MODE_CASCADE);
4195 enable_dma(info->dma_level);
4196 }
4197
4198 if ( mgsl_allocate_dma_buffers(info) < 0 ) {
4199 printk( "%s(%d):Cant allocate DMA buffers on device %s DMA=%d\n",
4200 __FILE__,__LINE__,info->device_name, info->dma_level );
4201 goto errout;
4202 }
4203
4204 return 0;
4205 errout:
4206 mgsl_release_resources(info);
4207 return -ENODEV;
4208
4209 } /* end of mgsl_claim_resources() */
4210
4211 static void mgsl_release_resources(struct mgsl_struct *info)
4212 {
4213 if ( debug_level >= DEBUG_LEVEL_INFO )
4214 printk( "%s(%d):mgsl_release_resources(%s) entry\n",
4215 __FILE__,__LINE__,info->device_name );
4216
4217 if ( info->irq_requested ) {
4218 free_irq(info->irq_level, info);
4219 info->irq_requested = 0;
4220 }
4221 if ( info->dma_requested ) {
4222 disable_dma(info->dma_level);
4223 free_dma(info->dma_level);
4224 info->dma_requested = 0;
4225 }
4226 mgsl_free_dma_buffers(info);
4227 mgsl_free_intermediate_rxbuffer_memory(info);
4228 mgsl_free_intermediate_txbuffer_memory(info);
4229
4230 if ( info->io_addr_requested ) {
4231 release_region(info->io_base,info->io_addr_size);
4232 info->io_addr_requested = 0;
4233 }
4234 if ( info->shared_mem_requested ) {
4235 release_mem_region(info->phys_memory_base,0x40000);
4236 info->shared_mem_requested = 0;
4237 }
4238 if ( info->lcr_mem_requested ) {
4239 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
4240 info->lcr_mem_requested = 0;
4241 }
4242 if (info->memory_base){
4243 iounmap(info->memory_base);
4244 info->memory_base = NULL;
4245 }
4246 if (info->lcr_base){
4247 iounmap(info->lcr_base - info->lcr_offset);
4248 info->lcr_base = NULL;
4249 }
4250
4251 if ( debug_level >= DEBUG_LEVEL_INFO )
4252 printk( "%s(%d):mgsl_release_resources(%s) exit\n",
4253 __FILE__,__LINE__,info->device_name );
4254
4255 } /* end of mgsl_release_resources() */
4256
4257 /* mgsl_add_device()
4258 *
4259 * Add the specified device instance data structure to the
4260 * global linked list of devices and increment the device count.
4261 *
4262 * Arguments: info pointer to device instance data
4263 * Return Value: None
4264 */
4265 static void mgsl_add_device( struct mgsl_struct *info )
4266 {
4267 info->next_device = NULL;
4268 info->line = mgsl_device_count;
4269 sprintf(info->device_name,"ttySL%d",info->line);
4270
4271 if (info->line < MAX_TOTAL_DEVICES) {
4272 if (maxframe[info->line])
4273 info->max_frame_size = maxframe[info->line];
4274 info->dosyncppp = dosyncppp[info->line];
4275
4276 if (txdmabufs[info->line]) {
4277 info->num_tx_dma_buffers = txdmabufs[info->line];
4278 if (info->num_tx_dma_buffers < 1)
4279 info->num_tx_dma_buffers = 1;
4280 }
4281
4282 if (txholdbufs[info->line]) {
4283 info->num_tx_holding_buffers = txholdbufs[info->line];
4284 if (info->num_tx_holding_buffers < 1)
4285 info->num_tx_holding_buffers = 1;
4286 else if (info->num_tx_holding_buffers > MAX_TX_HOLDING_BUFFERS)
4287 info->num_tx_holding_buffers = MAX_TX_HOLDING_BUFFERS;
4288 }
4289 }
4290
4291 mgsl_device_count++;
4292
4293 if ( !mgsl_device_list )
4294 mgsl_device_list = info;
4295 else {
4296 struct mgsl_struct *current_dev = mgsl_device_list;
4297 while( current_dev->next_device )
4298 current_dev = current_dev->next_device;
4299 current_dev->next_device = info;
4300 }
4301
4302 if ( info->max_frame_size < 4096 )
4303 info->max_frame_size = 4096;
4304 else if ( info->max_frame_size > 65535 )
4305 info->max_frame_size = 65535;
4306
4307 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4308 printk( "SyncLink PCI v%d %s: IO=%04X IRQ=%d Mem=%08X,%08X MaxFrameSize=%u\n",
4309 info->hw_version + 1, info->device_name, info->io_base, info->irq_level,
4310 info->phys_memory_base, info->phys_lcr_base,
4311 info->max_frame_size );
4312 } else {
4313 printk( "SyncLink ISA %s: IO=%04X IRQ=%d DMA=%d MaxFrameSize=%u\n",
4314 info->device_name, info->io_base, info->irq_level, info->dma_level,
4315 info->max_frame_size );
4316 }
4317
4318 #ifdef CONFIG_HDLC
4319 hdlcdev_init(info);
4320 #endif
4321
4322 } /* end of mgsl_add_device() */
4323
4324 /* mgsl_allocate_device()
4325 *
4326 * Allocate and initialize a device instance structure
4327 *
4328 * Arguments: none
4329 * Return Value: pointer to mgsl_struct if success, otherwise NULL
4330 */
4331 static struct mgsl_struct* mgsl_allocate_device(void)
4332 {
4333 struct mgsl_struct *info;
4334
4335 info = (struct mgsl_struct *)kmalloc(sizeof(struct mgsl_struct),
4336 GFP_KERNEL);
4337
4338 if (!info) {
4339 printk("Error can't allocate device instance data\n");
4340 } else {
4341 memset(info, 0, sizeof(struct mgsl_struct));
4342 info->magic = MGSL_MAGIC;
4343 INIT_WORK(&info->task, mgsl_bh_handler, info);
4344 info->max_frame_size = 4096;
4345 info->close_delay = 5*HZ/10;
4346 info->closing_wait = 30*HZ;
4347 init_waitqueue_head(&info->open_wait);
4348 init_waitqueue_head(&info->close_wait);
4349 init_waitqueue_head(&info->status_event_wait_q);
4350 init_waitqueue_head(&info->event_wait_q);
4351 spin_lock_init(&info->irq_spinlock);
4352 spin_lock_init(&info->netlock);
4353 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
4354 info->idle_mode = HDLC_TXIDLE_FLAGS;
4355 info->num_tx_dma_buffers = 1;
4356 info->num_tx_holding_buffers = 0;
4357 }
4358
4359 return info;
4360
4361 } /* end of mgsl_allocate_device()*/
4362
4363 static struct tty_operations mgsl_ops = {
4364 .open = mgsl_open,
4365 .close = mgsl_close,
4366 .write = mgsl_write,
4367 .put_char = mgsl_put_char,
4368 .flush_chars = mgsl_flush_chars,
4369 .write_room = mgsl_write_room,
4370 .chars_in_buffer = mgsl_chars_in_buffer,
4371 .flush_buffer = mgsl_flush_buffer,
4372 .ioctl = mgsl_ioctl,
4373 .throttle = mgsl_throttle,
4374 .unthrottle = mgsl_unthrottle,
4375 .send_xchar = mgsl_send_xchar,
4376 .break_ctl = mgsl_break,
4377 .wait_until_sent = mgsl_wait_until_sent,
4378 .read_proc = mgsl_read_proc,
4379 .set_termios = mgsl_set_termios,
4380 .stop = mgsl_stop,
4381 .start = mgsl_start,
4382 .hangup = mgsl_hangup,
4383 .tiocmget = tiocmget,
4384 .tiocmset = tiocmset,
4385 };
4386
4387 /*
4388 * perform tty device initialization
4389 */
4390 static int mgsl_init_tty(void)
4391 {
4392 int rc;
4393
4394 serial_driver = alloc_tty_driver(128);
4395 if (!serial_driver)
4396 return -ENOMEM;
4397
4398 serial_driver->owner = THIS_MODULE;
4399 serial_driver->driver_name = "synclink";
4400 serial_driver->name = "ttySL";
4401 serial_driver->major = ttymajor;
4402 serial_driver->minor_start = 64;
4403 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
4404 serial_driver->subtype = SERIAL_TYPE_NORMAL;
4405 serial_driver->init_termios = tty_std_termios;
4406 serial_driver->init_termios.c_cflag =
4407 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
4408 serial_driver->flags = TTY_DRIVER_REAL_RAW;
4409 tty_set_operations(serial_driver, &mgsl_ops);
4410 if ((rc = tty_register_driver(serial_driver)) < 0) {
4411 printk("%s(%d):Couldn't register serial driver\n",
4412 __FILE__,__LINE__);
4413 put_tty_driver(serial_driver);
4414 serial_driver = NULL;
4415 return rc;
4416 }
4417
4418 printk("%s %s, tty major#%d\n",
4419 driver_name, driver_version,
4420 serial_driver->major);
4421 return 0;
4422 }
4423
4424 /* enumerate user specified ISA adapters
4425 */
4426 static void mgsl_enum_isa_devices(void)
4427 {
4428 struct mgsl_struct *info;
4429 int i;
4430
4431 /* Check for user specified ISA devices */
4432
4433 for (i=0 ;(i < MAX_ISA_DEVICES) && io[i] && irq[i]; i++){
4434 if ( debug_level >= DEBUG_LEVEL_INFO )
4435 printk("ISA device specified io=%04X,irq=%d,dma=%d\n",
4436 io[i], irq[i], dma[i] );
4437
4438 info = mgsl_allocate_device();
4439 if ( !info ) {
4440 /* error allocating device instance data */
4441 if ( debug_level >= DEBUG_LEVEL_ERROR )
4442 printk( "can't allocate device instance data.\n");
4443 continue;
4444 }
4445
4446 /* Copy user configuration info to device instance data */
4447 info->io_base = (unsigned int)io[i];
4448 info->irq_level = (unsigned int)irq[i];
4449 info->irq_level = irq_canonicalize(info->irq_level);
4450 info->dma_level = (unsigned int)dma[i];
4451 info->bus_type = MGSL_BUS_TYPE_ISA;
4452 info->io_addr_size = 16;
4453 info->irq_flags = 0;
4454
4455 mgsl_add_device( info );
4456 }
4457 }
4458
4459 static void synclink_cleanup(void)
4460 {
4461 int rc;
4462 struct mgsl_struct *info;
4463 struct mgsl_struct *tmp;
4464
4465 printk("Unloading %s: %s\n", driver_name, driver_version);
4466
4467 if (serial_driver) {
4468 if ((rc = tty_unregister_driver(serial_driver)))
4469 printk("%s(%d) failed to unregister tty driver err=%d\n",
4470 __FILE__,__LINE__,rc);
4471 put_tty_driver(serial_driver);
4472 }
4473
4474 info = mgsl_device_list;
4475 while(info) {
4476 #ifdef CONFIG_HDLC
4477 hdlcdev_exit(info);
4478 #endif
4479 mgsl_release_resources(info);
4480 tmp = info;
4481 info = info->next_device;
4482 kfree(tmp);
4483 }
4484
4485 if (pci_registered)
4486 pci_unregister_driver(&synclink_pci_driver);
4487 }
4488
4489 static int __init synclink_init(void)
4490 {
4491 int rc;
4492
4493 if (break_on_load) {
4494 mgsl_get_text_ptr();
4495 BREAKPOINT();
4496 }
4497
4498 printk("%s %s\n", driver_name, driver_version);
4499
4500 mgsl_enum_isa_devices();
4501 if ((rc = pci_register_driver(&synclink_pci_driver)) < 0)
4502 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
4503 else
4504 pci_registered = 1;
4505
4506 if ((rc = mgsl_init_tty()) < 0)
4507 goto error;
4508
4509 return 0;
4510
4511 error:
4512 synclink_cleanup();
4513 return rc;
4514 }
4515
4516 static void __exit synclink_exit(void)
4517 {
4518 synclink_cleanup();
4519 }
4520
4521 module_init(synclink_init);
4522 module_exit(synclink_exit);
4523
4524 /*
4525 * usc_RTCmd()
4526 *
4527 * Issue a USC Receive/Transmit command to the
4528 * Channel Command/Address Register (CCAR).
4529 *
4530 * Notes:
4531 *
4532 * The command is encoded in the most significant 5 bits <15..11>
4533 * of the CCAR value. Bits <10..7> of the CCAR must be preserved
4534 * and Bits <6..0> must be written as zeros.
4535 *
4536 * Arguments:
4537 *
4538 * info pointer to device information structure
4539 * Cmd command mask (use symbolic macros)
4540 *
4541 * Return Value:
4542 *
4543 * None
4544 */
4545 static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd )
4546 {
4547 /* output command to CCAR in bits <15..11> */
4548 /* preserve bits <10..7>, bits <6..0> must be zero */
4549
4550 outw( Cmd + info->loopback_bits, info->io_base + CCAR );
4551
4552 /* Read to flush write to CCAR */
4553 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4554 inw( info->io_base + CCAR );
4555
4556 } /* end of usc_RTCmd() */
4557
4558 /*
4559 * usc_DmaCmd()
4560 *
4561 * Issue a DMA command to the DMA Command/Address Register (DCAR).
4562 *
4563 * Arguments:
4564 *
4565 * info pointer to device information structure
4566 * Cmd DMA command mask (usc_DmaCmd_XX Macros)
4567 *
4568 * Return Value:
4569 *
4570 * None
4571 */
4572 static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd )
4573 {
4574 /* write command mask to DCAR */
4575 outw( Cmd + info->mbre_bit, info->io_base );
4576
4577 /* Read to flush write to DCAR */
4578 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4579 inw( info->io_base );
4580
4581 } /* end of usc_DmaCmd() */
4582
4583 /*
4584 * usc_OutDmaReg()
4585 *
4586 * Write a 16-bit value to a USC DMA register
4587 *
4588 * Arguments:
4589 *
4590 * info pointer to device info structure
4591 * RegAddr register address (number) for write
4592 * RegValue 16-bit value to write to register
4593 *
4594 * Return Value:
4595 *
4596 * None
4597 *
4598 */
4599 static void usc_OutDmaReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4600 {
4601 /* Note: The DCAR is located at the adapter base address */
4602 /* Note: must preserve state of BIT8 in DCAR */
4603
4604 outw( RegAddr + info->mbre_bit, info->io_base );
4605 outw( RegValue, info->io_base );
4606
4607 /* Read to flush write to DCAR */
4608 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4609 inw( info->io_base );
4610
4611 } /* end of usc_OutDmaReg() */
4612
4613 /*
4614 * usc_InDmaReg()
4615 *
4616 * Read a 16-bit value from a DMA register
4617 *
4618 * Arguments:
4619 *
4620 * info pointer to device info structure
4621 * RegAddr register address (number) to read from
4622 *
4623 * Return Value:
4624 *
4625 * The 16-bit value read from register
4626 *
4627 */
4628 static u16 usc_InDmaReg( struct mgsl_struct *info, u16 RegAddr )
4629 {
4630 /* Note: The DCAR is located at the adapter base address */
4631 /* Note: must preserve state of BIT8 in DCAR */
4632
4633 outw( RegAddr + info->mbre_bit, info->io_base );
4634 return inw( info->io_base );
4635
4636 } /* end of usc_InDmaReg() */
4637
4638 /*
4639 *
4640 * usc_OutReg()
4641 *
4642 * Write a 16-bit value to a USC serial channel register
4643 *
4644 * Arguments:
4645 *
4646 * info pointer to device info structure
4647 * RegAddr register address (number) to write to
4648 * RegValue 16-bit value to write to register
4649 *
4650 * Return Value:
4651 *
4652 * None
4653 *
4654 */
4655 static void usc_OutReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4656 {
4657 outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4658 outw( RegValue, info->io_base + CCAR );
4659
4660 /* Read to flush write to CCAR */
4661 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4662 inw( info->io_base + CCAR );
4663
4664 } /* end of usc_OutReg() */
4665
4666 /*
4667 * usc_InReg()
4668 *
4669 * Reads a 16-bit value from a USC serial channel register
4670 *
4671 * Arguments:
4672 *
4673 * info pointer to device extension
4674 * RegAddr register address (number) to read from
4675 *
4676 * Return Value:
4677 *
4678 * 16-bit value read from register
4679 */
4680 static u16 usc_InReg( struct mgsl_struct *info, u16 RegAddr )
4681 {
4682 outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4683 return inw( info->io_base + CCAR );
4684
4685 } /* end of usc_InReg() */
4686
4687 /* usc_set_sdlc_mode()
4688 *
4689 * Set up the adapter for SDLC DMA communications.
4690 *
4691 * Arguments: info pointer to device instance data
4692 * Return Value: NONE
4693 */
4694 static void usc_set_sdlc_mode( struct mgsl_struct *info )
4695 {
4696 u16 RegValue;
4697 int PreSL1660;
4698
4699 /*
4700 * determine if the IUSC on the adapter is pre-SL1660. If
4701 * not, take advantage of the UnderWait feature of more
4702 * modern chips. If an underrun occurs and this bit is set,
4703 * the transmitter will idle the programmed idle pattern
4704 * until the driver has time to service the underrun. Otherwise,
4705 * the dma controller may get the cycles previously requested
4706 * and begin transmitting queued tx data.
4707 */
4708 usc_OutReg(info,TMCR,0x1f);
4709 RegValue=usc_InReg(info,TMDR);
4710 if ( RegValue == IUSC_PRE_SL1660 )
4711 PreSL1660 = 1;
4712 else
4713 PreSL1660 = 0;
4714
4715
4716 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
4717 {
4718 /*
4719 ** Channel Mode Register (CMR)
4720 **
4721 ** <15..14> 10 Tx Sub Modes, Send Flag on Underrun
4722 ** <13> 0 0 = Transmit Disabled (initially)
4723 ** <12> 0 1 = Consecutive Idles share common 0
4724 ** <11..8> 1110 Transmitter Mode = HDLC/SDLC Loop
4725 ** <7..4> 0000 Rx Sub Modes, addr/ctrl field handling
4726 ** <3..0> 0110 Receiver Mode = HDLC/SDLC
4727 **
4728 ** 1000 1110 0000 0110 = 0x8e06
4729 */
4730 RegValue = 0x8e06;
4731
4732 /*--------------------------------------------------
4733 * ignore user options for UnderRun Actions and
4734 * preambles
4735 *--------------------------------------------------*/
4736 }
4737 else
4738 {
4739 /* Channel mode Register (CMR)
4740 *
4741 * <15..14> 00 Tx Sub modes, Underrun Action
4742 * <13> 0 1 = Send Preamble before opening flag
4743 * <12> 0 1 = Consecutive Idles share common 0
4744 * <11..8> 0110 Transmitter mode = HDLC/SDLC
4745 * <7..4> 0000 Rx Sub modes, addr/ctrl field handling
4746 * <3..0> 0110 Receiver mode = HDLC/SDLC
4747 *
4748 * 0000 0110 0000 0110 = 0x0606
4749 */
4750 if (info->params.mode == MGSL_MODE_RAW) {
4751 RegValue = 0x0001; /* Set Receive mode = external sync */
4752
4753 usc_OutReg( info, IOCR, /* Set IOCR DCD is RxSync Detect Input */
4754 (unsigned short)((usc_InReg(info, IOCR) & ~(BIT13|BIT12)) | BIT12));
4755
4756 /*
4757 * TxSubMode:
4758 * CMR <15> 0 Don't send CRC on Tx Underrun
4759 * CMR <14> x undefined
4760 * CMR <13> 0 Send preamble before openning sync
4761 * CMR <12> 0 Send 8-bit syncs, 1=send Syncs per TxLength
4762 *
4763 * TxMode:
4764 * CMR <11-8) 0100 MonoSync
4765 *
4766 * 0x00 0100 xxxx xxxx 04xx
4767 */
4768 RegValue |= 0x0400;
4769 }
4770 else {
4771
4772 RegValue = 0x0606;
4773
4774 if ( info->params.flags & HDLC_FLAG_UNDERRUN_ABORT15 )
4775 RegValue |= BIT14;
4776 else if ( info->params.flags & HDLC_FLAG_UNDERRUN_FLAG )
4777 RegValue |= BIT15;
4778 else if ( info->params.flags & HDLC_FLAG_UNDERRUN_CRC )
4779 RegValue |= BIT15 + BIT14;
4780 }
4781
4782 if ( info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE )
4783 RegValue |= BIT13;
4784 }
4785
4786 if ( info->params.mode == MGSL_MODE_HDLC &&
4787 (info->params.flags & HDLC_FLAG_SHARE_ZERO) )
4788 RegValue |= BIT12;
4789
4790 if ( info->params.addr_filter != 0xff )
4791 {
4792 /* set up receive address filtering */
4793 usc_OutReg( info, RSR, info->params.addr_filter );
4794 RegValue |= BIT4;
4795 }
4796
4797 usc_OutReg( info, CMR, RegValue );
4798 info->cmr_value = RegValue;
4799
4800 /* Receiver mode Register (RMR)
4801 *
4802 * <15..13> 000 encoding
4803 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4804 * <10> 1 1 = Set CRC to all 1s (use for SDLC/HDLC)
4805 * <9> 0 1 = Include Receive chars in CRC
4806 * <8> 1 1 = Use Abort/PE bit as abort indicator
4807 * <7..6> 00 Even parity
4808 * <5> 0 parity disabled
4809 * <4..2> 000 Receive Char Length = 8 bits
4810 * <1..0> 00 Disable Receiver
4811 *
4812 * 0000 0101 0000 0000 = 0x0500
4813 */
4814
4815 RegValue = 0x0500;
4816
4817 switch ( info->params.encoding ) {
4818 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
4819 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
4820 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 + BIT13; break;
4821 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
4822 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 + BIT13; break;
4823 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14; break;
4824 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break;
4825 }
4826
4827 if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
4828 RegValue |= BIT9;
4829 else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
4830 RegValue |= ( BIT12 | BIT10 | BIT9 );
4831
4832 usc_OutReg( info, RMR, RegValue );
4833
4834 /* Set the Receive count Limit Register (RCLR) to 0xffff. */
4835 /* When an opening flag of an SDLC frame is recognized the */
4836 /* Receive Character count (RCC) is loaded with the value in */
4837 /* RCLR. The RCC is decremented for each received byte. The */
4838 /* value of RCC is stored after the closing flag of the frame */
4839 /* allowing the frame size to be computed. */
4840
4841 usc_OutReg( info, RCLR, RCLRVALUE );
4842
4843 usc_RCmd( info, RCmd_SelectRicrdma_level );
4844
4845 /* Receive Interrupt Control Register (RICR)
4846 *
4847 * <15..8> ? RxFIFO DMA Request Level
4848 * <7> 0 Exited Hunt IA (Interrupt Arm)
4849 * <6> 0 Idle Received IA
4850 * <5> 0 Break/Abort IA
4851 * <4> 0 Rx Bound IA
4852 * <3> 1 Queued status reflects oldest 2 bytes in FIFO
4853 * <2> 0 Abort/PE IA
4854 * <1> 1 Rx Overrun IA
4855 * <0> 0 Select TC0 value for readback
4856 *
4857 * 0000 0000 0000 1000 = 0x000a
4858 */
4859
4860 /* Carry over the Exit Hunt and Idle Received bits */
4861 /* in case they have been armed by usc_ArmEvents. */
4862
4863 RegValue = usc_InReg( info, RICR ) & 0xc0;
4864
4865 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4866 usc_OutReg( info, RICR, (u16)(0x030a | RegValue) );
4867 else
4868 usc_OutReg( info, RICR, (u16)(0x140a | RegValue) );
4869
4870 /* Unlatch all Rx status bits and clear Rx status IRQ Pending */
4871
4872 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
4873 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
4874
4875 /* Transmit mode Register (TMR)
4876 *
4877 * <15..13> 000 encoding
4878 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4879 * <10> 1 1 = Start CRC as all 1s (use for SDLC/HDLC)
4880 * <9> 0 1 = Tx CRC Enabled
4881 * <8> 0 1 = Append CRC to end of transmit frame
4882 * <7..6> 00 Transmit parity Even
4883 * <5> 0 Transmit parity Disabled
4884 * <4..2> 000 Tx Char Length = 8 bits
4885 * <1..0> 00 Disable Transmitter
4886 *
4887 * 0000 0100 0000 0000 = 0x0400
4888 */
4889
4890 RegValue = 0x0400;
4891
4892 switch ( info->params.encoding ) {
4893 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
4894 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
4895 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 + BIT13; break;
4896 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
4897 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 + BIT13; break;
4898 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14; break;
4899 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break;
4900 }
4901
4902 if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
4903 RegValue |= BIT9 + BIT8;
4904 else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
4905 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8);
4906
4907 usc_OutReg( info, TMR, RegValue );
4908
4909 usc_set_txidle( info );
4910
4911
4912 usc_TCmd( info, TCmd_SelectTicrdma_level );
4913
4914 /* Transmit Interrupt Control Register (TICR)
4915 *
4916 * <15..8> ? Transmit FIFO DMA Level
4917 * <7> 0 Present IA (Interrupt Arm)
4918 * <6> 0 Idle Sent IA
4919 * <5> 1 Abort Sent IA
4920 * <4> 1 EOF/EOM Sent IA
4921 * <3> 0 CRC Sent IA
4922 * <2> 1 1 = Wait for SW Trigger to Start Frame
4923 * <1> 1 Tx Underrun IA
4924 * <0> 0 TC0 constant on read back
4925 *
4926 * 0000 0000 0011 0110 = 0x0036
4927 */
4928
4929 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4930 usc_OutReg( info, TICR, 0x0736 );
4931 else
4932 usc_OutReg( info, TICR, 0x1436 );
4933
4934 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
4935 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
4936
4937 /*
4938 ** Transmit Command/Status Register (TCSR)
4939 **
4940 ** <15..12> 0000 TCmd
4941 ** <11> 0/1 UnderWait
4942 ** <10..08> 000 TxIdle
4943 ** <7> x PreSent
4944 ** <6> x IdleSent
4945 ** <5> x AbortSent
4946 ** <4> x EOF/EOM Sent
4947 ** <3> x CRC Sent
4948 ** <2> x All Sent
4949 ** <1> x TxUnder
4950 ** <0> x TxEmpty
4951 **
4952 ** 0000 0000 0000 0000 = 0x0000
4953 */
4954 info->tcsr_value = 0;
4955
4956 if ( !PreSL1660 )
4957 info->tcsr_value |= TCSR_UNDERWAIT;
4958
4959 usc_OutReg( info, TCSR, info->tcsr_value );
4960
4961 /* Clock mode Control Register (CMCR)
4962 *
4963 * <15..14> 00 counter 1 Source = Disabled
4964 * <13..12> 00 counter 0 Source = Disabled
4965 * <11..10> 11 BRG1 Input is TxC Pin
4966 * <9..8> 11 BRG0 Input is TxC Pin
4967 * <7..6> 01 DPLL Input is BRG1 Output
4968 * <5..3> XXX TxCLK comes from Port 0
4969 * <2..0> XXX RxCLK comes from Port 1
4970 *
4971 * 0000 1111 0111 0111 = 0x0f77
4972 */
4973
4974 RegValue = 0x0f40;
4975
4976 if ( info->params.flags & HDLC_FLAG_RXC_DPLL )
4977 RegValue |= 0x0003; /* RxCLK from DPLL */
4978 else if ( info->params.flags & HDLC_FLAG_RXC_BRG )
4979 RegValue |= 0x0004; /* RxCLK from BRG0 */
4980 else if ( info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4981 RegValue |= 0x0006; /* RxCLK from TXC Input */
4982 else
4983 RegValue |= 0x0007; /* RxCLK from Port1 */
4984
4985 if ( info->params.flags & HDLC_FLAG_TXC_DPLL )
4986 RegValue |= 0x0018; /* TxCLK from DPLL */
4987 else if ( info->params.flags & HDLC_FLAG_TXC_BRG )
4988 RegValue |= 0x0020; /* TxCLK from BRG0 */
4989 else if ( info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4990 RegValue |= 0x0038; /* RxCLK from TXC Input */
4991 else
4992 RegValue |= 0x0030; /* TxCLK from Port0 */
4993
4994 usc_OutReg( info, CMCR, RegValue );
4995
4996
4997 /* Hardware Configuration Register (HCR)
4998 *
4999 * <15..14> 00 CTR0 Divisor:00=32,01=16,10=8,11=4
5000 * <13> 0 CTR1DSel:0=CTR0Div determines CTR0Div
5001 * <12> 0 CVOK:0=report code violation in biphase
5002 * <11..10> 00 DPLL Divisor:00=32,01=16,10=8,11=4
5003 * <9..8> XX DPLL mode:00=disable,01=NRZ,10=Biphase,11=Biphase Level
5004 * <7..6> 00 reserved
5005 * <5> 0 BRG1 mode:0=continuous,1=single cycle
5006 * <4> X BRG1 Enable
5007 * <3..2> 00 reserved
5008 * <1> 0 BRG0 mode:0=continuous,1=single cycle
5009 * <0> 0 BRG0 Enable
5010 */
5011
5012 RegValue = 0x0000;
5013
5014 if ( info->params.flags & (HDLC_FLAG_RXC_DPLL + HDLC_FLAG_TXC_DPLL) ) {
5015 u32 XtalSpeed;
5016 u32 DpllDivisor;
5017 u16 Tc;
5018
5019 /* DPLL is enabled. Use BRG1 to provide continuous reference clock */
5020 /* for DPLL. DPLL mode in HCR is dependent on the encoding used. */
5021
5022 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
5023 XtalSpeed = 11059200;
5024 else
5025 XtalSpeed = 14745600;
5026
5027 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
5028 DpllDivisor = 16;
5029 RegValue |= BIT10;
5030 }
5031 else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
5032 DpllDivisor = 8;
5033 RegValue |= BIT11;
5034 }
5035 else
5036 DpllDivisor = 32;
5037
5038 /* Tc = (Xtal/Speed) - 1 */
5039 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
5040 /* then rounding up gives a more precise time constant. Instead */
5041 /* of rounding up and then subtracting 1 we just don't subtract */
5042 /* the one in this case. */
5043
5044 /*--------------------------------------------------
5045 * ejz: for DPLL mode, application should use the
5046 * same clock speed as the partner system, even
5047 * though clocking is derived from the input RxData.
5048 * In case the user uses a 0 for the clock speed,
5049 * default to 0xffffffff and don't try to divide by
5050 * zero
5051 *--------------------------------------------------*/
5052 if ( info->params.clock_speed )
5053 {
5054 Tc = (u16)((XtalSpeed/DpllDivisor)/info->params.clock_speed);
5055 if ( !((((XtalSpeed/DpllDivisor) % info->params.clock_speed) * 2)
5056 / info->params.clock_speed) )
5057 Tc--;
5058 }
5059 else
5060 Tc = -1;
5061
5062
5063 /* Write 16-bit Time Constant for BRG1 */
5064 usc_OutReg( info, TC1R, Tc );
5065
5066 RegValue |= BIT4; /* enable BRG1 */
5067
5068 switch ( info->params.encoding ) {
5069 case HDLC_ENCODING_NRZ:
5070 case HDLC_ENCODING_NRZB:
5071 case HDLC_ENCODING_NRZI_MARK:
5072 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT8; break;
5073 case HDLC_ENCODING_BIPHASE_MARK:
5074 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT9; break;
5075 case HDLC_ENCODING_BIPHASE_LEVEL:
5076 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 + BIT8; break;
5077 }
5078 }
5079
5080 usc_OutReg( info, HCR, RegValue );
5081
5082
5083 /* Channel Control/status Register (CCSR)
5084 *
5085 * <15> X RCC FIFO Overflow status (RO)
5086 * <14> X RCC FIFO Not Empty status (RO)
5087 * <13> 0 1 = Clear RCC FIFO (WO)
5088 * <12> X DPLL Sync (RW)
5089 * <11> X DPLL 2 Missed Clocks status (RO)
5090 * <10> X DPLL 1 Missed Clock status (RO)
5091 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
5092 * <7> X SDLC Loop On status (RO)
5093 * <6> X SDLC Loop Send status (RO)
5094 * <5> 1 Bypass counters for TxClk and RxClk (RW)
5095 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
5096 * <1..0> 00 reserved
5097 *
5098 * 0000 0000 0010 0000 = 0x0020
5099 */
5100
5101 usc_OutReg( info, CCSR, 0x1020 );
5102
5103
5104 if ( info->params.flags & HDLC_FLAG_AUTO_CTS ) {
5105 usc_OutReg( info, SICR,
5106 (u16)(usc_InReg(info,SICR) | SICR_CTS_INACTIVE) );
5107 }
5108
5109
5110 /* enable Master Interrupt Enable bit (MIE) */
5111 usc_EnableMasterIrqBit( info );
5112
5113 usc_ClearIrqPendingBits( info, RECEIVE_STATUS + RECEIVE_DATA +
5114 TRANSMIT_STATUS + TRANSMIT_DATA + MISC);
5115
5116 /* arm RCC underflow interrupt */
5117 usc_OutReg(info, SICR, (u16)(usc_InReg(info,SICR) | BIT3));
5118 usc_EnableInterrupts(info, MISC);
5119
5120 info->mbre_bit = 0;
5121 outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */
5122 usc_DmaCmd( info, DmaCmd_ResetAllChannels ); /* disable both DMA channels */
5123 info->mbre_bit = BIT8;
5124 outw( BIT8, info->io_base ); /* set Master Bus Enable (DCAR) */
5125
5126 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
5127 /* Enable DMAEN (Port 7, Bit 14) */
5128 /* This connects the DMA request signal to the ISA bus */
5129 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) & ~BIT14));
5130 }
5131
5132 /* DMA Control Register (DCR)
5133 *
5134 * <15..14> 10 Priority mode = Alternating Tx/Rx
5135 * 01 Rx has priority
5136 * 00 Tx has priority
5137 *
5138 * <13> 1 Enable Priority Preempt per DCR<15..14>
5139 * (WARNING DCR<11..10> must be 00 when this is 1)
5140 * 0 Choose activate channel per DCR<11..10>
5141 *
5142 * <12> 0 Little Endian for Array/List
5143 * <11..10> 00 Both Channels can use each bus grant
5144 * <9..6> 0000 reserved
5145 * <5> 0 7 CLK - Minimum Bus Re-request Interval
5146 * <4> 0 1 = drive D/C and S/D pins
5147 * <3> 1 1 = Add one wait state to all DMA cycles.
5148 * <2> 0 1 = Strobe /UAS on every transfer.
5149 * <1..0> 11 Addr incrementing only affects LS24 bits
5150 *
5151 * 0110 0000 0000 1011 = 0x600b
5152 */
5153
5154 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5155 /* PCI adapter does not need DMA wait state */
5156 usc_OutDmaReg( info, DCR, 0xa00b );
5157 }
5158 else
5159 usc_OutDmaReg( info, DCR, 0x800b );
5160
5161
5162 /* Receive DMA mode Register (RDMR)
5163 *
5164 * <15..14> 11 DMA mode = Linked List Buffer mode
5165 * <13> 1 RSBinA/L = store Rx status Block in Arrary/List entry
5166 * <12> 1 Clear count of List Entry after fetching
5167 * <11..10> 00 Address mode = Increment
5168 * <9> 1 Terminate Buffer on RxBound
5169 * <8> 0 Bus Width = 16bits
5170 * <7..0> ? status Bits (write as 0s)
5171 *
5172 * 1111 0010 0000 0000 = 0xf200
5173 */
5174
5175 usc_OutDmaReg( info, RDMR, 0xf200 );
5176
5177
5178 /* Transmit DMA mode Register (TDMR)
5179 *
5180 * <15..14> 11 DMA mode = Linked List Buffer mode
5181 * <13> 1 TCBinA/L = fetch Tx Control Block from List entry
5182 * <12> 1 Clear count of List Entry after fetching
5183 * <11..10> 00 Address mode = Increment
5184 * <9> 1 Terminate Buffer on end of frame
5185 * <8> 0 Bus Width = 16bits
5186 * <7..0> ? status Bits (Read Only so write as 0)
5187 *
5188 * 1111 0010 0000 0000 = 0xf200
5189 */
5190
5191 usc_OutDmaReg( info, TDMR, 0xf200 );
5192
5193
5194 /* DMA Interrupt Control Register (DICR)
5195 *
5196 * <15> 1 DMA Interrupt Enable
5197 * <14> 0 1 = Disable IEO from USC
5198 * <13> 0 1 = Don't provide vector during IntAck
5199 * <12> 1 1 = Include status in Vector
5200 * <10..2> 0 reserved, Must be 0s
5201 * <1> 0 1 = Rx DMA Interrupt Enabled
5202 * <0> 0 1 = Tx DMA Interrupt Enabled
5203 *
5204 * 1001 0000 0000 0000 = 0x9000
5205 */
5206
5207 usc_OutDmaReg( info, DICR, 0x9000 );
5208
5209 usc_InDmaReg( info, RDMR ); /* clear pending receive DMA IRQ bits */
5210 usc_InDmaReg( info, TDMR ); /* clear pending transmit DMA IRQ bits */
5211 usc_OutDmaReg( info, CDIR, 0x0303 ); /* clear IUS and Pending for Tx and Rx */
5212
5213 /* Channel Control Register (CCR)
5214 *
5215 * <15..14> 10 Use 32-bit Tx Control Blocks (TCBs)
5216 * <13> 0 Trigger Tx on SW Command Disabled
5217 * <12> 0 Flag Preamble Disabled
5218 * <11..10> 00 Preamble Length
5219 * <9..8> 00 Preamble Pattern
5220 * <7..6> 10 Use 32-bit Rx status Blocks (RSBs)
5221 * <5> 0 Trigger Rx on SW Command Disabled
5222 * <4..0> 0 reserved
5223 *
5224 * 1000 0000 1000 0000 = 0x8080
5225 */
5226
5227 RegValue = 0x8080;
5228
5229 switch ( info->params.preamble_length ) {
5230 case HDLC_PREAMBLE_LENGTH_16BITS: RegValue |= BIT10; break;
5231 case HDLC_PREAMBLE_LENGTH_32BITS: RegValue |= BIT11; break;
5232 case HDLC_PREAMBLE_LENGTH_64BITS: RegValue |= BIT11 + BIT10; break;
5233 }
5234
5235 switch ( info->params.preamble ) {
5236 case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue |= BIT8 + BIT12; break;
5237 case HDLC_PREAMBLE_PATTERN_ONES: RegValue |= BIT8; break;
5238 case HDLC_PREAMBLE_PATTERN_10: RegValue |= BIT9; break;
5239 case HDLC_PREAMBLE_PATTERN_01: RegValue |= BIT9 + BIT8; break;
5240 }
5241
5242 usc_OutReg( info, CCR, RegValue );
5243
5244
5245 /*
5246 * Burst/Dwell Control Register
5247 *
5248 * <15..8> 0x20 Maximum number of transfers per bus grant
5249 * <7..0> 0x00 Maximum number of clock cycles per bus grant
5250 */
5251
5252 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5253 /* don't limit bus occupancy on PCI adapter */
5254 usc_OutDmaReg( info, BDCR, 0x0000 );
5255 }
5256 else
5257 usc_OutDmaReg( info, BDCR, 0x2000 );
5258
5259 usc_stop_transmitter(info);
5260 usc_stop_receiver(info);
5261
5262 } /* end of usc_set_sdlc_mode() */
5263
5264 /* usc_enable_loopback()
5265 *
5266 * Set the 16C32 for internal loopback mode.
5267 * The TxCLK and RxCLK signals are generated from the BRG0 and
5268 * the TxD is looped back to the RxD internally.
5269 *
5270 * Arguments: info pointer to device instance data
5271 * enable 1 = enable loopback, 0 = disable
5272 * Return Value: None
5273 */
5274 static void usc_enable_loopback(struct mgsl_struct *info, int enable)
5275 {
5276 if (enable) {
5277 /* blank external TXD output */
5278 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) | (BIT7+BIT6));
5279
5280 /* Clock mode Control Register (CMCR)
5281 *
5282 * <15..14> 00 counter 1 Disabled
5283 * <13..12> 00 counter 0 Disabled
5284 * <11..10> 11 BRG1 Input is TxC Pin
5285 * <9..8> 11 BRG0 Input is TxC Pin
5286 * <7..6> 01 DPLL Input is BRG1 Output
5287 * <5..3> 100 TxCLK comes from BRG0
5288 * <2..0> 100 RxCLK comes from BRG0
5289 *
5290 * 0000 1111 0110 0100 = 0x0f64
5291 */
5292
5293 usc_OutReg( info, CMCR, 0x0f64 );
5294
5295 /* Write 16-bit Time Constant for BRG0 */
5296 /* use clock speed if available, otherwise use 8 for diagnostics */
5297 if (info->params.clock_speed) {
5298 if (info->bus_type == MGSL_BUS_TYPE_PCI)
5299 usc_OutReg(info, TC0R, (u16)((11059200/info->params.clock_speed)-1));
5300 else
5301 usc_OutReg(info, TC0R, (u16)((14745600/info->params.clock_speed)-1));
5302 } else
5303 usc_OutReg(info, TC0R, (u16)8);
5304
5305 /* Hardware Configuration Register (HCR) Clear Bit 1, BRG0
5306 mode = Continuous Set Bit 0 to enable BRG0. */
5307 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5308
5309 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5310 usc_OutReg(info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004));
5311
5312 /* set Internal Data loopback mode */
5313 info->loopback_bits = 0x300;
5314 outw( 0x0300, info->io_base + CCAR );
5315 } else {
5316 /* enable external TXD output */
5317 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) & ~(BIT7+BIT6));
5318
5319 /* clear Internal Data loopback mode */
5320 info->loopback_bits = 0;
5321 outw( 0,info->io_base + CCAR );
5322 }
5323
5324 } /* end of usc_enable_loopback() */
5325
5326 /* usc_enable_aux_clock()
5327 *
5328 * Enabled the AUX clock output at the specified frequency.
5329 *
5330 * Arguments:
5331 *
5332 * info pointer to device extension
5333 * data_rate data rate of clock in bits per second
5334 * A data rate of 0 disables the AUX clock.
5335 *
5336 * Return Value: None
5337 */
5338 static void usc_enable_aux_clock( struct mgsl_struct *info, u32 data_rate )
5339 {
5340 u32 XtalSpeed;
5341 u16 Tc;
5342
5343 if ( data_rate ) {
5344 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
5345 XtalSpeed = 11059200;
5346 else
5347 XtalSpeed = 14745600;
5348
5349
5350 /* Tc = (Xtal/Speed) - 1 */
5351 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
5352 /* then rounding up gives a more precise time constant. Instead */
5353 /* of rounding up and then subtracting 1 we just don't subtract */
5354 /* the one in this case. */
5355
5356
5357 Tc = (u16)(XtalSpeed/data_rate);
5358 if ( !(((XtalSpeed % data_rate) * 2) / data_rate) )
5359 Tc--;
5360
5361 /* Write 16-bit Time Constant for BRG0 */
5362 usc_OutReg( info, TC0R, Tc );
5363
5364 /*
5365 * Hardware Configuration Register (HCR)
5366 * Clear Bit 1, BRG0 mode = Continuous
5367 * Set Bit 0 to enable BRG0.
5368 */
5369
5370 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5371
5372 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5373 usc_OutReg( info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
5374 } else {
5375 /* data rate == 0 so turn off BRG0 */
5376 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
5377 }
5378
5379 } /* end of usc_enable_aux_clock() */
5380
5381 /*
5382 *
5383 * usc_process_rxoverrun_sync()
5384 *
5385 * This function processes a receive overrun by resetting the
5386 * receive DMA buffers and issuing a Purge Rx FIFO command
5387 * to allow the receiver to continue receiving.
5388 *
5389 * Arguments:
5390 *
5391 * info pointer to device extension
5392 *
5393 * Return Value: None
5394 */
5395 static void usc_process_rxoverrun_sync( struct mgsl_struct *info )
5396 {
5397 int start_index;
5398 int end_index;
5399 int frame_start_index;
5400 int start_of_frame_found = FALSE;
5401 int end_of_frame_found = FALSE;
5402 int reprogram_dma = FALSE;
5403
5404 DMABUFFERENTRY *buffer_list = info->rx_buffer_list;
5405 u32 phys_addr;
5406
5407 usc_DmaCmd( info, DmaCmd_PauseRxChannel );
5408 usc_RCmd( info, RCmd_EnterHuntmode );
5409 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5410
5411 /* CurrentRxBuffer points to the 1st buffer of the next */
5412 /* possibly available receive frame. */
5413
5414 frame_start_index = start_index = end_index = info->current_rx_buffer;
5415
5416 /* Search for an unfinished string of buffers. This means */
5417 /* that a receive frame started (at least one buffer with */
5418 /* count set to zero) but there is no terminiting buffer */
5419 /* (status set to non-zero). */
5420
5421 while( !buffer_list[end_index].count )
5422 {
5423 /* Count field has been reset to zero by 16C32. */
5424 /* This buffer is currently in use. */
5425
5426 if ( !start_of_frame_found )
5427 {
5428 start_of_frame_found = TRUE;
5429 frame_start_index = end_index;
5430 end_of_frame_found = FALSE;
5431 }
5432
5433 if ( buffer_list[end_index].status )
5434 {
5435 /* Status field has been set by 16C32. */
5436 /* This is the last buffer of a received frame. */
5437
5438 /* We want to leave the buffers for this frame intact. */
5439 /* Move on to next possible frame. */
5440
5441 start_of_frame_found = FALSE;
5442 end_of_frame_found = TRUE;
5443 }
5444
5445 /* advance to next buffer entry in linked list */
5446 end_index++;
5447 if ( end_index == info->rx_buffer_count )
5448 end_index = 0;
5449
5450 if ( start_index == end_index )
5451 {
5452 /* The entire list has been searched with all Counts == 0 and */
5453 /* all Status == 0. The receive buffers are */
5454 /* completely screwed, reset all receive buffers! */
5455 mgsl_reset_rx_dma_buffers( info );
5456 frame_start_index = 0;
5457 start_of_frame_found = FALSE;
5458 reprogram_dma = TRUE;
5459 break;
5460 }
5461 }
5462
5463 if ( start_of_frame_found && !end_of_frame_found )
5464 {
5465 /* There is an unfinished string of receive DMA buffers */
5466 /* as a result of the receiver overrun. */
5467
5468 /* Reset the buffers for the unfinished frame */
5469 /* and reprogram the receive DMA controller to start */
5470 /* at the 1st buffer of unfinished frame. */
5471
5472 start_index = frame_start_index;
5473
5474 do
5475 {
5476 *((unsigned long *)&(info->rx_buffer_list[start_index++].count)) = DMABUFFERSIZE;
5477
5478 /* Adjust index for wrap around. */
5479 if ( start_index == info->rx_buffer_count )
5480 start_index = 0;
5481
5482 } while( start_index != end_index );
5483
5484 reprogram_dma = TRUE;
5485 }
5486
5487 if ( reprogram_dma )
5488 {
5489 usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
5490 usc_ClearIrqPendingBits(info, RECEIVE_DATA|RECEIVE_STATUS);
5491 usc_UnlatchRxstatusBits(info, RECEIVE_DATA|RECEIVE_STATUS);
5492
5493 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
5494
5495 /* This empties the receive FIFO and loads the RCC with RCLR */
5496 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5497
5498 /* program 16C32 with physical address of 1st DMA buffer entry */
5499 phys_addr = info->rx_buffer_list[frame_start_index].phys_entry;
5500 usc_OutDmaReg( info, NRARL, (u16)phys_addr );
5501 usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
5502
5503 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5504 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5505 usc_EnableInterrupts( info, RECEIVE_STATUS );
5506
5507 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5508 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5509
5510 usc_OutDmaReg( info, RDIAR, BIT3 + BIT2 );
5511 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5512 usc_DmaCmd( info, DmaCmd_InitRxChannel );
5513 if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
5514 usc_EnableReceiver(info,ENABLE_AUTO_DCD);
5515 else
5516 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5517 }
5518 else
5519 {
5520 /* This empties the receive FIFO and loads the RCC with RCLR */
5521 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5522 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5523 }
5524
5525 } /* end of usc_process_rxoverrun_sync() */
5526
5527 /* usc_stop_receiver()
5528 *
5529 * Disable USC receiver
5530 *
5531 * Arguments: info pointer to device instance data
5532 * Return Value: None
5533 */
5534 static void usc_stop_receiver( struct mgsl_struct *info )
5535 {
5536 if (debug_level >= DEBUG_LEVEL_ISR)
5537 printk("%s(%d):usc_stop_receiver(%s)\n",
5538 __FILE__,__LINE__, info->device_name );
5539
5540 /* Disable receive DMA channel. */
5541 /* This also disables receive DMA channel interrupts */
5542 usc_DmaCmd( info, DmaCmd_ResetRxChannel );
5543
5544 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5545 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5546 usc_DisableInterrupts( info, RECEIVE_DATA + RECEIVE_STATUS );
5547
5548 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
5549
5550 /* This empties the receive FIFO and loads the RCC with RCLR */
5551 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5552 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5553
5554 info->rx_enabled = 0;
5555 info->rx_overflow = 0;
5556 info->rx_rcc_underrun = 0;
5557
5558 } /* end of stop_receiver() */
5559
5560 /* usc_start_receiver()
5561 *
5562 * Enable the USC receiver
5563 *
5564 * Arguments: info pointer to device instance data
5565 * Return Value: None
5566 */
5567 static void usc_start_receiver( struct mgsl_struct *info )
5568 {
5569 u32 phys_addr;
5570
5571 if (debug_level >= DEBUG_LEVEL_ISR)
5572 printk("%s(%d):usc_start_receiver(%s)\n",
5573 __FILE__,__LINE__, info->device_name );
5574
5575 mgsl_reset_rx_dma_buffers( info );
5576 usc_stop_receiver( info );
5577
5578 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5579 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5580
5581 if ( info->params.mode == MGSL_MODE_HDLC ||
5582 info->params.mode == MGSL_MODE_RAW ) {
5583 /* DMA mode Transfers */
5584 /* Program the DMA controller. */
5585 /* Enable the DMA controller end of buffer interrupt. */
5586
5587 /* program 16C32 with physical address of 1st DMA buffer entry */
5588 phys_addr = info->rx_buffer_list[0].phys_entry;
5589 usc_OutDmaReg( info, NRARL, (u16)phys_addr );
5590 usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
5591
5592 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5593 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5594 usc_EnableInterrupts( info, RECEIVE_STATUS );
5595
5596 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5597 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5598
5599 usc_OutDmaReg( info, RDIAR, BIT3 + BIT2 );
5600 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5601 usc_DmaCmd( info, DmaCmd_InitRxChannel );
5602 if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
5603 usc_EnableReceiver(info,ENABLE_AUTO_DCD);
5604 else
5605 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5606 } else {
5607 usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
5608 usc_ClearIrqPendingBits(info, RECEIVE_DATA + RECEIVE_STATUS);
5609 usc_EnableInterrupts(info, RECEIVE_DATA);
5610
5611 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5612 usc_RCmd( info, RCmd_EnterHuntmode );
5613
5614 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5615 }
5616
5617 usc_OutReg( info, CCSR, 0x1020 );
5618
5619 info->rx_enabled = 1;
5620
5621 } /* end of usc_start_receiver() */
5622
5623 /* usc_start_transmitter()
5624 *
5625 * Enable the USC transmitter and send a transmit frame if
5626 * one is loaded in the DMA buffers.
5627 *
5628 * Arguments: info pointer to device instance data
5629 * Return Value: None
5630 */
5631 static void usc_start_transmitter( struct mgsl_struct *info )
5632 {
5633 u32 phys_addr;
5634 unsigned int FrameSize;
5635
5636 if (debug_level >= DEBUG_LEVEL_ISR)
5637 printk("%s(%d):usc_start_transmitter(%s)\n",
5638 __FILE__,__LINE__, info->device_name );
5639
5640 if ( info->xmit_cnt ) {
5641
5642 /* If auto RTS enabled and RTS is inactive, then assert */
5643 /* RTS and set a flag indicating that the driver should */
5644 /* negate RTS when the transmission completes. */
5645
5646 info->drop_rts_on_tx_done = 0;
5647
5648 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
5649 usc_get_serial_signals( info );
5650 if ( !(info->serial_signals & SerialSignal_RTS) ) {
5651 info->serial_signals |= SerialSignal_RTS;
5652 usc_set_serial_signals( info );
5653 info->drop_rts_on_tx_done = 1;
5654 }
5655 }
5656
5657
5658 if ( info->params.mode == MGSL_MODE_ASYNC ) {
5659 if ( !info->tx_active ) {
5660 usc_UnlatchTxstatusBits(info, TXSTATUS_ALL);
5661 usc_ClearIrqPendingBits(info, TRANSMIT_STATUS + TRANSMIT_DATA);
5662 usc_EnableInterrupts(info, TRANSMIT_DATA);
5663 usc_load_txfifo(info);
5664 }
5665 } else {
5666 /* Disable transmit DMA controller while programming. */
5667 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5668
5669 /* Transmit DMA buffer is loaded, so program USC */
5670 /* to send the frame contained in the buffers. */
5671
5672 FrameSize = info->tx_buffer_list[info->start_tx_dma_buffer].rcc;
5673
5674 /* if operating in Raw sync mode, reset the rcc component
5675 * of the tx dma buffer entry, otherwise, the serial controller
5676 * will send a closing sync char after this count.
5677 */
5678 if ( info->params.mode == MGSL_MODE_RAW )
5679 info->tx_buffer_list[info->start_tx_dma_buffer].rcc = 0;
5680
5681 /* Program the Transmit Character Length Register (TCLR) */
5682 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
5683 usc_OutReg( info, TCLR, (u16)FrameSize );
5684
5685 usc_RTCmd( info, RTCmd_PurgeTxFifo );
5686
5687 /* Program the address of the 1st DMA Buffer Entry in linked list */
5688 phys_addr = info->tx_buffer_list[info->start_tx_dma_buffer].phys_entry;
5689 usc_OutDmaReg( info, NTARL, (u16)phys_addr );
5690 usc_OutDmaReg( info, NTARU, (u16)(phys_addr >> 16) );
5691
5692 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5693 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
5694 usc_EnableInterrupts( info, TRANSMIT_STATUS );
5695
5696 if ( info->params.mode == MGSL_MODE_RAW &&
5697 info->num_tx_dma_buffers > 1 ) {
5698 /* When running external sync mode, attempt to 'stream' transmit */
5699 /* by filling tx dma buffers as they become available. To do this */
5700 /* we need to enable Tx DMA EOB Status interrupts : */
5701 /* */
5702 /* 1. Arm End of Buffer (EOB) Transmit DMA Interrupt (BIT2 of TDIAR) */
5703 /* 2. Enable Transmit DMA Interrupts (BIT0 of DICR) */
5704
5705 usc_OutDmaReg( info, TDIAR, BIT2|BIT3 );
5706 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT0) );
5707 }
5708
5709 /* Initialize Transmit DMA Channel */
5710 usc_DmaCmd( info, DmaCmd_InitTxChannel );
5711
5712 usc_TCmd( info, TCmd_SendFrame );
5713
5714 info->tx_timer.expires = jiffies + msecs_to_jiffies(5000);
5715 add_timer(&info->tx_timer);
5716 }
5717 info->tx_active = 1;
5718 }
5719
5720 if ( !info->tx_enabled ) {
5721 info->tx_enabled = 1;
5722 if ( info->params.flags & HDLC_FLAG_AUTO_CTS )
5723 usc_EnableTransmitter(info,ENABLE_AUTO_CTS);
5724 else
5725 usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
5726 }
5727
5728 } /* end of usc_start_transmitter() */
5729
5730 /* usc_stop_transmitter()
5731 *
5732 * Stops the transmitter and DMA
5733 *
5734 * Arguments: info pointer to device isntance data
5735 * Return Value: None
5736 */
5737 static void usc_stop_transmitter( struct mgsl_struct *info )
5738 {
5739 if (debug_level >= DEBUG_LEVEL_ISR)
5740 printk("%s(%d):usc_stop_transmitter(%s)\n",
5741 __FILE__,__LINE__, info->device_name );
5742
5743 del_timer(&info->tx_timer);
5744
5745 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5746 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5747 usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5748
5749 usc_EnableTransmitter(info,DISABLE_UNCONDITIONAL);
5750 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5751 usc_RTCmd( info, RTCmd_PurgeTxFifo );
5752
5753 info->tx_enabled = 0;
5754 info->tx_active = 0;
5755
5756 } /* end of usc_stop_transmitter() */
5757
5758 /* usc_load_txfifo()
5759 *
5760 * Fill the transmit FIFO until the FIFO is full or
5761 * there is no more data to load.
5762 *
5763 * Arguments: info pointer to device extension (instance data)
5764 * Return Value: None
5765 */
5766 static void usc_load_txfifo( struct mgsl_struct *info )
5767 {
5768 int Fifocount;
5769 u8 TwoBytes[2];
5770
5771 if ( !info->xmit_cnt && !info->x_char )
5772 return;
5773
5774 /* Select transmit FIFO status readback in TICR */
5775 usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
5776
5777 /* load the Transmit FIFO until FIFOs full or all data sent */
5778
5779 while( (Fifocount = usc_InReg(info, TICR) >> 8) && info->xmit_cnt ) {
5780 /* there is more space in the transmit FIFO and */
5781 /* there is more data in transmit buffer */
5782
5783 if ( (info->xmit_cnt > 1) && (Fifocount > 1) && !info->x_char ) {
5784 /* write a 16-bit word from transmit buffer to 16C32 */
5785
5786 TwoBytes[0] = info->xmit_buf[info->xmit_tail++];
5787 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5788 TwoBytes[1] = info->xmit_buf[info->xmit_tail++];
5789 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5790
5791 outw( *((u16 *)TwoBytes), info->io_base + DATAREG);
5792
5793 info->xmit_cnt -= 2;
5794 info->icount.tx += 2;
5795 } else {
5796 /* only 1 byte left to transmit or 1 FIFO slot left */
5797
5798 outw( (inw( info->io_base + CCAR) & 0x0780) | (TDR+LSBONLY),
5799 info->io_base + CCAR );
5800
5801 if (info->x_char) {
5802 /* transmit pending high priority char */
5803 outw( info->x_char,info->io_base + CCAR );
5804 info->x_char = 0;
5805 } else {
5806 outw( info->xmit_buf[info->xmit_tail++],info->io_base + CCAR );
5807 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5808 info->xmit_cnt--;
5809 }
5810 info->icount.tx++;
5811 }
5812 }
5813
5814 } /* end of usc_load_txfifo() */
5815
5816 /* usc_reset()
5817 *
5818 * Reset the adapter to a known state and prepare it for further use.
5819 *
5820 * Arguments: info pointer to device instance data
5821 * Return Value: None
5822 */
5823 static void usc_reset( struct mgsl_struct *info )
5824 {
5825 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5826 int i;
5827 u32 readval;
5828
5829 /* Set BIT30 of Misc Control Register */
5830 /* (Local Control Register 0x50) to force reset of USC. */
5831
5832 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5833 u32 *LCR0BRDR = (u32 *)(info->lcr_base + 0x28);
5834
5835 info->misc_ctrl_value |= BIT30;
5836 *MiscCtrl = info->misc_ctrl_value;
5837
5838 /*
5839 * Force at least 170ns delay before clearing
5840 * reset bit. Each read from LCR takes at least
5841 * 30ns so 10 times for 300ns to be safe.
5842 */
5843 for(i=0;i<10;i++)
5844 readval = *MiscCtrl;
5845
5846 info->misc_ctrl_value &= ~BIT30;
5847 *MiscCtrl = info->misc_ctrl_value;
5848
5849 *LCR0BRDR = BUS_DESCRIPTOR(
5850 1, // Write Strobe Hold (0-3)
5851 2, // Write Strobe Delay (0-3)
5852 2, // Read Strobe Delay (0-3)
5853 0, // NWDD (Write data-data) (0-3)
5854 4, // NWAD (Write Addr-data) (0-31)
5855 0, // NXDA (Read/Write Data-Addr) (0-3)
5856 0, // NRDD (Read Data-Data) (0-3)
5857 5 // NRAD (Read Addr-Data) (0-31)
5858 );
5859 } else {
5860 /* do HW reset */
5861 outb( 0,info->io_base + 8 );
5862 }
5863
5864 info->mbre_bit = 0;
5865 info->loopback_bits = 0;
5866 info->usc_idle_mode = 0;
5867
5868 /*
5869 * Program the Bus Configuration Register (BCR)
5870 *
5871 * <15> 0 Don't use separate address
5872 * <14..6> 0 reserved
5873 * <5..4> 00 IAckmode = Default, don't care
5874 * <3> 1 Bus Request Totem Pole output
5875 * <2> 1 Use 16 Bit data bus
5876 * <1> 0 IRQ Totem Pole output
5877 * <0> 0 Don't Shift Right Addr
5878 *
5879 * 0000 0000 0000 1100 = 0x000c
5880 *
5881 * By writing to io_base + SDPIN the Wait/Ack pin is
5882 * programmed to work as a Wait pin.
5883 */
5884
5885 outw( 0x000c,info->io_base + SDPIN );
5886
5887
5888 outw( 0,info->io_base );
5889 outw( 0,info->io_base + CCAR );
5890
5891 /* select little endian byte ordering */
5892 usc_RTCmd( info, RTCmd_SelectLittleEndian );
5893
5894
5895 /* Port Control Register (PCR)
5896 *
5897 * <15..14> 11 Port 7 is Output (~DMAEN, Bit 14 : 0 = Enabled)
5898 * <13..12> 11 Port 6 is Output (~INTEN, Bit 12 : 0 = Enabled)
5899 * <11..10> 00 Port 5 is Input (No Connect, Don't Care)
5900 * <9..8> 00 Port 4 is Input (No Connect, Don't Care)
5901 * <7..6> 11 Port 3 is Output (~RTS, Bit 6 : 0 = Enabled )
5902 * <5..4> 11 Port 2 is Output (~DTR, Bit 4 : 0 = Enabled )
5903 * <3..2> 01 Port 1 is Input (Dedicated RxC)
5904 * <1..0> 01 Port 0 is Input (Dedicated TxC)
5905 *
5906 * 1111 0000 1111 0101 = 0xf0f5
5907 */
5908
5909 usc_OutReg( info, PCR, 0xf0f5 );
5910
5911
5912 /*
5913 * Input/Output Control Register
5914 *
5915 * <15..14> 00 CTS is active low input
5916 * <13..12> 00 DCD is active low input
5917 * <11..10> 00 TxREQ pin is input (DSR)
5918 * <9..8> 00 RxREQ pin is input (RI)
5919 * <7..6> 00 TxD is output (Transmit Data)
5920 * <5..3> 000 TxC Pin in Input (14.7456MHz Clock)
5921 * <2..0> 100 RxC is Output (drive with BRG0)
5922 *
5923 * 0000 0000 0000 0100 = 0x0004
5924 */
5925
5926 usc_OutReg( info, IOCR, 0x0004 );
5927
5928 } /* end of usc_reset() */
5929
5930 /* usc_set_async_mode()
5931 *
5932 * Program adapter for asynchronous communications.
5933 *
5934 * Arguments: info pointer to device instance data
5935 * Return Value: None
5936 */
5937 static void usc_set_async_mode( struct mgsl_struct *info )
5938 {
5939 u16 RegValue;
5940
5941 /* disable interrupts while programming USC */
5942 usc_DisableMasterIrqBit( info );
5943
5944 outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */
5945 usc_DmaCmd( info, DmaCmd_ResetAllChannels ); /* disable both DMA channels */
5946
5947 usc_loopback_frame( info );
5948
5949 /* Channel mode Register (CMR)
5950 *
5951 * <15..14> 00 Tx Sub modes, 00 = 1 Stop Bit
5952 * <13..12> 00 00 = 16X Clock
5953 * <11..8> 0000 Transmitter mode = Asynchronous
5954 * <7..6> 00 reserved?
5955 * <5..4> 00 Rx Sub modes, 00 = 16X Clock
5956 * <3..0> 0000 Receiver mode = Asynchronous
5957 *
5958 * 0000 0000 0000 0000 = 0x0
5959 */
5960
5961 RegValue = 0;
5962 if ( info->params.stop_bits != 1 )
5963 RegValue |= BIT14;
5964 usc_OutReg( info, CMR, RegValue );
5965
5966
5967 /* Receiver mode Register (RMR)
5968 *
5969 * <15..13> 000 encoding = None
5970 * <12..08> 00000 reserved (Sync Only)
5971 * <7..6> 00 Even parity
5972 * <5> 0 parity disabled
5973 * <4..2> 000 Receive Char Length = 8 bits
5974 * <1..0> 00 Disable Receiver
5975 *
5976 * 0000 0000 0000 0000 = 0x0
5977 */
5978
5979 RegValue = 0;
5980
5981 if ( info->params.data_bits != 8 )
5982 RegValue |= BIT4+BIT3+BIT2;
5983
5984 if ( info->params.parity != ASYNC_PARITY_NONE ) {
5985 RegValue |= BIT5;
5986 if ( info->params.parity != ASYNC_PARITY_ODD )
5987 RegValue |= BIT6;
5988 }
5989
5990 usc_OutReg( info, RMR, RegValue );
5991
5992
5993 /* Set IRQ trigger level */
5994
5995 usc_RCmd( info, RCmd_SelectRicrIntLevel );
5996
5997
5998 /* Receive Interrupt Control Register (RICR)
5999 *
6000 * <15..8> ? RxFIFO IRQ Request Level
6001 *
6002 * Note: For async mode the receive FIFO level must be set
6003 * to 0 to avoid the situation where the FIFO contains fewer bytes
6004 * than the trigger level and no more data is expected.
6005 *
6006 * <7> 0 Exited Hunt IA (Interrupt Arm)
6007 * <6> 0 Idle Received IA
6008 * <5> 0 Break/Abort IA
6009 * <4> 0 Rx Bound IA
6010 * <3> 0 Queued status reflects oldest byte in FIFO
6011 * <2> 0 Abort/PE IA
6012 * <1> 0 Rx Overrun IA
6013 * <0> 0 Select TC0 value for readback
6014 *
6015 * 0000 0000 0100 0000 = 0x0000 + (FIFOLEVEL in MSB)
6016 */
6017
6018 usc_OutReg( info, RICR, 0x0000 );
6019
6020 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
6021 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
6022
6023
6024 /* Transmit mode Register (TMR)
6025 *
6026 * <15..13> 000 encoding = None
6027 * <12..08> 00000 reserved (Sync Only)
6028 * <7..6> 00 Transmit parity Even
6029 * <5> 0 Transmit parity Disabled
6030 * <4..2> 000 Tx Char Length = 8 bits
6031 * <1..0> 00 Disable Transmitter
6032 *
6033 * 0000 0000 0000 0000 = 0x0
6034 */
6035
6036 RegValue = 0;
6037
6038 if ( info->params.data_bits != 8 )
6039 RegValue |= BIT4+BIT3+BIT2;
6040
6041 if ( info->params.parity != ASYNC_PARITY_NONE ) {
6042 RegValue |= BIT5;
6043 if ( info->params.parity != ASYNC_PARITY_ODD )
6044 RegValue |= BIT6;
6045 }
6046
6047 usc_OutReg( info, TMR, RegValue );
6048
6049 usc_set_txidle( info );
6050
6051
6052 /* Set IRQ trigger level */
6053
6054 usc_TCmd( info, TCmd_SelectTicrIntLevel );
6055
6056
6057 /* Transmit Interrupt Control Register (TICR)
6058 *
6059 * <15..8> ? Transmit FIFO IRQ Level
6060 * <7> 0 Present IA (Interrupt Arm)
6061 * <6> 1 Idle Sent IA
6062 * <5> 0 Abort Sent IA
6063 * <4> 0 EOF/EOM Sent IA
6064 * <3> 0 CRC Sent IA
6065 * <2> 0 1 = Wait for SW Trigger to Start Frame
6066 * <1> 0 Tx Underrun IA
6067 * <0> 0 TC0 constant on read back
6068 *
6069 * 0000 0000 0100 0000 = 0x0040
6070 */
6071
6072 usc_OutReg( info, TICR, 0x1f40 );
6073
6074 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
6075 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
6076
6077 usc_enable_async_clock( info, info->params.data_rate );
6078
6079
6080 /* Channel Control/status Register (CCSR)
6081 *
6082 * <15> X RCC FIFO Overflow status (RO)
6083 * <14> X RCC FIFO Not Empty status (RO)
6084 * <13> 0 1 = Clear RCC FIFO (WO)
6085 * <12> X DPLL in Sync status (RO)
6086 * <11> X DPLL 2 Missed Clocks status (RO)
6087 * <10> X DPLL 1 Missed Clock status (RO)
6088 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
6089 * <7> X SDLC Loop On status (RO)
6090 * <6> X SDLC Loop Send status (RO)
6091 * <5> 1 Bypass counters for TxClk and RxClk (RW)
6092 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
6093 * <1..0> 00 reserved
6094 *
6095 * 0000 0000 0010 0000 = 0x0020
6096 */
6097
6098 usc_OutReg( info, CCSR, 0x0020 );
6099
6100 usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA +
6101 RECEIVE_DATA + RECEIVE_STATUS );
6102
6103 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA +
6104 RECEIVE_DATA + RECEIVE_STATUS );
6105
6106 usc_EnableMasterIrqBit( info );
6107
6108 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
6109 /* Enable INTEN (Port 6, Bit12) */
6110 /* This connects the IRQ request signal to the ISA bus */
6111 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
6112 }
6113
6114 if (info->params.loopback) {
6115 info->loopback_bits = 0x300;
6116 outw(0x0300, info->io_base + CCAR);
6117 }
6118
6119 } /* end of usc_set_async_mode() */
6120
6121 /* usc_loopback_frame()
6122 *
6123 * Loop back a small (2 byte) dummy SDLC frame.
6124 * Interrupts and DMA are NOT used. The purpose of this is to
6125 * clear any 'stale' status info left over from running in async mode.
6126 *
6127 * The 16C32 shows the strange behaviour of marking the 1st
6128 * received SDLC frame with a CRC error even when there is no
6129 * CRC error. To get around this a small dummy from of 2 bytes
6130 * is looped back when switching from async to sync mode.
6131 *
6132 * Arguments: info pointer to device instance data
6133 * Return Value: None
6134 */
6135 static void usc_loopback_frame( struct mgsl_struct *info )
6136 {
6137 int i;
6138 unsigned long oldmode = info->params.mode;
6139
6140 info->params.mode = MGSL_MODE_HDLC;
6141
6142 usc_DisableMasterIrqBit( info );
6143
6144 usc_set_sdlc_mode( info );
6145 usc_enable_loopback( info, 1 );
6146
6147 /* Write 16-bit Time Constant for BRG0 */
6148 usc_OutReg( info, TC0R, 0 );
6149
6150 /* Channel Control Register (CCR)
6151 *
6152 * <15..14> 00 Don't use 32-bit Tx Control Blocks (TCBs)
6153 * <13> 0 Trigger Tx on SW Command Disabled
6154 * <12> 0 Flag Preamble Disabled
6155 * <11..10> 00 Preamble Length = 8-Bits
6156 * <9..8> 01 Preamble Pattern = flags
6157 * <7..6> 10 Don't use 32-bit Rx status Blocks (RSBs)
6158 * <5> 0 Trigger Rx on SW Command Disabled
6159 * <4..0> 0 reserved
6160 *
6161 * 0000 0001 0000 0000 = 0x0100
6162 */
6163
6164 usc_OutReg( info, CCR, 0x0100 );
6165
6166 /* SETUP RECEIVER */
6167 usc_RTCmd( info, RTCmd_PurgeRxFifo );
6168 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
6169
6170 /* SETUP TRANSMITTER */
6171 /* Program the Transmit Character Length Register (TCLR) */
6172 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
6173 usc_OutReg( info, TCLR, 2 );
6174 usc_RTCmd( info, RTCmd_PurgeTxFifo );
6175
6176 /* unlatch Tx status bits, and start transmit channel. */
6177 usc_UnlatchTxstatusBits(info,TXSTATUS_ALL);
6178 outw(0,info->io_base + DATAREG);
6179
6180 /* ENABLE TRANSMITTER */
6181 usc_TCmd( info, TCmd_SendFrame );
6182 usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
6183
6184 /* WAIT FOR RECEIVE COMPLETE */
6185 for (i=0 ; i<1000 ; i++)
6186 if (usc_InReg( info, RCSR ) & (BIT8 + BIT4 + BIT3 + BIT1))
6187 break;
6188
6189 /* clear Internal Data loopback mode */
6190 usc_enable_loopback(info, 0);
6191
6192 usc_EnableMasterIrqBit(info);
6193
6194 info->params.mode = oldmode;
6195
6196 } /* end of usc_loopback_frame() */
6197
6198 /* usc_set_sync_mode() Programs the USC for SDLC communications.
6199 *
6200 * Arguments: info pointer to adapter info structure
6201 * Return Value: None
6202 */
6203 static void usc_set_sync_mode( struct mgsl_struct *info )
6204 {
6205 usc_loopback_frame( info );
6206 usc_set_sdlc_mode( info );
6207
6208 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
6209 /* Enable INTEN (Port 6, Bit12) */
6210 /* This connects the IRQ request signal to the ISA bus */
6211 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
6212 }
6213
6214 usc_enable_aux_clock(info, info->params.clock_speed);
6215
6216 if (info->params.loopback)
6217 usc_enable_loopback(info,1);
6218
6219 } /* end of mgsl_set_sync_mode() */
6220
6221 /* usc_set_txidle() Set the HDLC idle mode for the transmitter.
6222 *
6223 * Arguments: info pointer to device instance data
6224 * Return Value: None
6225 */
6226 static void usc_set_txidle( struct mgsl_struct *info )
6227 {
6228 u16 usc_idle_mode = IDLEMODE_FLAGS;
6229
6230 /* Map API idle mode to USC register bits */
6231
6232 switch( info->idle_mode ){
6233 case HDLC_TXIDLE_FLAGS: usc_idle_mode = IDLEMODE_FLAGS; break;
6234 case HDLC_TXIDLE_ALT_ZEROS_ONES: usc_idle_mode = IDLEMODE_ALT_ONE_ZERO; break;
6235 case HDLC_TXIDLE_ZEROS: usc_idle_mode = IDLEMODE_ZERO; break;
6236 case HDLC_TXIDLE_ONES: usc_idle_mode = IDLEMODE_ONE; break;
6237 case HDLC_TXIDLE_ALT_MARK_SPACE: usc_idle_mode = IDLEMODE_ALT_MARK_SPACE; break;
6238 case HDLC_TXIDLE_SPACE: usc_idle_mode = IDLEMODE_SPACE; break;
6239 case HDLC_TXIDLE_MARK: usc_idle_mode = IDLEMODE_MARK; break;
6240 }
6241
6242 info->usc_idle_mode = usc_idle_mode;
6243 //usc_OutReg(info, TCSR, usc_idle_mode);
6244 info->tcsr_value &= ~IDLEMODE_MASK; /* clear idle mode bits */
6245 info->tcsr_value += usc_idle_mode;
6246 usc_OutReg(info, TCSR, info->tcsr_value);
6247
6248 /*
6249 * if SyncLink WAN adapter is running in external sync mode, the
6250 * transmitter has been set to Monosync in order to try to mimic
6251 * a true raw outbound bit stream. Monosync still sends an open/close
6252 * sync char at the start/end of a frame. Try to match those sync
6253 * patterns to the idle mode set here
6254 */
6255 if ( info->params.mode == MGSL_MODE_RAW ) {
6256 unsigned char syncpat = 0;
6257 switch( info->idle_mode ) {
6258 case HDLC_TXIDLE_FLAGS:
6259 syncpat = 0x7e;
6260 break;
6261 case HDLC_TXIDLE_ALT_ZEROS_ONES:
6262 syncpat = 0x55;
6263 break;
6264 case HDLC_TXIDLE_ZEROS:
6265 case HDLC_TXIDLE_SPACE:
6266 syncpat = 0x00;
6267 break;
6268 case HDLC_TXIDLE_ONES:
6269 case HDLC_TXIDLE_MARK:
6270 syncpat = 0xff;
6271 break;
6272 case HDLC_TXIDLE_ALT_MARK_SPACE:
6273 syncpat = 0xaa;
6274 break;
6275 }
6276
6277 usc_SetTransmitSyncChars(info,syncpat,syncpat);
6278 }
6279
6280 } /* end of usc_set_txidle() */
6281
6282 /* usc_get_serial_signals()
6283 *
6284 * Query the adapter for the state of the V24 status (input) signals.
6285 *
6286 * Arguments: info pointer to device instance data
6287 * Return Value: None
6288 */
6289 static void usc_get_serial_signals( struct mgsl_struct *info )
6290 {
6291 u16 status;
6292
6293 /* clear all serial signals except DTR and RTS */
6294 info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
6295
6296 /* Read the Misc Interrupt status Register (MISR) to get */
6297 /* the V24 status signals. */
6298
6299 status = usc_InReg( info, MISR );
6300
6301 /* set serial signal bits to reflect MISR */
6302
6303 if ( status & MISCSTATUS_CTS )
6304 info->serial_signals |= SerialSignal_CTS;
6305
6306 if ( status & MISCSTATUS_DCD )
6307 info->serial_signals |= SerialSignal_DCD;
6308
6309 if ( status & MISCSTATUS_RI )
6310 info->serial_signals |= SerialSignal_RI;
6311
6312 if ( status & MISCSTATUS_DSR )
6313 info->serial_signals |= SerialSignal_DSR;
6314
6315 } /* end of usc_get_serial_signals() */
6316
6317 /* usc_set_serial_signals()
6318 *
6319 * Set the state of DTR and RTS based on contents of
6320 * serial_signals member of device extension.
6321 *
6322 * Arguments: info pointer to device instance data
6323 * Return Value: None
6324 */
6325 static void usc_set_serial_signals( struct mgsl_struct *info )
6326 {
6327 u16 Control;
6328 unsigned char V24Out = info->serial_signals;
6329
6330 /* get the current value of the Port Control Register (PCR) */
6331
6332 Control = usc_InReg( info, PCR );
6333
6334 if ( V24Out & SerialSignal_RTS )
6335 Control &= ~(BIT6);
6336 else
6337 Control |= BIT6;
6338
6339 if ( V24Out & SerialSignal_DTR )
6340 Control &= ~(BIT4);
6341 else
6342 Control |= BIT4;
6343
6344 usc_OutReg( info, PCR, Control );
6345
6346 } /* end of usc_set_serial_signals() */
6347
6348 /* usc_enable_async_clock()
6349 *
6350 * Enable the async clock at the specified frequency.
6351 *
6352 * Arguments: info pointer to device instance data
6353 * data_rate data rate of clock in bps
6354 * 0 disables the AUX clock.
6355 * Return Value: None
6356 */
6357 static void usc_enable_async_clock( struct mgsl_struct *info, u32 data_rate )
6358 {
6359 if ( data_rate ) {
6360 /*
6361 * Clock mode Control Register (CMCR)
6362 *
6363 * <15..14> 00 counter 1 Disabled
6364 * <13..12> 00 counter 0 Disabled
6365 * <11..10> 11 BRG1 Input is TxC Pin
6366 * <9..8> 11 BRG0 Input is TxC Pin
6367 * <7..6> 01 DPLL Input is BRG1 Output
6368 * <5..3> 100 TxCLK comes from BRG0
6369 * <2..0> 100 RxCLK comes from BRG0
6370 *
6371 * 0000 1111 0110 0100 = 0x0f64
6372 */
6373
6374 usc_OutReg( info, CMCR, 0x0f64 );
6375
6376
6377 /*
6378 * Write 16-bit Time Constant for BRG0
6379 * Time Constant = (ClkSpeed / data_rate) - 1
6380 * ClkSpeed = 921600 (ISA), 691200 (PCI)
6381 */
6382
6383 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
6384 usc_OutReg( info, TC0R, (u16)((691200/data_rate) - 1) );
6385 else
6386 usc_OutReg( info, TC0R, (u16)((921600/data_rate) - 1) );
6387
6388
6389 /*
6390 * Hardware Configuration Register (HCR)
6391 * Clear Bit 1, BRG0 mode = Continuous
6392 * Set Bit 0 to enable BRG0.
6393 */
6394
6395 usc_OutReg( info, HCR,
6396 (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
6397
6398
6399 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
6400
6401 usc_OutReg( info, IOCR,
6402 (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
6403 } else {
6404 /* data rate == 0 so turn off BRG0 */
6405 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
6406 }
6407
6408 } /* end of usc_enable_async_clock() */
6409
6410 /*
6411 * Buffer Structures:
6412 *
6413 * Normal memory access uses virtual addresses that can make discontiguous
6414 * physical memory pages appear to be contiguous in the virtual address
6415 * space (the processors memory mapping handles the conversions).
6416 *
6417 * DMA transfers require physically contiguous memory. This is because
6418 * the DMA system controller and DMA bus masters deal with memory using
6419 * only physical addresses.
6420 *
6421 * This causes a problem under Windows NT when large DMA buffers are
6422 * needed. Fragmentation of the nonpaged pool prevents allocations of
6423 * physically contiguous buffers larger than the PAGE_SIZE.
6424 *
6425 * However the 16C32 supports Bus Master Scatter/Gather DMA which
6426 * allows DMA transfers to physically discontiguous buffers. Information
6427 * about each data transfer buffer is contained in a memory structure
6428 * called a 'buffer entry'. A list of buffer entries is maintained
6429 * to track and control the use of the data transfer buffers.
6430 *
6431 * To support this strategy we will allocate sufficient PAGE_SIZE
6432 * contiguous memory buffers to allow for the total required buffer
6433 * space.
6434 *
6435 * The 16C32 accesses the list of buffer entries using Bus Master
6436 * DMA. Control information is read from the buffer entries by the
6437 * 16C32 to control data transfers. status information is written to
6438 * the buffer entries by the 16C32 to indicate the status of completed
6439 * transfers.
6440 *
6441 * The CPU writes control information to the buffer entries to control
6442 * the 16C32 and reads status information from the buffer entries to
6443 * determine information about received and transmitted frames.
6444 *
6445 * Because the CPU and 16C32 (adapter) both need simultaneous access
6446 * to the buffer entries, the buffer entry memory is allocated with
6447 * HalAllocateCommonBuffer(). This restricts the size of the buffer
6448 * entry list to PAGE_SIZE.
6449 *
6450 * The actual data buffers on the other hand will only be accessed
6451 * by the CPU or the adapter but not by both simultaneously. This allows
6452 * Scatter/Gather packet based DMA procedures for using physically
6453 * discontiguous pages.
6454 */
6455
6456 /*
6457 * mgsl_reset_tx_dma_buffers()
6458 *
6459 * Set the count for all transmit buffers to 0 to indicate the
6460 * buffer is available for use and set the current buffer to the
6461 * first buffer. This effectively makes all buffers free and
6462 * discards any data in buffers.
6463 *
6464 * Arguments: info pointer to device instance data
6465 * Return Value: None
6466 */
6467 static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info )
6468 {
6469 unsigned int i;
6470
6471 for ( i = 0; i < info->tx_buffer_count; i++ ) {
6472 *((unsigned long *)&(info->tx_buffer_list[i].count)) = 0;
6473 }
6474
6475 info->current_tx_buffer = 0;
6476 info->start_tx_dma_buffer = 0;
6477 info->tx_dma_buffers_used = 0;
6478
6479 info->get_tx_holding_index = 0;
6480 info->put_tx_holding_index = 0;
6481 info->tx_holding_count = 0;
6482
6483 } /* end of mgsl_reset_tx_dma_buffers() */
6484
6485 /*
6486 * num_free_tx_dma_buffers()
6487 *
6488 * returns the number of free tx dma buffers available
6489 *
6490 * Arguments: info pointer to device instance data
6491 * Return Value: number of free tx dma buffers
6492 */
6493 static int num_free_tx_dma_buffers(struct mgsl_struct *info)
6494 {
6495 return info->tx_buffer_count - info->tx_dma_buffers_used;
6496 }
6497
6498 /*
6499 * mgsl_reset_rx_dma_buffers()
6500 *
6501 * Set the count for all receive buffers to DMABUFFERSIZE
6502 * and set the current buffer to the first buffer. This effectively
6503 * makes all buffers free and discards any data in buffers.
6504 *
6505 * Arguments: info pointer to device instance data
6506 * Return Value: None
6507 */
6508 static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info )
6509 {
6510 unsigned int i;
6511
6512 for ( i = 0; i < info->rx_buffer_count; i++ ) {
6513 *((unsigned long *)&(info->rx_buffer_list[i].count)) = DMABUFFERSIZE;
6514 // info->rx_buffer_list[i].count = DMABUFFERSIZE;
6515 // info->rx_buffer_list[i].status = 0;
6516 }
6517
6518 info->current_rx_buffer = 0;
6519
6520 } /* end of mgsl_reset_rx_dma_buffers() */
6521
6522 /*
6523 * mgsl_free_rx_frame_buffers()
6524 *
6525 * Free the receive buffers used by a received SDLC
6526 * frame such that the buffers can be reused.
6527 *
6528 * Arguments:
6529 *
6530 * info pointer to device instance data
6531 * StartIndex index of 1st receive buffer of frame
6532 * EndIndex index of last receive buffer of frame
6533 *
6534 * Return Value: None
6535 */
6536 static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex )
6537 {
6538 int Done = 0;
6539 DMABUFFERENTRY *pBufEntry;
6540 unsigned int Index;
6541
6542 /* Starting with 1st buffer entry of the frame clear the status */
6543 /* field and set the count field to DMA Buffer Size. */
6544
6545 Index = StartIndex;
6546
6547 while( !Done ) {
6548 pBufEntry = &(info->rx_buffer_list[Index]);
6549
6550 if ( Index == EndIndex ) {
6551 /* This is the last buffer of the frame! */
6552 Done = 1;
6553 }
6554
6555 /* reset current buffer for reuse */
6556 // pBufEntry->status = 0;
6557 // pBufEntry->count = DMABUFFERSIZE;
6558 *((unsigned long *)&(pBufEntry->count)) = DMABUFFERSIZE;
6559
6560 /* advance to next buffer entry in linked list */
6561 Index++;
6562 if ( Index == info->rx_buffer_count )
6563 Index = 0;
6564 }
6565
6566 /* set current buffer to next buffer after last buffer of frame */
6567 info->current_rx_buffer = Index;
6568
6569 } /* end of free_rx_frame_buffers() */
6570
6571 /* mgsl_get_rx_frame()
6572 *
6573 * This function attempts to return a received SDLC frame from the
6574 * receive DMA buffers. Only frames received without errors are returned.
6575 *
6576 * Arguments: info pointer to device extension
6577 * Return Value: 1 if frame returned, otherwise 0
6578 */
6579 static int mgsl_get_rx_frame(struct mgsl_struct *info)
6580 {
6581 unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */
6582 unsigned short status;
6583 DMABUFFERENTRY *pBufEntry;
6584 unsigned int framesize = 0;
6585 int ReturnCode = 0;
6586 unsigned long flags;
6587 struct tty_struct *tty = info->tty;
6588 int return_frame = 0;
6589
6590 /*
6591 * current_rx_buffer points to the 1st buffer of the next available
6592 * receive frame. To find the last buffer of the frame look for
6593 * a non-zero status field in the buffer entries. (The status
6594 * field is set by the 16C32 after completing a receive frame.
6595 */
6596
6597 StartIndex = EndIndex = info->current_rx_buffer;
6598
6599 while( !info->rx_buffer_list[EndIndex].status ) {
6600 /*
6601 * If the count field of the buffer entry is non-zero then
6602 * this buffer has not been used. (The 16C32 clears the count
6603 * field when it starts using the buffer.) If an unused buffer
6604 * is encountered then there are no frames available.
6605 */
6606
6607 if ( info->rx_buffer_list[EndIndex].count )
6608 goto Cleanup;
6609
6610 /* advance to next buffer entry in linked list */
6611 EndIndex++;
6612 if ( EndIndex == info->rx_buffer_count )
6613 EndIndex = 0;
6614
6615 /* if entire list searched then no frame available */
6616 if ( EndIndex == StartIndex ) {
6617 /* If this occurs then something bad happened,
6618 * all buffers have been 'used' but none mark
6619 * the end of a frame. Reset buffers and receiver.
6620 */
6621
6622 if ( info->rx_enabled ){
6623 spin_lock_irqsave(&info->irq_spinlock,flags);
6624 usc_start_receiver(info);
6625 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6626 }
6627 goto Cleanup;
6628 }
6629 }
6630
6631
6632 /* check status of receive frame */
6633
6634 status = info->rx_buffer_list[EndIndex].status;
6635
6636 if ( status & (RXSTATUS_SHORT_FRAME + RXSTATUS_OVERRUN +
6637 RXSTATUS_CRC_ERROR + RXSTATUS_ABORT) ) {
6638 if ( status & RXSTATUS_SHORT_FRAME )
6639 info->icount.rxshort++;
6640 else if ( status & RXSTATUS_ABORT )
6641 info->icount.rxabort++;
6642 else if ( status & RXSTATUS_OVERRUN )
6643 info->icount.rxover++;
6644 else {
6645 info->icount.rxcrc++;
6646 if ( info->params.crc_type & HDLC_CRC_RETURN_EX )
6647 return_frame = 1;
6648 }
6649 framesize = 0;
6650 #ifdef CONFIG_HDLC
6651 {
6652 struct net_device_stats *stats = hdlc_stats(info->netdev);
6653 stats->rx_errors++;
6654 stats->rx_frame_errors++;
6655 }
6656 #endif
6657 } else
6658 return_frame = 1;
6659
6660 if ( return_frame ) {
6661 /* receive frame has no errors, get frame size.
6662 * The frame size is the starting value of the RCC (which was
6663 * set to 0xffff) minus the ending value of the RCC (decremented
6664 * once for each receive character) minus 2 for the 16-bit CRC.
6665 */
6666
6667 framesize = RCLRVALUE - info->rx_buffer_list[EndIndex].rcc;
6668
6669 /* adjust frame size for CRC if any */
6670 if ( info->params.crc_type == HDLC_CRC_16_CCITT )
6671 framesize -= 2;
6672 else if ( info->params.crc_type == HDLC_CRC_32_CCITT )
6673 framesize -= 4;
6674 }
6675
6676 if ( debug_level >= DEBUG_LEVEL_BH )
6677 printk("%s(%d):mgsl_get_rx_frame(%s) status=%04X size=%d\n",
6678 __FILE__,__LINE__,info->device_name,status,framesize);
6679
6680 if ( debug_level >= DEBUG_LEVEL_DATA )
6681 mgsl_trace_block(info,info->rx_buffer_list[StartIndex].virt_addr,
6682 min_t(int, framesize, DMABUFFERSIZE),0);
6683
6684 if (framesize) {
6685 if ( ( (info->params.crc_type & HDLC_CRC_RETURN_EX) &&
6686 ((framesize+1) > info->max_frame_size) ) ||
6687 (framesize > info->max_frame_size) )
6688 info->icount.rxlong++;
6689 else {
6690 /* copy dma buffer(s) to contiguous intermediate buffer */
6691 int copy_count = framesize;
6692 int index = StartIndex;
6693 unsigned char *ptmp = info->intermediate_rxbuffer;
6694
6695 if ( !(status & RXSTATUS_CRC_ERROR))
6696 info->icount.rxok++;
6697
6698 while(copy_count) {
6699 int partial_count;
6700 if ( copy_count > DMABUFFERSIZE )
6701 partial_count = DMABUFFERSIZE;
6702 else
6703 partial_count = copy_count;
6704
6705 pBufEntry = &(info->rx_buffer_list[index]);
6706 memcpy( ptmp, pBufEntry->virt_addr, partial_count );
6707 ptmp += partial_count;
6708 copy_count -= partial_count;
6709
6710 if ( ++index == info->rx_buffer_count )
6711 index = 0;
6712 }
6713
6714 if ( info->params.crc_type & HDLC_CRC_RETURN_EX ) {
6715 ++framesize;
6716 *ptmp = (status & RXSTATUS_CRC_ERROR ?
6717 RX_CRC_ERROR :
6718 RX_OK);
6719
6720 if ( debug_level >= DEBUG_LEVEL_DATA )
6721 printk("%s(%d):mgsl_get_rx_frame(%s) rx frame status=%d\n",
6722 __FILE__,__LINE__,info->device_name,
6723 *ptmp);
6724 }
6725
6726 #ifdef CONFIG_HDLC
6727 if (info->netcount)
6728 hdlcdev_rx(info,info->intermediate_rxbuffer,framesize);
6729 else
6730 #endif
6731 ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
6732 }
6733 }
6734 /* Free the buffers used by this frame. */
6735 mgsl_free_rx_frame_buffers( info, StartIndex, EndIndex );
6736
6737 ReturnCode = 1;
6738
6739 Cleanup:
6740
6741 if ( info->rx_enabled && info->rx_overflow ) {
6742 /* The receiver needs to restarted because of
6743 * a receive overflow (buffer or FIFO). If the
6744 * receive buffers are now empty, then restart receiver.
6745 */
6746
6747 if ( !info->rx_buffer_list[EndIndex].status &&
6748 info->rx_buffer_list[EndIndex].count ) {
6749 spin_lock_irqsave(&info->irq_spinlock,flags);
6750 usc_start_receiver(info);
6751 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6752 }
6753 }
6754
6755 return ReturnCode;
6756
6757 } /* end of mgsl_get_rx_frame() */
6758
6759 /* mgsl_get_raw_rx_frame()
6760 *
6761 * This function attempts to return a received frame from the
6762 * receive DMA buffers when running in external loop mode. In this mode,
6763 * we will return at most one DMABUFFERSIZE frame to the application.
6764 * The USC receiver is triggering off of DCD going active to start a new
6765 * frame, and DCD going inactive to terminate the frame (similar to
6766 * processing a closing flag character).
6767 *
6768 * In this routine, we will return DMABUFFERSIZE "chunks" at a time.
6769 * If DCD goes inactive, the last Rx DMA Buffer will have a non-zero
6770 * status field and the RCC field will indicate the length of the
6771 * entire received frame. We take this RCC field and get the modulus
6772 * of RCC and DMABUFFERSIZE to determine if number of bytes in the
6773 * last Rx DMA buffer and return that last portion of the frame.
6774 *
6775 * Arguments: info pointer to device extension
6776 * Return Value: 1 if frame returned, otherwise 0
6777 */
6778 static int mgsl_get_raw_rx_frame(struct mgsl_struct *info)
6779 {
6780 unsigned int CurrentIndex, NextIndex;
6781 unsigned short status;
6782 DMABUFFERENTRY *pBufEntry;
6783 unsigned int framesize = 0;
6784 int ReturnCode = 0;
6785 unsigned long flags;
6786 struct tty_struct *tty = info->tty;
6787
6788 /*
6789 * current_rx_buffer points to the 1st buffer of the next available
6790 * receive frame. The status field is set by the 16C32 after
6791 * completing a receive frame. If the status field of this buffer
6792 * is zero, either the USC is still filling this buffer or this
6793 * is one of a series of buffers making up a received frame.
6794 *
6795 * If the count field of this buffer is zero, the USC is either
6796 * using this buffer or has used this buffer. Look at the count
6797 * field of the next buffer. If that next buffer's count is
6798 * non-zero, the USC is still actively using the current buffer.
6799 * Otherwise, if the next buffer's count field is zero, the
6800 * current buffer is complete and the USC is using the next
6801 * buffer.
6802 */
6803 CurrentIndex = NextIndex = info->current_rx_buffer;
6804 ++NextIndex;
6805 if ( NextIndex == info->rx_buffer_count )
6806 NextIndex = 0;
6807
6808 if ( info->rx_buffer_list[CurrentIndex].status != 0 ||
6809 (info->rx_buffer_list[CurrentIndex].count == 0 &&
6810 info->rx_buffer_list[NextIndex].count == 0)) {
6811 /*
6812 * Either the status field of this dma buffer is non-zero
6813 * (indicating the last buffer of a receive frame) or the next
6814 * buffer is marked as in use -- implying this buffer is complete
6815 * and an intermediate buffer for this received frame.
6816 */
6817
6818 status = info->rx_buffer_list[CurrentIndex].status;
6819
6820 if ( status & (RXSTATUS_SHORT_FRAME + RXSTATUS_OVERRUN +
6821 RXSTATUS_CRC_ERROR + RXSTATUS_ABORT) ) {
6822 if ( status & RXSTATUS_SHORT_FRAME )
6823 info->icount.rxshort++;
6824 else if ( status & RXSTATUS_ABORT )
6825 info->icount.rxabort++;
6826 else if ( status & RXSTATUS_OVERRUN )
6827 info->icount.rxover++;
6828 else
6829 info->icount.rxcrc++;
6830 framesize = 0;
6831 } else {
6832 /*
6833 * A receive frame is available, get frame size and status.
6834 *
6835 * The frame size is the starting value of the RCC (which was
6836 * set to 0xffff) minus the ending value of the RCC (decremented
6837 * once for each receive character) minus 2 or 4 for the 16-bit
6838 * or 32-bit CRC.
6839 *
6840 * If the status field is zero, this is an intermediate buffer.
6841 * It's size is 4K.
6842 *
6843 * If the DMA Buffer Entry's Status field is non-zero, the
6844 * receive operation completed normally (ie: DCD dropped). The
6845 * RCC field is valid and holds the received frame size.
6846 * It is possible that the RCC field will be zero on a DMA buffer
6847 * entry with a non-zero status. This can occur if the total
6848 * frame size (number of bytes between the time DCD goes active
6849 * to the time DCD goes inactive) exceeds 65535 bytes. In this
6850 * case the 16C32 has underrun on the RCC count and appears to
6851 * stop updating this counter to let us know the actual received
6852 * frame size. If this happens (non-zero status and zero RCC),
6853 * simply return the entire RxDMA Buffer
6854 */
6855 if ( status ) {
6856 /*
6857 * In the event that the final RxDMA Buffer is
6858 * terminated with a non-zero status and the RCC
6859 * field is zero, we interpret this as the RCC
6860 * having underflowed (received frame > 65535 bytes).
6861 *
6862 * Signal the event to the user by passing back
6863 * a status of RxStatus_CrcError returning the full
6864 * buffer and let the app figure out what data is
6865 * actually valid
6866 */
6867 if ( info->rx_buffer_list[CurrentIndex].rcc )
6868 framesize = RCLRVALUE - info->rx_buffer_list[CurrentIndex].rcc;
6869 else
6870 framesize = DMABUFFERSIZE;
6871 }
6872 else
6873 framesize = DMABUFFERSIZE;
6874 }
6875
6876 if ( framesize > DMABUFFERSIZE ) {
6877 /*
6878 * if running in raw sync mode, ISR handler for
6879 * End Of Buffer events terminates all buffers at 4K.
6880 * If this frame size is said to be >4K, get the
6881 * actual number of bytes of the frame in this buffer.
6882 */
6883 framesize = framesize % DMABUFFERSIZE;
6884 }
6885
6886
6887 if ( debug_level >= DEBUG_LEVEL_BH )
6888 printk("%s(%d):mgsl_get_raw_rx_frame(%s) status=%04X size=%d\n",
6889 __FILE__,__LINE__,info->device_name,status,framesize);
6890
6891 if ( debug_level >= DEBUG_LEVEL_DATA )
6892 mgsl_trace_block(info,info->rx_buffer_list[CurrentIndex].virt_addr,
6893 min_t(int, framesize, DMABUFFERSIZE),0);
6894
6895 if (framesize) {
6896 /* copy dma buffer(s) to contiguous intermediate buffer */
6897 /* NOTE: we never copy more than DMABUFFERSIZE bytes */
6898
6899 pBufEntry = &(info->rx_buffer_list[CurrentIndex]);
6900 memcpy( info->intermediate_rxbuffer, pBufEntry->virt_addr, framesize);
6901 info->icount.rxok++;
6902
6903 ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
6904 }
6905
6906 /* Free the buffers used by this frame. */
6907 mgsl_free_rx_frame_buffers( info, CurrentIndex, CurrentIndex );
6908
6909 ReturnCode = 1;
6910 }
6911
6912
6913 if ( info->rx_enabled && info->rx_overflow ) {
6914 /* The receiver needs to restarted because of
6915 * a receive overflow (buffer or FIFO). If the
6916 * receive buffers are now empty, then restart receiver.
6917 */
6918
6919 if ( !info->rx_buffer_list[CurrentIndex].status &&
6920 info->rx_buffer_list[CurrentIndex].count ) {
6921 spin_lock_irqsave(&info->irq_spinlock,flags);
6922 usc_start_receiver(info);
6923 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6924 }
6925 }
6926
6927 return ReturnCode;
6928
6929 } /* end of mgsl_get_raw_rx_frame() */
6930
6931 /* mgsl_load_tx_dma_buffer()
6932 *
6933 * Load the transmit DMA buffer with the specified data.
6934 *
6935 * Arguments:
6936 *
6937 * info pointer to device extension
6938 * Buffer pointer to buffer containing frame to load
6939 * BufferSize size in bytes of frame in Buffer
6940 *
6941 * Return Value: None
6942 */
6943 static void mgsl_load_tx_dma_buffer(struct mgsl_struct *info,
6944 const char *Buffer, unsigned int BufferSize)
6945 {
6946 unsigned short Copycount;
6947 unsigned int i = 0;
6948 DMABUFFERENTRY *pBufEntry;
6949
6950 if ( debug_level >= DEBUG_LEVEL_DATA )
6951 mgsl_trace_block(info,Buffer, min_t(int, BufferSize, DMABUFFERSIZE), 1);
6952
6953 if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
6954 /* set CMR:13 to start transmit when
6955 * next GoAhead (abort) is received
6956 */
6957 info->cmr_value |= BIT13;
6958 }
6959
6960 /* begin loading the frame in the next available tx dma
6961 * buffer, remember it's starting location for setting
6962 * up tx dma operation
6963 */
6964 i = info->current_tx_buffer;
6965 info->start_tx_dma_buffer = i;
6966
6967 /* Setup the status and RCC (Frame Size) fields of the 1st */
6968 /* buffer entry in the transmit DMA buffer list. */
6969
6970 info->tx_buffer_list[i].status = info->cmr_value & 0xf000;
6971 info->tx_buffer_list[i].rcc = BufferSize;
6972 info->tx_buffer_list[i].count = BufferSize;
6973
6974 /* Copy frame data from 1st source buffer to the DMA buffers. */
6975 /* The frame data may span multiple DMA buffers. */
6976
6977 while( BufferSize ){
6978 /* Get a pointer to next DMA buffer entry. */
6979 pBufEntry = &info->tx_buffer_list[i++];
6980
6981 if ( i == info->tx_buffer_count )
6982 i=0;
6983
6984 /* Calculate the number of bytes that can be copied from */
6985 /* the source buffer to this DMA buffer. */
6986 if ( BufferSize > DMABUFFERSIZE )
6987 Copycount = DMABUFFERSIZE;
6988 else
6989 Copycount = BufferSize;
6990
6991 /* Actually copy data from source buffer to DMA buffer. */
6992 /* Also set the data count for this individual DMA buffer. */
6993 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
6994 mgsl_load_pci_memory(pBufEntry->virt_addr, Buffer,Copycount);
6995 else
6996 memcpy(pBufEntry->virt_addr, Buffer, Copycount);
6997
6998 pBufEntry->count = Copycount;
6999
7000 /* Advance source pointer and reduce remaining data count. */
7001 Buffer += Copycount;
7002 BufferSize -= Copycount;
7003
7004 ++info->tx_dma_buffers_used;
7005 }
7006
7007 /* remember next available tx dma buffer */
7008 info->current_tx_buffer = i;
7009
7010 } /* end of mgsl_load_tx_dma_buffer() */
7011
7012 /*
7013 * mgsl_register_test()
7014 *
7015 * Performs a register test of the 16C32.
7016 *
7017 * Arguments: info pointer to device instance data
7018 * Return Value: TRUE if test passed, otherwise FALSE
7019 */
7020 static BOOLEAN mgsl_register_test( struct mgsl_struct *info )
7021 {
7022 static unsigned short BitPatterns[] =
7023 { 0x0000, 0xffff, 0xaaaa, 0x5555, 0x1234, 0x6969, 0x9696, 0x0f0f };
7024 static unsigned int Patterncount = ARRAY_SIZE(BitPatterns);
7025 unsigned int i;
7026 BOOLEAN rc = TRUE;
7027 unsigned long flags;
7028
7029 spin_lock_irqsave(&info->irq_spinlock,flags);
7030 usc_reset(info);
7031
7032 /* Verify the reset state of some registers. */
7033
7034 if ( (usc_InReg( info, SICR ) != 0) ||
7035 (usc_InReg( info, IVR ) != 0) ||
7036 (usc_InDmaReg( info, DIVR ) != 0) ){
7037 rc = FALSE;
7038 }
7039
7040 if ( rc == TRUE ){
7041 /* Write bit patterns to various registers but do it out of */
7042 /* sync, then read back and verify values. */
7043
7044 for ( i = 0 ; i < Patterncount ; i++ ) {
7045 usc_OutReg( info, TC0R, BitPatterns[i] );
7046 usc_OutReg( info, TC1R, BitPatterns[(i+1)%Patterncount] );
7047 usc_OutReg( info, TCLR, BitPatterns[(i+2)%Patterncount] );
7048 usc_OutReg( info, RCLR, BitPatterns[(i+3)%Patterncount] );
7049 usc_OutReg( info, RSR, BitPatterns[(i+4)%Patterncount] );
7050 usc_OutDmaReg( info, TBCR, BitPatterns[(i+5)%Patterncount] );
7051
7052 if ( (usc_InReg( info, TC0R ) != BitPatterns[i]) ||
7053 (usc_InReg( info, TC1R ) != BitPatterns[(i+1)%Patterncount]) ||
7054 (usc_InReg( info, TCLR ) != BitPatterns[(i+2)%Patterncount]) ||
7055 (usc_InReg( info, RCLR ) != BitPatterns[(i+3)%Patterncount]) ||
7056 (usc_InReg( info, RSR ) != BitPatterns[(i+4)%Patterncount]) ||
7057 (usc_InDmaReg( info, TBCR ) != BitPatterns[(i+5)%Patterncount]) ){
7058 rc = FALSE;
7059 break;
7060 }
7061 }
7062 }
7063
7064 usc_reset(info);
7065 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7066
7067 return rc;
7068
7069 } /* end of mgsl_register_test() */
7070
7071 /* mgsl_irq_test() Perform interrupt test of the 16C32.
7072 *
7073 * Arguments: info pointer to device instance data
7074 * Return Value: TRUE if test passed, otherwise FALSE
7075 */
7076 static BOOLEAN mgsl_irq_test( struct mgsl_struct *info )
7077 {
7078 unsigned long EndTime;
7079 unsigned long flags;
7080
7081 spin_lock_irqsave(&info->irq_spinlock,flags);
7082 usc_reset(info);
7083
7084 /*
7085 * Setup 16C32 to interrupt on TxC pin (14MHz clock) transition.
7086 * The ISR sets irq_occurred to 1.
7087 */
7088
7089 info->irq_occurred = FALSE;
7090
7091 /* Enable INTEN gate for ISA adapter (Port 6, Bit12) */
7092 /* Enable INTEN (Port 6, Bit12) */
7093 /* This connects the IRQ request signal to the ISA bus */
7094 /* on the ISA adapter. This has no effect for the PCI adapter */
7095 usc_OutReg( info, PCR, (unsigned short)((usc_InReg(info, PCR) | BIT13) & ~BIT12) );
7096
7097 usc_EnableMasterIrqBit(info);
7098 usc_EnableInterrupts(info, IO_PIN);
7099 usc_ClearIrqPendingBits(info, IO_PIN);
7100
7101 usc_UnlatchIostatusBits(info, MISCSTATUS_TXC_LATCHED);
7102 usc_EnableStatusIrqs(info, SICR_TXC_ACTIVE + SICR_TXC_INACTIVE);
7103
7104 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7105
7106 EndTime=100;
7107 while( EndTime-- && !info->irq_occurred ) {
7108 msleep_interruptible(10);
7109 }
7110
7111 spin_lock_irqsave(&info->irq_spinlock,flags);
7112 usc_reset(info);
7113 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7114
7115 if ( !info->irq_occurred )
7116 return FALSE;
7117 else
7118 return TRUE;
7119
7120 } /* end of mgsl_irq_test() */
7121
7122 /* mgsl_dma_test()
7123 *
7124 * Perform a DMA test of the 16C32. A small frame is
7125 * transmitted via DMA from a transmit buffer to a receive buffer
7126 * using single buffer DMA mode.
7127 *
7128 * Arguments: info pointer to device instance data
7129 * Return Value: TRUE if test passed, otherwise FALSE
7130 */
7131 static BOOLEAN mgsl_dma_test( struct mgsl_struct *info )
7132 {
7133 unsigned short FifoLevel;
7134 unsigned long phys_addr;
7135 unsigned int FrameSize;
7136 unsigned int i;
7137 char *TmpPtr;
7138 BOOLEAN rc = TRUE;
7139 unsigned short status=0;
7140 unsigned long EndTime;
7141 unsigned long flags;
7142 MGSL_PARAMS tmp_params;
7143
7144 /* save current port options */
7145 memcpy(&tmp_params,&info->params,sizeof(MGSL_PARAMS));
7146 /* load default port options */
7147 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
7148
7149 #define TESTFRAMESIZE 40
7150
7151 spin_lock_irqsave(&info->irq_spinlock,flags);
7152
7153 /* setup 16C32 for SDLC DMA transfer mode */
7154
7155 usc_reset(info);
7156 usc_set_sdlc_mode(info);
7157 usc_enable_loopback(info,1);
7158
7159 /* Reprogram the RDMR so that the 16C32 does NOT clear the count
7160 * field of the buffer entry after fetching buffer address. This
7161 * way we can detect a DMA failure for a DMA read (which should be
7162 * non-destructive to system memory) before we try and write to
7163 * memory (where a failure could corrupt system memory).
7164 */
7165
7166 /* Receive DMA mode Register (RDMR)
7167 *
7168 * <15..14> 11 DMA mode = Linked List Buffer mode
7169 * <13> 1 RSBinA/L = store Rx status Block in List entry
7170 * <12> 0 1 = Clear count of List Entry after fetching
7171 * <11..10> 00 Address mode = Increment
7172 * <9> 1 Terminate Buffer on RxBound
7173 * <8> 0 Bus Width = 16bits
7174 * <7..0> ? status Bits (write as 0s)
7175 *
7176 * 1110 0010 0000 0000 = 0xe200
7177 */
7178
7179 usc_OutDmaReg( info, RDMR, 0xe200 );
7180
7181 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7182
7183
7184 /* SETUP TRANSMIT AND RECEIVE DMA BUFFERS */
7185
7186 FrameSize = TESTFRAMESIZE;
7187
7188 /* setup 1st transmit buffer entry: */
7189 /* with frame size and transmit control word */
7190
7191 info->tx_buffer_list[0].count = FrameSize;
7192 info->tx_buffer_list[0].rcc = FrameSize;
7193 info->tx_buffer_list[0].status = 0x4000;
7194
7195 /* build a transmit frame in 1st transmit DMA buffer */
7196
7197 TmpPtr = info->tx_buffer_list[0].virt_addr;
7198 for (i = 0; i < FrameSize; i++ )
7199 *TmpPtr++ = i;
7200
7201 /* setup 1st receive buffer entry: */
7202 /* clear status, set max receive buffer size */
7203
7204 info->rx_buffer_list[0].status = 0;
7205 info->rx_buffer_list[0].count = FrameSize + 4;
7206
7207 /* zero out the 1st receive buffer */
7208
7209 memset( info->rx_buffer_list[0].virt_addr, 0, FrameSize + 4 );
7210
7211 /* Set count field of next buffer entries to prevent */
7212 /* 16C32 from using buffers after the 1st one. */
7213
7214 info->tx_buffer_list[1].count = 0;
7215 info->rx_buffer_list[1].count = 0;
7216
7217
7218 /***************************/
7219 /* Program 16C32 receiver. */
7220 /***************************/
7221
7222 spin_lock_irqsave(&info->irq_spinlock,flags);
7223
7224 /* setup DMA transfers */
7225 usc_RTCmd( info, RTCmd_PurgeRxFifo );
7226
7227 /* program 16C32 receiver with physical address of 1st DMA buffer entry */
7228 phys_addr = info->rx_buffer_list[0].phys_entry;
7229 usc_OutDmaReg( info, NRARL, (unsigned short)phys_addr );
7230 usc_OutDmaReg( info, NRARU, (unsigned short)(phys_addr >> 16) );
7231
7232 /* Clear the Rx DMA status bits (read RDMR) and start channel */
7233 usc_InDmaReg( info, RDMR );
7234 usc_DmaCmd( info, DmaCmd_InitRxChannel );
7235
7236 /* Enable Receiver (RMR <1..0> = 10) */
7237 usc_OutReg( info, RMR, (unsigned short)((usc_InReg(info, RMR) & 0xfffc) | 0x0002) );
7238
7239 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7240
7241
7242 /*************************************************************/
7243 /* WAIT FOR RECEIVER TO DMA ALL PARAMETERS FROM BUFFER ENTRY */
7244 /*************************************************************/
7245
7246 /* Wait 100ms for interrupt. */
7247 EndTime = jiffies + msecs_to_jiffies(100);
7248
7249 for(;;) {
7250 if (time_after(jiffies, EndTime)) {
7251 rc = FALSE;
7252 break;
7253 }
7254
7255 spin_lock_irqsave(&info->irq_spinlock,flags);
7256 status = usc_InDmaReg( info, RDMR );
7257 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7258
7259 if ( !(status & BIT4) && (status & BIT5) ) {
7260 /* INITG (BIT 4) is inactive (no entry read in progress) AND */
7261 /* BUSY (BIT 5) is active (channel still active). */
7262 /* This means the buffer entry read has completed. */
7263 break;
7264 }
7265 }
7266
7267
7268 /******************************/
7269 /* Program 16C32 transmitter. */
7270 /******************************/
7271
7272 spin_lock_irqsave(&info->irq_spinlock,flags);
7273
7274 /* Program the Transmit Character Length Register (TCLR) */
7275 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
7276
7277 usc_OutReg( info, TCLR, (unsigned short)info->tx_buffer_list[0].count );
7278 usc_RTCmd( info, RTCmd_PurgeTxFifo );
7279
7280 /* Program the address of the 1st DMA Buffer Entry in linked list */
7281
7282 phys_addr = info->tx_buffer_list[0].phys_entry;
7283 usc_OutDmaReg( info, NTARL, (unsigned short)phys_addr );
7284 usc_OutDmaReg( info, NTARU, (unsigned short)(phys_addr >> 16) );
7285
7286 /* unlatch Tx status bits, and start transmit channel. */
7287
7288 usc_OutReg( info, TCSR, (unsigned short)(( usc_InReg(info, TCSR) & 0x0f00) | 0xfa) );
7289 usc_DmaCmd( info, DmaCmd_InitTxChannel );
7290
7291 /* wait for DMA controller to fill transmit FIFO */
7292
7293 usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
7294
7295 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7296
7297
7298 /**********************************/
7299 /* WAIT FOR TRANSMIT FIFO TO FILL */
7300 /**********************************/
7301
7302 /* Wait 100ms */
7303 EndTime = jiffies + msecs_to_jiffies(100);
7304
7305 for(;;) {
7306 if (time_after(jiffies, EndTime)) {
7307 rc = FALSE;
7308 break;
7309 }
7310
7311 spin_lock_irqsave(&info->irq_spinlock,flags);
7312 FifoLevel = usc_InReg(info, TICR) >> 8;
7313 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7314
7315 if ( FifoLevel < 16 )
7316 break;
7317 else
7318 if ( FrameSize < 32 ) {
7319 /* This frame is smaller than the entire transmit FIFO */
7320 /* so wait for the entire frame to be loaded. */
7321 if ( FifoLevel <= (32 - FrameSize) )
7322 break;
7323 }
7324 }
7325
7326
7327 if ( rc == TRUE )
7328 {
7329 /* Enable 16C32 transmitter. */
7330
7331 spin_lock_irqsave(&info->irq_spinlock,flags);
7332
7333 /* Transmit mode Register (TMR), <1..0> = 10, Enable Transmitter */
7334 usc_TCmd( info, TCmd_SendFrame );
7335 usc_OutReg( info, TMR, (unsigned short)((usc_InReg(info, TMR) & 0xfffc) | 0x0002) );
7336
7337 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7338
7339
7340 /******************************/
7341 /* WAIT FOR TRANSMIT COMPLETE */
7342 /******************************/
7343
7344 /* Wait 100ms */
7345 EndTime = jiffies + msecs_to_jiffies(100);
7346
7347 /* While timer not expired wait for transmit complete */
7348
7349 spin_lock_irqsave(&info->irq_spinlock,flags);
7350 status = usc_InReg( info, TCSR );
7351 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7352
7353 while ( !(status & (BIT6+BIT5+BIT4+BIT2+BIT1)) ) {
7354 if (time_after(jiffies, EndTime)) {
7355 rc = FALSE;
7356 break;
7357 }
7358
7359 spin_lock_irqsave(&info->irq_spinlock,flags);
7360 status = usc_InReg( info, TCSR );
7361 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7362 }
7363 }
7364
7365
7366 if ( rc == TRUE ){
7367 /* CHECK FOR TRANSMIT ERRORS */
7368 if ( status & (BIT5 + BIT1) )
7369 rc = FALSE;
7370 }
7371
7372 if ( rc == TRUE ) {
7373 /* WAIT FOR RECEIVE COMPLETE */
7374
7375 /* Wait 100ms */
7376 EndTime = jiffies + msecs_to_jiffies(100);
7377
7378 /* Wait for 16C32 to write receive status to buffer entry. */
7379 status=info->rx_buffer_list[0].status;
7380 while ( status == 0 ) {
7381 if (time_after(jiffies, EndTime)) {
7382 rc = FALSE;
7383 break;
7384 }
7385 status=info->rx_buffer_list[0].status;
7386 }
7387 }
7388
7389
7390 if ( rc == TRUE ) {
7391 /* CHECK FOR RECEIVE ERRORS */
7392 status = info->rx_buffer_list[0].status;
7393
7394 if ( status & (BIT8 + BIT3 + BIT1) ) {
7395 /* receive error has occurred */
7396 rc = FALSE;
7397 } else {
7398 if ( memcmp( info->tx_buffer_list[0].virt_addr ,
7399 info->rx_buffer_list[0].virt_addr, FrameSize ) ){
7400 rc = FALSE;
7401 }
7402 }
7403 }
7404
7405 spin_lock_irqsave(&info->irq_spinlock,flags);
7406 usc_reset( info );
7407 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7408
7409 /* restore current port options */
7410 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
7411
7412 return rc;
7413
7414 } /* end of mgsl_dma_test() */
7415
7416 /* mgsl_adapter_test()
7417 *
7418 * Perform the register, IRQ, and DMA tests for the 16C32.
7419 *
7420 * Arguments: info pointer to device instance data
7421 * Return Value: 0 if success, otherwise -ENODEV
7422 */
7423 static int mgsl_adapter_test( struct mgsl_struct *info )
7424 {
7425 if ( debug_level >= DEBUG_LEVEL_INFO )
7426 printk( "%s(%d):Testing device %s\n",
7427 __FILE__,__LINE__,info->device_name );
7428
7429 if ( !mgsl_register_test( info ) ) {
7430 info->init_error = DiagStatus_AddressFailure;
7431 printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
7432 __FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) );
7433 return -ENODEV;
7434 }
7435
7436 if ( !mgsl_irq_test( info ) ) {
7437 info->init_error = DiagStatus_IrqFailure;
7438 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
7439 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
7440 return -ENODEV;
7441 }
7442
7443 if ( !mgsl_dma_test( info ) ) {
7444 info->init_error = DiagStatus_DmaFailure;
7445 printk( "%s(%d):DMA test failure for device %s DMA=%d\n",
7446 __FILE__,__LINE__,info->device_name, (unsigned short)(info->dma_level) );
7447 return -ENODEV;
7448 }
7449
7450 if ( debug_level >= DEBUG_LEVEL_INFO )
7451 printk( "%s(%d):device %s passed diagnostics\n",
7452 __FILE__,__LINE__,info->device_name );
7453
7454 return 0;
7455
7456 } /* end of mgsl_adapter_test() */
7457
7458 /* mgsl_memory_test()
7459 *
7460 * Test the shared memory on a PCI adapter.
7461 *
7462 * Arguments: info pointer to device instance data
7463 * Return Value: TRUE if test passed, otherwise FALSE
7464 */
7465 static BOOLEAN mgsl_memory_test( struct mgsl_struct *info )
7466 {
7467 static unsigned long BitPatterns[] =
7468 { 0x0, 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
7469 unsigned long Patterncount = ARRAY_SIZE(BitPatterns);
7470 unsigned long i;
7471 unsigned long TestLimit = SHARED_MEM_ADDRESS_SIZE/sizeof(unsigned long);
7472 unsigned long * TestAddr;
7473
7474 if ( info->bus_type != MGSL_BUS_TYPE_PCI )
7475 return TRUE;
7476
7477 TestAddr = (unsigned long *)info->memory_base;
7478
7479 /* Test data lines with test pattern at one location. */
7480
7481 for ( i = 0 ; i < Patterncount ; i++ ) {
7482 *TestAddr = BitPatterns[i];
7483 if ( *TestAddr != BitPatterns[i] )
7484 return FALSE;
7485 }
7486
7487 /* Test address lines with incrementing pattern over */
7488 /* entire address range. */
7489
7490 for ( i = 0 ; i < TestLimit ; i++ ) {
7491 *TestAddr = i * 4;
7492 TestAddr++;
7493 }
7494
7495 TestAddr = (unsigned long *)info->memory_base;
7496
7497 for ( i = 0 ; i < TestLimit ; i++ ) {
7498 if ( *TestAddr != i * 4 )
7499 return FALSE;
7500 TestAddr++;
7501 }
7502
7503 memset( info->memory_base, 0, SHARED_MEM_ADDRESS_SIZE );
7504
7505 return TRUE;
7506
7507 } /* End Of mgsl_memory_test() */
7508
7509
7510 /* mgsl_load_pci_memory()
7511 *
7512 * Load a large block of data into the PCI shared memory.
7513 * Use this instead of memcpy() or memmove() to move data
7514 * into the PCI shared memory.
7515 *
7516 * Notes:
7517 *
7518 * This function prevents the PCI9050 interface chip from hogging
7519 * the adapter local bus, which can starve the 16C32 by preventing
7520 * 16C32 bus master cycles.
7521 *
7522 * The PCI9050 documentation says that the 9050 will always release
7523 * control of the local bus after completing the current read
7524 * or write operation.
7525 *
7526 * It appears that as long as the PCI9050 write FIFO is full, the
7527 * PCI9050 treats all of the writes as a single burst transaction
7528 * and will not release the bus. This causes DMA latency problems
7529 * at high speeds when copying large data blocks to the shared
7530 * memory.
7531 *
7532 * This function in effect, breaks the a large shared memory write
7533 * into multiple transations by interleaving a shared memory read
7534 * which will flush the write FIFO and 'complete' the write
7535 * transation. This allows any pending DMA request to gain control
7536 * of the local bus in a timely fasion.
7537 *
7538 * Arguments:
7539 *
7540 * TargetPtr pointer to target address in PCI shared memory
7541 * SourcePtr pointer to source buffer for data
7542 * count count in bytes of data to copy
7543 *
7544 * Return Value: None
7545 */
7546 static void mgsl_load_pci_memory( char* TargetPtr, const char* SourcePtr,
7547 unsigned short count )
7548 {
7549 /* 16 32-bit writes @ 60ns each = 960ns max latency on local bus */
7550 #define PCI_LOAD_INTERVAL 64
7551
7552 unsigned short Intervalcount = count / PCI_LOAD_INTERVAL;
7553 unsigned short Index;
7554 unsigned long Dummy;
7555
7556 for ( Index = 0 ; Index < Intervalcount ; Index++ )
7557 {
7558 memcpy(TargetPtr, SourcePtr, PCI_LOAD_INTERVAL);
7559 Dummy = *((volatile unsigned long *)TargetPtr);
7560 TargetPtr += PCI_LOAD_INTERVAL;
7561 SourcePtr += PCI_LOAD_INTERVAL;
7562 }
7563
7564 memcpy( TargetPtr, SourcePtr, count % PCI_LOAD_INTERVAL );
7565
7566 } /* End Of mgsl_load_pci_memory() */
7567
7568 static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit)
7569 {
7570 int i;
7571 int linecount;
7572 if (xmit)
7573 printk("%s tx data:\n",info->device_name);
7574 else
7575 printk("%s rx data:\n",info->device_name);
7576
7577 while(count) {
7578 if (count > 16)
7579 linecount = 16;
7580 else
7581 linecount = count;
7582
7583 for(i=0;i<linecount;i++)
7584 printk("%02X ",(unsigned char)data[i]);
7585 for(;i<17;i++)
7586 printk(" ");
7587 for(i=0;i<linecount;i++) {
7588 if (data[i]>=040 && data[i]<=0176)
7589 printk("%c",data[i]);
7590 else
7591 printk(".");
7592 }
7593 printk("\n");
7594
7595 data += linecount;
7596 count -= linecount;
7597 }
7598 } /* end of mgsl_trace_block() */
7599
7600 /* mgsl_tx_timeout()
7601 *
7602 * called when HDLC frame times out
7603 * update stats and do tx completion processing
7604 *
7605 * Arguments: context pointer to device instance data
7606 * Return Value: None
7607 */
7608 static void mgsl_tx_timeout(unsigned long context)
7609 {
7610 struct mgsl_struct *info = (struct mgsl_struct*)context;
7611 unsigned long flags;
7612
7613 if ( debug_level >= DEBUG_LEVEL_INFO )
7614 printk( "%s(%d):mgsl_tx_timeout(%s)\n",
7615 __FILE__,__LINE__,info->device_name);
7616 if(info->tx_active &&
7617 (info->params.mode == MGSL_MODE_HDLC ||
7618 info->params.mode == MGSL_MODE_RAW) ) {
7619 info->icount.txtimeout++;
7620 }
7621 spin_lock_irqsave(&info->irq_spinlock,flags);
7622 info->tx_active = 0;
7623 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
7624
7625 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
7626 usc_loopmode_cancel_transmit( info );
7627
7628 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7629
7630 #ifdef CONFIG_HDLC
7631 if (info->netcount)
7632 hdlcdev_tx_done(info);
7633 else
7634 #endif
7635 mgsl_bh_transmit(info);
7636
7637 } /* end of mgsl_tx_timeout() */
7638
7639 /* signal that there are no more frames to send, so that
7640 * line is 'released' by echoing RxD to TxD when current
7641 * transmission is complete (or immediately if no tx in progress).
7642 */
7643 static int mgsl_loopmode_send_done( struct mgsl_struct * info )
7644 {
7645 unsigned long flags;
7646
7647 spin_lock_irqsave(&info->irq_spinlock,flags);
7648 if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
7649 if (info->tx_active)
7650 info->loopmode_send_done_requested = TRUE;
7651 else
7652 usc_loopmode_send_done(info);
7653 }
7654 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7655
7656 return 0;
7657 }
7658
7659 /* release the line by echoing RxD to TxD
7660 * upon completion of a transmit frame
7661 */
7662 static void usc_loopmode_send_done( struct mgsl_struct * info )
7663 {
7664 info->loopmode_send_done_requested = FALSE;
7665 /* clear CMR:13 to 0 to start echoing RxData to TxData */
7666 info->cmr_value &= ~BIT13;
7667 usc_OutReg(info, CMR, info->cmr_value);
7668 }
7669
7670 /* abort a transmit in progress while in HDLC LoopMode
7671 */
7672 static void usc_loopmode_cancel_transmit( struct mgsl_struct * info )
7673 {
7674 /* reset tx dma channel and purge TxFifo */
7675 usc_RTCmd( info, RTCmd_PurgeTxFifo );
7676 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
7677 usc_loopmode_send_done( info );
7678 }
7679
7680 /* for HDLC/SDLC LoopMode, setting CMR:13 after the transmitter is enabled
7681 * is an Insert Into Loop action. Upon receipt of a GoAhead sequence (RxAbort)
7682 * we must clear CMR:13 to begin repeating TxData to RxData
7683 */
7684 static void usc_loopmode_insert_request( struct mgsl_struct * info )
7685 {
7686 info->loopmode_insert_requested = TRUE;
7687
7688 /* enable RxAbort irq. On next RxAbort, clear CMR:13 to
7689 * begin repeating TxData on RxData (complete insertion)
7690 */
7691 usc_OutReg( info, RICR,
7692 (usc_InReg( info, RICR ) | RXSTATUS_ABORT_RECEIVED ) );
7693
7694 /* set CMR:13 to insert into loop on next GoAhead (RxAbort) */
7695 info->cmr_value |= BIT13;
7696 usc_OutReg(info, CMR, info->cmr_value);
7697 }
7698
7699 /* return 1 if station is inserted into the loop, otherwise 0
7700 */
7701 static int usc_loopmode_active( struct mgsl_struct * info)
7702 {
7703 return usc_InReg( info, CCSR ) & BIT7 ? 1 : 0 ;
7704 }
7705
7706 #ifdef CONFIG_HDLC
7707
7708 /**
7709 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
7710 * set encoding and frame check sequence (FCS) options
7711 *
7712 * dev pointer to network device structure
7713 * encoding serial encoding setting
7714 * parity FCS setting
7715 *
7716 * returns 0 if success, otherwise error code
7717 */
7718 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
7719 unsigned short parity)
7720 {
7721 struct mgsl_struct *info = dev_to_port(dev);
7722 unsigned char new_encoding;
7723 unsigned short new_crctype;
7724
7725 /* return error if TTY interface open */
7726 if (info->count)
7727 return -EBUSY;
7728
7729 switch (encoding)
7730 {
7731 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
7732 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
7733 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
7734 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
7735 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
7736 default: return -EINVAL;
7737 }
7738
7739 switch (parity)
7740 {
7741 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
7742 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
7743 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
7744 default: return -EINVAL;
7745 }
7746
7747 info->params.encoding = new_encoding;
7748 info->params.crc_type = new_crctype;
7749
7750 /* if network interface up, reprogram hardware */
7751 if (info->netcount)
7752 mgsl_program_hw(info);
7753
7754 return 0;
7755 }
7756
7757 /**
7758 * called by generic HDLC layer to send frame
7759 *
7760 * skb socket buffer containing HDLC frame
7761 * dev pointer to network device structure
7762 *
7763 * returns 0 if success, otherwise error code
7764 */
7765 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
7766 {
7767 struct mgsl_struct *info = dev_to_port(dev);
7768 struct net_device_stats *stats = hdlc_stats(dev);
7769 unsigned long flags;
7770
7771 if (debug_level >= DEBUG_LEVEL_INFO)
7772 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
7773
7774 /* stop sending until this frame completes */
7775 netif_stop_queue(dev);
7776
7777 /* copy data to device buffers */
7778 info->xmit_cnt = skb->len;
7779 mgsl_load_tx_dma_buffer(info, skb->data, skb->len);
7780
7781 /* update network statistics */
7782 stats->tx_packets++;
7783 stats->tx_bytes += skb->len;
7784
7785 /* done with socket buffer, so free it */
7786 dev_kfree_skb(skb);
7787
7788 /* save start time for transmit timeout detection */
7789 dev->trans_start = jiffies;
7790
7791 /* start hardware transmitter if necessary */
7792 spin_lock_irqsave(&info->irq_spinlock,flags);
7793 if (!info->tx_active)
7794 usc_start_transmitter(info);
7795 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7796
7797 return 0;
7798 }
7799
7800 /**
7801 * called by network layer when interface enabled
7802 * claim resources and initialize hardware
7803 *
7804 * dev pointer to network device structure
7805 *
7806 * returns 0 if success, otherwise error code
7807 */
7808 static int hdlcdev_open(struct net_device *dev)
7809 {
7810 struct mgsl_struct *info = dev_to_port(dev);
7811 int rc;
7812 unsigned long flags;
7813
7814 if (debug_level >= DEBUG_LEVEL_INFO)
7815 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
7816
7817 /* generic HDLC layer open processing */
7818 if ((rc = hdlc_open(dev)))
7819 return rc;
7820
7821 /* arbitrate between network and tty opens */
7822 spin_lock_irqsave(&info->netlock, flags);
7823 if (info->count != 0 || info->netcount != 0) {
7824 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
7825 spin_unlock_irqrestore(&info->netlock, flags);
7826 return -EBUSY;
7827 }
7828 info->netcount=1;
7829 spin_unlock_irqrestore(&info->netlock, flags);
7830
7831 /* claim resources and init adapter */
7832 if ((rc = startup(info)) != 0) {
7833 spin_lock_irqsave(&info->netlock, flags);
7834 info->netcount=0;
7835 spin_unlock_irqrestore(&info->netlock, flags);
7836 return rc;
7837 }
7838
7839 /* assert DTR and RTS, apply hardware settings */
7840 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
7841 mgsl_program_hw(info);
7842
7843 /* enable network layer transmit */
7844 dev->trans_start = jiffies;
7845 netif_start_queue(dev);
7846
7847 /* inform generic HDLC layer of current DCD status */
7848 spin_lock_irqsave(&info->irq_spinlock, flags);
7849 usc_get_serial_signals(info);
7850 spin_unlock_irqrestore(&info->irq_spinlock, flags);
7851 if (info->serial_signals & SerialSignal_DCD)
7852 netif_carrier_on(dev);
7853 else
7854 netif_carrier_off(dev);
7855 return 0;
7856 }
7857
7858 /**
7859 * called by network layer when interface is disabled
7860 * shutdown hardware and release resources
7861 *
7862 * dev pointer to network device structure
7863 *
7864 * returns 0 if success, otherwise error code
7865 */
7866 static int hdlcdev_close(struct net_device *dev)
7867 {
7868 struct mgsl_struct *info = dev_to_port(dev);
7869 unsigned long flags;
7870
7871 if (debug_level >= DEBUG_LEVEL_INFO)
7872 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
7873
7874 netif_stop_queue(dev);
7875
7876 /* shutdown adapter and release resources */
7877 shutdown(info);
7878
7879 hdlc_close(dev);
7880
7881 spin_lock_irqsave(&info->netlock, flags);
7882 info->netcount=0;
7883 spin_unlock_irqrestore(&info->netlock, flags);
7884
7885 return 0;
7886 }
7887
7888 /**
7889 * called by network layer to process IOCTL call to network device
7890 *
7891 * dev pointer to network device structure
7892 * ifr pointer to network interface request structure
7893 * cmd IOCTL command code
7894 *
7895 * returns 0 if success, otherwise error code
7896 */
7897 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7898 {
7899 const size_t size = sizeof(sync_serial_settings);
7900 sync_serial_settings new_line;
7901 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
7902 struct mgsl_struct *info = dev_to_port(dev);
7903 unsigned int flags;
7904
7905 if (debug_level >= DEBUG_LEVEL_INFO)
7906 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
7907
7908 /* return error if TTY interface open */
7909 if (info->count)
7910 return -EBUSY;
7911
7912 if (cmd != SIOCWANDEV)
7913 return hdlc_ioctl(dev, ifr, cmd);
7914
7915 switch(ifr->ifr_settings.type) {
7916 case IF_GET_IFACE: /* return current sync_serial_settings */
7917
7918 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
7919 if (ifr->ifr_settings.size < size) {
7920 ifr->ifr_settings.size = size; /* data size wanted */
7921 return -ENOBUFS;
7922 }
7923
7924 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7925 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7926 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7927 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
7928
7929 switch (flags){
7930 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
7931 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
7932 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
7933 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
7934 default: new_line.clock_type = CLOCK_DEFAULT;
7935 }
7936
7937 new_line.clock_rate = info->params.clock_speed;
7938 new_line.loopback = info->params.loopback ? 1:0;
7939
7940 if (copy_to_user(line, &new_line, size))
7941 return -EFAULT;
7942 return 0;
7943
7944 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
7945
7946 if(!capable(CAP_NET_ADMIN))
7947 return -EPERM;
7948 if (copy_from_user(&new_line, line, size))
7949 return -EFAULT;
7950
7951 switch (new_line.clock_type)
7952 {
7953 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
7954 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
7955 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
7956 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
7957 case CLOCK_DEFAULT: flags = info->params.flags &
7958 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7959 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7960 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7961 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
7962 default: return -EINVAL;
7963 }
7964
7965 if (new_line.loopback != 0 && new_line.loopback != 1)
7966 return -EINVAL;
7967
7968 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7969 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7970 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7971 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
7972 info->params.flags |= flags;
7973
7974 info->params.loopback = new_line.loopback;
7975
7976 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
7977 info->params.clock_speed = new_line.clock_rate;
7978 else
7979 info->params.clock_speed = 0;
7980
7981 /* if network interface up, reprogram hardware */
7982 if (info->netcount)
7983 mgsl_program_hw(info);
7984 return 0;
7985
7986 default:
7987 return hdlc_ioctl(dev, ifr, cmd);
7988 }
7989 }
7990
7991 /**
7992 * called by network layer when transmit timeout is detected
7993 *
7994 * dev pointer to network device structure
7995 */
7996 static void hdlcdev_tx_timeout(struct net_device *dev)
7997 {
7998 struct mgsl_struct *info = dev_to_port(dev);
7999 struct net_device_stats *stats = hdlc_stats(dev);
8000 unsigned long flags;
8001
8002 if (debug_level >= DEBUG_LEVEL_INFO)
8003 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
8004
8005 stats->tx_errors++;
8006 stats->tx_aborted_errors++;
8007
8008 spin_lock_irqsave(&info->irq_spinlock,flags);
8009 usc_stop_transmitter(info);
8010 spin_unlock_irqrestore(&info->irq_spinlock,flags);
8011
8012 netif_wake_queue(dev);
8013 }
8014
8015 /**
8016 * called by device driver when transmit completes
8017 * reenable network layer transmit if stopped
8018 *
8019 * info pointer to device instance information
8020 */
8021 static void hdlcdev_tx_done(struct mgsl_struct *info)
8022 {
8023 if (netif_queue_stopped(info->netdev))
8024 netif_wake_queue(info->netdev);
8025 }
8026
8027 /**
8028 * called by device driver when frame received
8029 * pass frame to network layer
8030 *
8031 * info pointer to device instance information
8032 * buf pointer to buffer contianing frame data
8033 * size count of data bytes in buf
8034 */
8035 static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size)
8036 {
8037 struct sk_buff *skb = dev_alloc_skb(size);
8038 struct net_device *dev = info->netdev;
8039 struct net_device_stats *stats = hdlc_stats(dev);
8040
8041 if (debug_level >= DEBUG_LEVEL_INFO)
8042 printk("hdlcdev_rx(%s)\n",dev->name);
8043
8044 if (skb == NULL) {
8045 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", dev->name);
8046 stats->rx_dropped++;
8047 return;
8048 }
8049
8050 memcpy(skb_put(skb, size),buf,size);
8051
8052 skb->protocol = hdlc_type_trans(skb, info->netdev);
8053
8054 stats->rx_packets++;
8055 stats->rx_bytes += size;
8056
8057 netif_rx(skb);
8058
8059 info->netdev->last_rx = jiffies;
8060 }
8061
8062 /**
8063 * called by device driver when adding device instance
8064 * do generic HDLC initialization
8065 *
8066 * info pointer to device instance information
8067 *
8068 * returns 0 if success, otherwise error code
8069 */
8070 static int hdlcdev_init(struct mgsl_struct *info)
8071 {
8072 int rc;
8073 struct net_device *dev;
8074 hdlc_device *hdlc;
8075
8076 /* allocate and initialize network and HDLC layer objects */
8077
8078 if (!(dev = alloc_hdlcdev(info))) {
8079 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
8080 return -ENOMEM;
8081 }
8082
8083 /* for network layer reporting purposes only */
8084 dev->base_addr = info->io_base;
8085 dev->irq = info->irq_level;
8086 dev->dma = info->dma_level;
8087
8088 /* network layer callbacks and settings */
8089 dev->do_ioctl = hdlcdev_ioctl;
8090 dev->open = hdlcdev_open;
8091 dev->stop = hdlcdev_close;
8092 dev->tx_timeout = hdlcdev_tx_timeout;
8093 dev->watchdog_timeo = 10*HZ;
8094 dev->tx_queue_len = 50;
8095
8096 /* generic HDLC layer callbacks and settings */
8097 hdlc = dev_to_hdlc(dev);
8098 hdlc->attach = hdlcdev_attach;
8099 hdlc->xmit = hdlcdev_xmit;
8100
8101 /* register objects with HDLC layer */
8102 if ((rc = register_hdlc_device(dev))) {
8103 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
8104 free_netdev(dev);
8105 return rc;
8106 }
8107
8108 info->netdev = dev;
8109 return 0;
8110 }
8111
8112 /**
8113 * called by device driver when removing device instance
8114 * do generic HDLC cleanup
8115 *
8116 * info pointer to device instance information
8117 */
8118 static void hdlcdev_exit(struct mgsl_struct *info)
8119 {
8120 unregister_hdlc_device(info->netdev);
8121 free_netdev(info->netdev);
8122 info->netdev = NULL;
8123 }
8124
8125 #endif /* CONFIG_HDLC */
8126
8127
8128 static int __devinit synclink_init_one (struct pci_dev *dev,
8129 const struct pci_device_id *ent)
8130 {
8131 struct mgsl_struct *info;
8132
8133 if (pci_enable_device(dev)) {
8134 printk("error enabling pci device %p\n", dev);
8135 return -EIO;
8136 }
8137
8138 if (!(info = mgsl_allocate_device())) {
8139 printk("can't allocate device instance data.\n");
8140 return -EIO;
8141 }
8142
8143 /* Copy user configuration info to device instance data */
8144
8145 info->io_base = pci_resource_start(dev, 2);
8146 info->irq_level = dev->irq;
8147 info->phys_memory_base = pci_resource_start(dev, 3);
8148
8149 /* Because veremap only works on page boundaries we must map
8150 * a larger area than is actually implemented for the LCR
8151 * memory range. We map a full page starting at the page boundary.
8152 */
8153 info->phys_lcr_base = pci_resource_start(dev, 0);
8154 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
8155 info->phys_lcr_base &= ~(PAGE_SIZE-1);
8156
8157 info->bus_type = MGSL_BUS_TYPE_PCI;
8158 info->io_addr_size = 8;
8159 info->irq_flags = IRQF_SHARED;
8160
8161 if (dev->device == 0x0210) {
8162 /* Version 1 PCI9030 based universal PCI adapter */
8163 info->misc_ctrl_value = 0x007c4080;
8164 info->hw_version = 1;
8165 } else {
8166 /* Version 0 PCI9050 based 5V PCI adapter
8167 * A PCI9050 bug prevents reading LCR registers if
8168 * LCR base address bit 7 is set. Maintain shadow
8169 * value so we can write to LCR misc control reg.
8170 */
8171 info->misc_ctrl_value = 0x087e4546;
8172 info->hw_version = 0;
8173 }
8174
8175 mgsl_add_device(info);
8176
8177 return 0;
8178 }
8179
8180 static void __devexit synclink_remove_one (struct pci_dev *dev)
8181 {
8182 }
8183
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