?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge with 2.5.75.
[linux-2.6/linux-mips.git] / include / linux / pci.h
bloba219c58ad88e2804466200f6977d1689c1f881a8
1 /*
2 * $Id: pci.h,v 1.87 1998/10/11 15:13:12 mj Exp $
3 *
4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
16
17 #ifndef LINUX_PCI_H
18 #define LINUX_PCI_H
19
20 #include <linux/mod_devicetable.h>
21
22 /*
23 * Under PCI, each device has 256 bytes of configuration address space,
24 * of which the first 64 bytes are standardized as follows:
25 */
26 #define PCI_VENDOR_ID 0x00 /* 16 bits */
27 #define PCI_DEVICE_ID 0x02 /* 16 bits */
28 #define PCI_COMMAND 0x04 /* 16 bits */
29 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
30 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
31 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
32 #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
33 #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
34 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
35 #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
36 #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
37 #define PCI_COMMAND_SERR 0x100 /* Enable SERR */
38 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
39
40 #define PCI_STATUS 0x06 /* 16 bits */
41 #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
42 #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
43 #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
44 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
45 #define PCI_STATUS_PARITY 0x100 /* Detected parity error */
46 #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
47 #define PCI_STATUS_DEVSEL_FAST 0x000
48 #define PCI_STATUS_DEVSEL_MEDIUM 0x200
49 #define PCI_STATUS_DEVSEL_SLOW 0x400
50 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
51 #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
52 #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
53 #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
54 #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
55
56 #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
57 revision */
58 #define PCI_REVISION_ID 0x08 /* Revision ID */
59 #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
60 #define PCI_CLASS_DEVICE 0x0a /* Device class */
61
62 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
63 #define PCI_LATENCY_TIMER 0x0d /* 8 bits */
64 #define PCI_HEADER_TYPE 0x0e /* 8 bits */
65 #define PCI_HEADER_TYPE_NORMAL 0
66 #define PCI_HEADER_TYPE_BRIDGE 1
67 #define PCI_HEADER_TYPE_CARDBUS 2
68
69 #define PCI_BIST 0x0f /* 8 bits */
70 #define PCI_BIST_CODE_MASK 0x0f /* Return result */
71 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
72 #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
73
74 /*
75 * Base addresses specify locations in memory or I/O space.
76 * Decoded size can be determined by writing a value of
77 * 0xffffffff to the register, and reading it back. Only
78 * 1 bits are decoded.
79 */
80 #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
81 #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
82 #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
83 #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
84 #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
85 #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
86 #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
87 #define PCI_BASE_ADDRESS_SPACE_IO 0x01
88 #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
89 #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
90 #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
91 #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
92 #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
93 #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
94 #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
95 #define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
96 /* bit 1 is reserved if address_space = 1 */
97
98 /* Header type 0 (normal devices) */
99 #define PCI_CARDBUS_CIS 0x28
100 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c
101 #define PCI_SUBSYSTEM_ID 0x2e
102 #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
103 #define PCI_ROM_ADDRESS_ENABLE 0x01
104 #define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
105
106 #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
107
108 /* 0x35-0x3b are reserved */
109 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
110 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
111 #define PCI_MIN_GNT 0x3e /* 8 bits */
112 #define PCI_MAX_LAT 0x3f /* 8 bits */
113
114 /* Header type 1 (PCI-to-PCI bridges) */
115 #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
116 #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
117 #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
118 #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
119 #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
120 #define PCI_IO_LIMIT 0x1d
121 #define PCI_IO_RANGE_TYPE_MASK 0x0fUL /* I/O bridging type */
122 #define PCI_IO_RANGE_TYPE_16 0x00
123 #define PCI_IO_RANGE_TYPE_32 0x01
124 #define PCI_IO_RANGE_MASK (~0x0fUL)
125 #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
126 #define PCI_MEMORY_BASE 0x20 /* Memory range behind */
127 #define PCI_MEMORY_LIMIT 0x22
128 #define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL
129 #define PCI_MEMORY_RANGE_MASK (~0x0fUL)
130 #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
131 #define PCI_PREF_MEMORY_LIMIT 0x26
132 #define PCI_PREF_RANGE_TYPE_MASK 0x0fUL
133 #define PCI_PREF_RANGE_TYPE_32 0x00
134 #define PCI_PREF_RANGE_TYPE_64 0x01
135 #define PCI_PREF_RANGE_MASK (~0x0fUL)
136 #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
137 #define PCI_PREF_LIMIT_UPPER32 0x2c
138 #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
139 #define PCI_IO_LIMIT_UPPER16 0x32
140 /* 0x34 same as for htype 0 */
141 /* 0x35-0x3b is reserved */
142 #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
143 /* 0x3c-0x3d are same as for htype 0 */
144 #define PCI_BRIDGE_CONTROL 0x3e
145 #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
146 #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
147 #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
148 #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
149 #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
150 #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
151 #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
152
153 /* Header type 2 (CardBus bridges) */
154 #define PCI_CB_CAPABILITY_LIST 0x14
155 /* 0x15 reserved */
156 #define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
157 #define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
158 #define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
159 #define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
160 #define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
161 #define PCI_CB_MEMORY_BASE_0 0x1c
162 #define PCI_CB_MEMORY_LIMIT_0 0x20
163 #define PCI_CB_MEMORY_BASE_1 0x24
164 #define PCI_CB_MEMORY_LIMIT_1 0x28
165 #define PCI_CB_IO_BASE_0 0x2c
166 #define PCI_CB_IO_BASE_0_HI 0x2e
167 #define PCI_CB_IO_LIMIT_0 0x30
168 #define PCI_CB_IO_LIMIT_0_HI 0x32
169 #define PCI_CB_IO_BASE_1 0x34
170 #define PCI_CB_IO_BASE_1_HI 0x36
171 #define PCI_CB_IO_LIMIT_1 0x38
172 #define PCI_CB_IO_LIMIT_1_HI 0x3a
173 #define PCI_CB_IO_RANGE_MASK (~0x03UL)
174 /* 0x3c-0x3d are same as for htype 0 */
175 #define PCI_CB_BRIDGE_CONTROL 0x3e
176 #define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
177 #define PCI_CB_BRIDGE_CTL_SERR 0x02
178 #define PCI_CB_BRIDGE_CTL_ISA 0x04
179 #define PCI_CB_BRIDGE_CTL_VGA 0x08
180 #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
181 #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
182 #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
183 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
184 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
185 #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
186 #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
187 #define PCI_CB_SUBSYSTEM_ID 0x42
188 #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
189 /* 0x48-0x7f reserved */
190
191 /* Capability lists */
192
193 #define PCI_CAP_LIST_ID 0 /* Capability ID */
194 #define PCI_CAP_ID_PM 0x01 /* Power Management */
195 #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
196 #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
197 #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
198 #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
199 #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
200 #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
201 #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
202 #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
203 #define PCI_CAP_SIZEOF 4
204
205 /* Power Management Registers */
206
207 #define PCI_PM_PMC 2 /* PM Capabilities Register */
208 #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
209 #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
210 #define PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */
211 #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
212 #define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */
213 #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
214 #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
215 #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
216 #define PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */
217 #define PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */
218 #define PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */
219 #define PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */
220 #define PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */
221 #define PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */
222 #define PCI_PM_CTRL 4 /* PM control and status register */
223 #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
224 #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
225 #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
226 #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
227 #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
228 #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
229 #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
230 #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
231 #define PCI_PM_DATA_REGISTER 7 /* (??) */
232 #define PCI_PM_SIZEOF 8
233
234 /* AGP registers */
235
236 #define PCI_AGP_VERSION 2 /* BCD version number */
237 #define PCI_AGP_RFU 3 /* Rest of capability flags */
238 #define PCI_AGP_STATUS 4 /* Status register */
239 #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
240 #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
241 #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
242 #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
243 #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
244 #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
245 #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
246 #define PCI_AGP_COMMAND 8 /* Control register */
247 #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
248 #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
249 #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
250 #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
251 #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
252 #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
253 #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate */
254 #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate */
255 #define PCI_AGP_SIZEOF 12
256
257 /* Vital Product Data */
258
259 #define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */
260 #define PCI_VPD_ADDR_MASK 0x7fff /* Address mask */
261 #define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */
262 #define PCI_VPD_DATA 4 /* 32-bits of data returned here */
263
264 /* Slot Identification */
265
266 #define PCI_SID_ESR 2 /* Expansion Slot Register */
267 #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
268 #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
269 #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
270
271 /* Message Signalled Interrupts registers */
272
273 #define PCI_MSI_FLAGS 2 /* Various flags */
274 #define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
275 #define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
276 #define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
277 #define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
278 #define PCI_MSI_RFU 3 /* Rest of capability flags */
279 #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
280 #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
281 #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
282 #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
283
284 /* CompactPCI Hotswap Register */
285
286 #define PCI_CHSWP_CSR 2 /* Control and Status Register */
287 #define PCI_CHSWP_DHA 0x01 /* Device Hiding Arm */
288 #define PCI_CHSWP_EIM 0x02 /* ENUM# Signal Mask */
289 #define PCI_CHSWP_PIE 0x04 /* Pending Insert or Extract */
290 #define PCI_CHSWP_LOO 0x08 /* LED On / Off */
291 #define PCI_CHSWP_PI 0x30 /* Programming Interface */
292 #define PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */
293 #define PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */
294
295 /* PCI-X registers */
296
297 #define PCI_X_CMD 2 /* Modes & Features */
298 #define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
299 #define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
300 #define PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */
301 #define PCI_X_CMD_MAX_SPLIT 0x0070 /* Max Outstanding Split Transactions */
302 #define PCI_X_DEVFN 4 /* A copy of devfn. */
303 #define PCI_X_BUSNR 5 /* Bus segment number */
304 #define PCI_X_STATUS 6 /* PCI-X capabilities */
305 #define PCI_X_STATUS_64BIT 0x0001 /* 64-bit device */
306 #define PCI_X_STATUS_133MHZ 0x0002 /* 133 MHz capable */
307 #define PCI_X_STATUS_SPL_DISC 0x0004 /* Split Completion Discarded */
308 #define PCI_X_STATUS_UNX_SPL 0x0008 /* Unexpected Split Completion */
309 #define PCI_X_STATUS_COMPLEX 0x0010 /* Device Complexity */
310 #define PCI_X_STATUS_MAX_READ 0x0060 /* Designed Maximum Memory Read Count */
311 #define PCI_X_STATUS_MAX_SPLIT 0x0380 /* Design Max Outstanding Split Trans */
312 #define PCI_X_STATUS_MAX_CUM 0x1c00 /* Designed Max Cumulative Read Size */
313 #define PCI_X_STATUS_SPL_ERR 0x2000 /* Rcvd Split Completion Error Msg */
314
315 /* Include the ID list */
316
317 #include <linux/pci_ids.h>
318
319 /*
320 * The PCI interface treats multi-function devices as independent
321 * devices. The slot/function address of each device is encoded
322 * in a single byte as follows:
323 *
324 * 7:3 = slot
325 * 2:0 = function
326 */
327 #define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
328 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
329 #define PCI_FUNC(devfn) ((devfn) & 0x07)
330
331 /* Ioctls for /proc/bus/pci/X/Y nodes. */
332 #define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8)
333 #define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */
334 #define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */
335 #define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */
336 #define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */
337
338 #ifdef __KERNEL__
339
340 #include <linux/types.h>
341 #include <linux/config.h>
342 #include <linux/ioport.h>
343 #include <linux/list.h>
344 #include <linux/errno.h>
345 #include <linux/device.h>
346
347 /* File state for mmap()s on /proc/bus/pci/X/Y */
348 enum pci_mmap_state {
349 pci_mmap_io,
350 pci_mmap_mem
351 };
352
353 /* This defines the direction arg to the DMA mapping routines. */
354 #define PCI_DMA_BIDIRECTIONAL 0
355 #define PCI_DMA_TODEVICE 1
356 #define PCI_DMA_FROMDEVICE 2
357 #define PCI_DMA_NONE 3
358
359 #define DEVICE_COUNT_COMPATIBLE 4
360 #define DEVICE_COUNT_IRQ 2
361 #define DEVICE_COUNT_DMA 2
362 #define DEVICE_COUNT_RESOURCE 12
363
364 /*
365 * The pci_dev structure is used to describe PCI devices.
366 */
367 struct pci_dev {
368 struct list_head global_list; /* node in list of all PCI devices */
369 struct list_head bus_list; /* node in per-bus list */
370 struct pci_bus *bus; /* bus this device is on */
371 struct pci_bus *subordinate; /* bus this device bridges to */
372
373 void *sysdata; /* hook for sys-specific extension */
374 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
375
376 unsigned int devfn; /* encoded device & function index */
377 unsigned short vendor;
378 unsigned short device;
379 unsigned short subsystem_vendor;
380 unsigned short subsystem_device;
381 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
382 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
383 u8 rom_base_reg; /* which config register controls the ROM */
384
385 struct pci_driver *driver; /* which driver has allocated this device */
386 u64 dma_mask; /* Mask of the bits of bus address this
387 device implements. Normally this is
388 0xffffffff. You only need to change
389 this if your device has broken DMA
390 or supports 64-bit transfers. */
391 struct list_head pools; /* pci_pools tied to this device */
392
393 u64 consistent_dma_mask;/* Like dma_mask, but for
394 pci_alloc_consistent mappings as
395 not all hardware supports
396 64 bit addresses for consistent
397 allocations such descriptors. */
398 u32 current_state; /* Current operating state. In ACPI-speak,
399 this is D0-D3, D0 being fully functional,
400 and D3 being off. */
401
402 struct device dev; /* Generic device interface */
403
404 /* device is compatible with these IDs */
405 unsigned short vendor_compatible[DEVICE_COUNT_COMPATIBLE];
406 unsigned short device_compatible[DEVICE_COUNT_COMPATIBLE];
407
408 /*
409 * Instead of touching interrupt line and base address registers
410 * directly, use the values stored here. They might be different!
411 */
412 unsigned int irq;
413 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
414 struct resource dma_resource[DEVICE_COUNT_DMA];
415 struct resource irq_resource[DEVICE_COUNT_IRQ];
416
417 char * slot_name; /* pointer to dev.bus_id */
418
419 /* These fields are used by common fixups */
420 unsigned int transparent:1; /* Transparent PCI bridge */
421 unsigned int multifunction:1;/* Part of multi-function device */
422 };
423
424 #define pci_dev_g(n) list_entry(n, struct pci_dev, global_list)
425 #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
426 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
427
428 /*
429 * For PCI devices, the region numbers are assigned this way:
430 *
431 * 0-5 standard PCI regions
432 * 6 expansion ROM
433 * 7-10 bridges: address space assigned to buses behind the bridge
434 */
435
436 #define PCI_ROM_RESOURCE 6
437 #define PCI_BRIDGE_RESOURCES 7
438 #define PCI_NUM_RESOURCES 11
439
440 #ifndef PCI_BUS_NUM_RESOURCES
441 #define PCI_BUS_NUM_RESOURCES 4
442 #endif
443
444 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
445
446 struct pci_bus {
447 struct list_head node; /* node in list of buses */
448 struct pci_bus *parent; /* parent bus this bridge is on */
449 struct list_head children; /* list of child buses */
450 struct list_head devices; /* list of devices on this bus */
451 struct pci_dev *self; /* bridge device as seen by parent */
452 struct resource *resource[PCI_BUS_NUM_RESOURCES];
453 /* address space routed to this bus */
454
455 struct pci_ops *ops; /* configuration access functions */
456 void *sysdata; /* hook for sys-specific extension */
457 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
458
459 unsigned char number; /* bus number */
460 unsigned char primary; /* number of primary bridge */
461 unsigned char secondary; /* number of secondary bridge */
462 unsigned char subordinate; /* max number of subordinate buses */
463
464 char name[48];
465
466 struct device * dev;
467 };
468
469 #define pci_bus_b(n) list_entry(n, struct pci_bus, node)
470
471 /*
472 * Error values that may be returned by PCI functions.
473 */
474 #define PCIBIOS_SUCCESSFUL 0x00
475 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
476 #define PCIBIOS_BAD_VENDOR_ID 0x83
477 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
478 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
479 #define PCIBIOS_SET_FAILED 0x88
480 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
481
482 /* Low-level architecture-dependent routines */
483
484 struct pci_ops {
485 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
486 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
487 };
488
489 struct pci_raw_ops {
490 int (*read)(int dom, int bus, int devfn, int reg, int len, u32 *val);
491 int (*write)(int dom, int bus, int devfn, int reg, int len, u32 val);
492 };
493
494 extern struct pci_raw_ops *raw_pci_ops;
495
496 struct pci_bus_region {
497 unsigned long start;
498 unsigned long end;
499 };
500
501 struct pci_dynids {
502 spinlock_t lock; /* protects list, index */
503 struct list_head list; /* for IDs added at runtime */
504 unsigned int use_driver_data:1; /* pci_driver->driver_data is used */
505 };
506
507 struct pci_driver {
508 struct list_head node;
509 char *name;
510 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
511 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
512 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
513 int (*save_state) (struct pci_dev *dev, u32 state); /* Save Device Context */
514 int (*suspend) (struct pci_dev *dev, u32 state); /* Device suspended */
515 int (*resume) (struct pci_dev *dev); /* Device woken up */
516 int (*enable_wake) (struct pci_dev *dev, u32 state, int enable); /* Enable wake event */
517
518 struct device_driver driver;
519 struct pci_dynids dynids;
520 };
521
522 #define to_pci_driver(drv) container_of(drv,struct pci_driver, driver)
523
524
525 /* these external functions are only available when PCI support is enabled */
526 #ifdef CONFIG_PCI
527
528 extern struct bus_type pci_bus_type;
529
530 /* Do NOT directly access these two variables, unless you are arch specific pci
531 * code, or pci core code. */
532 extern struct list_head pci_root_buses; /* list of all known PCI buses */
533 extern struct list_head pci_devices; /* list of all devices */
534
535 void pcibios_fixup_bus(struct pci_bus *);
536 int pcibios_enable_device(struct pci_dev *, int mask);
537 char *pcibios_setup (char *str);
538
539 /* Used only when drivers/pci/setup.c is used */
540 void pcibios_align_resource(void *, struct resource *,
541 unsigned long, unsigned long);
542 void pcibios_update_irq(struct pci_dev *, int irq);
543
544 /* Generic PCI functions used internally */
545
546 extern struct pci_bus *pci_find_bus(int domain, int busnr);
547 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus, struct pci_ops *ops, void *sysdata);
548 static inline struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata)
549 {
550 return pci_scan_bus_parented(NULL, bus, ops, sysdata);
551 }
552 int pci_scan_slot(struct pci_bus *bus, int devfn);
553 void pci_bus_add_devices(struct pci_bus *bus);
554 void pci_name_device(struct pci_dev *dev);
555 char *pci_class_name(u32 class);
556 void pci_read_bridge_bases(struct pci_bus *child);
557 struct resource *pci_find_parent_resource(const struct pci_dev *dev, struct resource *res);
558 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
559 extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
560 extern void pci_dev_put(struct pci_dev *dev);
561
562 extern void pci_remove_bus_device(struct pci_dev *dev);
563
564 /* Generic PCI functions exported to card drivers */
565
566 struct pci_dev *pci_find_device (unsigned int vendor, unsigned int device, const struct pci_dev *from);
567 struct pci_dev *pci_find_device_reverse (unsigned int vendor, unsigned int device, const struct pci_dev *from);
568 struct pci_dev *pci_find_subsys (unsigned int vendor, unsigned int device,
569 unsigned int ss_vendor, unsigned int ss_device,
570 const struct pci_dev *from);
571 struct pci_dev *pci_find_class (unsigned int class, const struct pci_dev *from);
572 struct pci_dev *pci_find_slot (unsigned int bus, unsigned int devfn);
573 int pci_find_capability (struct pci_dev *dev, int cap);
574 struct pci_bus * pci_find_next_bus(const struct pci_bus *from);
575
576 struct pci_dev *pci_get_device (unsigned int vendor, unsigned int device, struct pci_dev *from);
577 struct pci_dev *pci_get_subsys (unsigned int vendor, unsigned int device,
578 unsigned int ss_vendor, unsigned int ss_device,
579 struct pci_dev *from);
580 int pci_bus_read_config_byte (struct pci_bus *bus, unsigned int devfn, int where, u8 *val);
581 int pci_bus_read_config_word (struct pci_bus *bus, unsigned int devfn, int where, u16 *val);
582 int pci_bus_read_config_dword (struct pci_bus *bus, unsigned int devfn, int where, u32 *val);
583 int pci_bus_write_config_byte (struct pci_bus *bus, unsigned int devfn, int where, u8 val);
584 int pci_bus_write_config_word (struct pci_bus *bus, unsigned int devfn, int where, u16 val);
585 int pci_bus_write_config_dword (struct pci_bus *bus, unsigned int devfn, int where, u32 val);
586
587 static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val)
588 {
589 return pci_bus_read_config_byte (dev->bus, dev->devfn, where, val);
590 }
591 static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val)
592 {
593 return pci_bus_read_config_word (dev->bus, dev->devfn, where, val);
594 }
595 static inline int pci_read_config_dword(struct pci_dev *dev, int where, u32 *val)
596 {
597 return pci_bus_read_config_dword (dev->bus, dev->devfn, where, val);
598 }
599 static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val)
600 {
601 return pci_bus_write_config_byte (dev->bus, dev->devfn, where, val);
602 }
603 static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val)
604 {
605 return pci_bus_write_config_word (dev->bus, dev->devfn, where, val);
606 }
607 static inline int pci_write_config_dword(struct pci_dev *dev, int where, u32 val)
608 {
609 return pci_bus_write_config_dword (dev->bus, dev->devfn, where, val);
610 }
611
612 int pci_enable_device(struct pci_dev *dev);
613 int pci_enable_device_bars(struct pci_dev *dev, int mask);
614 void pci_disable_device(struct pci_dev *dev);
615 void pci_set_master(struct pci_dev *dev);
616 #define HAVE_PCI_SET_MWI
617 int pci_set_mwi(struct pci_dev *dev);
618 void pci_clear_mwi(struct pci_dev *dev);
619 int pci_set_dma_mask(struct pci_dev *dev, u64 mask);
620 int pci_dac_set_dma_mask(struct pci_dev *dev, u64 mask);
621 int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask);
622 int pci_assign_resource(struct pci_dev *dev, int i);
623
624 /* Power management related routines */
625 int pci_save_state(struct pci_dev *dev, u32 *buffer);
626 int pci_restore_state(struct pci_dev *dev, u32 *buffer);
627 int pci_set_power_state(struct pci_dev *dev, int state);
628 int pci_enable_wake(struct pci_dev *dev, u32 state, int enable);
629
630 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
631 void pci_bus_assign_resources(struct pci_bus *bus);
632 void pci_bus_size_bridges(struct pci_bus *bus);
633 int pci_claim_resource(struct pci_dev *, int);
634 void pci_assign_unassigned_resources(void);
635 void pdev_enable_device(struct pci_dev *);
636 void pdev_sort_resources(struct pci_dev *, struct resource_list *);
637 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
638 int (*)(struct pci_dev *, u8, u8));
639 #define HAVE_PCI_REQ_REGIONS 2
640 int pci_request_regions(struct pci_dev *, char *);
641 void pci_release_regions(struct pci_dev *);
642 int pci_request_region(struct pci_dev *, int, char *);
643 void pci_release_region(struct pci_dev *, int);
644
645 /* drivers/pci/bus.c */
646 void pci_enable_bridges(struct pci_bus *bus);
647
648 /* New-style probing supporting hot-pluggable devices */
649 int pci_register_driver(struct pci_driver *);
650 void pci_unregister_driver(struct pci_driver *);
651 void pci_remove_behind_bridge(struct pci_dev *);
652 struct pci_driver *pci_dev_driver(const struct pci_dev *);
653 const struct pci_device_id *pci_match_device(const struct pci_device_id *ids, const struct pci_dev *dev);
654 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass);
655
656 /* kmem_cache style wrapper around pci_alloc_consistent() */
657 struct pci_pool *pci_pool_create (const char *name, struct pci_dev *dev,
658 size_t size, size_t align, size_t allocation);
659 void pci_pool_destroy (struct pci_pool *pool);
660
661 void *pci_pool_alloc (struct pci_pool *pool, int flags, dma_addr_t *handle);
662 void pci_pool_free (struct pci_pool *pool, void *vaddr, dma_addr_t addr);
663
664 #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
665 extern struct pci_dev *isa_bridge;
666 #endif
667
668 #endif /* CONFIG_PCI */
669
670 /* Include architecture-dependent settings and functions */
671
672 #include <asm/pci.h>
673
674 /*
675 * If the system does not have PCI, clearly these return errors. Define
676 * these as simple inline functions to avoid hair in drivers.
677 */
678
679 #ifndef CONFIG_PCI
680 #define _PCI_NOP(o,s,t) \
681 static inline int pci_##o##_config_##s (struct pci_dev *dev, int where, t val) \
682 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
683 #define _PCI_NOP_ALL(o,x) _PCI_NOP(o,byte,u8 x) \
684 _PCI_NOP(o,word,u16 x) \
685 _PCI_NOP(o,dword,u32 x)
686 _PCI_NOP_ALL(read, *)
687 _PCI_NOP_ALL(write,)
688
689 static inline struct pci_dev *pci_find_device(unsigned int vendor, unsigned int device, const struct pci_dev *from)
690 { return NULL; }
691
692 static inline struct pci_dev *pci_find_class(unsigned int class, const struct pci_dev *from)
693 { return NULL; }
694
695 static inline struct pci_dev *pci_find_slot(unsigned int bus, unsigned int devfn)
696 { return NULL; }
697
698 static inline struct pci_dev *pci_find_subsys(unsigned int vendor, unsigned int device,
699 unsigned int ss_vendor, unsigned int ss_device, const struct pci_dev *from)
700 { return NULL; }
701
702 static inline struct pci_dev *pci_get_device (unsigned int vendor, unsigned int device, struct pci_dev *from)
703 { return NULL; }
704
705 static inline struct pci_dev *pci_get_subsys (unsigned int vendor, unsigned int device,
706 unsigned int ss_vendor, unsigned int ss_device, struct pci_dev *from)
707 { return NULL; }
708
709 static inline void pci_set_master(struct pci_dev *dev) { }
710 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
711 static inline void pci_disable_device(struct pci_dev *dev) { }
712 static inline int pci_module_init(struct pci_driver *drv) { return -ENODEV; }
713 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) { return -EIO; }
714 static inline int pci_dac_set_dma_mask(struct pci_dev *dev, u64 mask) { return -EIO; }
715 static inline int pci_assign_resource(struct pci_dev *dev, int i) { return -EBUSY;}
716 static inline int pci_register_driver(struct pci_driver *drv) { return 0;}
717 static inline void pci_unregister_driver(struct pci_driver *drv) { }
718 static inline int scsi_to_pci_dma_dir(unsigned char scsi_dir) { return scsi_dir; }
719 static inline int pci_find_capability (struct pci_dev *dev, int cap) {return 0; }
720 static inline const struct pci_device_id *pci_match_device(const struct pci_device_id *ids, const struct pci_dev *dev) { return NULL; }
721
722 /* Power management related routines */
723 static inline int pci_save_state(struct pci_dev *dev, u32 *buffer) { return 0; }
724 static inline int pci_restore_state(struct pci_dev *dev, u32 *buffer) { return 0; }
725 static inline int pci_set_power_state(struct pci_dev *dev, int state) { return 0; }
726 static inline int pci_enable_wake(struct pci_dev *dev, u32 state, int enable) { return 0; }
727
728 #define isa_bridge ((struct pci_dev *)NULL)
729
730 #else
731
732 /*
733 * a helper function which helps ensure correct pci_driver
734 * setup and cleanup for commonly-encountered hotplug/modular cases
735 *
736 * This MUST stay in a header, as it checks for -DMODULE
737 */
738 static inline int pci_module_init(struct pci_driver *drv)
739 {
740 int rc = pci_register_driver (drv);
741
742 if (rc > 0)
743 return 0;
744
745 /* iff CONFIG_HOTPLUG and built into kernel, we should
746 * leave the driver around for future hotplug events.
747 * For the module case, a hotplug daemon of some sort
748 * should load a module in response to an insert event. */
749 #if defined(CONFIG_HOTPLUG) && !defined(MODULE)
750 if (rc == 0)
751 return 0;
752 #else
753 if (rc == 0)
754 rc = -ENODEV;
755 #endif
756
757 /* if we get here, we need to clean up pci driver instance
758 * and return some sort of error */
759 pci_unregister_driver (drv);
760
761 return rc;
762 }
763
764 /*
765 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
766 * a PCI domain is defined to be a set of PCI busses which share
767 * configuration space.
768 */
769 #ifndef CONFIG_PCI_DOMAINS
770 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
771 static inline int pci_name_bus(char *name, struct pci_bus *bus)
772 {
773 sprintf(name, "%02x", bus->number);
774 return 0;
775 }
776 #endif
777
778 #endif /* !CONFIG_PCI */
779
780 /* these helpers provide future and backwards compatibility
781 * for accessing popular PCI BAR info */
782 #define pci_resource_start(dev,bar) ((dev)->resource[(bar)].start)
783 #define pci_resource_end(dev,bar) ((dev)->resource[(bar)].end)
784 #define pci_resource_flags(dev,bar) ((dev)->resource[(bar)].flags)
785 #define pci_resource_len(dev,bar) \
786 ((pci_resource_start((dev),(bar)) == 0 && \
787 pci_resource_end((dev),(bar)) == \
788 pci_resource_start((dev),(bar))) ? 0 : \
789 \
790 (pci_resource_end((dev),(bar)) - \
791 pci_resource_start((dev),(bar)) + 1))
792
793 /* Similar to the helpers above, these manipulate per-pci_dev
794 * driver-specific data. They are really just a wrapper around
795 * the generic device structure functions of these calls.
796 */
797 static inline void *pci_get_drvdata (struct pci_dev *pdev)
798 {
799 return dev_get_drvdata(&pdev->dev);
800 }
801
802 static inline void pci_set_drvdata (struct pci_dev *pdev, void *data)
803 {
804 dev_set_drvdata(&pdev->dev, data);
805 }
806
807 /* If you want to know what to call your pci_dev, ask this function.
808 * Again, it's a wrapper around the generic device.
809 */
810 static inline char *pci_name(struct pci_dev *pdev)
811 {
812 return pdev->dev.bus_id;
813 }
814
815 /*
816 * The world is not perfect and supplies us with broken PCI devices.
817 * For at least a part of these bugs we need a work-around, so both
818 * generic (drivers/pci/quirks.c) and per-architecture code can define
819 * fixup hooks to be called for particular buggy devices.
820 */
821
822 struct pci_fixup {
823 int pass;
824 u16 vendor, device; /* You can use PCI_ANY_ID here of course */
825 void (*hook)(struct pci_dev *dev);
826 };
827
828 extern struct pci_fixup pcibios_fixups[];
829
830 #define PCI_FIXUP_HEADER 1 /* Called immediately after reading configuration header */
831 #define PCI_FIXUP_FINAL 2 /* Final phase of device fixups */
832
833 void pci_fixup_device(int pass, struct pci_dev *dev);
834
835 extern int pci_pci_problems;
836 #define PCIPCI_FAIL 1
837 #define PCIPCI_TRITON 2
838 #define PCIPCI_NATOMA 4
839 #define PCIPCI_VIAETBF 8
840 #define PCIPCI_VSFX 16
841 #define PCIPCI_ALIMAGIK 32
842
843 #endif /* __KERNEL__ */
844 #endif /* LINUX_PCI_H */
Mirror of the linux-mips.org kernel tree