include/asm-cris/cacheflush.h

   1 #ifndef _CRIS_CACHEFLUSH_H
   2 #define _CRIS_CACHEFLUSH_H
   3
   4 /* Keep includes the same across arches.  */
   5 #include <linux/mm.h>
   6
   7 /* The cache doesn't need to be flushed when TLB entries change because
   8  * the cache is mapped to physical memory, not virtual memory
   9  */
  10 #define flush_cache_all()                       do { } while (0)
  11 #define flush_cache_mm(mm)                      do { } while (0)
  12 #define flush_cache_range(vma, start, end)      do { } while (0)
  13 #define flush_cache_page(vma, vmaddr)           do { } while (0)
  14 #define flush_page_to_ram(page)                 do { } while (0)
  15 #define flush_dcache_page(page)                 do { } while (0)
  16 #define flush_icache_range(start, end)          do { } while (0)
  17 #define flush_icache_page(vma,pg)               do { } while (0)
  18 #define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
  19
  20 void global_flush_tlb(void);
  21 int change_page_attr(struct page *page, int numpages, pgprot_t prot);
  22
  23 #endif /* _CRIS_CACHEFLUSH_H */