2 * Intel e752x Memory Controller kernel module
3 * (C) 2004 Linux Networx (http://lnxi.com)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
7 * See "enum e752x_chips" below for supported chipsets
9 * Written by Tom Zimmerman
12 * Thayne Harbaugh at realmsys.com (?)
13 * Wang Zhenyu at intel.com
14 * Dave Jiang at mvista.com
16 * $Id: edac_e752x.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $
20 #include <linux/config.h>
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/pci.h>
24 #include <linux/pci_ids.h>
25 #include <linux/slab.h>
28 static int force_function_unhide
;
30 #define e752x_printk(level, fmt, arg...) \
31 edac_printk(level, "e752x", fmt, ##arg)
33 #define e752x_mc_printk(mci, level, fmt, arg...) \
34 edac_mc_chipset_printk(mci, level, "e752x", fmt, ##arg)
36 #ifndef PCI_DEVICE_ID_INTEL_7520_0
37 #define PCI_DEVICE_ID_INTEL_7520_0 0x3590
38 #endif /* PCI_DEVICE_ID_INTEL_7520_0 */
40 #ifndef PCI_DEVICE_ID_INTEL_7520_1_ERR
41 #define PCI_DEVICE_ID_INTEL_7520_1_ERR 0x3591
42 #endif /* PCI_DEVICE_ID_INTEL_7520_1_ERR */
44 #ifndef PCI_DEVICE_ID_INTEL_7525_0
45 #define PCI_DEVICE_ID_INTEL_7525_0 0x359E
46 #endif /* PCI_DEVICE_ID_INTEL_7525_0 */
48 #ifndef PCI_DEVICE_ID_INTEL_7525_1_ERR
49 #define PCI_DEVICE_ID_INTEL_7525_1_ERR 0x3593
50 #endif /* PCI_DEVICE_ID_INTEL_7525_1_ERR */
52 #ifndef PCI_DEVICE_ID_INTEL_7320_0
53 #define PCI_DEVICE_ID_INTEL_7320_0 0x3592
54 #endif /* PCI_DEVICE_ID_INTEL_7320_0 */
56 #ifndef PCI_DEVICE_ID_INTEL_7320_1_ERR
57 #define PCI_DEVICE_ID_INTEL_7320_1_ERR 0x3593
58 #endif /* PCI_DEVICE_ID_INTEL_7320_1_ERR */
60 #define E752X_NR_CSROWS 8 /* number of csrows */
62 /* E752X register addresses - device 0 function 0 */
63 #define E752X_DRB 0x60 /* DRAM row boundary register (8b) */
64 #define E752X_DRA 0x70 /* DRAM row attribute register (8b) */
66 * 31:30 Device width row 7
67 * 01=x8 10=x4 11=x8 DDR2
68 * 27:26 Device width row 6
69 * 23:22 Device width row 5
70 * 19:20 Device width row 4
71 * 15:14 Device width row 3
72 * 11:10 Device width row 2
73 * 7:6 Device width row 1
74 * 3:2 Device width row 0
76 #define E752X_DRC 0x7C /* DRAM controller mode reg (32b) */
77 /* FIXME:IS THIS RIGHT? */
79 * 22 Number channels 0=1,1=2
80 * 19:18 DRB Granularity 32/64MB
82 #define E752X_DRM 0x80 /* Dimm mapping register */
83 #define E752X_DDRCSR 0x9A /* DDR control and status reg (16b) */
85 * 14:12 1 single A, 2 single B, 3 dual
87 #define E752X_TOLM 0xC4 /* DRAM top of low memory reg (16b) */
88 #define E752X_REMAPBASE 0xC6 /* DRAM remap base address reg (16b) */
89 #define E752X_REMAPLIMIT 0xC8 /* DRAM remap limit address reg (16b) */
90 #define E752X_REMAPOFFSET 0xCA /* DRAM remap limit offset reg (16b) */
92 /* E752X register addresses - device 0 function 1 */
93 #define E752X_FERR_GLOBAL 0x40 /* Global first error register (32b) */
94 #define E752X_NERR_GLOBAL 0x44 /* Global next error register (32b) */
95 #define E752X_HI_FERR 0x50 /* Hub interface first error reg (8b) */
96 #define E752X_HI_NERR 0x52 /* Hub interface next error reg (8b) */
97 #define E752X_HI_ERRMASK 0x54 /* Hub interface error mask reg (8b) */
98 #define E752X_HI_SMICMD 0x5A /* Hub interface SMI command reg (8b) */
99 #define E752X_SYSBUS_FERR 0x60 /* System buss first error reg (16b) */
100 #define E752X_SYSBUS_NERR 0x62 /* System buss next error reg (16b) */
101 #define E752X_SYSBUS_ERRMASK 0x64 /* System buss error mask reg (16b) */
102 #define E752X_SYSBUS_SMICMD 0x6A /* System buss SMI command reg (16b) */
103 #define E752X_BUF_FERR 0x70 /* Memory buffer first error reg (8b) */
104 #define E752X_BUF_NERR 0x72 /* Memory buffer next error reg (8b) */
105 #define E752X_BUF_ERRMASK 0x74 /* Memory buffer error mask reg (8b) */
106 #define E752X_BUF_SMICMD 0x7A /* Memory buffer SMI command reg (8b) */
107 #define E752X_DRAM_FERR 0x80 /* DRAM first error register (16b) */
108 #define E752X_DRAM_NERR 0x82 /* DRAM next error register (16b) */
109 #define E752X_DRAM_ERRMASK 0x84 /* DRAM error mask register (8b) */
110 #define E752X_DRAM_SMICMD 0x8A /* DRAM SMI command register (8b) */
111 #define E752X_DRAM_RETR_ADD 0xAC /* DRAM Retry address register (32b) */
112 #define E752X_DRAM_SEC1_ADD 0xA0 /* DRAM first correctable memory */
113 /* error address register (32b) */
116 * 30:2 CE address (64 byte block 34:6)
120 #define E752X_DRAM_SEC2_ADD 0xC8 /* DRAM first correctable memory */
121 /* error address register (32b) */
124 * 30:2 CE address (64 byte block 34:6)
128 #define E752X_DRAM_DED_ADD 0xA4 /* DRAM first uncorrectable memory */
129 /* error address register (32b) */
132 * 30:2 CE address (64 byte block 34:6)
136 #define E752X_DRAM_SCRB_ADD 0xA8 /* DRAM first uncorrectable scrub memory */
137 /* error address register (32b) */
140 * 30:2 CE address (64 byte block 34:6)
144 #define E752X_DRAM_SEC1_SYNDROME 0xC4 /* DRAM first correctable memory */
145 /* error syndrome register (16b) */
146 #define E752X_DRAM_SEC2_SYNDROME 0xC6 /* DRAM second correctable memory */
147 /* error syndrome register (16b) */
148 #define E752X_DEVPRES1 0xF4 /* Device Present 1 register (8b) */
150 /* ICH5R register addresses - device 30 function 0 */
151 #define ICH5R_PCI_STAT 0x06 /* PCI status register (16b) */
152 #define ICH5R_PCI_2ND_STAT 0x1E /* PCI status secondary reg (16b) */
153 #define ICH5R_PCI_BRIDGE_CTL 0x3E /* PCI bridge control register (16b) */
162 struct pci_dev
*bridge_ck
;
163 struct pci_dev
*dev_d0f0
;
164 struct pci_dev
*dev_d0f1
;
171 const struct e752x_dev_info
*dev_info
;
174 struct e752x_dev_info
{
177 const char *ctl_name
;
180 struct e752x_error_info
{
193 u16 dram_sec1_syndrome
;
194 u16 dram_sec2_syndrome
;
200 static const struct e752x_dev_info e752x_devs
[] = {
202 .err_dev
= PCI_DEVICE_ID_INTEL_7520_1_ERR
,
203 .ctl_dev
= PCI_DEVICE_ID_INTEL_7520_0
,
207 .err_dev
= PCI_DEVICE_ID_INTEL_7525_1_ERR
,
208 .ctl_dev
= PCI_DEVICE_ID_INTEL_7525_0
,
212 .err_dev
= PCI_DEVICE_ID_INTEL_7320_1_ERR
,
213 .ctl_dev
= PCI_DEVICE_ID_INTEL_7320_0
,
218 static unsigned long ctl_page_to_phys(struct mem_ctl_info
*mci
,
222 struct e752x_pvt
*pvt
= (struct e752x_pvt
*) mci
->pvt_info
;
224 debugf3("%s()\n", __func__
);
226 if (page
< pvt
->tolm
)
229 if ((page
>= 0x100000) && (page
< pvt
->remapbase
))
232 remap
= (page
- pvt
->tolm
) + pvt
->remapbase
;
234 if (remap
< pvt
->remaplimit
)
237 e752x_printk(KERN_ERR
, "Invalid page %lx - out of range\n", page
);
238 return pvt
->tolm
- 1;
241 static void do_process_ce(struct mem_ctl_info
*mci
, u16 error_one
,
242 u32 sec1_add
, u16 sec1_syndrome
)
248 struct e752x_pvt
*pvt
= (struct e752x_pvt
*) mci
->pvt_info
;
250 debugf3("%s()\n", __func__
);
252 /* convert the addr to 4k page */
253 page
= sec1_add
>> (PAGE_SHIFT
- 4);
255 /* FIXME - check for -1 */
256 if (pvt
->mc_symmetric
) {
257 /* chip select are bits 14 & 13 */
258 row
= ((page
>> 1) & 3);
259 e752x_printk(KERN_WARNING
,
260 "Test row %d Table %d %d %d %d %d %d %d %d\n", row
,
261 pvt
->map
[0], pvt
->map
[1], pvt
->map
[2], pvt
->map
[3],
262 pvt
->map
[4], pvt
->map
[5], pvt
->map
[6], pvt
->map
[7]);
264 /* test for channel remapping */
265 for (i
= 0; i
< 8; i
++) {
266 if (pvt
->map
[i
] == row
)
270 e752x_printk(KERN_WARNING
, "Test computed row %d\n", i
);
275 e752x_mc_printk(mci
, KERN_WARNING
,
276 "row %d not found in remap table\n", row
);
278 row
= edac_mc_find_csrow_by_page(mci
, page
);
280 /* 0 = channel A, 1 = channel B */
281 channel
= !(error_one
& 1);
286 edac_mc_handle_ce(mci
, page
, 0, sec1_syndrome
, row
, channel
,
290 static inline void process_ce(struct mem_ctl_info
*mci
, u16 error_one
,
291 u32 sec1_add
, u16 sec1_syndrome
, int *error_found
,
297 do_process_ce(mci
, error_one
, sec1_add
, sec1_syndrome
);
300 static void do_process_ue(struct mem_ctl_info
*mci
, u16 error_one
,
301 u32 ded_add
, u32 scrb_add
)
303 u32 error_2b
, block_page
;
305 struct e752x_pvt
*pvt
= (struct e752x_pvt
*) mci
->pvt_info
;
307 debugf3("%s()\n", __func__
);
309 if (error_one
& 0x0202) {
312 /* convert to 4k address */
313 block_page
= error_2b
>> (PAGE_SHIFT
- 4);
315 row
= pvt
->mc_symmetric
?
316 /* chip select are bits 14 & 13 */
317 ((block_page
>> 1) & 3) :
318 edac_mc_find_csrow_by_page(mci
, block_page
);
320 edac_mc_handle_ue(mci
, block_page
, 0, row
,
321 "e752x UE from Read");
323 if (error_one
& 0x0404) {
326 /* convert to 4k address */
327 block_page
= error_2b
>> (PAGE_SHIFT
- 4);
329 row
= pvt
->mc_symmetric
?
330 /* chip select are bits 14 & 13 */
331 ((block_page
>> 1) & 3) :
332 edac_mc_find_csrow_by_page(mci
, block_page
);
334 edac_mc_handle_ue(mci
, block_page
, 0, row
,
335 "e752x UE from Scruber");
339 static inline void process_ue(struct mem_ctl_info
*mci
, u16 error_one
,
340 u32 ded_add
, u32 scrb_add
, int *error_found
, int handle_error
)
345 do_process_ue(mci
, error_one
, ded_add
, scrb_add
);
348 static inline void process_ue_no_info_wr(struct mem_ctl_info
*mci
,
349 int *error_found
, int handle_error
)
356 debugf3("%s()\n", __func__
);
357 edac_mc_handle_ue_no_info(mci
, "e752x UE log memory write");
360 static void do_process_ded_retry(struct mem_ctl_info
*mci
, u16 error
,
365 struct e752x_pvt
*pvt
= (struct e752x_pvt
*) mci
->pvt_info
;
367 error_1b
= retry_add
;
368 page
= error_1b
>> (PAGE_SHIFT
- 4); /* convert the addr to 4k page */
369 row
= pvt
->mc_symmetric
?
370 ((page
>> 1) & 3) : /* chip select are bits 14 & 13 */
371 edac_mc_find_csrow_by_page(mci
, page
);
372 e752x_mc_printk(mci
, KERN_WARNING
,
373 "CE page 0x%lx, row %d : Memory read retry\n",
374 (long unsigned int) page
, row
);
377 static inline void process_ded_retry(struct mem_ctl_info
*mci
, u16 error
,
378 u32 retry_add
, int *error_found
, int handle_error
)
383 do_process_ded_retry(mci
, error
, retry_add
);
386 static inline void process_threshold_ce(struct mem_ctl_info
*mci
, u16 error
,
387 int *error_found
, int handle_error
)
392 e752x_mc_printk(mci
, KERN_WARNING
, "Memory threshold CE\n");
395 static char *global_message
[11] = {
396 "PCI Express C1", "PCI Express C", "PCI Express B1",
397 "PCI Express B", "PCI Express A1", "PCI Express A",
398 "DMA Controler", "HUB Interface", "System Bus",
399 "DRAM Controler", "Internal Buffer"
402 static char *fatal_message
[2] = { "Non-Fatal ", "Fatal " };
404 static void do_global_error(int fatal
, u32 errors
)
408 for (i
= 0; i
< 11; i
++) {
409 if (errors
& (1 << i
))
410 e752x_printk(KERN_WARNING
, "%sError %s\n",
411 fatal_message
[fatal
], global_message
[i
]);
415 static inline void global_error(int fatal
, u32 errors
, int *error_found
,
421 do_global_error(fatal
, errors
);
424 static char *hub_message
[7] = {
425 "HI Address or Command Parity", "HI Illegal Access",
426 "HI Internal Parity", "Out of Range Access",
427 "HI Data Parity", "Enhanced Config Access",
428 "Hub Interface Target Abort"
431 static void do_hub_error(int fatal
, u8 errors
)
435 for (i
= 0; i
< 7; i
++) {
436 if (errors
& (1 << i
))
437 e752x_printk(KERN_WARNING
, "%sError %s\n",
438 fatal_message
[fatal
], hub_message
[i
]);
442 static inline void hub_error(int fatal
, u8 errors
, int *error_found
,
448 do_hub_error(fatal
, errors
);
451 static char *membuf_message
[4] = {
452 "Internal PMWB to DRAM parity",
453 "Internal PMWB to System Bus Parity",
454 "Internal System Bus or IO to PMWB Parity",
455 "Internal DRAM to PMWB Parity"
458 static void do_membuf_error(u8 errors
)
462 for (i
= 0; i
< 4; i
++) {
463 if (errors
& (1 << i
))
464 e752x_printk(KERN_WARNING
, "Non-Fatal Error %s\n",
469 static inline void membuf_error(u8 errors
, int *error_found
, int handle_error
)
474 do_membuf_error(errors
);
477 static char *sysbus_message
[10] = {
478 "Addr or Request Parity",
479 "Data Strobe Glitch",
480 "Addr Strobe Glitch",
483 "Non DRAM Lock Error",
486 "IO Subsystem Parity"
489 static void do_sysbus_error(int fatal
, u32 errors
)
493 for (i
= 0; i
< 10; i
++) {
494 if (errors
& (1 << i
))
495 e752x_printk(KERN_WARNING
, "%sError System Bus %s\n",
496 fatal_message
[fatal
], sysbus_message
[i
]);
500 static inline void sysbus_error(int fatal
, u32 errors
, int *error_found
,
506 do_sysbus_error(fatal
, errors
);
509 static void e752x_check_hub_interface(struct e752x_error_info
*info
,
510 int *error_found
, int handle_error
)
514 //pci_read_config_byte(dev,E752X_HI_FERR,&stat8);
516 stat8
= info
->hi_ferr
;
518 if(stat8
& 0x7f) { /* Error, so process */
522 hub_error(1, stat8
& 0x2b, error_found
, handle_error
);
525 hub_error(0, stat8
& 0x54, error_found
, handle_error
);
528 //pci_read_config_byte(dev,E752X_HI_NERR,&stat8);
530 stat8
= info
->hi_nerr
;
532 if(stat8
& 0x7f) { /* Error, so process */
536 hub_error(1, stat8
& 0x2b, error_found
, handle_error
);
539 hub_error(0, stat8
& 0x54, error_found
, handle_error
);
543 static void e752x_check_sysbus(struct e752x_error_info
*info
,
544 int *error_found
, int handle_error
)
548 //pci_read_config_dword(dev,E752X_SYSBUS_FERR,&stat32);
549 stat32
= info
->sysbus_ferr
+ (info
->sysbus_nerr
<< 16);
552 return; /* no errors */
554 error32
= (stat32
>> 16) & 0x3ff;
555 stat32
= stat32
& 0x3ff;
558 sysbus_error(1, stat32
& 0x083, error_found
, handle_error
);
561 sysbus_error(0, stat32
& 0x37c, error_found
, handle_error
);
564 sysbus_error(1, error32
& 0x083, error_found
, handle_error
);
567 sysbus_error(0, error32
& 0x37c, error_found
, handle_error
);
570 static void e752x_check_membuf (struct e752x_error_info
*info
,
571 int *error_found
, int handle_error
)
575 stat8
= info
->buf_ferr
;
577 if (stat8
& 0x0f) { /* Error, so process */
579 membuf_error(stat8
, error_found
, handle_error
);
582 stat8
= info
->buf_nerr
;
584 if (stat8
& 0x0f) { /* Error, so process */
586 membuf_error(stat8
, error_found
, handle_error
);
590 static void e752x_check_dram (struct mem_ctl_info
*mci
,
591 struct e752x_error_info
*info
, int *error_found
,
594 u16 error_one
, error_next
;
596 error_one
= info
->dram_ferr
;
597 error_next
= info
->dram_nerr
;
599 /* decode and report errors */
600 if(error_one
& 0x0101) /* check first error correctable */
601 process_ce(mci
, error_one
, info
->dram_sec1_add
,
602 info
->dram_sec1_syndrome
, error_found
,
605 if(error_next
& 0x0101) /* check next error correctable */
606 process_ce(mci
, error_next
, info
->dram_sec2_add
,
607 info
->dram_sec2_syndrome
, error_found
,
610 if(error_one
& 0x4040)
611 process_ue_no_info_wr(mci
, error_found
, handle_error
);
613 if(error_next
& 0x4040)
614 process_ue_no_info_wr(mci
, error_found
, handle_error
);
616 if(error_one
& 0x2020)
617 process_ded_retry(mci
, error_one
, info
->dram_retr_add
,
618 error_found
, handle_error
);
620 if(error_next
& 0x2020)
621 process_ded_retry(mci
, error_next
, info
->dram_retr_add
,
622 error_found
, handle_error
);
624 if(error_one
& 0x0808)
625 process_threshold_ce(mci
, error_one
, error_found
,
628 if(error_next
& 0x0808)
629 process_threshold_ce(mci
, error_next
, error_found
,
632 if(error_one
& 0x0606)
633 process_ue(mci
, error_one
, info
->dram_ded_add
,
634 info
->dram_scrb_add
, error_found
, handle_error
);
636 if(error_next
& 0x0606)
637 process_ue(mci
, error_next
, info
->dram_ded_add
,
638 info
->dram_scrb_add
, error_found
, handle_error
);
641 static void e752x_get_error_info (struct mem_ctl_info
*mci
,
642 struct e752x_error_info
*info
)
645 struct e752x_pvt
*pvt
;
647 memset(info
, 0, sizeof(*info
));
648 pvt
= (struct e752x_pvt
*) mci
->pvt_info
;
650 pci_read_config_dword(dev
, E752X_FERR_GLOBAL
, &info
->ferr_global
);
652 if (info
->ferr_global
) {
653 pci_read_config_byte(dev
, E752X_HI_FERR
, &info
->hi_ferr
);
654 pci_read_config_word(dev
, E752X_SYSBUS_FERR
,
656 pci_read_config_byte(dev
, E752X_BUF_FERR
, &info
->buf_ferr
);
657 pci_read_config_word(dev
, E752X_DRAM_FERR
,
659 pci_read_config_dword(dev
, E752X_DRAM_SEC1_ADD
,
660 &info
->dram_sec1_add
);
661 pci_read_config_word(dev
, E752X_DRAM_SEC1_SYNDROME
,
662 &info
->dram_sec1_syndrome
);
663 pci_read_config_dword(dev
, E752X_DRAM_DED_ADD
,
664 &info
->dram_ded_add
);
665 pci_read_config_dword(dev
, E752X_DRAM_SCRB_ADD
,
666 &info
->dram_scrb_add
);
667 pci_read_config_dword(dev
, E752X_DRAM_RETR_ADD
,
668 &info
->dram_retr_add
);
670 if (info
->hi_ferr
& 0x7f)
671 pci_write_config_byte(dev
, E752X_HI_FERR
,
674 if (info
->sysbus_ferr
)
675 pci_write_config_word(dev
, E752X_SYSBUS_FERR
,
678 if (info
->buf_ferr
& 0x0f)
679 pci_write_config_byte(dev
, E752X_BUF_FERR
,
683 pci_write_bits16(pvt
->bridge_ck
, E752X_DRAM_FERR
,
684 info
->dram_ferr
, info
->dram_ferr
);
686 pci_write_config_dword(dev
, E752X_FERR_GLOBAL
,
690 pci_read_config_dword(dev
, E752X_NERR_GLOBAL
, &info
->nerr_global
);
692 if (info
->nerr_global
) {
693 pci_read_config_byte(dev
, E752X_HI_NERR
, &info
->hi_nerr
);
694 pci_read_config_word(dev
, E752X_SYSBUS_NERR
,
696 pci_read_config_byte(dev
, E752X_BUF_NERR
, &info
->buf_nerr
);
697 pci_read_config_word(dev
, E752X_DRAM_NERR
,
699 pci_read_config_dword(dev
, E752X_DRAM_SEC2_ADD
,
700 &info
->dram_sec2_add
);
701 pci_read_config_word(dev
, E752X_DRAM_SEC2_SYNDROME
,
702 &info
->dram_sec2_syndrome
);
704 if (info
->hi_nerr
& 0x7f)
705 pci_write_config_byte(dev
, E752X_HI_NERR
,
708 if (info
->sysbus_nerr
)
709 pci_write_config_word(dev
, E752X_SYSBUS_NERR
,
712 if (info
->buf_nerr
& 0x0f)
713 pci_write_config_byte(dev
, E752X_BUF_NERR
,
717 pci_write_bits16(pvt
->bridge_ck
, E752X_DRAM_NERR
,
718 info
->dram_nerr
, info
->dram_nerr
);
720 pci_write_config_dword(dev
, E752X_NERR_GLOBAL
,
725 static int e752x_process_error_info (struct mem_ctl_info
*mci
,
726 struct e752x_error_info
*info
, int handle_errors
)
732 error32
= (info
->ferr_global
>> 18) & 0x3ff;
733 stat32
= (info
->ferr_global
>> 4) & 0x7ff;
736 global_error(1, error32
, &error_found
, handle_errors
);
739 global_error(0, stat32
, &error_found
, handle_errors
);
741 error32
= (info
->nerr_global
>> 18) & 0x3ff;
742 stat32
= (info
->nerr_global
>> 4) & 0x7ff;
745 global_error(1, error32
, &error_found
, handle_errors
);
748 global_error(0, stat32
, &error_found
, handle_errors
);
750 e752x_check_hub_interface(info
, &error_found
, handle_errors
);
751 e752x_check_sysbus(info
, &error_found
, handle_errors
);
752 e752x_check_membuf(info
, &error_found
, handle_errors
);
753 e752x_check_dram(mci
, info
, &error_found
, handle_errors
);
757 static void e752x_check(struct mem_ctl_info
*mci
)
759 struct e752x_error_info info
;
761 debugf3("%s()\n", __func__
);
762 e752x_get_error_info(mci
, &info
);
763 e752x_process_error_info(mci
, &info
, 1);
766 static int e752x_probe1(struct pci_dev
*pdev
, int dev_idx
)
772 struct mem_ctl_info
*mci
= NULL
;
773 struct e752x_pvt
*pvt
= NULL
;
776 int drc_chan
; /* Number of channels 0=1chan,1=2chan */
777 int drc_drbg
; /* DRB granularity 0=64mb, 1=128mb */
778 int drc_ddim
; /* DRAM Data Integrity Mode 0=none,2=edac */
780 unsigned long last_cumul_size
;
781 struct pci_dev
*dev
= NULL
;
782 struct e752x_error_info discard
;
784 debugf0("%s(): mci\n", __func__
);
785 debugf0("Starting Probe1\n");
787 /* check to see if device 0 function 1 is enabled; if it isn't, we
788 * assume the BIOS has reserved it for a reason and is expecting
789 * exclusive access, we take care not to violate that assumption and
791 pci_read_config_byte(pdev
, E752X_DEVPRES1
, &stat8
);
792 if (!force_function_unhide
&& !(stat8
& (1 << 5))) {
793 printk(KERN_INFO
"Contact your BIOS vendor to see if the "
794 "E752x error registers can be safely un-hidden\n");
798 pci_write_config_byte(pdev
, E752X_DEVPRES1
, stat8
);
800 /* need to find out the number of channels */
801 pci_read_config_dword(pdev
, E752X_DRC
, &drc
);
802 pci_read_config_word(pdev
, E752X_DDRCSR
, &ddrcsr
);
803 /* FIXME: should check >>12 or 0xf, true for all? */
804 /* Dual channel = 1, Single channel = 0 */
805 drc_chan
= (((ddrcsr
>> 12) & 3) == 3);
806 drc_drbg
= drc_chan
+ 1; /* 128 in dual mode, 64 in single */
807 drc_ddim
= (drc
>> 20) & 0x3;
809 mci
= edac_mc_alloc(sizeof(*pvt
), E752X_NR_CSROWS
, drc_chan
+ 1);
816 debugf3("%s(): init mci\n", __func__
);
817 mci
->mtype_cap
= MEM_FLAG_RDDR
;
818 mci
->edac_ctl_cap
= EDAC_FLAG_NONE
| EDAC_FLAG_SECDED
|
820 /* FIXME - what if different memory types are in different csrows? */
821 mci
->mod_name
= EDAC_MOD_STR
;
822 mci
->mod_ver
= "$Revision: 1.5.2.11 $";
825 debugf3("%s(): init pvt\n", __func__
);
826 pvt
= (struct e752x_pvt
*) mci
->pvt_info
;
827 pvt
->dev_info
= &e752x_devs
[dev_idx
];
828 pvt
->bridge_ck
= pci_get_device(PCI_VENDOR_ID_INTEL
,
829 pvt
->dev_info
->err_dev
,
832 if (pvt
->bridge_ck
== NULL
)
833 pvt
->bridge_ck
= pci_scan_single_device(pdev
->bus
,
836 if (pvt
->bridge_ck
== NULL
) {
837 e752x_printk(KERN_ERR
, "error reporting device not found:"
838 "vendor %x device 0x%x (broken BIOS?)\n",
839 PCI_VENDOR_ID_INTEL
, e752x_devs
[dev_idx
].err_dev
);
843 pvt
->mc_symmetric
= ((ddrcsr
& 0x10) != 0);
844 debugf3("%s(): more mci init\n", __func__
);
845 mci
->ctl_name
= pvt
->dev_info
->ctl_name
;
846 mci
->edac_check
= e752x_check
;
847 mci
->ctl_page_to_phys
= ctl_page_to_phys
;
849 /* find out the device types */
850 pci_read_config_dword(pdev
, E752X_DRA
, &dra
);
853 * The dram row boundary (DRB) reg values are boundary address for
854 * each DRAM row with a granularity of 64 or 128MB (single/dual
855 * channel operation). DRB regs are cumulative; therefore DRB7 will
856 * contain the total memory contained in all eight rows.
858 for (last_cumul_size
= index
= 0; index
< mci
->nr_csrows
; index
++) {
862 /* mem_dev 0=x8, 1=x4 */
863 int mem_dev
= (dra
>> (index
* 4 + 2)) & 0x3;
864 struct csrow_info
*csrow
= &mci
->csrows
[index
];
866 mem_dev
= (mem_dev
== 2);
867 pci_read_config_byte(mci
->pdev
, E752X_DRB
+ index
, &value
);
868 /* convert a 128 or 64 MiB DRB to a page size. */
869 cumul_size
= value
<< (25 + drc_drbg
- PAGE_SHIFT
);
870 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__
, index
,
873 if (cumul_size
== last_cumul_size
)
874 continue; /* not populated */
876 csrow
->first_page
= last_cumul_size
;
877 csrow
->last_page
= cumul_size
- 1;
878 csrow
->nr_pages
= cumul_size
- last_cumul_size
;
879 last_cumul_size
= cumul_size
;
880 csrow
->grain
= 1 << 12; /* 4KiB - resolution of CELOG */
881 csrow
->mtype
= MEM_RDDR
; /* only one type supported */
882 csrow
->dtype
= mem_dev
? DEV_X4
: DEV_X8
;
885 * if single channel or x8 devices then SECDED
886 * if dual channel and x4 then S4ECD4ED
889 if (drc_chan
&& mem_dev
) {
890 csrow
->edac_mode
= EDAC_S4ECD4ED
;
891 mci
->edac_cap
|= EDAC_FLAG_S4ECD4ED
;
893 csrow
->edac_mode
= EDAC_SECDED
;
894 mci
->edac_cap
|= EDAC_FLAG_SECDED
;
897 csrow
->edac_mode
= EDAC_NONE
;
900 /* Fill in the memory map table */
906 for (index
= 0; index
< 8; index
+= 2) {
907 pci_read_config_byte(mci
->pdev
, E752X_DRB
+ index
,
910 /* test if there is a dimm in this slot */
912 /* no dimm in the slot, so flag it as empty */
913 pvt
->map
[index
] = 0xff;
914 pvt
->map
[index
+ 1] = 0xff;
915 } else { /* there is a dimm in the slot */
916 pvt
->map
[index
] = row
;
919 /* test the next value to see if the dimm is
921 pci_read_config_byte(mci
->pdev
,
922 E752X_DRB
+ index
+ 1,
924 pvt
->map
[index
+ 1] = (value
== last
) ?
925 0xff : /* the dimm is single sided,
928 row
; /* this is a double sided dimm
929 * to save the next row #
937 /* set the map type. 1 = normal, 0 = reversed */
938 pci_read_config_byte(mci
->pdev
, E752X_DRM
, &stat8
);
939 pvt
->map_type
= ((stat8
& 0x0f) > ((stat8
>> 4) & 0x0f));
941 mci
->edac_cap
|= EDAC_FLAG_NONE
;
942 debugf3("%s(): tolm, remapbase, remaplimit\n", __func__
);
944 /* load the top of low memory, remap base, and remap limit vars */
945 pci_read_config_word(mci
->pdev
, E752X_TOLM
, &pci_data
);
946 pvt
->tolm
= ((u32
) pci_data
) << 4;
947 pci_read_config_word(mci
->pdev
, E752X_REMAPBASE
, &pci_data
);
948 pvt
->remapbase
= ((u32
) pci_data
) << 14;
949 pci_read_config_word(mci
->pdev
, E752X_REMAPLIMIT
, &pci_data
);
950 pvt
->remaplimit
= ((u32
) pci_data
) << 14;
951 e752x_printk(KERN_INFO
,
952 "tolm = %x, remapbase = %x, remaplimit = %x\n", pvt
->tolm
,
953 pvt
->remapbase
, pvt
->remaplimit
);
955 if (edac_mc_add_mc(mci
)) {
956 debugf3("%s(): failed edac_mc_add_mc()\n", __func__
);
960 dev
= pci_get_device(PCI_VENDOR_ID_INTEL
, e752x_devs
[dev_idx
].ctl_dev
,
963 /* find the error reporting device and clear errors */
964 dev
= pvt
->dev_d0f1
= pci_dev_get(pvt
->bridge_ck
);
965 /* Turn off error disable & SMI in case the BIOS turned it on */
966 pci_write_config_byte(dev
, E752X_HI_ERRMASK
, 0x00);
967 pci_write_config_byte(dev
, E752X_HI_SMICMD
, 0x00);
968 pci_write_config_word(dev
, E752X_SYSBUS_ERRMASK
, 0x00);
969 pci_write_config_word(dev
, E752X_SYSBUS_SMICMD
, 0x00);
970 pci_write_config_byte(dev
, E752X_BUF_ERRMASK
, 0x00);
971 pci_write_config_byte(dev
, E752X_BUF_SMICMD
, 0x00);
972 pci_write_config_byte(dev
, E752X_DRAM_ERRMASK
, 0x00);
973 pci_write_config_byte(dev
, E752X_DRAM_SMICMD
, 0x00);
975 e752x_get_error_info(mci
, &discard
); /* clear other MCH errors */
977 /* get this far and it's successful */
978 debugf3("%s(): success\n", __func__
);
984 pci_dev_put(pvt
->dev_d0f0
);
987 pci_dev_put(pvt
->dev_d0f1
);
990 pci_dev_put(pvt
->bridge_ck
);
998 /* returns count (>= 0), or negative on error */
999 static int __devinit
e752x_init_one(struct pci_dev
*pdev
,
1000 const struct pci_device_id
*ent
)
1002 debugf0("%s()\n", __func__
);
1004 /* wake up and enable device */
1005 if(pci_enable_device(pdev
) < 0)
1008 return e752x_probe1(pdev
, ent
->driver_data
);
1011 static void __devexit
e752x_remove_one(struct pci_dev
*pdev
)
1013 struct mem_ctl_info
*mci
;
1014 struct e752x_pvt
*pvt
;
1016 debugf0("%s()\n", __func__
);
1018 if ((mci
= edac_mc_del_mc(pdev
)) == NULL
)
1021 pvt
= (struct e752x_pvt
*) mci
->pvt_info
;
1022 pci_dev_put(pvt
->dev_d0f0
);
1023 pci_dev_put(pvt
->dev_d0f1
);
1024 pci_dev_put(pvt
->bridge_ck
);
1028 static const struct pci_device_id e752x_pci_tbl
[] __devinitdata
= {
1030 PCI_VEND_DEV(INTEL
, 7520_0
), PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
1034 PCI_VEND_DEV(INTEL
, 7525_0
), PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
1038 PCI_VEND_DEV(INTEL
, 7320_0
), PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
1043 } /* 0 terminated list. */
1046 MODULE_DEVICE_TABLE(pci
, e752x_pci_tbl
);
1048 static struct pci_driver e752x_driver
= {
1049 .name
= EDAC_MOD_STR
,
1050 .probe
= e752x_init_one
,
1051 .remove
= __devexit_p(e752x_remove_one
),
1052 .id_table
= e752x_pci_tbl
,
1055 static int __init
e752x_init(void)
1059 debugf3("%s()\n", __func__
);
1060 pci_rc
= pci_register_driver(&e752x_driver
);
1061 return (pci_rc
< 0) ? pci_rc
: 0;
1064 static void __exit
e752x_exit(void)
1066 debugf3("%s()\n", __func__
);
1067 pci_unregister_driver(&e752x_driver
);
1070 module_init(e752x_init
);
1071 module_exit(e752x_exit
);
1073 MODULE_LICENSE("GPL");
1074 MODULE_AUTHOR("Linux Networx (http://lnxi.com) Tom Zimmerman\n");
1075 MODULE_DESCRIPTION("MC support for Intel e752x memory controllers");
1077 module_param(force_function_unhide
, int, 0444);
1078 MODULE_PARM_DESC(force_function_unhide
, "if BIOS sets Dev0:Fun1 up as hidden:"
1079 " 1=force unhide and hope BIOS doesn't fight driver for Dev0:Fun1 access");