1 /* $Id: cmd64x.c,v 1.21 2000/01/30 23:23:16
3 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
4 * Note, this driver is not used at all on other systems because
5 * there the "BIOS" has done all of the following already.
6 * Due to massive hardware bugs, UltraDMA is only supported
7 * on the 646U2 and not on the 646U.
9 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
10 * Copyright (C) 1998 David S. Miller (davem@redhat.com)
11 * Copyright (C) 1999-2000 Andre Hedrick (andre@suse.com)
14 #include <linux/config.h>
15 #include <linux/types.h>
16 #include <linux/pci.h>
17 #include <linux/delay.h>
18 #include <linux/hdreg.h>
19 #include <linux/ide.h>
22 #include "ide_modes.h"
25 #define SPLIT_BYTE(B,H,L) ((H)=(B>>4), (L)=(B-((B>>4)<<4)))
31 #define cmdprintk(x...) printk(##x)
33 #define cmdprintk(x...)
37 * CMD64x specific registers definition.
41 #define CNTRL_DIS_RA0 0x40
42 #define CNTRL_DIS_RA1 0x80
43 #define CNTRL_ENA_2ND 0x08
51 #define ARTTIM23_DIS_RA2 0x04
52 #define ARTTIM23_DIS_RA3 0x08
63 #define UDIDETCR0 0x73
68 #define UDIDETCR1 0x7B
71 #undef DISPLAY_CMD64X_TIMINGS
73 #if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_PROC_FS)
74 #include <linux/stat.h>
75 #include <linux/proc_fs.h>
77 static int cmd64x_get_info(char *, char **, off_t
, int);
78 extern int (*cmd64x_display_info
)(char *, char **, off_t
, int); /* ide-proc.c */
79 extern char *ide_media_verbose(ide_drive_t
*);
80 static struct pci_dev
*bmide_dev
;
82 static int cmd64x_get_info (char *buffer
, char **addr
, off_t offset
, int count
)
85 u8 reg53
= 0, reg54
= 0, reg55
= 0, reg56
= 0; /* primary */
86 u8 reg57
= 0, reg58
= 0, reg5b
; /* secondary */
87 u8 reg72
= 0, reg73
= 0; /* primary */
88 u8 reg7a
= 0, reg7b
= 0; /* secondary */
89 u8 hi_byte
= 0, lo_byte
= 0;
91 switch(bmide_dev
->device
) {
92 case PCI_DEVICE_ID_CMD_648
:
93 p
+= sprintf(p
, "\n CMD648 Chipset.\n");
95 case PCI_DEVICE_ID_CMD_646
:
96 p
+= sprintf(p
, "\n CMD646 Chipset.\n");
98 case PCI_DEVICE_ID_CMD_643
:
99 p
+= sprintf(p
, "\n CMD643 Chipset.\n");
102 p
+= sprintf(p
, "\n CMD64? Chipse.\n");
105 (void) pci_read_config_byte(bmide_dev
, ARTTIM0
, ®53
);
106 (void) pci_read_config_byte(bmide_dev
, DRWTIM0
, ®54
);
107 (void) pci_read_config_byte(bmide_dev
, ARTTIM1
, ®55
);
108 (void) pci_read_config_byte(bmide_dev
, DRWTIM1
, ®56
);
109 (void) pci_read_config_byte(bmide_dev
, ARTTIM2
, ®57
);
110 (void) pci_read_config_byte(bmide_dev
, DRWTIM2
, ®58
);
111 (void) pci_read_config_byte(bmide_dev
, DRWTIM3
, ®5b
);
112 (void) pci_read_config_byte(bmide_dev
, BMIDESR0
, ®72
);
113 (void) pci_read_config_byte(bmide_dev
, UDIDETCR0
, ®73
);
114 (void) pci_read_config_byte(bmide_dev
, BMIDESR1
, ®7a
);
115 (void) pci_read_config_byte(bmide_dev
, UDIDETCR1
, ®7b
);
117 p
+= sprintf(p
, "--------------- Primary Channel ---------------- Secondary Channel -------------\n");
118 p
+= sprintf(p
, " %sabled %sabled\n",
119 (reg72
&0x80) ? "dis" : " en", (reg7a
&0x80) ? "dis" : " en");
120 p
+= sprintf(p
, "--------------- drive0 --------- drive1 -------- drive0 ---------- drive1 ------\n");
121 p
+= sprintf(p
, "DMA enabled: %s %s %s %s\n",
122 (reg72
&0x20) ? "yes" : "no ", (reg72
&0x40) ? "yes" : "no ", (reg7a
&0x20) ? "yes" : "no ", (reg7a
&0x40) ? "yes" : "no " );
123 p
+= sprintf(p
, "UDMA enabled: %s %s %s %s\n",
124 (reg73
&0x01) ? "yes" : "no ", (reg73
&0x02) ? "yes" : "no ", (reg7b
&0x01) ? "yes" : "no ", (reg7b
&0x02) ? "yes" : "no " );
125 p
+= sprintf(p
, "UDMA enabled: %s %s %s %s\n",
126 (reg73
&0x15) ? "4" : (reg73
&0x25) ? "3" : (reg73
&0x11) ? "2" : (reg73
&0x21) ? "1" : (reg73
&0x31) ? "0" : "X",
127 (reg73
&0x4A) ? "4" : (reg73
&0x8A) ? "3" : (reg73
&0x42) ? "2" : (reg73
&0x82) ? "1" : (reg73
&0xC2) ? "0" : "X",
128 (reg7b
&0x15) ? "4" : (reg7b
&0x25) ? "3" : (reg7b
&0x11) ? "2" : (reg7b
&0x21) ? "1" : (reg7b
&0x31) ? "0" : "X",
129 (reg7b
&0x4A) ? "4" : (reg7b
&0x8A) ? "3" : (reg7b
&0x42) ? "2" : (reg7b
&0x82) ? "1" : (reg7b
&0xC2) ? "0" : "X" );
130 p
+= sprintf(p
, "DMA enabled: %s %s %s %s\n",
131 (reg73
&0x10) ? "2" : (reg73
&0x20) ? "1" : (reg73
&0x30) ? "0" : "X",
132 (reg73
&0x40) ? "2" : (reg73
&0x80) ? "1" : (reg73
&0xC0) ? "0" : "X",
133 (reg7b
&0x10) ? "2" : (reg7b
&0x20) ? "1" : (reg7b
&0x30) ? "0" : "X",
134 (reg7b
&0x40) ? "2" : (reg7b
&0x80) ? "1" : (reg7b
&0xC0) ? "0" : "X" );
135 p
+= sprintf(p
, "PIO\n");
137 SPLIT_BYTE(reg53
, hi_byte
, lo_byte
);
138 p
+= sprintf(p
, "ARTTIM0 = 0x%02x, HI = 0x%02x, LOW = 0x%02x\n", reg53
, hi_byte
, lo_byte
);
139 SPLIT_BYTE(reg54
, hi_byte
, lo_byte
);
140 p
+= sprintf(p
, "DRWTIM0 = 0x%02x, HI = 0x%02x, LOW = 0x%02x\n", reg54
, hi_byte
, lo_byte
);
141 SPLIT_BYTE(reg55
, hi_byte
, lo_byte
);
142 p
+= sprintf(p
, "ARTTIM1 = 0x%02x, HI = 0x%02x, LOW = 0x%02x\n", reg55
, hi_byte
, lo_byte
);
143 SPLIT_BYTE(reg56
, hi_byte
, lo_byte
);
144 p
+= sprintf(p
, "DRWTIM1 = 0x%02x, HI = 0x%02x, LOW = 0x%02x\n", reg56
, hi_byte
, lo_byte
);
145 SPLIT_BYTE(reg57
, hi_byte
, lo_byte
);
146 p
+= sprintf(p
, "ARTTIM23 = 0x%02x, HI = 0x%02x, LOW = 0x%02x\n", reg57
, hi_byte
, lo_byte
);
147 SPLIT_BYTE(reg58
, hi_byte
, lo_byte
);
148 p
+= sprintf(p
, "DRWTIM2 = 0x%02x, HI = 0x%02x, LOW = 0x%02x\n", reg58
, hi_byte
, lo_byte
);
149 SPLIT_BYTE(reg5b
, hi_byte
, lo_byte
);
150 p
+= sprintf(p
, "DRWTIM3 = 0x%02x, HI = 0x%02x, LOW = 0x%02x\n", reg5b
, hi_byte
, lo_byte
);
151 SPLIT_BYTE(reg73
, hi_byte
, lo_byte
);
152 p
+= sprintf(p
, "UDIDETCR0 = 0x%02x, HI = 0x%02x, LOW = 0x%02x\n", reg73
, hi_byte
, lo_byte
);
153 SPLIT_BYTE(reg7b
, hi_byte
, lo_byte
);
154 p
+= sprintf(p
, "UDIDETCR1 = 0x%02x, HI = 0x%02x, LOW = 0x%02x\n", reg7b
, hi_byte
, lo_byte
);
156 return p
-buffer
; /* => must be less than 4k! */
158 #endif /* defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_PROC_FS) */
160 byte cmd64x_proc
= 0;
163 * Registers and masks for easy access by drive index:
166 static byte prefetch_regs
[4] = {CNTRL
, CNTRL
, ARTTIM23
, ARTTIM23
};
167 static byte prefetch_masks
[4] = {CNTRL_DIS_RA0
, CNTRL_DIS_RA1
, ARTTIM23_DIS_RA2
, ARTTIM23_DIS_RA3
};
171 * This routine writes the prepared setup/active/recovery counts
172 * for a drive into the cmd646 chipset registers to active them.
174 static void program_drive_counts (ide_drive_t
*drive
, int setup_count
, int active_count
, int recovery_count
)
177 ide_drive_t
*drives
= HWIF(drive
)->drives
;
179 static const byte setup_counts
[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
180 static const byte recovery_counts
[] =
181 {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
182 static const byte arttim_regs
[2][2] = {
183 { ARTTIM0
, ARTTIM1
},
184 { ARTTIM23
, ARTTIM23
}
186 static const byte drwtim_regs
[2][2] = {
187 { DRWTIM0
, DRWTIM1
},
190 int channel
= (int) HWIF(drive
)->channel
;
191 int slave
= (drives
!= drive
); /* Is this really the best way to determine this?? */
193 cmdprintk("program_drive_count parameters = s(%d),a(%d),r(%d),p(%d)\n", setup_count
,
194 active_count
, recovery_count
, drive
->present
);
196 * Set up address setup count registers.
197 * Primary interface has individual count/timing registers for
198 * each drive. Secondary interface has one common set of registers,
199 * for address setup so we merge these timings, using the slowest
203 drive
->drive_data
= setup_count
;
204 setup_count
= IDE_MAX(drives
[0].drive_data
, drives
[1].drive_data
);
205 cmdprintk("Secondary interface, setup_count = %d\n", setup_count
);
209 * Convert values to internal chipset representation
211 setup_count
= (setup_count
> 5) ? 0xc0 : (int) setup_counts
[setup_count
];
212 active_count
&= 0xf; /* Remember, max value is 16 */
213 recovery_count
= (int) recovery_counts
[recovery_count
];
215 cmdprintk("Final values = %d,%d,%d\n", setup_count
, active_count
, recovery_count
);
218 * Now that everything is ready, program the new timings
220 __save_flags (flags
);
223 * Program the address_setup clocks into ARTTIM reg,
224 * and then the active/recovery counts into the DRWTIM reg
226 (void) pci_read_config_byte(HWIF(drive
)->pci_dev
, arttim_regs
[channel
][slave
], &temp_b
);
227 (void) pci_write_config_byte(HWIF(drive
)->pci_dev
, arttim_regs
[channel
][slave
],
228 ((byte
) setup_count
) | (temp_b
& 0x3f));
229 (void) pci_write_config_byte(HWIF(drive
)->pci_dev
, drwtim_regs
[channel
][slave
],
230 (byte
) ((active_count
<< 4) | recovery_count
));
231 cmdprintk ("Write %x to %x\n", ((byte
) setup_count
) | (temp_b
& 0x3f), arttim_regs
[channel
][slave
]);
232 cmdprintk ("Write %x to %x\n", (byte
) ((active_count
<< 4) | recovery_count
), drwtim_regs
[channel
][slave
]);
233 __restore_flags(flags
);
237 * Attempts to set the interface PIO mode.
238 * The preferred method of selecting PIO modes (e.g. mode 4) is
239 * "echo 'piomode:4' > /proc/ide/hdx/settings". Special cases are
240 * 8: prefetch off, 9: prefetch on, 255: auto-select best mode.
241 * Called with 255 at boot time.
243 static void cmd64x_tuneproc (ide_drive_t
*drive
, byte mode_wanted
)
245 int setup_time
, active_time
, recovery_time
, clock_time
, pio_mode
, cycle_time
;
246 byte recovery_count2
, cycle_count
;
247 int setup_count
, active_count
, recovery_count
;
248 int bus_speed
= ide_system_bus_speed();
252 switch (mode_wanted
) {
253 case 8: /* set prefetch off */
254 case 9: /* set prefetch on */
256 /*set_prefetch_mode(index, mode_wanted);*/
257 cmdprintk("%s: %sabled cmd640 prefetch\n", drive
->name
, mode_wanted
? "en" : "dis");
261 mode_wanted
= ide_get_best_pio_mode (drive
, mode_wanted
, 5, &d
);
262 pio_mode
= d
.pio_mode
;
263 cycle_time
= d
.cycle_time
;
266 * I copied all this complicated stuff from cmd640.c and made a few minor changes.
267 * For now I am just going to pray that it is correct.
271 setup_time
= ide_pio_timings
[pio_mode
].setup_time
;
272 active_time
= ide_pio_timings
[pio_mode
].active_time
;
273 recovery_time
= cycle_time
- (setup_time
+ active_time
);
274 clock_time
= 1000 / bus_speed
;
275 cycle_count
= (cycle_time
+ clock_time
- 1) / clock_time
;
277 setup_count
= (setup_time
+ clock_time
- 1) / clock_time
;
279 active_count
= (active_time
+ clock_time
- 1) / clock_time
;
281 recovery_count
= (recovery_time
+ clock_time
- 1) / clock_time
;
282 recovery_count2
= cycle_count
- (setup_count
+ active_count
);
283 if (recovery_count2
> recovery_count
)
284 recovery_count
= recovery_count2
;
285 if (recovery_count
> 16) {
286 active_count
+= recovery_count
- 16;
289 if (active_count
> 16)
290 active_count
= 16; /* maximum allowed by cmd646 */
293 * In a perfect world, we might set the drive pio mode here
294 * (using WIN_SETFEATURE) before continuing.
296 * But we do not, because:
297 * 1) this is the wrong place to do it (proper is do_special() in ide.c)
298 * 2) in practice this is rarely, if ever, necessary
300 program_drive_counts (drive
, setup_count
, active_count
, recovery_count
);
302 cmdprintk("%s: selected cmd646 PIO mode%d : %d (%dns)%s, clocks=%d/%d/%d\n",
303 drive
->name
, pio_mode
, mode_wanted
, cycle_time
,
304 d
.overridden
? " (overriding vendor mode)" : "",
305 setup_count
, active_count
, recovery_count
);
308 static int tune_chipset_for_dma (ide_drive_t
*drive
, byte speed
)
311 struct hd_driveid
*id
= drive
->id
;
312 ide_hwif_t
*hwif
= HWIF(drive
);
313 struct pci_dev
*dev
= hwif
->pci_dev
;
314 unsigned long dma_base
= hwif
->dma_base
;
315 byte unit
= (drive
->select
.b
.unit
& 0x01);
317 u8 reg72
= 0, reg73
= 0; /* primary */
318 u8 reg7a
= 0, reg7b
= 0; /* secondary */
319 u8 pciU
= (hwif
->channel
) ? UDIDETCR1
: UDIDETCR0
;
320 u8 pciD
= (hwif
->channel
) ? BMIDESR1
: BMIDESR0
;
321 u8 regU
= (hwif
->channel
) ? 2 : 0;
322 u8 regD
= (hwif
->channel
) ? 2 : 0;
324 (void) pci_read_config_byte(dev
, BMIDESR0
, ®72
);
325 (void) pci_read_config_byte(dev
, UDIDETCR0
, ®73
);
326 (void) pci_read_config_byte(dev
, BMIDESR1
, ®7a
);
327 (void) pci_read_config_byte(dev
, UDIDETCR1
, ®7b
);
331 pciU
= unit
? 0x4A : 0x15;
333 pciU
= unit
? 0x8A : 0x25;
335 pciU
= unit
? 0x42 : 0x11;
337 pciU
= unit
? 0x82 : 0x21;
339 pciU
= unit
? 0xC2 : 0x31
340 (reg73
&0x15)?"4":(reg73
&0x25)?"3":(reg73
&0x11)?"2":(reg73
&0x21)?"1":(reg73
&0x31)?"0":"X",
341 (reg73
&0x4A)?"4":(reg73
&0x8A)?"3":(reg73
&0x42)?"2":(reg73
&0x82)?"1":(reg73
&0xC2)?"0":"X",
342 (reg7b
&0x15)?"4":(reg7b
&0x25)?"3":(reg7b
&0x11)?"2":(reg7b
&0x21)?"1":(reg7b
&0x31)?"0":"X",
343 (reg7b
&0x4A)?"4":(reg7b
&0x8A)?"3":(reg7b
&0x42)?"2":(reg7b
&0x82)?"1":(reg7b
&0xC2)?"0":"X",
346 pciD
= unit
? 0x40 : 0x10;
348 pciD
= unit
? 0x80 : 0x20;
350 pciD
= unit
? 0xC0 : 0x30;
354 (reg73
&0x10)?"2":(reg73
&0x20)?"1":(reg73
&0x30)?"0":"X",
355 (reg73
&0x40)?"2":(reg73
&0x80)?"1":(reg73
&0xC0)?"0":"X",
356 (reg7b
&0x10)?"2":(reg7b
&0x20)?"1":(reg7b
&0x30)?"0":"X",
357 (reg7b
&0x40)?"2":(reg7b
&0x80)?"1":(reg7b
&0xC0)?"0":"X" );
363 (void) ide_config_drive_speed(drive
, speed
);
364 outb(inb(dma_base
+2)|(1<<(5+unit
)), dma_base
+2);
369 static void config_chipset_for_pio (ide_drive_t
*drive
, byte set_speed
)
372 byte set_pio
= ide_get_best_pio_mode(drive
, 4, 5, NULL
);
374 cmd64x_tuneproc(drive
, set_pio
);
375 speed
= XFER_PIO_0
+ set_pio
;
377 (void) ide_config_drive_speed(drive
, speed
);
380 static int config_chipset_for_dma (ide_drive_t
*drive
, unsigned int rev
, byte ultra_66
)
382 struct hd_driveid
*id
= drive
->id
;
383 ide_hwif_t
*hwif
= HWIF(drive
);
384 struct pci_dev
*dev
= hwif
->pci_dev
;
385 unsigned long dma_base
= hwif
->dma_base
;
387 byte unit
= (drive
->select
.b
.unit
& 0x01);
390 byte udma_timing_bits
= 0x00;
391 byte udma_33
= ((rev
>= 0x05) || (ultra_66
)) ? 1 : 0;
392 byte udma_66
= ((id
->hw_config
& 0x2000) && (hwif
->udma_four
)) ? 1 : 0;
393 /* int drive_number = ((hwif->channel ? 2 : 0) + unit); */
396 switch(dev
->device
) {
397 case PCI_DEVICE_ID_CMD_643
:
398 case PCI_DEVICE_ID_CMD_646
:
399 case PCI_DEVICE_ID_CMD_648
:
404 if (drive
->media
!= ide_disk
) {
405 cmdprintk("CMD64X: drive->media != ide_disk at double check, inital check failed!!\n");
406 return ((int) ide_dma_off
);
409 /* UltraDMA only supported on PCI646U and PCI646U2,
410 * which correspond to revisions 0x03, 0x05 and 0x07 respectively.
411 * Actually, although the CMD tech support people won't
412 * tell me the details, the 0x03 revision cannot support
413 * UDMA correctly without hardware modifications, and even
414 * then it only works with Quantum disks due to some
415 * hold time assumptions in the 646U part which are fixed
417 * So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
420 if ((id
->dma_ultra
& 0x0010) && (udma_66
) && (udma_33
)) {
422 udma_timing_bits
= 0x10; /* 2 clock */
423 } else if ((id
->dma_ultra
& 0x0008) && (udma_66
) && (udma_33
)) {
425 udma_timing_bits
= 0x20; /* 3 clock */
426 } else if ((id
->dma_ultra
& 0x0004) && (udma_33
)) {
428 udma_timing_bits
= 0x10; /* 2 clock */
429 } else if ((id
->dma_ultra
& 0x0002) && (udma_33
)) {
431 udma_timing_bits
= 0x20; /* 3 clock */
432 } else if ((id
->dma_ultra
& 0x0001) && (udma_33
)) {
434 udma_timing_bits
= 0x30; /* 4 clock */
435 } else if (id
->dma_mword
& 0x0004) {
436 speed
= XFER_MW_DMA_2
;
437 } else if (id
->dma_mword
& 0x0002) {
438 speed
= XFER_MW_DMA_1
;
439 } else if (id
->dma_mword
& 0x0001) {
440 speed
= XFER_MW_DMA_0
;
441 } else if (id
->dma_1word
& 0x0004) {
442 speed
= XFER_SW_DMA_2
;
443 } else if (id
->dma_1word
& 0x0002) {
444 speed
= XFER_SW_DMA_1
;
445 } else if (id
->dma_1word
& 0x0001) {
446 speed
= XFER_SW_DMA_0
;
451 config_chipset_for_pio(drive
, set_pio
);
454 return ((int) ide_dma_off_quietly
);
458 * This the alternate access method. :-(
459 * The correct method is to directly setup the pci-config space.
461 (void) ide_config_drive_speed(drive
, speed
);
462 outb(inb(dma_base
+2)|(1<<(5+unit
)), dma_base
+2);
464 if (speed
>= XFER_UDMA_0
) {
465 byte udma_ctrl
= inb(dma_base
+ 3);
466 /* Put this channel into UDMA mode. */
467 udma_ctrl
|= (1 << unit
);
468 udma_ctrl
&= ~(0x04 << unit
);
470 udma_ctrl
|= (0x04 << unit
);
471 udma_ctrl
&= ~(0x30 << (unit
* 2));
472 udma_ctrl
|= (udma_timing_bits
<< (unit
* 2));
473 outb(udma_ctrl
, dma_base
+3);
477 if (tune_chipset_for_dma(drive
, speed
))
478 return ((int) ide_dma_off
);
480 rval
= (int)( ((id
->dma_ultra
>> 11) & 3) ? ide_dma_on
:
481 ((id
->dma_ultra
>> 8) & 7) ? ide_dma_on
:
482 ((id
->dma_mword
>> 8) & 7) ? ide_dma_on
:
483 ((id
->dma_1word
>> 8) & 7) ? ide_dma_on
:
484 ide_dma_off_quietly
);
489 static int cmd64x_config_drive_for_dma (ide_drive_t
*drive
)
491 struct hd_driveid
*id
= drive
->id
;
492 ide_hwif_t
*hwif
= HWIF(drive
);
493 struct pci_dev
*dev
= hwif
->pci_dev
;
494 unsigned int class_rev
= 0;
495 byte can_ultra_33
= 0;
496 byte can_ultra_66
= 0;
497 ide_dma_action_t dma_func
= ide_dma_on
;
499 pci_read_config_dword(dev
, PCI_CLASS_REVISION
, &class_rev
);
502 switch(dev
->device
) {
503 case PCI_DEVICE_ID_CMD_643
:
507 case PCI_DEVICE_ID_CMD_646
:
508 can_ultra_33
= (class_rev
>= 0x05) ? 1 : 0;
511 case PCI_DEVICE_ID_CMD_648
:
516 return hwif
->dmaproc(ide_dma_off
, drive
);
519 if ((id
!= NULL
) && ((id
->capability
& 1) != 0) &&
520 hwif
->autodma
&& (drive
->media
== ide_disk
)) {
521 /* Consult the list of known "bad" drives */
522 if (ide_dmaproc(ide_dma_bad_drive
, drive
)) {
523 dma_func
= ide_dma_off
;
526 dma_func
= ide_dma_off_quietly
;
527 if ((id
->field_valid
& 4) && (can_ultra_33
)) {
528 if (id
->dma_ultra
& 0x001F) {
529 /* Force if Capable UltraDMA */
530 dma_func
= config_chipset_for_dma(drive
, class_rev
, can_ultra_66
);
531 if ((id
->field_valid
& 2) &&
532 (dma_func
!= ide_dma_on
))
535 } else if (id
->field_valid
& 2) {
537 if ((id
->dma_mword
& 0x0007) ||
538 (id
->dma_1word
& 0x0007)) {
539 /* Force if Capable regular DMA modes */
540 dma_func
= config_chipset_for_dma(drive
, class_rev
, 0);
541 if (dma_func
!= ide_dma_on
)
544 } else if (ide_dmaproc(ide_dma_good_drive
, drive
)) {
545 if (id
->eide_dma_time
> 150) {
548 /* Consult the list of known "good" drives */
549 dma_func
= config_chipset_for_dma(drive
, class_rev
, 0);
550 if (dma_func
!= ide_dma_on
)
555 } else if ((id
->capability
& 8) || (id
->field_valid
& 2)) {
557 dma_func
= ide_dma_off_quietly
;
559 config_chipset_for_pio(drive
, 1);
561 return HWIF(drive
)->dmaproc(dma_func
, drive
);
564 static int cmd64x_dmaproc (ide_dma_action_t func
, ide_drive_t
*drive
)
568 return cmd64x_config_drive_for_dma(drive
);
572 /* Other cases are done by generic IDE-DMA code. */
573 return ide_dmaproc(func
, drive
);
577 * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old
578 * event order for DMA transfers.
580 static int cmd646_1_dmaproc (ide_dma_action_t func
, ide_drive_t
*drive
)
582 ide_hwif_t
*hwif
= HWIF(drive
);
583 unsigned long dma_base
= hwif
->dma_base
;
586 if (func
== ide_dma_end
) {
587 drive
->waiting_for_dma
= 0;
588 dma_stat
= inb(dma_base
+2); /* get DMA status */
589 outb(inb(dma_base
)&~1, dma_base
); /* stop DMA */
590 outb(dma_stat
|6, dma_base
+2); /* clear the INTR & ERROR bits */
591 ide_destroy_dmatable(drive
); /* and free any DMA resources */
592 return (dma_stat
& 7) != 4; /* verify good DMA status */
595 /* Other cases are done by generic IDE-DMA code. */
596 return cmd64x_dmaproc(func
, drive
);
599 unsigned int __init
pci_init_cmd64x (struct pci_dev
*dev
, const char *name
)
601 unsigned char mrdmode
;
602 unsigned int class_rev
;
604 pci_read_config_dword(dev
, PCI_CLASS_REVISION
, &class_rev
);
608 if (dev
->resource
[PCI_ROM_RESOURCE
].start
)
609 pci_write_config_byte(dev
, PCI_ROM_ADDRESS
, dev
->resource
[PCI_ROM_RESOURCE
].start
| PCI_ROM_ADDRESS_ENABLE
);
612 switch(dev
->device
) {
613 case PCI_DEVICE_ID_CMD_643
:
615 case PCI_DEVICE_ID_CMD_646
:
616 printk("%s: chipset revision 0x%02X, ", name
, class_rev
);
620 printk("UltraDMA Capable");
623 printk("MultiWord DMA Force Limited");
627 printk("MultiWord DMA Limited, IRQ workaround enabled");
632 case PCI_DEVICE_ID_CMD_648
:
638 /* Set a good latency timer and cache line size value. */
639 (void) pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, 64);
641 (void) pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, 0x10);
644 /* Setup interrupts. */
645 (void) pci_read_config_byte(dev
, MRDMODE
, &mrdmode
);
647 (void) pci_write_config_byte(dev
, MRDMODE
, mrdmode
);
649 /* Use MEMORY READ LINE for reads.
650 * NOTE: Although not mentioned in the PCI0646U specs,
651 * these bits are write only and won't be read
652 * back as set or not. The PCI0646U2 specs clarify
655 (void) pci_write_config_byte(dev
, MRDMODE
, mrdmode
| 0x02);
657 /* Set reasonable active/recovery/address-setup values. */
658 (void) pci_write_config_byte(dev
, ARTTIM0
, 0x40);
659 (void) pci_write_config_byte(dev
, DRWTIM0
, 0x3f);
660 (void) pci_write_config_byte(dev
, ARTTIM1
, 0x40);
661 (void) pci_write_config_byte(dev
, DRWTIM1
, 0x3f);
663 (void) pci_write_config_byte(dev
, ARTTIM23
, 0x1c);
665 (void) pci_write_config_byte(dev
, ARTTIM23
, 0x5c);
667 (void) pci_write_config_byte(dev
, DRWTIM23
, 0x3f);
668 (void) pci_write_config_byte(dev
, DRWTIM3
, 0x3f);
670 #if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_PROC_FS)
673 cmd64x_display_info
= &cmd64x_get_info
;
674 #endif /* DISPLAY_CMD64X_TIMINGS && CONFIG_PROC_FS */
679 unsigned int __init
ata66_cmd64x (ide_hwif_t
*hwif
)
682 byte mask
= (hwif
->channel
) ? 0x02 : 0x01;
684 pci_read_config_byte(hwif
->pci_dev
, BMIDECSR
, &ata66
);
685 return (ata66
& mask
) ? 1 : 0;
688 void __init
ide_init_cmd64x (ide_hwif_t
*hwif
)
690 struct pci_dev
*dev
= hwif
->pci_dev
;
691 unsigned int class_rev
;
693 pci_read_config_dword(dev
, PCI_CLASS_REVISION
, &class_rev
);
696 hwif
->tuneproc
= &cmd64x_tuneproc
;
697 hwif
->drives
[0].autotune
= 1;
698 hwif
->drives
[0].autotune
= 1;
703 switch(dev
->device
) {
704 case PCI_DEVICE_ID_CMD_643
:
705 hwif
->dmaproc
= &cmd64x_dmaproc
;
707 case PCI_DEVICE_ID_CMD_646
:
708 hwif
->chipset
= ide_cmd646
;
709 if (class_rev
== 0x01) {
710 hwif
->dmaproc
= &cmd646_1_dmaproc
;
712 hwif
->dmaproc
= &cmd64x_dmaproc
;
715 case PCI_DEVICE_ID_CMD_648
:
716 hwif
->dmaproc
= &cmd64x_dmaproc
;