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Merge with Linux 2.4.0-test6-pre9.
[linux-2.6/linux-mips.git] / drivers / isdn / hisax / netjet.c
blobfd51217bf9d33181c232dbb705941645e263e2bf
1 /* $Id: netjet.c,v 1.20 2000/06/26 08:59:14 keil Exp $
2 *
3 * netjet.c low level stuff for Traverse Technologie NETJet ISDN cards
4 *
5 * Author Karsten Keil (keil@isdn4linux.de)
6 *
7 * Thanks to Traverse Technologie Australia for documents and informations
8 *
9 * This file is (c) under GNU PUBLIC LICENSE
10 *
11 */
12
13 #define __NO_VERSION__
14 #include <linux/config.h>
15 #include "hisax.h"
16 #include "isac.h"
17 #include "hscx.h"
18 #include "isdnl1.h"
19 #include <linux/pci.h>
20 #include <linux/interrupt.h>
21 #include <linux/ppp_defs.h>
22
23 #ifndef bus_to_virt
24 #define bus_to_virt (u_int *)
25 #endif
26
27 #ifndef virt_to_bus
28 #define virt_to_bus (u_int)
29 #endif
30
31 extern const char *CardType[];
32
33 const char *NETjet_revision = "$Revision: 1.18 $";
34
35 #define byteout(addr,val) outb(val,addr)
36 #define bytein(addr) inb(addr)
37
38 /* PCI stuff */
39 #define PCI_VENDOR_TRAVERSE_TECH 0xe159
40 #define PCI_NETJET_ID 0x0001
41
42 #define NETJET_CTRL 0x00
43 #define NETJET_DMACTRL 0x01
44 #define NETJET_AUXCTRL 0x02
45 #define NETJET_AUXDATA 0x03
46 #define NETJET_IRQMASK0 0x04
47 #define NETJET_IRQMASK1 0x05
48 #define NETJET_IRQSTAT0 0x06
49 #define NETJET_IRQSTAT1 0x07
50 #define NETJET_DMA_READ_START 0x08
51 #define NETJET_DMA_READ_IRQ 0x0c
52 #define NETJET_DMA_READ_END 0x10
53 #define NETJET_DMA_READ_ADR 0x14
54 #define NETJET_DMA_WRITE_START 0x18
55 #define NETJET_DMA_WRITE_IRQ 0x1c
56 #define NETJET_DMA_WRITE_END 0x20
57 #define NETJET_DMA_WRITE_ADR 0x24
58 #define NETJET_PULSE_CNT 0x28
59
60 #define NETJET_ISAC_OFF 0xc0
61 #define NETJET_ISACIRQ 0x10
62 #define NETJET_IRQM0_READ 0x0c
63 #define NETJET_IRQM0_READ_1 0x04
64 #define NETJET_IRQM0_READ_2 0x08
65 #define NETJET_IRQM0_WRITE 0x03
66 #define NETJET_IRQM0_WRITE_1 0x01
67 #define NETJET_IRQM0_WRITE_2 0x02
68
69 #define NETJET_DMA_TXSIZE 512
70 #define NETJET_DMA_RXSIZE 128
71
72 #define HDLC_ZERO_SEARCH 0
73 #define HDLC_FLAG_SEARCH 1
74 #define HDLC_FLAG_FOUND 2
75 #define HDLC_FRAME_FOUND 3
76 #define HDLC_NULL 4
77 #define HDLC_PART 5
78 #define HDLC_FULL 6
79
80 #define HDLC_FLAG_VALUE 0x7e
81
82 /* Interface functions */
83
84 static u_char
85 ReadISAC(struct IsdnCardState *cs, u_char offset)
86 {
87 long flags;
88 u_char ret;
89
90 save_flags(flags);
91 cli();
92 cs->hw.njet.auxd &= 0xfc;
93 cs->hw.njet.auxd |= (offset>>4) & 3;
94 byteout(cs->hw.njet.auxa, cs->hw.njet.auxd);
95 ret = bytein(cs->hw.njet.isac + ((offset & 0xf)<<2));
96 restore_flags(flags);
97 return(ret);
98 }
99
100 static void
101 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value)
102 {
103 long flags;
104
105 save_flags(flags);
106 cli();
107 cs->hw.njet.auxd &= 0xfc;
108 cs->hw.njet.auxd |= (offset>>4) & 3;
109 byteout(cs->hw.njet.auxa, cs->hw.njet.auxd);
110 byteout(cs->hw.njet.isac + ((offset & 0xf)<<2), value);
111 restore_flags(flags);
112 }
113
114 static void
115 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size)
116 {
117 cs->hw.njet.auxd &= 0xfc;
118 byteout(cs->hw.njet.auxa, cs->hw.njet.auxd);
119 insb(cs->hw.njet.isac, data, size);
120 }
121
122 __u16 fcstab[256] =
123 {
124 0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf,
125 0x8c48, 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7,
126 0x1081, 0x0108, 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e,
127 0x9cc9, 0x8d40, 0xbfdb, 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876,
128 0x2102, 0x308b, 0x0210, 0x1399, 0x6726, 0x76af, 0x4434, 0x55bd,
129 0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 0xfae7, 0xc87c, 0xd9f5,
130 0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 0x54b5, 0x453c,
131 0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 0xc974,
132 0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb,
133 0xce4c, 0xdfc5, 0xed5e, 0xfcd7, 0x8868, 0x99e1, 0xab7a, 0xbaf3,
134 0x5285, 0x430c, 0x7197, 0x601e, 0x14a1, 0x0528, 0x37b3, 0x263a,
135 0xdecd, 0xcf44, 0xfddf, 0xec56, 0x98e9, 0x8960, 0xbbfb, 0xaa72,
136 0x6306, 0x728f, 0x4014, 0x519d, 0x2522, 0x34ab, 0x0630, 0x17b9,
137 0xef4e, 0xfec7, 0xcc5c, 0xddd5, 0xa96a, 0xb8e3, 0x8a78, 0x9bf1,
138 0x7387, 0x620e, 0x5095, 0x411c, 0x35a3, 0x242a, 0x16b1, 0x0738,
139 0xffcf, 0xee46, 0xdcdd, 0xcd54, 0xb9eb, 0xa862, 0x9af9, 0x8b70,
140 0x8408, 0x9581, 0xa71a, 0xb693, 0xc22c, 0xd3a5, 0xe13e, 0xf0b7,
141 0x0840, 0x19c9, 0x2b52, 0x3adb, 0x4e64, 0x5fed, 0x6d76, 0x7cff,
142 0x9489, 0x8500, 0xb79b, 0xa612, 0xd2ad, 0xc324, 0xf1bf, 0xe036,
143 0x18c1, 0x0948, 0x3bd3, 0x2a5a, 0x5ee5, 0x4f6c, 0x7df7, 0x6c7e,
144 0xa50a, 0xb483, 0x8618, 0x9791, 0xe32e, 0xf2a7, 0xc03c, 0xd1b5,
145 0x2942, 0x38cb, 0x0a50, 0x1bd9, 0x6f66, 0x7eef, 0x4c74, 0x5dfd,
146 0xb58b, 0xa402, 0x9699, 0x8710, 0xf3af, 0xe226, 0xd0bd, 0xc134,
147 0x39c3, 0x284a, 0x1ad1, 0x0b58, 0x7fe7, 0x6e6e, 0x5cf5, 0x4d7c,
148 0xc60c, 0xd785, 0xe51e, 0xf497, 0x8028, 0x91a1, 0xa33a, 0xb2b3,
149 0x4a44, 0x5bcd, 0x6956, 0x78df, 0x0c60, 0x1de9, 0x2f72, 0x3efb,
150 0xd68d, 0xc704, 0xf59f, 0xe416, 0x90a9, 0x8120, 0xb3bb, 0xa232,
151 0x5ac5, 0x4b4c, 0x79d7, 0x685e, 0x1ce1, 0x0d68, 0x3ff3, 0x2e7a,
152 0xe70e, 0xf687, 0xc41c, 0xd595, 0xa12a, 0xb0a3, 0x8238, 0x93b1,
153 0x6b46, 0x7acf, 0x4854, 0x59dd, 0x2d62, 0x3ceb, 0x0e70, 0x1ff9,
154 0xf78f, 0xe606, 0xd49d, 0xc514, 0xb1ab, 0xa022, 0x92b9, 0x8330,
155 0x7bc7, 0x6a4e, 0x58d5, 0x495c, 0x3de3, 0x2c6a, 0x1ef1, 0x0f78
156 };
157
158 static void
159 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size)
160 {
161 cs->hw.njet.auxd &= 0xfc;
162 byteout(cs->hw.njet.auxa, cs->hw.njet.auxd);
163 outsb(cs->hw.njet.isac, data, size);
164 }
165
166 void fill_mem(struct BCState *bcs, u_int *pos, u_int cnt, int chan, u_char fill)
167 {
168 u_int mask=0x000000ff, val = 0, *p=pos;
169 u_int i;
170
171 val |= fill;
172 if (chan) {
173 val <<= 8;
174 mask <<= 8;
175 }
176 mask ^= 0xffffffff;
177 for (i=0; i<cnt; i++) {
178 *p &= mask;
179 *p++ |= val;
180 if (p > bcs->hw.tiger.s_end)
181 p = bcs->hw.tiger.send;
182 }
183 }
184
185 void
186 mode_tiger(struct BCState *bcs, int mode, int bc)
187 {
188 struct IsdnCardState *cs = bcs->cs;
189
190 if (cs->debug & L1_DEB_HSCX)
191 debugl1(cs, "Tiger mode %d bchan %d/%d",
192 mode, bc, bcs->channel);
193 bcs->mode = mode;
194 bcs->channel = bc;
195 switch (mode) {
196 case (L1_MODE_NULL):
197 fill_mem(bcs, bcs->hw.tiger.send,
198 NETJET_DMA_TXSIZE, bc, 0xff);
199 if (cs->debug & L1_DEB_HSCX)
200 debugl1(cs, "Tiger stat rec %d/%d send %d",
201 bcs->hw.tiger.r_tot, bcs->hw.tiger.r_err,
202 bcs->hw.tiger.s_tot);
203 if ((cs->bcs[0].mode == L1_MODE_NULL) &&
204 (cs->bcs[1].mode == L1_MODE_NULL)) {
205 cs->hw.njet.dmactrl = 0;
206 byteout(cs->hw.njet.base + NETJET_DMACTRL,
207 cs->hw.njet.dmactrl);
208 byteout(cs->hw.njet.base + NETJET_IRQMASK0, 0);
209 }
210 break;
211 case (L1_MODE_TRANS):
212 break;
213 case (L1_MODE_HDLC):
214 fill_mem(bcs, bcs->hw.tiger.send,
215 NETJET_DMA_TXSIZE, bc, 0xff);
216 bcs->hw.tiger.r_state = HDLC_ZERO_SEARCH;
217 bcs->hw.tiger.r_tot = 0;
218 bcs->hw.tiger.r_bitcnt = 0;
219 bcs->hw.tiger.r_one = 0;
220 bcs->hw.tiger.r_err = 0;
221 bcs->hw.tiger.s_tot = 0;
222 if (! cs->hw.njet.dmactrl) {
223 fill_mem(bcs, bcs->hw.tiger.send,
224 NETJET_DMA_TXSIZE, !bc, 0xff);
225 cs->hw.njet.dmactrl = 1;
226 byteout(cs->hw.njet.base + NETJET_DMACTRL,
227 cs->hw.njet.dmactrl);
228 byteout(cs->hw.njet.base + NETJET_IRQMASK0, 0x3f);
229 }
230 bcs->hw.tiger.sendp = bcs->hw.tiger.send;
231 bcs->hw.tiger.free = NETJET_DMA_TXSIZE;
232 test_and_set_bit(BC_FLG_EMPTY, &bcs->Flag);
233 break;
234 }
235 if (cs->debug & L1_DEB_HSCX)
236 debugl1(cs, "tiger: set %x %x %x %x/%x pulse=%d",
237 bytein(cs->hw.njet.base + NETJET_DMACTRL),
238 bytein(cs->hw.njet.base + NETJET_IRQMASK0),
239 bytein(cs->hw.njet.base + NETJET_IRQSTAT0),
240 inl(cs->hw.njet.base + NETJET_DMA_READ_ADR),
241 inl(cs->hw.njet.base + NETJET_DMA_WRITE_ADR),
242 bytein(cs->hw.njet.base + NETJET_PULSE_CNT));
243 }
244
245 static u_char dummyrr(struct IsdnCardState *cs, int chan, u_char off)
246 {
247 return(5);
248 }
249
250 static void dummywr(struct IsdnCardState *cs, int chan, u_char off, u_char value)
251 {
252 }
253
254 static void printframe(struct IsdnCardState *cs, u_char *buf, int count, char *s) {
255 char tmp[128];
256 char *t = tmp;
257 int i=count,j;
258 u_char *p = buf;
259
260 t += sprintf(t, "tiger %s(%4d)", s, count);
261 while (i>0) {
262 if (i>16)
263 j=16;
264 else
265 j=i;
266 QuickHex(t, p, j);
267 debugl1(cs, tmp);
268 p += j;
269 i -= j;
270 t = tmp;
271 t += sprintf(t, "tiger %s ", s);
272 }
273 }
274
275 #define MAKE_RAW_BYTE for (j=0; j<8; j++) { \
276 bitcnt++;\
277 s_val >>= 1;\
278 if (val & 1) {\
279 s_one++;\
280 s_val |= 0x80;\
281 } else {\
282 s_one = 0;\
283 s_val &= 0x7f;\
284 }\
285 if (bitcnt==8) {\
286 bcs->hw.tiger.sendbuf[s_cnt++] = s_val;\
287 bitcnt = 0;\
288 }\
289 if (s_one == 5) {\
290 s_val >>= 1;\
291 s_val &= 0x7f;\
292 bitcnt++;\
293 s_one = 0;\
294 }\
295 if (bitcnt==8) {\
296 bcs->hw.tiger.sendbuf[s_cnt++] = s_val;\
297 bitcnt = 0;\
298 }\
299 val >>= 1;\
300 }
301
302 static int make_raw_data(struct BCState *bcs) {
303 register u_int i,s_cnt=0;
304 register u_char j;
305 register u_char val;
306 register u_char s_one = 0;
307 register u_char s_val = 0;
308 register u_char bitcnt = 0;
309 u_int fcs;
310
311 if (!bcs->tx_skb) {
312 debugl1(bcs->cs, "tiger make_raw: NULL skb");
313 return(1);
314 }
315 bcs->hw.tiger.sendbuf[s_cnt++] = HDLC_FLAG_VALUE;
316 fcs = PPP_INITFCS;
317 for (i=0; i<bcs->tx_skb->len; i++) {
318 val = bcs->tx_skb->data[i];
319 fcs = PPP_FCS (fcs, val);
320 MAKE_RAW_BYTE;
321 }
322 fcs ^= 0xffff;
323 val = fcs & 0xff;
324 MAKE_RAW_BYTE;
325 val = (fcs>>8) & 0xff;
326 MAKE_RAW_BYTE;
327 val = HDLC_FLAG_VALUE;
328 for (j=0; j<8; j++) {
329 bitcnt++;
330 s_val >>= 1;
331 if (val & 1)
332 s_val |= 0x80;
333 else
334 s_val &= 0x7f;
335 if (bitcnt==8) {
336 bcs->hw.tiger.sendbuf[s_cnt++] = s_val;
337 bitcnt = 0;
338 }
339 val >>= 1;
340 }
341 if (bcs->cs->debug & L1_DEB_HSCX)
342 debugl1(bcs->cs,"tiger make_raw: in %ld out %d.%d",
343 bcs->tx_skb->len, s_cnt, bitcnt);
344 if (bitcnt) {
345 while (8>bitcnt++) {
346 s_val >>= 1;
347 s_val |= 0x80;
348 }
349 bcs->hw.tiger.sendbuf[s_cnt++] = s_val;
350 bcs->hw.tiger.sendbuf[s_cnt++] = 0xff; // NJ<->NJ thoughput bug fix
351 }
352 bcs->hw.tiger.sendcnt = s_cnt;
353 bcs->tx_cnt -= bcs->tx_skb->len;
354 bcs->hw.tiger.sp = bcs->hw.tiger.sendbuf;
355 return(0);
356 }
357
358 static void got_frame(struct BCState *bcs, int count) {
359 struct sk_buff *skb;
360
361 if (!(skb = dev_alloc_skb(count)))
362 printk(KERN_WARNING "TIGER: receive out of memory\n");
363 else {
364 memcpy(skb_put(skb, count), bcs->hw.tiger.rcvbuf, count);
365 skb_queue_tail(&bcs->rqueue, skb);
366 }
367 bcs->event |= 1 << B_RCVBUFREADY;
368 queue_task(&bcs->tqueue, &tq_immediate);
369 mark_bh(IMMEDIATE_BH);
370
371 if (bcs->cs->debug & L1_DEB_RECEIVE_FRAME)
372 printframe(bcs->cs, bcs->hw.tiger.rcvbuf, count, "rec");
373 }
374
375
376
377 static void read_raw(struct BCState *bcs, u_int *buf, int cnt){
378 int i;
379 register u_char j;
380 register u_char val;
381 u_int *pend = bcs->hw.tiger.rec +NETJET_DMA_RXSIZE -1;
382 register u_char state = bcs->hw.tiger.r_state;
383 register u_char r_one = bcs->hw.tiger.r_one;
384 register u_char r_val = bcs->hw.tiger.r_val;
385 register u_int bitcnt = bcs->hw.tiger.r_bitcnt;
386 u_int *p = buf;
387
388 for (i=0;i<cnt;i++) {
389 val = bcs->channel ? ((*p>>8) & 0xff) : (*p & 0xff);
390 p++;
391 if (p > pend)
392 p = bcs->hw.tiger.rec;
393 if (val == 0xff) {
394 state = HDLC_ZERO_SEARCH;
395 bcs->hw.tiger.r_tot++;
396 bitcnt = 0;
397 r_one = 0;
398 continue;
399 }
400 for (j=0;j<8;j++) {
401 if (state == HDLC_ZERO_SEARCH) {
402 if (val & 1) {
403 r_one++;
404 } else {
405 r_one=0;
406 state= HDLC_FLAG_SEARCH;
407 if (bcs->cs->debug & L1_DEB_HSCX)
408 debugl1(bcs->cs,"tiger read_raw: zBit(%d,%d,%d) %x",
409 bcs->hw.tiger.r_tot,i,j,val);
410 }
411 } else if (state == HDLC_FLAG_SEARCH) {
412 if (val & 1) {
413 r_one++;
414 if (r_one>6) {
415 state=HDLC_ZERO_SEARCH;
416 }
417 } else {
418 if (r_one==6) {
419 bitcnt=0;
420 r_val=0;
421 state=HDLC_FLAG_FOUND;
422 if (bcs->cs->debug & L1_DEB_HSCX)
423 debugl1(bcs->cs,"tiger read_raw: flag(%d,%d,%d) %x",
424 bcs->hw.tiger.r_tot,i,j,val);
425 }
426 r_one=0;
427 }
428 } else if (state == HDLC_FLAG_FOUND) {
429 if (val & 1) {
430 r_one++;
431 if (r_one>6) {
432 state=HDLC_ZERO_SEARCH;
433 } else {
434 r_val >>= 1;
435 r_val |= 0x80;
436 bitcnt++;
437 }
438 } else {
439 if (r_one==6) {
440 bitcnt=0;
441 r_val=0;
442 r_one=0;
443 val >>= 1;
444 continue;
445 } else if (r_one!=5) {
446 r_val >>= 1;
447 r_val &= 0x7f;
448 bitcnt++;
449 }
450 r_one=0;
451 }
452 if ((state != HDLC_ZERO_SEARCH) &&
453 !(bitcnt & 7)) {
454 state=HDLC_FRAME_FOUND;
455 bcs->hw.tiger.r_fcs = PPP_INITFCS;
456 bcs->hw.tiger.rcvbuf[0] = r_val;
457 bcs->hw.tiger.r_fcs = PPP_FCS (bcs->hw.tiger.r_fcs, r_val);
458 if (bcs->cs->debug & L1_DEB_HSCX)
459 debugl1(bcs->cs,"tiger read_raw: byte1(%d,%d,%d) rval %x val %x i %x",
460 bcs->hw.tiger.r_tot,i,j,r_val,val,
461 bcs->cs->hw.njet.irqstat0);
462 }
463 } else if (state == HDLC_FRAME_FOUND) {
464 if (val & 1) {
465 r_one++;
466 if (r_one>6) {
467 state=HDLC_ZERO_SEARCH;
468 bitcnt=0;
469 } else {
470 r_val >>= 1;
471 r_val |= 0x80;
472 bitcnt++;
473 }
474 } else {
475 if (r_one==6) {
476 r_val=0;
477 r_one=0;
478 bitcnt++;
479 if (bitcnt & 7) {
480 debugl1(bcs->cs, "tiger: frame not byte aligned");
481 state=HDLC_FLAG_SEARCH;
482 bcs->hw.tiger.r_err++;
483 #ifdef ERROR_STATISTIC
484 bcs->err_inv++;
485 #endif
486 } else {
487 if (bcs->cs->debug & L1_DEB_HSCX)
488 debugl1(bcs->cs,"tiger frame end(%d,%d): fcs(%x) i %x",
489 i,j,bcs->hw.tiger.r_fcs, bcs->cs->hw.njet.irqstat0);
490 if (bcs->hw.tiger.r_fcs == PPP_GOODFCS) {
491 got_frame(bcs, (bitcnt>>3)-3);
492 } else {
493 if (bcs->cs->debug) {
494 debugl1(bcs->cs, "tiger FCS error");
495 printframe(bcs->cs, bcs->hw.tiger.rcvbuf,
496 (bitcnt>>3)-1, "rec");
497 bcs->hw.tiger.r_err++;
498 }
499 #ifdef ERROR_STATISTIC
500 bcs->err_crc++;
501 #endif
502 }
503 state=HDLC_FLAG_FOUND;
504 }
505 bitcnt=0;
506 } else if (r_one==5) {
507 val >>= 1;
508 r_one=0;
509 continue;
510 } else {
511 r_val >>= 1;
512 r_val &= 0x7f;
513 bitcnt++;
514 }
515 r_one=0;
516 }
517 if ((state == HDLC_FRAME_FOUND) &&
518 !(bitcnt & 7)) {
519 if ((bitcnt>>3)>=HSCX_BUFMAX) {
520 debugl1(bcs->cs, "tiger: frame too big");
521 r_val=0;
522 state=HDLC_FLAG_SEARCH;
523 bcs->hw.tiger.r_err++;
524 #ifdef ERROR_STATISTIC
525 bcs->err_inv++;
526 #endif
527 } else {
528 bcs->hw.tiger.rcvbuf[(bitcnt>>3)-1] = r_val;
529 bcs->hw.tiger.r_fcs =
530 PPP_FCS (bcs->hw.tiger.r_fcs, r_val);
531 }
532 }
533 }
534 val >>= 1;
535 }
536 bcs->hw.tiger.r_tot++;
537 }
538 bcs->hw.tiger.r_state = state;
539 bcs->hw.tiger.r_one = r_one;
540 bcs->hw.tiger.r_val = r_val;
541 bcs->hw.tiger.r_bitcnt = bitcnt;
542 }
543
544 static void read_tiger(struct IsdnCardState *cs) {
545 u_int *p;
546 int cnt = NETJET_DMA_RXSIZE/2;
547
548 if ((cs->hw.njet.irqstat0 & cs->hw.njet.last_is0) & NETJET_IRQM0_READ) {
549 debugl1(cs,"tiger warn read double dma %x/%x",
550 cs->hw.njet.irqstat0, cs->hw.njet.last_is0);
551 #ifdef ERROR_STATISTIC
552 if (cs->bcs[0].mode)
553 cs->bcs[0].err_rdo++;
554 if (cs->bcs[1].mode)
555 cs->bcs[1].err_rdo++;
556 #endif
557 return;
558 } else {
559 cs->hw.njet.last_is0 &= ~NETJET_IRQM0_READ;
560 cs->hw.njet.last_is0 |= (cs->hw.njet.irqstat0 & NETJET_IRQM0_READ);
561 }
562 if (cs->hw.njet.irqstat0 & NETJET_IRQM0_READ_1)
563 p = cs->bcs[0].hw.tiger.rec + NETJET_DMA_RXSIZE - 1;
564 else
565 p = cs->bcs[0].hw.tiger.rec + cnt - 1;
566 if (cs->bcs[0].mode == L1_MODE_HDLC)
567 read_raw(cs->bcs, p, cnt);
568 if (cs->bcs[1].mode == L1_MODE_HDLC)
569 read_raw(cs->bcs + 1, p, cnt);
570 cs->hw.njet.irqstat0 &= ~NETJET_IRQM0_READ;
571 }
572
573 static void write_raw(struct BCState *bcs, u_int *buf, int cnt);
574
575 static void fill_dma(struct BCState *bcs)
576 {
577 register u_int *p, *sp;
578 register int cnt;
579
580 if (!bcs->tx_skb)
581 return;
582 if (bcs->cs->debug & L1_DEB_HSCX)
583 debugl1(bcs->cs,"tiger fill_dma1: c%d %4x", bcs->channel,
584 bcs->Flag);
585 if (test_and_set_bit(BC_FLG_BUSY, &bcs->Flag))
586 return;
587 if (make_raw_data(bcs))
588 return;
589 if (bcs->cs->debug & L1_DEB_HSCX)
590 debugl1(bcs->cs,"tiger fill_dma2: c%d %4x", bcs->channel,
591 bcs->Flag);
592 if (test_and_clear_bit(BC_FLG_NOFRAME, &bcs->Flag)) {
593 write_raw(bcs, bcs->hw.tiger.sendp, bcs->hw.tiger.free);
594 } else if (test_and_clear_bit(BC_FLG_HALF, &bcs->Flag)) {
595 p = bus_to_virt(inl(bcs->cs->hw.njet.base + NETJET_DMA_READ_ADR));
596 sp = bcs->hw.tiger.sendp;
597 if (p == bcs->hw.tiger.s_end)
598 p = bcs->hw.tiger.send -1;
599 if (sp == bcs->hw.tiger.s_end)
600 sp = bcs->hw.tiger.send -1;
601 cnt = p - sp;
602 if (cnt <0) {
603 write_raw(bcs, bcs->hw.tiger.sendp, bcs->hw.tiger.free);
604 } else {
605 p++;
606 cnt++;
607 if (p > bcs->hw.tiger.s_end)
608 p = bcs->hw.tiger.send;
609 p++;
610 cnt++;
611 if (p > bcs->hw.tiger.s_end)
612 p = bcs->hw.tiger.send;
613 write_raw(bcs, p, bcs->hw.tiger.free - cnt);
614 }
615 } else if (test_and_clear_bit(BC_FLG_EMPTY, &bcs->Flag)) {
616 p = bus_to_virt(inl(bcs->cs->hw.njet.base + NETJET_DMA_READ_ADR));
617 cnt = bcs->hw.tiger.s_end - p;
618 if (cnt < 2) {
619 p = bcs->hw.tiger.send + 1;
620 cnt = NETJET_DMA_TXSIZE/2 - 2;
621 } else {
622 p++;
623 p++;
624 if (cnt <= (NETJET_DMA_TXSIZE/2))
625 cnt += NETJET_DMA_TXSIZE/2;
626 cnt--;
627 cnt--;
628 }
629 write_raw(bcs, p, cnt);
630 }
631 if (bcs->cs->debug & L1_DEB_HSCX)
632 debugl1(bcs->cs,"tiger fill_dma3: c%d %4x", bcs->channel,
633 bcs->Flag);
634 }
635
636 static void write_raw(struct BCState *bcs, u_int *buf, int cnt) {
637 u_int mask, val, *p=buf;
638 u_int i, s_cnt;
639
640 if (cnt <= 0)
641 return;
642 if (test_bit(BC_FLG_BUSY, &bcs->Flag)) {
643 if (bcs->hw.tiger.sendcnt> cnt) {
644 s_cnt = cnt;
645 bcs->hw.tiger.sendcnt -= cnt;
646 } else {
647 s_cnt = bcs->hw.tiger.sendcnt;
648 bcs->hw.tiger.sendcnt = 0;
649 }
650 if (bcs->channel)
651 mask = 0xffff00ff;
652 else
653 mask = 0xffffff00;
654 for (i=0; i<s_cnt; i++) {
655 val = bcs->channel ? ((bcs->hw.tiger.sp[i] <<8) & 0xff00) :
656 (bcs->hw.tiger.sp[i]);
657 *p &= mask;
658 *p++ |= val;
659 if (p>bcs->hw.tiger.s_end)
660 p = bcs->hw.tiger.send;
661 }
662 bcs->hw.tiger.s_tot += s_cnt;
663 if (bcs->cs->debug & L1_DEB_HSCX)
664 debugl1(bcs->cs,"tiger write_raw: c%d %x-%x %d/%d %d %x", bcs->channel,
665 (u_int)buf, (u_int)p, s_cnt, cnt,
666 bcs->hw.tiger.sendcnt, bcs->cs->hw.njet.irqstat0);
667 if (bcs->cs->debug & L1_DEB_HSCX_FIFO)
668 printframe(bcs->cs, bcs->hw.tiger.sp, s_cnt, "snd");
669 bcs->hw.tiger.sp += s_cnt;
670 bcs->hw.tiger.sendp = p;
671 if (!bcs->hw.tiger.sendcnt) {
672 if (!bcs->tx_skb) {
673 debugl1(bcs->cs,"tiger write_raw: NULL skb s_cnt %d", s_cnt);
674 } else {
675 if (bcs->st->lli.l1writewakeup &&
676 (PACKET_NOACK != bcs->tx_skb->pkt_type))
677 bcs->st->lli.l1writewakeup(bcs->st, bcs->tx_skb->len);
678 dev_kfree_skb_any(bcs->tx_skb);
679 bcs->tx_skb = NULL;
680 }
681 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
682 bcs->hw.tiger.free = cnt - s_cnt;
683 if (bcs->hw.tiger.free > (NETJET_DMA_TXSIZE/2))
684 test_and_set_bit(BC_FLG_HALF, &bcs->Flag);
685 else {
686 test_and_clear_bit(BC_FLG_HALF, &bcs->Flag);
687 test_and_set_bit(BC_FLG_NOFRAME, &bcs->Flag);
688 }
689 if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
690 fill_dma(bcs);
691 } else {
692 mask ^= 0xffffffff;
693 if (s_cnt < cnt) {
694 for (i=s_cnt; i<cnt;i++) {
695 *p++ |= mask;
696 if (p>bcs->hw.tiger.s_end)
697 p = bcs->hw.tiger.send;
698 }
699 if (bcs->cs->debug & L1_DEB_HSCX)
700 debugl1(bcs->cs, "tiger write_raw: fill rest %d",
701 cnt - s_cnt);
702 }
703 bcs->event |= 1 << B_XMTBUFREADY;
704 queue_task(&bcs->tqueue, &tq_immediate);
705 mark_bh(IMMEDIATE_BH);
706 }
707 }
708 } else if (test_and_clear_bit(BC_FLG_NOFRAME, &bcs->Flag)) {
709 test_and_set_bit(BC_FLG_HALF, &bcs->Flag);
710 fill_mem(bcs, buf, cnt, bcs->channel, 0xff);
711 bcs->hw.tiger.free += cnt;
712 if (bcs->cs->debug & L1_DEB_HSCX)
713 debugl1(bcs->cs,"tiger write_raw: fill half");
714 } else if (test_and_clear_bit(BC_FLG_HALF, &bcs->Flag)) {
715 test_and_set_bit(BC_FLG_EMPTY, &bcs->Flag);
716 fill_mem(bcs, buf, cnt, bcs->channel, 0xff);
717 if (bcs->cs->debug & L1_DEB_HSCX)
718 debugl1(bcs->cs,"tiger write_raw: fill full");
719 }
720 }
721
722 static void write_tiger(struct IsdnCardState *cs) {
723 u_int *p, cnt = NETJET_DMA_TXSIZE/2;
724
725 if ((cs->hw.njet.irqstat0 & cs->hw.njet.last_is0) & NETJET_IRQM0_WRITE) {
726 debugl1(cs,"tiger warn write double dma %x/%x",
727 cs->hw.njet.irqstat0, cs->hw.njet.last_is0);
728 #ifdef ERROR_STATISTIC
729 if (cs->bcs[0].mode)
730 cs->bcs[0].err_tx++;
731 if (cs->bcs[1].mode)
732 cs->bcs[1].err_tx++;
733 #endif
734 return;
735 } else {
736 cs->hw.njet.last_is0 &= ~NETJET_IRQM0_WRITE;
737 cs->hw.njet.last_is0 |= (cs->hw.njet.irqstat0 & NETJET_IRQM0_WRITE);
738 }
739 if (cs->hw.njet.irqstat0 & NETJET_IRQM0_WRITE_1)
740 p = cs->bcs[0].hw.tiger.send + NETJET_DMA_TXSIZE - 1;
741 else
742 p = cs->bcs[0].hw.tiger.send + cnt - 1;
743 if (cs->bcs[0].mode == L1_MODE_HDLC)
744 write_raw(cs->bcs, p, cnt);
745 if (cs->bcs[1].mode == L1_MODE_HDLC)
746 write_raw(cs->bcs + 1, p, cnt);
747 cs->hw.njet.irqstat0 &= ~NETJET_IRQM0_WRITE;
748 }
749
750 static void
751 tiger_l2l1(struct PStack *st, int pr, void *arg)
752 {
753 struct sk_buff *skb = arg;
754 long flags;
755
756 switch (pr) {
757 case (PH_DATA | REQUEST):
758 save_flags(flags);
759 cli();
760 if (st->l1.bcs->tx_skb) {
761 skb_queue_tail(&st->l1.bcs->squeue, skb);
762 restore_flags(flags);
763 } else {
764 st->l1.bcs->tx_skb = skb;
765 st->l1.bcs->cs->BC_Send_Data(st->l1.bcs);
766 restore_flags(flags);
767 }
768 break;
769 case (PH_PULL | INDICATION):
770 if (st->l1.bcs->tx_skb) {
771 printk(KERN_WARNING "tiger_l2l1: this shouldn't happen\n");
772 break;
773 }
774 save_flags(flags);
775 cli();
776 st->l1.bcs->tx_skb = skb;
777 st->l1.bcs->cs->BC_Send_Data(st->l1.bcs);
778 restore_flags(flags);
779 break;
780 case (PH_PULL | REQUEST):
781 if (!st->l1.bcs->tx_skb) {
782 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
783 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
784 } else
785 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
786 break;
787 case (PH_ACTIVATE | REQUEST):
788 test_and_set_bit(BC_FLG_ACTIV, &st->l1.bcs->Flag);
789 mode_tiger(st->l1.bcs, st->l1.mode, st->l1.bc);
790 l1_msg_b(st, pr, arg);
791 break;
792 case (PH_DEACTIVATE | REQUEST):
793 l1_msg_b(st, pr, arg);
794 break;
795 case (PH_DEACTIVATE | CONFIRM):
796 test_and_clear_bit(BC_FLG_ACTIV, &st->l1.bcs->Flag);
797 test_and_clear_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
798 mode_tiger(st->l1.bcs, 0, st->l1.bc);
799 st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
800 break;
801 }
802 }
803
804
805 void
806 close_tigerstate(struct BCState *bcs)
807 {
808 mode_tiger(bcs, 0, bcs->channel);
809 if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
810 if (bcs->hw.tiger.rcvbuf) {
811 kfree(bcs->hw.tiger.rcvbuf);
812 bcs->hw.tiger.rcvbuf = NULL;
813 }
814 if (bcs->hw.tiger.sendbuf) {
815 kfree(bcs->hw.tiger.sendbuf);
816 bcs->hw.tiger.sendbuf = NULL;
817 }
818 discard_queue(&bcs->rqueue);
819 discard_queue(&bcs->squeue);
820 if (bcs->tx_skb) {
821 dev_kfree_skb_any(bcs->tx_skb);
822 bcs->tx_skb = NULL;
823 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
824 }
825 }
826 }
827
828 static int
829 open_tigerstate(struct IsdnCardState *cs, struct BCState *bcs)
830 {
831 if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
832 if (!(bcs->hw.tiger.rcvbuf = kmalloc(HSCX_BUFMAX, GFP_ATOMIC))) {
833 printk(KERN_WARNING
834 "HiSax: No memory for tiger.rcvbuf\n");
835 return (1);
836 }
837 if (!(bcs->hw.tiger.sendbuf = kmalloc(RAW_BUFMAX, GFP_ATOMIC))) {
838 printk(KERN_WARNING
839 "HiSax: No memory for tiger.sendbuf\n");
840 return (1);
841 }
842 skb_queue_head_init(&bcs->rqueue);
843 skb_queue_head_init(&bcs->squeue);
844 }
845 bcs->tx_skb = NULL;
846 bcs->hw.tiger.sendcnt = 0;
847 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
848 bcs->event = 0;
849 bcs->tx_cnt = 0;
850 return (0);
851 }
852
853 int
854 setstack_tiger(struct PStack *st, struct BCState *bcs)
855 {
856 bcs->channel = st->l1.bc;
857 if (open_tigerstate(st->l1.hardware, bcs))
858 return (-1);
859 st->l1.bcs = bcs;
860 st->l2.l2l1 = tiger_l2l1;
861 setstack_manager(st);
862 bcs->st = st;
863 setstack_l1_B(st);
864 return (0);
865 }
866
867
868 __initfunc(void
869 inittiger(struct IsdnCardState *cs))
870 {
871 if (!(cs->bcs[0].hw.tiger.send = kmalloc(NETJET_DMA_TXSIZE * sizeof(unsigned int),
872 GFP_KERNEL | GFP_DMA))) {
873 printk(KERN_WARNING
874 "HiSax: No memory for tiger.send\n");
875 return;
876 }
877 cs->bcs[0].hw.tiger.s_irq = cs->bcs[0].hw.tiger.send + NETJET_DMA_TXSIZE/2 - 1;
878 cs->bcs[0].hw.tiger.s_end = cs->bcs[0].hw.tiger.send + NETJET_DMA_TXSIZE - 1;
879 cs->bcs[1].hw.tiger.send = cs->bcs[0].hw.tiger.send;
880 cs->bcs[1].hw.tiger.s_irq = cs->bcs[0].hw.tiger.s_irq;
881 cs->bcs[1].hw.tiger.s_end = cs->bcs[0].hw.tiger.s_end;
882
883 memset(cs->bcs[0].hw.tiger.send, 0xff, NETJET_DMA_TXSIZE * sizeof(unsigned int));
884 debugl1(cs, "tiger: send buf %x - %x", (u_int)cs->bcs[0].hw.tiger.send,
885 (u_int)(cs->bcs[0].hw.tiger.send + NETJET_DMA_TXSIZE - 1));
886 outl(virt_to_bus(cs->bcs[0].hw.tiger.send),
887 cs->hw.njet.base + NETJET_DMA_READ_START);
888 outl(virt_to_bus(cs->bcs[0].hw.tiger.s_irq),
889 cs->hw.njet.base + NETJET_DMA_READ_IRQ);
890 outl(virt_to_bus(cs->bcs[0].hw.tiger.s_end),
891 cs->hw.njet.base + NETJET_DMA_READ_END);
892 if (!(cs->bcs[0].hw.tiger.rec = kmalloc(NETJET_DMA_RXSIZE * sizeof(unsigned int),
893 GFP_KERNEL | GFP_DMA))) {
894 printk(KERN_WARNING
895 "HiSax: No memory for tiger.rec\n");
896 return;
897 }
898 debugl1(cs, "tiger: rec buf %x - %x", (u_int)cs->bcs[0].hw.tiger.rec,
899 (u_int)(cs->bcs[0].hw.tiger.rec + NETJET_DMA_RXSIZE - 1));
900 cs->bcs[1].hw.tiger.rec = cs->bcs[0].hw.tiger.rec;
901 memset(cs->bcs[0].hw.tiger.rec, 0xff, NETJET_DMA_RXSIZE * sizeof(unsigned int));
902 outl(virt_to_bus(cs->bcs[0].hw.tiger.rec),
903 cs->hw.njet.base + NETJET_DMA_WRITE_START);
904 outl(virt_to_bus(cs->bcs[0].hw.tiger.rec + NETJET_DMA_RXSIZE/2 - 1),
905 cs->hw.njet.base + NETJET_DMA_WRITE_IRQ);
906 outl(virt_to_bus(cs->bcs[0].hw.tiger.rec + NETJET_DMA_RXSIZE - 1),
907 cs->hw.njet.base + NETJET_DMA_WRITE_END);
908 debugl1(cs, "tiger: dmacfg %x/%x pulse=%d",
909 inl(cs->hw.njet.base + NETJET_DMA_WRITE_ADR),
910 inl(cs->hw.njet.base + NETJET_DMA_READ_ADR),
911 bytein(cs->hw.njet.base + NETJET_PULSE_CNT));
912 cs->hw.njet.last_is0 = 0;
913 cs->bcs[0].BC_SetStack = setstack_tiger;
914 cs->bcs[1].BC_SetStack = setstack_tiger;
915 cs->bcs[0].BC_Close = close_tigerstate;
916 cs->bcs[1].BC_Close = close_tigerstate;
917 }
918
919 void
920 releasetiger(struct IsdnCardState *cs)
921 {
922 if (cs->bcs[0].hw.tiger.send) {
923 kfree(cs->bcs[0].hw.tiger.send);
924 cs->bcs[0].hw.tiger.send = NULL;
925 }
926 if (cs->bcs[1].hw.tiger.send) {
927 cs->bcs[1].hw.tiger.send = NULL;
928 }
929 if (cs->bcs[0].hw.tiger.rec) {
930 kfree(cs->bcs[0].hw.tiger.rec);
931 cs->bcs[0].hw.tiger.rec = NULL;
932 }
933 if (cs->bcs[1].hw.tiger.rec) {
934 cs->bcs[1].hw.tiger.rec = NULL;
935 }
936 }
937
938 static void
939 netjet_interrupt(int intno, void *dev_id, struct pt_regs *regs)
940 {
941 struct IsdnCardState *cs = dev_id;
942 u_char val, sval;
943 long flags;
944
945 if (!cs) {
946 printk(KERN_WARNING "NETjet: Spurious interrupt!\n");
947 return;
948 }
949 if (!((sval = bytein(cs->hw.njet.base + NETJET_IRQSTAT1)) &
950 NETJET_ISACIRQ)) {
951 val = ReadISAC(cs, ISAC_ISTA);
952 if (cs->debug & L1_DEB_ISAC)
953 debugl1(cs, "tiger: i1 %x %x", sval, val);
954 if (val) {
955 isac_interrupt(cs, val);
956 WriteISAC(cs, ISAC_MASK, 0xFF);
957 WriteISAC(cs, ISAC_MASK, 0x0);
958 }
959 }
960 save_flags(flags);
961 cli();
962 if ((sval = bytein(cs->hw.njet.base + NETJET_IRQSTAT0))) {
963 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
964 restore_flags(flags);
965 return;
966 }
967 cs->hw.njet.irqstat0 = sval;
968 restore_flags(flags);
969 /* debugl1(cs, "tiger: ist0 %x %x %x %x/%x pulse=%d",
970 sval,
971 bytein(cs->hw.njet.base + NETJET_DMACTRL),
972 bytein(cs->hw.njet.base + NETJET_IRQMASK0),
973 inl(cs->hw.njet.base + NETJET_DMA_READ_ADR),
974 inl(cs->hw.njet.base + NETJET_DMA_WRITE_ADR),
975 bytein(cs->hw.njet.base + NETJET_PULSE_CNT));
976 */
977 /* cs->hw.njet.irqmask0 = ((0x0f & cs->hw.njet.irqstat0) ^ 0x0f) | 0x30;
978 */ byteout(cs->hw.njet.base + NETJET_IRQSTAT0, cs->hw.njet.irqstat0);
979 /* byteout(cs->hw.njet.base + NETJET_IRQMASK0, cs->hw.njet.irqmask0);
980 */ if (cs->hw.njet.irqstat0 & NETJET_IRQM0_READ)
981 read_tiger(cs);
982 if (cs->hw.njet.irqstat0 & NETJET_IRQM0_WRITE)
983 write_tiger(cs);
984 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
985 } else
986 restore_flags(flags);
987
988 /* if (!testcnt--) {
989 cs->hw.njet.dmactrl = 0;
990 byteout(cs->hw.njet.base + NETJET_DMACTRL,
991 cs->hw.njet.dmactrl);
992 byteout(cs->hw.njet.base + NETJET_IRQMASK0, 0);
993 }
994 */
995 }
996
997 static void
998 reset_netjet(struct IsdnCardState *cs)
999 {
1000 long flags;
1001
1002 save_flags(flags);
1003 sti();
1004 cs->hw.njet.ctrl_reg = 0xff; /* Reset On */
1005 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg);
1006 set_current_state(TASK_UNINTERRUPTIBLE);
1007 schedule_timeout((10*HZ)/1000); /* Timeout 10ms */
1008 cs->hw.njet.ctrl_reg = 0x00; /* Reset Off and status read clear */
1009 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg);
1010 set_current_state(TASK_UNINTERRUPTIBLE);
1011 schedule_timeout((10*HZ)/1000); /* Timeout 10ms */
1012 restore_flags(flags);
1013 cs->hw.njet.auxd = 0;
1014 cs->hw.njet.dmactrl = 0;
1015 byteout(cs->hw.njet.base + NETJET_AUXCTRL, ~NETJET_ISACIRQ);
1016 byteout(cs->hw.njet.base + NETJET_IRQMASK1, NETJET_ISACIRQ);
1017 byteout(cs->hw.njet.auxa, cs->hw.njet.auxd);
1018 }
1019
1020 void
1021 release_io_netjet(struct IsdnCardState *cs)
1022 {
1023 byteout(cs->hw.njet.base + NETJET_IRQMASK0, 0);
1024 byteout(cs->hw.njet.base + NETJET_IRQMASK1, 0);
1025 releasetiger(cs);
1026 release_region(cs->hw.njet.base, 256);
1027 }
1028
1029
1030 static int
1031 NETjet_card_msg(struct IsdnCardState *cs, int mt, void *arg)
1032 {
1033 switch (mt) {
1034 case CARD_RESET:
1035 reset_netjet(cs);
1036 return(0);
1037 case CARD_RELEASE:
1038 release_io_netjet(cs);
1039 return(0);
1040 case CARD_INIT:
1041 inittiger(cs);
1042 clear_pending_isac_ints(cs);
1043 initisac(cs);
1044 /* Reenable all IRQ */
1045 cs->writeisac(cs, ISAC_MASK, 0);
1046 return(0);
1047 case CARD_TEST:
1048 return(0);
1049 }
1050 return(0);
1051 }
1052
1053 static struct pci_dev *dev_netjet __initdata = NULL;
1054
1055 __initfunc(int
1056 setup_netjet(struct IsdnCard *card))
1057 {
1058 int bytecnt;
1059 struct IsdnCardState *cs = card->cs;
1060 char tmp[64];
1061 #if CONFIG_PCI
1062 #endif
1063 strcpy(tmp, NETjet_revision);
1064 printk(KERN_INFO "HiSax: Traverse Tech. NETjet driver Rev. %s\n", HiSax_getrev(tmp));
1065 if (cs->typ != ISDN_CTYPE_NETJET)
1066 return(0);
1067 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1068 #if CONFIG_PCI
1069 if (!pci_present()) {
1070 printk(KERN_ERR "Netjet: no PCI bus present\n");
1071 return(0);
1072 }
1073 if ((dev_netjet = pci_find_device(PCI_VENDOR_TRAVERSE_TECH,
1074 PCI_NETJET_ID, dev_netjet))) {
1075 if (pci_enable_device(dev_netjet))
1076 return (0);
1077 cs->irq = dev_netjet->irq;
1078 if (!cs->irq) {
1079 printk(KERN_WARNING "NETjet: No IRQ for PCI card found\n");
1080 return(0);
1081 }
1082 cs->hw.njet.base = pci_resource_start(dev_netjet, 0);
1083 if (!cs->hw.njet.base) {
1084 printk(KERN_WARNING "NETjet: No IO-Adr for PCI card found\n");
1085 return(0);
1086 }
1087 } else {
1088 printk(KERN_WARNING "NETjet: No PCI card found\n");
1089 return(0);
1090 }
1091 cs->hw.njet.auxa = cs->hw.njet.base + NETJET_AUXDATA;
1092 cs->hw.njet.isac = cs->hw.njet.base | NETJET_ISAC_OFF;
1093 bytecnt = 256;
1094 #else
1095 printk(KERN_WARNING "NETjet: NO_PCI_BIOS\n");
1096 printk(KERN_WARNING "NETjet: unable to config NETJET PCI\n");
1097 return (0);
1098 #endif /* CONFIG_PCI */
1099 printk(KERN_INFO
1100 "NETjet: PCI card configured at 0x%x IRQ %d\n",
1101 cs->hw.njet.base, cs->irq);
1102 if (check_region(cs->hw.njet.base, bytecnt)) {
1103 printk(KERN_WARNING
1104 "HiSax: %s config port %x-%x already in use\n",
1105 CardType[card->typ],
1106 cs->hw.njet.base,
1107 cs->hw.njet.base + bytecnt);
1108 return (0);
1109 } else {
1110 request_region(cs->hw.njet.base, bytecnt, "netjet isdn");
1111 }
1112 reset_netjet(cs);
1113 cs->readisac = &ReadISAC;
1114 cs->writeisac = &WriteISAC;
1115 cs->readisacfifo = &ReadISACfifo;
1116 cs->writeisacfifo = &WriteISACfifo;
1117 cs->BC_Read_Reg = &dummyrr;
1118 cs->BC_Write_Reg = &dummywr;
1119 cs->BC_Send_Data = &fill_dma;
1120 cs->cardmsg = &NETjet_card_msg;
1121 cs->irq_func = &netjet_interrupt;
1122 cs->irq_flags |= SA_SHIRQ;
1123 ISACVersion(cs, "NETjet:");
1124 return (1);
1125 }
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