drivers/char/agp/agp.h

   1 /*
   2  * AGPGART module version 0.99
   3  * Copyright (C) 1999 Jeff Hartmann
   4  * Copyright (C) 1999 Precision Insight, Inc.
   5  * Copyright (C) 1999 Xi Graphics, Inc.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11  * and/or sell copies of the Software, and to permit persons to whom the
  12  * Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included
  15  * in all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  18  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * JEFF HARTMANN, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM,
  21  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  22  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
  23  * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #ifndef _AGP_BACKEND_PRIV_H
  28 #define _AGP_BACKEND_PRIV_H 1
  29
  30 enum aper_size_type {
  31         U8_APER_SIZE,
  32         U16_APER_SIZE,
  33         U32_APER_SIZE,
  34         LVL2_APER_SIZE,
  35         FIXED_APER_SIZE
  36 };
  37
  38 typedef struct _gatt_mask {
  39         unsigned long mask;
  40         u32 type;
  41         /* totally device specific, for integrated chipsets that
  42          * might have different types of memory masks.  For other
  43          * devices this will probably be ignored */
  44 } gatt_mask;
  45
  46 typedef struct _aper_size_info_8 {
  47         int size;
  48         int num_entries;
  49         int page_order;
  50         u8 size_value;
  51 } aper_size_info_8;
  52
  53 typedef struct _aper_size_info_16 {
  54         int size;
  55         int num_entries;
  56         int page_order;
  57         u16 size_value;
  58 } aper_size_info_16;
  59
  60 typedef struct _aper_size_info_32 {
  61         int size;
  62         int num_entries;
  63         int page_order;
  64         u32 size_value;
  65 } aper_size_info_32;
  66
  67 typedef struct _aper_size_info_lvl2 {
  68         int size;
  69         int num_entries;
  70         u32 size_value;
  71 } aper_size_info_lvl2;
  72
  73 typedef struct _aper_size_info_fixed {
  74         int size;
  75         int num_entries;
  76         int page_order;
  77 } aper_size_info_fixed;
  78
  79 struct agp_bridge_data {
  80         agp_version *version;
  81         void *aperture_sizes;
  82         void *previous_size;
  83         void *current_size;
  84         void *dev_private_data;
  85         struct pci_dev *dev;
  86         gatt_mask *masks;
  87         unsigned long *gatt_table;
  88         unsigned long *gatt_table_real;
  89         unsigned long scratch_page;
  90         unsigned long gart_bus_addr;
  91         unsigned long gatt_bus_addr;
  92         u32 mode;
  93         enum chipset_type type;
  94         enum aper_size_type size_type;
  95         u32 *key_list;
  96         atomic_t current_memory_agp;
  97         atomic_t agp_in_use;
  98         int max_memory_agp;     /* in number of pages */
  99         int needs_scratch_page;
 100         int aperture_size_idx;
 101         int num_aperture_sizes;
 102         int num_of_masks;
 103         int capndx;
 104
 105         /* Links to driver specific functions */
 106
 107         int (*fetch_size) (void);
 108         int (*configure) (void);
 109         void (*agp_enable) (u32);
 110         void (*cleanup) (void);
 111         void (*tlb_flush) (agp_memory *);
 112         unsigned long (*mask_memory) (unsigned long, int);
 113         void (*cache_flush) (void);
 114         int (*create_gatt_table) (void);
 115         int (*free_gatt_table) (void);
 116         int (*insert_memory) (agp_memory *, off_t, int);
 117         int (*remove_memory) (agp_memory *, off_t, int);
 118         agp_memory *(*alloc_by_type) (size_t, int);
 119         void (*free_by_type) (agp_memory *);
 120 };
 121
 122 #define OUTREG32(mmap, addr, val)   __raw_writel((val), (mmap)+(addr))
 123 #define OUTREG16(mmap, addr, val)   __raw_writew((val), (mmap)+(addr))
 124 #define OUTREG8 (mmap, addr, val)   __raw_writeb((val), (mmap)+(addr))
 125
 126 #define INREG32(mmap, addr)         __raw_readl((mmap)+(addr))
 127 #define INREG16(mmap, addr)         __raw_readw((mmap)+(addr))
 128 #define INREG8 (mmap, addr)         __raw_readb((mmap)+(addr))
 129
 130 #define CACHE_FLUSH     agp_bridge.cache_flush
 131 #define A_SIZE_8(x)     ((aper_size_info_8 *) x)
 132 #define A_SIZE_16(x)    ((aper_size_info_16 *) x)
 133 #define A_SIZE_32(x)    ((aper_size_info_32 *) x)
 134 #define A_SIZE_LVL2(x)  ((aper_size_info_lvl2 *) x)
 135 #define A_SIZE_FIX(x)   ((aper_size_info_fixed *) x)
 136 #define A_IDX8()        (A_SIZE_8(agp_bridge.aperture_sizes) + i)
 137 #define A_IDX16()       (A_SIZE_16(agp_bridge.aperture_sizes) + i)
 138 #define A_IDX32()       (A_SIZE_32(agp_bridge.aperture_sizes) + i)
 139 #define A_IDXLVL2()     (A_SIZE_LVL2(agp_bridge.aperture_sizes) + i)
 140 #define A_IDXFIX()      (A_SIZE_FIX(agp_bridge.aperture_sizes) + i)
 141 #define MAXKEY          (4096 * 32)
 142
 143 #ifndef min
 144 #define min(a,b)        (((a)<(b))?(a):(b))
 145 #endif
 146
 147 #define arraysize(x)            (sizeof(x)/sizeof(*(x)))
 148
 149 #define AGPGART_MODULE_NAME     "agpgart"
 150 #define PFX                     AGPGART_MODULE_NAME ": "
 151
 152 #define PGE_EMPTY(p) (!(p) || (p) == (unsigned long) agp_bridge.scratch_page)
 153
 154 #ifndef PCI_DEVICE_ID_VIA_82C691_0
 155 #define PCI_DEVICE_ID_VIA_82C691_0      0x0691
 156 #endif
 157 #ifndef PCI_DEVICE_ID_VIA_82C691_1
 158 #define PCI_DEVICE_ID_VIA_82C691_1      0x8691
 159 #endif
 160 #ifndef PCI_DEVICE_ID_INTEL_810_0
 161 #define PCI_DEVICE_ID_INTEL_810_0       0x7120
 162 #endif
 163 #ifndef PCI_DEVICE_ID_INTEL_840_0
 164 #define PCI_DEVICE_ID_INTEL_840_0               0x1a21
 165 #endif
 166 #ifndef PCI_DEVICE_ID_INTEL_810_DC100_0
 167 #define PCI_DEVICE_ID_INTEL_810_DC100_0 0x7122
 168 #endif
 169 #ifndef PCI_DEVICE_ID_INTEL_810_E_0
 170 #define PCI_DEVICE_ID_INTEL_810_E_0     0x7124
 171 #endif
 172 #ifndef PCI_DEVICE_ID_INTEL_82443GX_0
 173 #define PCI_DEVICE_ID_INTEL_82443GX_0   0x71a0
 174 #endif
 175 #ifndef PCI_DEVICE_ID_INTEL_810_1
 176 #define PCI_DEVICE_ID_INTEL_810_1       0x7121
 177 #endif
 178 #ifndef PCI_DEVICE_ID_INTEL_810_DC100_1
 179 #define PCI_DEVICE_ID_INTEL_810_DC100_1 0x7123
 180 #endif
 181 #ifndef PCI_DEVICE_ID_INTEL_810_E_1
 182 #define PCI_DEVICE_ID_INTEL_810_E_1     0x7125
 183 #endif
 184 #ifndef PCI_DEVICE_ID_INTEL_815_0
 185 #define PCI_DEVICE_ID_INTEL_815_0       0x1130
 186 #endif
 187 #ifndef PCI_DEVICE_ID_INTEL_815_1
 188 #define PCI_DEVICE_ID_INTEL_815_1       0x1132
 189 #endif
 190 #ifndef PCI_DEVICE_ID_INTEL_82443GX_1
 191 #define PCI_DEVICE_ID_INTEL_82443GX_1   0x71a1
 192 #endif
 193 #ifndef PCI_DEVICE_ID_AMD_IRONGATE_0
 194 #define PCI_DEVICE_ID_AMD_IRONGATE_0    0x7006
 195 #endif
 196 #ifndef PCI_VENDOR_ID_AL
 197 #define PCI_VENDOR_ID_AL                0x10b9
 198 #endif
 199 #ifndef PCI_DEVICE_ID_AL_M1541_0
 200 #define PCI_DEVICE_ID_AL_M1541_0        0x1541
 201 #endif
 202
 203 /* intel register */
 204 #define INTEL_APBASE    0x10
 205 #define INTEL_APSIZE    0xb4
 206 #define INTEL_ATTBASE   0xb8
 207 #define INTEL_AGPCTRL   0xb0
 208 #define INTEL_NBXCFG    0x50
 209 #define INTEL_ERRSTS    0x91
 210
 211 /* intel i840 registers */
 212 #define INTEL_I840_MCHCFG   0x50
 213 #define INTEL_I840_ERRSTS       0xc8
 214
 215 /* intel i810 registers */
 216 #define I810_GMADDR 0x10
 217 #define I810_MMADDR 0x14
 218 #define I810_PTE_BASE          0x10000
 219 #define I810_PTE_MAIN_UNCACHED 0x00000000
 220 #define I810_PTE_LOCAL         0x00000002
 221 #define I810_PTE_VALID         0x00000001
 222 #define I810_SMRAM_MISCC       0x70
 223 #define I810_GFX_MEM_WIN_SIZE  0x00010000
 224 #define I810_GFX_MEM_WIN_32M   0x00010000
 225 #define I810_GMS               0x000000c0
 226 #define I810_GMS_DISABLE       0x00000000
 227 #define I810_PGETBL_CTL        0x2020
 228 #define I810_PGETBL_ENABLED    0x00000001
 229 #define I810_DRAM_CTL          0x3000
 230 #define I810_DRAM_ROW_0        0x00000001
 231 #define I810_DRAM_ROW_0_SDRAM  0x00000001
 232
 233 /* VIA register */
 234 #define VIA_APBASE      0x10
 235 #define VIA_GARTCTRL    0x80
 236 #define VIA_APSIZE      0x84
 237 #define VIA_ATTBASE     0x88
 238
 239 /* SiS registers */
 240 #define SIS_APBASE      0x10
 241 #define SIS_ATTBASE     0x90
 242 #define SIS_APSIZE      0x94
 243 #define SIS_TLBCNTRL    0x97
 244 #define SIS_TLBFLUSH    0x98
 245
 246 /* AMD registers */
 247 #define AMD_APBASE      0x10
 248 #define AMD_MMBASE      0x14
 249 #define AMD_APSIZE      0xac
 250 #define AMD_MODECNTL    0xb0
 251 #define AMD_MODECNTL2   0xb2
 252 #define AMD_GARTENABLE  0x02    /* In mmio region (16-bit register) */
 253 #define AMD_ATTBASE     0x04    /* In mmio region (32-bit register) */
 254 #define AMD_TLBFLUSH    0x0c    /* In mmio region (32-bit register) */
 255 #define AMD_CACHEENTRY  0x10    /* In mmio region (32-bit register) */
 256
 257 /* ALi registers */
 258 #define ALI_APBASE      0x10
 259 #define ALI_AGPCTRL     0xb8
 260 #define ALI_ATTBASE     0xbc
 261 #define ALI_TLBCTRL     0xc0
 262
 263 #endif                          /* _AGP_BACKEND_PRIV_H */