?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Pull one more egcs 1.1.2 workaround.
[linux-2.6/linux-mips.git] / sound / oss / swarm_cs4297a.c
blobf9adfad6720f962046a4370d5d766ac9010f0aa9
1 /*******************************************************************************
2 *
3 * "swarm_cs4297a.c" -- Cirrus Logic-Crystal CS4297a linux audio driver.
4 *
5 * Copyright (C) 2001 Broadcom Corporation.
6 * Copyright (C) 2000,2001 Cirrus Logic Corp.
7 * -- adapted from drivers by Thomas Sailer,
8 * -- but don't bug him; Problems should go to:
9 * -- tom woller (twoller@crystal.cirrus.com) or
10 * (audio@crystal.cirrus.com).
11 * -- adapted from cs4281 PCI driver for cs4297a on
12 * BCM1250 Synchronous Serial interface
13 * (kwalker@broadcom.com)
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
28 *
29 * Module command line parameters:
30 * none
31 *
32 * Supported devices:
33 * /dev/dsp standard /dev/dsp device, (mostly) OSS compatible
34 * /dev/mixer standard /dev/mixer device, (mostly) OSS compatible
35 * /dev/midi simple MIDI UART interface, no ioctl
36 *
37 * Modification History
38 * 08/20/00 trw - silence and no stopping DAC until release
39 * 08/23/00 trw - added CS_DBG statements, fix interrupt hang issue on DAC stop.
40 * 09/18/00 trw - added 16bit only record with conversion
41 * 09/24/00 trw - added Enhanced Full duplex (separate simultaneous
42 * capture/playback rates)
43 * 10/03/00 trw - fixed mmap (fixed GRECORD and the XMMS mmap test plugin
44 * libOSSm.so)
45 * 10/11/00 trw - modified for 2.4.0-test9 kernel enhancements (NR_MAP removal)
46 * 11/03/00 trw - fixed interrupt loss/stutter, added debug.
47 * 11/10/00 bkz - added __devinit to cs4297a_hw_init()
48 * 11/10/00 trw - fixed SMP and capture spinlock hang.
49 * 12/04/00 trw - cleaned up CSDEBUG flags and added "defaultorder" moduleparm.
50 * 12/05/00 trw - fixed polling (myth2), and added underrun swptr fix.
51 * 12/08/00 trw - added PM support.
52 * 12/14/00 trw - added wrapper code, builds under 2.4.0, 2.2.17-20, 2.2.17-8
53 * (RH/Dell base), 2.2.18, 2.2.12. cleaned up code mods by ident.
54 * 12/19/00 trw - added PM support for 2.2 base (apm_callback). other PM cleanup.
55 * 12/21/00 trw - added fractional "defaultorder" inputs. if >100 then use
56 * defaultorder-100 as power of 2 for the buffer size. example:
57 * 106 = 2^(106-100) = 2^6 = 64 bytes for the buffer size.
58 *
59 *******************************************************************************/
60
61 #include <linux/list.h>
62 #include <linux/version.h>
63 #include <linux/module.h>
64 #include <linux/string.h>
65 #include <linux/ioport.h>
66 #include <linux/sched.h>
67 #include <linux/delay.h>
68 #include <linux/sound.h>
69 #include <linux/slab.h>
70 #include <linux/soundcard.h>
71 #include <linux/ac97_codec.h>
72 #include <linux/pci.h>
73 #include <linux/bitops.h>
74 #include <asm/io.h>
75 #include <asm/dma.h>
76 #include <linux/init.h>
77 #include <linux/poll.h>
78 #include <linux/smp_lock.h>
79 #include <linux/wrapper.h>
80 #include <asm/uaccess.h>
81 #include <asm/hardirq.h>
82
83 #include <asm/sibyte/sb1250_regs.h>
84 #include <asm/sibyte/sb1250_int.h>
85 #include <asm/sibyte/sb1250_dma.h>
86 #include <asm/sibyte/sb1250_scd.h>
87 #include <asm/sibyte/sb1250_syncser.h>
88 #include <asm/sibyte/sb1250_mac.h>
89 #include <asm/sibyte/sb1250.h>
90 #include <asm/sibyte/64bit.h>
91
92 struct cs4297a_state;
93 EXPORT_NO_SYMBOLS;
94
95 static void stop_dac(struct cs4297a_state *s);
96 static void stop_adc(struct cs4297a_state *s);
97 static void start_dac(struct cs4297a_state *s);
98 static void start_adc(struct cs4297a_state *s);
99 #undef OSS_DOCUMENTED_MIXER_SEMANTICS
100
101 // ---------------------------------------------------------------------
102
103 #define CS4297a_MAGIC 0xf00beef1
104
105 // buffer order determines the size of the dma buffer for the driver.
106 // under Linux, a smaller buffer allows more responsiveness from many of the
107 // applications (e.g. games). A larger buffer allows some of the apps (esound)
108 // to not underrun the dma buffer as easily. As default, use 32k (order=3)
109 // rather than 64k as some of the games work more responsively.
110 // log base 2( buff sz = 32k).
111
112 //static unsigned long defaultorder = 3;
113 //MODULE_PARM(defaultorder, "i");
114
115 //
116 // Turn on/off debugging compilation by commenting out "#define CSDEBUG"
117 //
118 #define CSDEBUG 0
119 #if CSDEBUG
120 #define CSDEBUG_INTERFACE 1
121 #else
122 #undef CSDEBUG_INTERFACE
123 #endif
124 //
125 // cs_debugmask areas
126 //
127 #define CS_INIT 0x00000001 // initialization and probe functions
128 #define CS_ERROR 0x00000002 // tmp debugging bit placeholder
129 #define CS_INTERRUPT 0x00000004 // interrupt handler (separate from all other)
130 #define CS_FUNCTION 0x00000008 // enter/leave functions
131 #define CS_WAVE_WRITE 0x00000010 // write information for wave
132 #define CS_WAVE_READ 0x00000020 // read information for wave
133 #define CS_AC97 0x00000040 // AC97 register access
134 #define CS_DESCR 0x00000080 // descriptor management
135 #define CS_OPEN 0x00000400 // all open functions in the driver
136 #define CS_RELEASE 0x00000800 // all release functions in the driver
137 #define CS_PARMS 0x00001000 // functional and operational parameters
138 #define CS_IOCTL 0x00002000 // ioctl (non-mixer)
139 #define CS_TMP 0x10000000 // tmp debug mask bit
140
141 //
142 // CSDEBUG is usual mode is set to 1, then use the
143 // cs_debuglevel and cs_debugmask to turn on or off debugging.
144 // Debug level of 1 has been defined to be kernel errors and info
145 // that should be printed on any released driver.
146 //
147 #if CSDEBUG
148 #define CS_DBGOUT(mask,level,x) if((cs_debuglevel >= (level)) && ((mask) & cs_debugmask) ) {x;}
149 #else
150 #define CS_DBGOUT(mask,level,x)
151 #endif
152
153 #if CSDEBUG
154 static unsigned long cs_debuglevel = 4; // levels range from 1-9
155 static unsigned long cs_debugmask = CS_INIT /*| CS_IOCTL*/;
156 MODULE_PARM(cs_debuglevel, "i");
157 MODULE_PARM(cs_debugmask, "i");
158 #endif
159 #define CS_TRUE 1
160 #define CS_FALSE 0
161
162 #define CS_TYPE_ADC 0
163 #define CS_TYPE_DAC 1
164
165 #define SER_BASE (A_SER_BASE_1 + KSEG1)
166 #define SS_CSR(t) (SER_BASE+t)
167 #define SS_TXTBL(t) (SER_BASE+R_SER_TX_TABLE_BASE+(t*8))
168 #define SS_RXTBL(t) (SER_BASE+R_SER_RX_TABLE_BASE+(t*8))
169
170 #define FRAME_BYTES 32
171 #define FRAME_SAMPLE_BYTES 4
172
173 /* Should this be variable? */
174 #define SAMPLE_BUF_SIZE (16*1024)
175 #define SAMPLE_FRAME_COUNT (SAMPLE_BUF_SIZE / FRAME_SAMPLE_BYTES)
176 /* The driver can explode/shrink the frames to/from a smaller sample
177 buffer */
178 #define DMA_BLOAT_FACTOR 1
179 #define DMA_DESCR (SAMPLE_FRAME_COUNT / DMA_BLOAT_FACTOR)
180 #define DMA_BUF_SIZE (DMA_DESCR * FRAME_BYTES)
181
182 /* Use the maxmium count (255 == 5.1 ms between interrupts) */
183 #define DMA_INT_CNT ((1 << S_DMA_INT_PKTCNT) - 1)
184
185 /* Figure this out: how many TX DMAs ahead to schedule a reg access */
186 #define REG_LATENCY 150
187
188 #define FRAME_TX_US 20
189
190 #define SERDMA_NEXTBUF(d,f) (((d)->f+1) % (d)->ringsz)
191
192 static const char invalid_magic[] =
193 KERN_CRIT "cs4297a: invalid magic value\n";
194
195 #define VALIDATE_STATE(s) \
196 ({ \
197 if (!(s) || (s)->magic != CS4297a_MAGIC) { \
198 printk(invalid_magic); \
199 return -ENXIO; \
200 } \
201 })
202
203 struct list_head cs4297a_devs = { &cs4297a_devs, &cs4297a_devs };
204
205 typedef struct serdma_descr_s {
206 u64 descr_a;
207 u64 descr_b;
208 } serdma_descr_t;
209
210 typedef unsigned long paddr_t;
211
212 typedef struct serdma_s {
213 unsigned ringsz;
214 serdma_descr_t *descrtab;
215 serdma_descr_t *descrtab_end;
216 paddr_t descrtab_phys;
217
218 serdma_descr_t *descr_add;
219 serdma_descr_t *descr_rem;
220
221 u64 *dma_buf; // buffer for DMA contents (frames)
222 paddr_t dma_buf_phys;
223 u16 *sample_buf; // tmp buffer for sample conversions
224 u16 *sb_swptr;
225 u16 *sb_hwptr;
226 u16 *sb_end;
227
228 dma_addr_t dmaaddr;
229 // unsigned buforder; // Log base 2 of 'dma_buf' size in bytes..
230 unsigned numfrag; // # of 'fragments' in the buffer.
231 unsigned fragshift; // Log base 2 of fragment size.
232 unsigned hwptr, swptr;
233 unsigned total_bytes; // # bytes process since open.
234 unsigned blocks; // last returned blocks value GETOPTR
235 unsigned wakeup; // interrupt occurred on block
236 int count;
237 unsigned underrun; // underrun flag
238 unsigned error; // over/underrun
239 wait_queue_head_t wait;
240 wait_queue_head_t reg_wait;
241 // redundant, but makes calculations easier
242 unsigned fragsize; // 2**fragshift..
243 unsigned sbufsz; // 2**buforder.
244 unsigned fragsamples;
245 // OSS stuff
246 unsigned mapped:1; // Buffer mapped in cs4297a_mmap()?
247 unsigned ready:1; // prog_dmabuf_dac()/adc() successful?
248 unsigned endcleared:1;
249 unsigned type:1; // adc or dac buffer (CS_TYPE_XXX)
250 unsigned ossfragshift;
251 int ossmaxfrags;
252 unsigned subdivision;
253 } serdma_t;
254
255 struct cs4297a_state {
256 // magic
257 unsigned int magic;
258
259 struct list_head list;
260
261 // soundcore stuff
262 int dev_audio;
263 int dev_mixer;
264
265 // hardware resources
266 unsigned int irq;
267
268 struct {
269 unsigned int rx_ovrrn; /* FIFO */
270 unsigned int rx_overflow; /* staging buffer */
271 unsigned int tx_underrun;
272 unsigned int rx_bad;
273 unsigned int rx_good;
274 } stats;
275
276 // mixer registers
277 struct {
278 unsigned short vol[10];
279 unsigned int recsrc;
280 unsigned int modcnt;
281 unsigned short micpreamp;
282 } mix;
283
284 // wave stuff
285 struct properties {
286 unsigned fmt;
287 unsigned fmt_original; // original requested format
288 unsigned channels;
289 unsigned rate;
290 } prop_dac, prop_adc;
291 unsigned conversion:1; // conversion from 16 to 8 bit in progress
292 unsigned ena;
293 spinlock_t lock;
294 struct semaphore open_sem;
295 struct semaphore open_sem_adc;
296 struct semaphore open_sem_dac;
297 mode_t open_mode;
298 wait_queue_head_t open_wait;
299 wait_queue_head_t open_wait_adc;
300 wait_queue_head_t open_wait_dac;
301
302 dma_addr_t dmaaddr_sample_buf;
303 unsigned buforder_sample_buf; // Log base 2 of 'dma_buf' size in bytes..
304
305 serdma_t dma_dac, dma_adc;
306
307 volatile u16 read_value;
308 volatile u16 read_reg;
309 volatile u64 reg_request;
310 };
311
312 #if 1
313 #define prog_codec(a,b)
314 #define dealloc_dmabuf(a,b);
315 #endif
316
317 static int prog_dmabuf_adc(struct cs4297a_state *s)
318 {
319 s->dma_adc.ready = 1;
320 return 0;
321 }
322
323
324 static int prog_dmabuf_dac(struct cs4297a_state *s)
325 {
326 s->dma_dac.ready = 1;
327 return 0;
328 }
329
330 static void clear_advance(void *buf, unsigned bsize, unsigned bptr,
331 unsigned len, unsigned char c)
332 {
333 if (bptr + len > bsize) {
334 unsigned x = bsize - bptr;
335 memset(((char *) buf) + bptr, c, x);
336 bptr = 0;
337 len -= x;
338 }
339 CS_DBGOUT(CS_WAVE_WRITE, 4, printk(KERN_INFO
340 "cs4297a: clear_advance(): memset %d at 0x%.8x for %d size \n",
341 (unsigned)c, (unsigned)((char *) buf) + bptr, len));
342 memset(((char *) buf) + bptr, c, len);
343 }
344
345 #if CSDEBUG
346
347 // DEBUG ROUTINES
348
349 #define SOUND_MIXER_CS_GETDBGLEVEL _SIOWR('M',120, int)
350 #define SOUND_MIXER_CS_SETDBGLEVEL _SIOWR('M',121, int)
351 #define SOUND_MIXER_CS_GETDBGMASK _SIOWR('M',122, int)
352 #define SOUND_MIXER_CS_SETDBGMASK _SIOWR('M',123, int)
353
354 static void cs_printioctl(unsigned int x)
355 {
356 unsigned int i;
357 unsigned char vidx;
358 // Index of mixtable1[] member is Device ID
359 // and must be <= SOUND_MIXER_NRDEVICES.
360 // Value of array member is index into s->mix.vol[]
361 static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = {
362 [SOUND_MIXER_PCM] = 1, // voice
363 [SOUND_MIXER_LINE1] = 2, // AUX
364 [SOUND_MIXER_CD] = 3, // CD
365 [SOUND_MIXER_LINE] = 4, // Line
366 [SOUND_MIXER_SYNTH] = 5, // FM
367 [SOUND_MIXER_MIC] = 6, // Mic
368 [SOUND_MIXER_SPEAKER] = 7, // Speaker
369 [SOUND_MIXER_RECLEV] = 8, // Recording level
370 [SOUND_MIXER_VOLUME] = 9 // Master Volume
371 };
372
373 switch (x) {
374 case SOUND_MIXER_CS_GETDBGMASK:
375 CS_DBGOUT(CS_IOCTL, 4,
376 printk("SOUND_MIXER_CS_GETDBGMASK:\n"));
377 break;
378 case SOUND_MIXER_CS_GETDBGLEVEL:
379 CS_DBGOUT(CS_IOCTL, 4,
380 printk("SOUND_MIXER_CS_GETDBGLEVEL:\n"));
381 break;
382 case SOUND_MIXER_CS_SETDBGMASK:
383 CS_DBGOUT(CS_IOCTL, 4,
384 printk("SOUND_MIXER_CS_SETDBGMASK:\n"));
385 break;
386 case SOUND_MIXER_CS_SETDBGLEVEL:
387 CS_DBGOUT(CS_IOCTL, 4,
388 printk("SOUND_MIXER_CS_SETDBGLEVEL:\n"));
389 break;
390 case OSS_GETVERSION:
391 CS_DBGOUT(CS_IOCTL, 4, printk("OSS_GETVERSION:\n"));
392 break;
393 case SNDCTL_DSP_SYNC:
394 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SYNC:\n"));
395 break;
396 case SNDCTL_DSP_SETDUPLEX:
397 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETDUPLEX:\n"));
398 break;
399 case SNDCTL_DSP_GETCAPS:
400 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETCAPS:\n"));
401 break;
402 case SNDCTL_DSP_RESET:
403 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_RESET:\n"));
404 break;
405 case SNDCTL_DSP_SPEED:
406 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SPEED:\n"));
407 break;
408 case SNDCTL_DSP_STEREO:
409 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_STEREO:\n"));
410 break;
411 case SNDCTL_DSP_CHANNELS:
412 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_CHANNELS:\n"));
413 break;
414 case SNDCTL_DSP_GETFMTS:
415 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETFMTS:\n"));
416 break;
417 case SNDCTL_DSP_SETFMT:
418 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETFMT:\n"));
419 break;
420 case SNDCTL_DSP_POST:
421 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_POST:\n"));
422 break;
423 case SNDCTL_DSP_GETTRIGGER:
424 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETTRIGGER:\n"));
425 break;
426 case SNDCTL_DSP_SETTRIGGER:
427 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETTRIGGER:\n"));
428 break;
429 case SNDCTL_DSP_GETOSPACE:
430 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETOSPACE:\n"));
431 break;
432 case SNDCTL_DSP_GETISPACE:
433 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETISPACE:\n"));
434 break;
435 case SNDCTL_DSP_NONBLOCK:
436 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_NONBLOCK:\n"));
437 break;
438 case SNDCTL_DSP_GETODELAY:
439 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETODELAY:\n"));
440 break;
441 case SNDCTL_DSP_GETIPTR:
442 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETIPTR:\n"));
443 break;
444 case SNDCTL_DSP_GETOPTR:
445 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETOPTR:\n"));
446 break;
447 case SNDCTL_DSP_GETBLKSIZE:
448 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETBLKSIZE:\n"));
449 break;
450 case SNDCTL_DSP_SETFRAGMENT:
451 CS_DBGOUT(CS_IOCTL, 4,
452 printk("SNDCTL_DSP_SETFRAGMENT:\n"));
453 break;
454 case SNDCTL_DSP_SUBDIVIDE:
455 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SUBDIVIDE:\n"));
456 break;
457 case SOUND_PCM_READ_RATE:
458 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_RATE:\n"));
459 break;
460 case SOUND_PCM_READ_CHANNELS:
461 CS_DBGOUT(CS_IOCTL, 4,
462 printk("SOUND_PCM_READ_CHANNELS:\n"));
463 break;
464 case SOUND_PCM_READ_BITS:
465 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_BITS:\n"));
466 break;
467 case SOUND_PCM_WRITE_FILTER:
468 CS_DBGOUT(CS_IOCTL, 4,
469 printk("SOUND_PCM_WRITE_FILTER:\n"));
470 break;
471 case SNDCTL_DSP_SETSYNCRO:
472 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETSYNCRO:\n"));
473 break;
474 case SOUND_PCM_READ_FILTER:
475 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_FILTER:\n"));
476 break;
477 case SOUND_MIXER_PRIVATE1:
478 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE1:\n"));
479 break;
480 case SOUND_MIXER_PRIVATE2:
481 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE2:\n"));
482 break;
483 case SOUND_MIXER_PRIVATE3:
484 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE3:\n"));
485 break;
486 case SOUND_MIXER_PRIVATE4:
487 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE4:\n"));
488 break;
489 case SOUND_MIXER_PRIVATE5:
490 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE5:\n"));
491 break;
492 case SOUND_MIXER_INFO:
493 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_INFO:\n"));
494 break;
495 case SOUND_OLD_MIXER_INFO:
496 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_OLD_MIXER_INFO:\n"));
497 break;
498
499 default:
500 switch (_IOC_NR(x)) {
501 case SOUND_MIXER_VOLUME:
502 CS_DBGOUT(CS_IOCTL, 4,
503 printk("SOUND_MIXER_VOLUME:\n"));
504 break;
505 case SOUND_MIXER_SPEAKER:
506 CS_DBGOUT(CS_IOCTL, 4,
507 printk("SOUND_MIXER_SPEAKER:\n"));
508 break;
509 case SOUND_MIXER_RECLEV:
510 CS_DBGOUT(CS_IOCTL, 4,
511 printk("SOUND_MIXER_RECLEV:\n"));
512 break;
513 case SOUND_MIXER_MIC:
514 CS_DBGOUT(CS_IOCTL, 4,
515 printk("SOUND_MIXER_MIC:\n"));
516 break;
517 case SOUND_MIXER_SYNTH:
518 CS_DBGOUT(CS_IOCTL, 4,
519 printk("SOUND_MIXER_SYNTH:\n"));
520 break;
521 case SOUND_MIXER_RECSRC:
522 CS_DBGOUT(CS_IOCTL, 4,
523 printk("SOUND_MIXER_RECSRC:\n"));
524 break;
525 case SOUND_MIXER_DEVMASK:
526 CS_DBGOUT(CS_IOCTL, 4,
527 printk("SOUND_MIXER_DEVMASK:\n"));
528 break;
529 case SOUND_MIXER_RECMASK:
530 CS_DBGOUT(CS_IOCTL, 4,
531 printk("SOUND_MIXER_RECMASK:\n"));
532 break;
533 case SOUND_MIXER_STEREODEVS:
534 CS_DBGOUT(CS_IOCTL, 4,
535 printk("SOUND_MIXER_STEREODEVS:\n"));
536 break;
537 case SOUND_MIXER_CAPS:
538 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_CAPS:\n"));
539 break;
540 default:
541 i = _IOC_NR(x);
542 if (i >= SOUND_MIXER_NRDEVICES
543 || !(vidx = mixtable1[i])) {
544 CS_DBGOUT(CS_IOCTL, 4, printk
545 ("UNKNOWN IOCTL: 0x%.8x NR=%d\n",
546 x, i));
547 } else {
548 CS_DBGOUT(CS_IOCTL, 4, printk
549 ("SOUND_MIXER_IOCTL AC9x: 0x%.8x NR=%d\n",
550 x, i));
551 }
552 break;
553 }
554 }
555 }
556 #endif
557
558
559 static int ser_init(struct cs4297a_state *s)
560 {
561 int i;
562
563 CS_DBGOUT(CS_INIT, 2,
564 printk(KERN_INFO "cs4297a: Setting up serial parameters\n"));
565
566 out64(M_SYNCSER_CMD_RX_RESET | M_SYNCSER_CMD_TX_RESET, SS_CSR(R_SER_CMD));
567
568 out64(M_SYNCSER_MSB_FIRST, SS_CSR(R_SER_MODE));
569 out64(32, SS_CSR(R_SER_MINFRM_SZ));
570 out64(32, SS_CSR(R_SER_MAXFRM_SZ));
571
572 out64(1, SS_CSR(R_SER_TX_RD_THRSH));
573 out64(4, SS_CSR(R_SER_TX_WR_THRSH));
574 out64(8, SS_CSR(R_SER_RX_RD_THRSH));
575
576 /* This looks good from experimentation */
577 out64((M_SYNCSER_TXSYNC_INT | V_SYNCSER_TXSYNC_DLY(0) | M_SYNCSER_TXCLK_EXT |
578 M_SYNCSER_RXSYNC_INT | V_SYNCSER_RXSYNC_DLY(1) | M_SYNCSER_RXCLK_EXT | M_SYNCSER_RXSYNC_EDGE),
579 SS_CSR(R_SER_LINE_MODE));
580
581 /* This looks good from experimentation */
582 out64(V_SYNCSER_SEQ_COUNT(14) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE,
583 SS_TXTBL(0));
584 out64(V_SYNCSER_SEQ_COUNT(15) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
585 SS_TXTBL(1));
586 out64(V_SYNCSER_SEQ_COUNT(13) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
587 SS_TXTBL(2));
588 out64(V_SYNCSER_SEQ_COUNT( 0) | M_SYNCSER_SEQ_ENABLE |
589 M_SYNCSER_SEQ_STROBE | M_SYNCSER_SEQ_LAST, SS_TXTBL(3));
590
591 out64(V_SYNCSER_SEQ_COUNT(14) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE,
592 SS_RXTBL(0));
593 out64(V_SYNCSER_SEQ_COUNT(15) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
594 SS_RXTBL(1));
595 out64(V_SYNCSER_SEQ_COUNT(13) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
596 SS_RXTBL(2));
597 out64(V_SYNCSER_SEQ_COUNT( 0) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE |
598 M_SYNCSER_SEQ_LAST, SS_RXTBL(3));
599
600 for (i=4; i<16; i++) {
601 /* Just in case... */
602 out64(M_SYNCSER_SEQ_LAST, SS_TXTBL(i));
603 out64(M_SYNCSER_SEQ_LAST, SS_RXTBL(i));
604 }
605
606 return 0;
607 }
608
609 static int init_serdma(serdma_t *dma)
610 {
611 CS_DBGOUT(CS_INIT, 2,
612 printk(KERN_ERR "cs4297a: desc - %d sbufsize - %d dbufsize - %d\n",
613 DMA_DESCR, SAMPLE_BUF_SIZE, DMA_BUF_SIZE));
614
615 /* Descriptors */
616 dma->ringsz = DMA_DESCR;
617 dma->descrtab = kmalloc(dma->ringsz * sizeof(serdma_descr_t), GFP_KERNEL);
618 if (!dma->descrtab) {
619 printk(KERN_ERR "cs4297a: kmalloc descrtab failed\n");
620 return -1;
621 }
622 memset(dma->descrtab, 0, dma->ringsz * sizeof(serdma_descr_t));
623 dma->descrtab_end = dma->descrtab + dma->ringsz;
624 /* XXX bloddy mess, use proper DMA API here ... */
625 dma->descrtab_phys = PHYSADDR((long)dma->descrtab);
626 dma->descr_add = dma->descr_rem = dma->descrtab;
627
628 /* Frame buffer area */
629 dma->dma_buf = kmalloc(DMA_BUF_SIZE, GFP_KERNEL);
630 if (!dma->dma_buf) {
631 printk(KERN_ERR "cs4297a: kmalloc dma_buf failed\n");
632 kfree(dma->descrtab);
633 return -1;
634 }
635 memset(dma->dma_buf, 0, DMA_BUF_SIZE);
636 dma->dma_buf_phys = PHYSADDR((long)dma->dma_buf);
637
638 /* Samples buffer area */
639 dma->sbufsz = SAMPLE_BUF_SIZE;
640 dma->sample_buf = kmalloc(dma->sbufsz, GFP_KERNEL);
641 if (!dma->sample_buf) {
642 printk(KERN_ERR "cs4297a: kmalloc sample_buf failed\n");
643 kfree(dma->descrtab);
644 kfree(dma->dma_buf);
645 return -1;
646 }
647 dma->sb_swptr = dma->sb_hwptr = dma->sample_buf;
648 dma->sb_end = (u16 *)((void *)dma->sample_buf + dma->sbufsz);
649 dma->fragsize = dma->sbufsz >> 1;
650
651 CS_DBGOUT(CS_INIT, 4,
652 printk(KERN_ERR "cs4297a: descrtab - %08x dma_buf - %x sample_buf - %x\n",
653 (int)dma->descrtab, (int)dma->dma_buf,
654 (int)dma->sample_buf));
655
656 return 0;
657 }
658
659 static int dma_init(struct cs4297a_state *s)
660 {
661 int i;
662
663 CS_DBGOUT(CS_INIT, 2,
664 printk(KERN_INFO "cs4297a: Setting up DMA\n"));
665
666 if (init_serdma(&s->dma_adc) ||
667 init_serdma(&s->dma_dac))
668 return -1;
669
670 if (in64(SS_CSR(R_SER_DMA_DSCR_COUNT_RX))||
671 in64(SS_CSR(R_SER_DMA_DSCR_COUNT_TX))) {
672 panic("DMA state corrupted?!");
673 }
674
675 /* Initialize now - the descr/buffer pairings will never
676 change... */
677 for (i=0; i<DMA_DESCR; i++) {
678 s->dma_dac.descrtab[i].descr_a = M_DMA_SERRX_SOP | V_DMA_DSCRA_A_SIZE(1) |
679 (s->dma_dac.dma_buf_phys + i*FRAME_BYTES);
680 s->dma_dac.descrtab[i].descr_b = V_DMA_DSCRB_PKT_SIZE(FRAME_BYTES);
681 s->dma_adc.descrtab[i].descr_a = V_DMA_DSCRA_A_SIZE(1) |
682 (s->dma_adc.dma_buf_phys + i*FRAME_BYTES);
683 s->dma_adc.descrtab[i].descr_b = 0;
684 }
685
686 out64((M_DMA_EOP_INT_EN | V_DMA_INT_PKTCNT(DMA_INT_CNT) |
687 V_DMA_RINGSZ(DMA_DESCR) | M_DMA_TDX_EN),
688 SS_CSR(R_SER_DMA_CONFIG0_RX));
689 out64(M_DMA_L2CA, SS_CSR(R_SER_DMA_CONFIG1_RX));
690 out64(s->dma_adc.descrtab_phys, SS_CSR(R_SER_DMA_DSCR_BASE_RX));
691
692 out64(V_DMA_RINGSZ(DMA_DESCR), SS_CSR(R_SER_DMA_CONFIG0_TX));
693 out64(M_DMA_L2CA | M_DMA_NO_DSCR_UPDT, SS_CSR(R_SER_DMA_CONFIG1_TX));
694 out64(s->dma_dac.descrtab_phys, SS_CSR(R_SER_DMA_DSCR_BASE_TX));
695
696 /* Prep the receive DMA descriptor ring */
697 out64(DMA_DESCR, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
698
699 out64(M_SYNCSER_DMA_RX_EN | M_SYNCSER_DMA_TX_EN, SS_CSR(R_SER_DMA_ENABLE));
700
701 out64((M_SYNCSER_RX_SYNC_ERR | M_SYNCSER_RX_OVERRUN | M_SYNCSER_RX_EOP_COUNT),
702 SS_CSR(R_SER_INT_MASK));
703
704 /* Enable the rx/tx; let the codec warm up to the sync and
705 start sending good frames before the receive FIFO is
706 enabled */
707 out64(M_SYNCSER_CMD_TX_EN, SS_CSR(R_SER_CMD));
708 udelay(1000);
709 out64(M_SYNCSER_CMD_RX_EN | M_SYNCSER_CMD_TX_EN, SS_CSR(R_SER_CMD));
710
711 /* XXXKW is this magic? (the "1" part) */
712 while ((in64(SS_CSR(R_SER_STATUS)) & 0xf1) != 1)
713 ;
714
715 CS_DBGOUT(CS_INIT, 4,
716 printk(KERN_INFO "cs4297a: status: %08x\n",
717 (unsigned int)(in64(SS_CSR(R_SER_STATUS)) & 0xffffffff)));
718
719 return 0;
720 }
721
722 static int serdma_reg_access(struct cs4297a_state *s, u64 data)
723 {
724 serdma_t *d = &s->dma_dac;
725 u64 *data_p;
726 unsigned swptr;
727 int flags;
728 serdma_descr_t *descr;
729
730 if (s->reg_request) {
731 printk(KERN_ERR "cs4297a: attempt to issue multiple reg_access\n");
732 return -1;
733 }
734
735 if (s->ena & FMODE_WRITE) {
736 /* Since a writer has the DSP open, we have to mux the
737 request in */
738 s->reg_request = data;
739 interruptible_sleep_on(&s->dma_dac.reg_wait);
740 /* XXXKW how can I deal with the starvation case where
741 the opener isn't writing? */
742 } else {
743 /* Be safe when changing ring pointers */
744 spin_lock_irqsave(&s->lock, flags);
745 if (d->hwptr != d->swptr) {
746 printk(KERN_ERR "cs4297a: reg access found bookkeeping error (hw/sw = %d/%d\n",
747 d->hwptr, d->swptr);
748 spin_unlock_irqrestore(&s->lock, flags);
749 return -1;
750 }
751 swptr = d->swptr;
752 d->hwptr = d->swptr = (d->swptr + 1) % d->ringsz;
753 spin_unlock_irqrestore(&s->lock, flags);
754
755 descr = &d->descrtab[swptr];
756 data_p = &d->dma_buf[swptr * 4];
757 *data_p = data;
758 out64(1, SS_CSR(R_SER_DMA_DSCR_COUNT_TX));
759 CS_DBGOUT(CS_DESCR, 4,
760 printk(KERN_INFO "cs4297a: add_tx %p (%x -> %x)\n",
761 data_p, swptr, d->hwptr));
762 }
763
764 CS_DBGOUT(CS_FUNCTION, 6,
765 printk(KERN_INFO "cs4297a: serdma_reg_access()-\n"));
766
767 return 0;
768 }
769
770 //****************************************************************************
771 // "cs4297a_read_ac97" -- Reads an AC97 register
772 //****************************************************************************
773 static int cs4297a_read_ac97(struct cs4297a_state *s, u32 offset,
774 u32 * value)
775 {
776 CS_DBGOUT(CS_AC97, 1,
777 printk(KERN_INFO "cs4297a: read reg %2x\n", offset));
778 if (serdma_reg_access(s, (0xCLL << 60) | (1LL << 47) | ((u64)(offset & 0x7F) << 40)))
779 return -1;
780
781 interruptible_sleep_on(&s->dma_adc.reg_wait);
782 *value = s->read_value;
783 CS_DBGOUT(CS_AC97, 2,
784 printk(KERN_INFO "cs4297a: rdr reg %x -> %x\n", s->read_reg, s->read_value));
785
786 return 0;
787 }
788
789
790 //****************************************************************************
791 // "cs4297a_write_ac97()"-- writes an AC97 register
792 //****************************************************************************
793 static int cs4297a_write_ac97(struct cs4297a_state *s, u32 offset,
794 u32 value)
795 {
796 CS_DBGOUT(CS_AC97, 1,
797 printk(KERN_INFO "cs4297a: write reg %2x -> %04x\n", offset, value));
798 return (serdma_reg_access(s, (0xELL << 60) | ((u64)(offset & 0x7F) << 40) | ((value & 0xffff) << 12)));
799 }
800
801 static void stop_dac(struct cs4297a_state *s)
802 {
803 unsigned long flags;
804
805 CS_DBGOUT(CS_WAVE_WRITE, 3, printk(KERN_INFO "cs4297a: stop_dac():\n"));
806 spin_lock_irqsave(&s->lock, flags);
807 s->ena &= ~FMODE_WRITE;
808 #if 0
809 /* XXXKW what do I really want here? My theory for now is
810 that I just flip the "ena" bit, and the interrupt handler
811 will stop processing the xmit channel */
812 out64((s->ena & FMODE_READ) ? M_SYNCSER_DMA_RX_EN : 0,
813 SS_CSR(R_SER_DMA_ENABLE));
814 #endif
815
816 spin_unlock_irqrestore(&s->lock, flags);
817 }
818
819
820 static void start_dac(struct cs4297a_state *s)
821 {
822 unsigned long flags;
823
824 CS_DBGOUT(CS_FUNCTION, 3, printk(KERN_INFO "cs4297a: start_dac()+\n"));
825 spin_lock_irqsave(&s->lock, flags);
826 if (!(s->ena & FMODE_WRITE) && (s->dma_dac.mapped ||
827 (s->dma_dac.count > 0
828 && s->dma_dac.ready))) {
829 s->ena |= FMODE_WRITE;
830 /* XXXKW what do I really want here? My theory for
831 now is that I just flip the "ena" bit, and the
832 interrupt handler will start processing the xmit
833 channel */
834
835 CS_DBGOUT(CS_WAVE_WRITE | CS_PARMS, 8, printk(KERN_INFO
836 "cs4297a: start_dac(): start dma\n"));
837
838 }
839 spin_unlock_irqrestore(&s->lock, flags);
840 CS_DBGOUT(CS_FUNCTION, 3,
841 printk(KERN_INFO "cs4297a: start_dac()-\n"));
842 }
843
844
845 static void stop_adc(struct cs4297a_state *s)
846 {
847 unsigned long flags;
848
849 CS_DBGOUT(CS_FUNCTION, 3,
850 printk(KERN_INFO "cs4297a: stop_adc()+\n"));
851
852 spin_lock_irqsave(&s->lock, flags);
853 s->ena &= ~FMODE_READ;
854
855 if (s->conversion == 1) {
856 s->conversion = 0;
857 s->prop_adc.fmt = s->prop_adc.fmt_original;
858 }
859 /* Nothing to do really, I need to keep the DMA going
860 XXXKW when do I get here, and is there more I should do? */
861 spin_unlock_irqrestore(&s->lock, flags);
862 CS_DBGOUT(CS_FUNCTION, 3,
863 printk(KERN_INFO "cs4297a: stop_adc()-\n"));
864 }
865
866
867 static void start_adc(struct cs4297a_state *s)
868 {
869 unsigned long flags;
870
871 CS_DBGOUT(CS_FUNCTION, 2,
872 printk(KERN_INFO "cs4297a: start_adc()+\n"));
873
874 if (!(s->ena & FMODE_READ) &&
875 (s->dma_adc.mapped || s->dma_adc.count <=
876 (signed) (s->dma_adc.sbufsz - 2 * s->dma_adc.fragsize))
877 && s->dma_adc.ready) {
878 if (s->prop_adc.fmt & AFMT_S8 || s->prop_adc.fmt & AFMT_U8) {
879 //
880 // now only use 16 bit capture, due to truncation issue
881 // in the chip, noticable distortion occurs.
882 // allocate buffer and then convert from 16 bit to
883 // 8 bit for the user buffer.
884 //
885 s->prop_adc.fmt_original = s->prop_adc.fmt;
886 if (s->prop_adc.fmt & AFMT_S8) {
887 s->prop_adc.fmt &= ~AFMT_S8;
888 s->prop_adc.fmt |= AFMT_S16_LE;
889 }
890 if (s->prop_adc.fmt & AFMT_U8) {
891 s->prop_adc.fmt &= ~AFMT_U8;
892 s->prop_adc.fmt |= AFMT_U16_LE;
893 }
894 //
895 // prog_dmabuf_adc performs a stop_adc() but that is
896 // ok since we really haven't started the DMA yet.
897 //
898 prog_codec(s, CS_TYPE_ADC);
899
900 prog_dmabuf_adc(s);
901 s->conversion = 1;
902 }
903 spin_lock_irqsave(&s->lock, flags);
904 s->ena |= FMODE_READ;
905 /* Nothing to do really, I am probably already
906 DMAing... XXXKW when do I get here, and is there
907 more I should do? */
908 spin_unlock_irqrestore(&s->lock, flags);
909
910 CS_DBGOUT(CS_PARMS, 6, printk(KERN_INFO
911 "cs4297a: start_adc(): start adc\n"));
912 }
913 CS_DBGOUT(CS_FUNCTION, 2,
914 printk(KERN_INFO "cs4297a: start_adc()-\n"));
915
916 }
917
918
919 // call with spinlock held!
920 static void cs4297a_update_ptr(struct cs4297a_state *s, int intflag)
921 {
922 int good_diff, diff, diff2;
923 u64 *data_p, data;
924 u32 *s_ptr;
925 unsigned hwptr;
926 u32 status;
927 serdma_t *d;
928 serdma_descr_t *descr;
929
930 // update ADC pointer
931 status = intflag ? in64(SS_CSR(R_SER_STATUS)) : 0;
932
933 if ((s->ena & FMODE_READ) || (status & (M_SYNCSER_RX_EOP_COUNT))) {
934 d = &s->dma_adc;
935 hwptr = (unsigned) (((in64(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) -
936 d->descrtab_phys) / sizeof(serdma_descr_t));
937
938 if (s->ena & FMODE_READ) {
939 CS_DBGOUT(CS_FUNCTION, 2,
940 printk(KERN_INFO "cs4297a: upd_rcv sw->hw->hw %x/%x/%x (int-%d)n",
941 d->swptr, d->hwptr, hwptr, intflag));
942 /* Number of DMA buffers available for software: */
943 diff2 = diff = (d->ringsz + hwptr - d->hwptr) % d->ringsz;
944 d->hwptr = hwptr;
945 good_diff = 0;
946 s_ptr = (u32 *)&(d->dma_buf[d->swptr*4]);
947 descr = &d->descrtab[d->swptr];
948 while (diff2--) {
949 u64 data = *(u64 *)s_ptr;
950 u64 descr_a;
951 u16 left, right;
952 descr_a = descr->descr_a;
953 descr->descr_a &= ~M_DMA_SERRX_SOP;
954 if ((descr_a & M_DMA_DSCRA_A_ADDR) != PHYSADDR((long)s_ptr)) {
955 printk(KERN_ERR "cs4297a: RX Bad address (read)\n");
956 }
957 if (((data & 0x9800000000000000) != 0x9800000000000000) ||
958 (!(descr_a & M_DMA_SERRX_SOP)) ||
959 (G_DMA_DSCRB_PKT_SIZE(descr->descr_b) != FRAME_BYTES)) {
960 s->stats.rx_bad++;
961 printk(KERN_DEBUG "cs4297a: RX Bad attributes (read)\n");
962 continue;
963 }
964 s->stats.rx_good++;
965 if ((data >> 61) == 7) {
966 s->read_value = (data >> 12) & 0xffff;
967 s->read_reg = (data >> 40) & 0x7f;
968 wake_up(&d->reg_wait);
969 }
970 if (d->count && (d->sb_hwptr == d->sb_swptr)) {
971 s->stats.rx_overflow++;
972 printk(KERN_DEBUG "cs4297a: RX overflow\n");
973 continue;
974 }
975 good_diff++;
976 left = ((s_ptr[1] & 0xff) << 8) | ((s_ptr[2] >> 24) & 0xff);
977 right = (s_ptr[2] >> 4) & 0xffff;
978 *d->sb_hwptr++ = left;
979 *d->sb_hwptr++ = right;
980 if (d->sb_hwptr == d->sb_end)
981 d->sb_hwptr = d->sample_buf;
982 descr++;
983 if (descr == d->descrtab_end) {
984 descr = d->descrtab;
985 s_ptr = (u32 *)s->dma_adc.dma_buf;
986 } else {
987 s_ptr += 8;
988 }
989 }
990 d->total_bytes += good_diff * FRAME_SAMPLE_BYTES;
991 d->count += good_diff * FRAME_SAMPLE_BYTES;
992 if (d->count > d->sbufsz) {
993 printk(KERN_ERR "cs4297a: bogus receive overflow!!\n");
994 }
995 d->swptr = (d->swptr + diff) % d->ringsz;
996 out64(diff, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
997 if (d->mapped) {
998 if (d->count >= (signed) d->fragsize)
999 wake_up(&d->wait);
1000 } else {
1001 if (d->count > 0) {
1002 CS_DBGOUT(CS_WAVE_READ, 4,
1003 printk(KERN_INFO
1004 "cs4297a: update count -> %d\n", d->count));
1005 wake_up(&d->wait);
1006 }
1007 }
1008 } else {
1009 /* Receive is going even if no one is
1010 listening (for register accesses and to
1011 avoid FIFO overrun) */
1012 diff2 = diff = (hwptr + d->ringsz - d->hwptr) % d->ringsz;
1013 if (!diff) {
1014 printk(KERN_ERR "cs4297a: RX full or empty?\n");
1015 }
1016
1017 descr = &d->descrtab[d->swptr];
1018 data_p = &d->dma_buf[d->swptr*4];
1019
1020 /* Force this to happen at least once; I got
1021 here because of an interrupt, so there must
1022 be a buffer to process. */
1023 do {
1024 data = *data_p;
1025 if ((descr->descr_a & M_DMA_DSCRA_A_ADDR) != PHYSADDR((long)data_p)) {
1026 printk(KERN_ERR "cs4297a: RX Bad address %d (%llx %lx)\n", d->swptr,
1027 (long long)(descr->descr_a & M_DMA_DSCRA_A_ADDR),
1028 (long)PHYSADDR((long)data_p));
1029 }
1030 if (!(data & (1LL << 63)) ||
1031 !(descr->descr_a & M_DMA_SERRX_SOP) ||
1032 (G_DMA_DSCRB_PKT_SIZE(descr->descr_b) != FRAME_BYTES)) {
1033 s->stats.rx_bad++;
1034 printk(KERN_DEBUG "cs4297a: RX Bad attributes\n");
1035 } else {
1036 s->stats.rx_good++;
1037 if ((data >> 61) == 7) {
1038 s->read_value = (data >> 12) & 0xffff;
1039 s->read_reg = (data >> 40) & 0x7f;
1040 wake_up(&d->reg_wait);
1041 }
1042 }
1043 descr->descr_a &= ~M_DMA_SERRX_SOP;
1044 descr++;
1045 d->swptr++;
1046 data_p += 4;
1047 if (descr == d->descrtab_end) {
1048 descr = d->descrtab;
1049 d->swptr = 0;
1050 data_p = d->dma_buf;
1051 }
1052 out64(1, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
1053 } while (--diff);
1054 d->hwptr = hwptr;
1055
1056 CS_DBGOUT(CS_DESCR, 6,
1057 printk(KERN_INFO "cs4297a: hw/sw %x/%x\n", d->hwptr, d->swptr));
1058 }
1059
1060 CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO
1061 "cs4297a: cs4297a_update_ptr(): s=0x%.8x hwptr=%d total_bytes=%d count=%d \n",
1062 (unsigned)s, d->hwptr,
1063 d->total_bytes, d->count));
1064 }
1065
1066 /* XXXKW worry about s->reg_request -- there is a starvation
1067 case if s->ena has FMODE_WRITE on, but the client isn't
1068 doing writes */
1069
1070 // update DAC pointer
1071 //
1072 // check for end of buffer, means that we are going to wait for another interrupt
1073 // to allow silence to fill the fifos on the part, to keep pops down to a minimum.
1074 //
1075 if (s->ena & FMODE_WRITE) {
1076 serdma_t *d = &s->dma_dac;
1077 hwptr = (unsigned) (((in64(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
1078 d->descrtab_phys) / sizeof(serdma_descr_t));
1079 diff = (d->ringsz + hwptr - d->hwptr) % d->ringsz;
1080 CS_DBGOUT(CS_WAVE_WRITE, 4, printk(KERN_INFO
1081 "cs4297a: cs4297a_update_ptr(): hw/hw/sw %x/%x/%x diff %d count %d\n",
1082 d->hwptr, hwptr, d->swptr, diff, d->count));
1083 d->hwptr = hwptr;
1084 /* XXXKW stereo? conversion? Just assume 2 16-bit samples for now */
1085 d->total_bytes += diff * FRAME_SAMPLE_BYTES;
1086 if (d->mapped) {
1087 d->count += diff * FRAME_SAMPLE_BYTES;
1088 if (d->count >= d->fragsize) {
1089 d->wakeup = 1;
1090 wake_up(&d->wait);
1091 if (d->count > d->sbufsz)
1092 d->count &= d->sbufsz - 1;
1093 }
1094 } else {
1095 d->count -= diff * FRAME_SAMPLE_BYTES;
1096 if (d->count <= 0) {
1097 //
1098 // fill with silence, and do not shut down the DAC.
1099 // Continue to play silence until the _release.
1100 //
1101 CS_DBGOUT(CS_WAVE_WRITE, 6, printk(KERN_INFO
1102 "cs4297a: cs4297a_update_ptr(): memset %d at 0x%.8x for %d size \n",
1103 (unsigned)(s->prop_dac.fmt &
1104 (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0,
1105 (unsigned)d->dma_buf,
1106 d->ringsz));
1107 memset(d->dma_buf, 0, d->ringsz * FRAME_BYTES);
1108 if (d->count < 0) {
1109 d->underrun = 1;
1110 s->stats.tx_underrun++;
1111 d->count = 0;
1112 CS_DBGOUT(CS_ERROR, 9, printk(KERN_INFO
1113 "cs4297a: cs4297a_update_ptr(): underrun\n"));
1114 }
1115 } else if (d->count <=
1116 (signed) d->fragsize
1117 && !d->endcleared) {
1118 /* XXXKW what is this for? */
1119 clear_advance(d->dma_buf,
1120 d->sbufsz,
1121 d->swptr,
1122 d->fragsize,
1123 0);
1124 d->endcleared = 1;
1125 }
1126 if ( (d->count <= (signed) d->sbufsz/2) || intflag)
1127 {
1128 CS_DBGOUT(CS_WAVE_WRITE, 4,
1129 printk(KERN_INFO
1130 "cs4297a: update count -> %d\n", d->count));
1131 wake_up(&d->wait);
1132 }
1133 }
1134 CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO
1135 "cs4297a: cs4297a_update_ptr(): s=0x%.8x hwptr=%d total_bytes=%d count=%d \n",
1136 (unsigned) s, d->hwptr,
1137 d->total_bytes, d->count));
1138 }
1139 }
1140
1141 static int mixer_ioctl(struct cs4297a_state *s, unsigned int cmd,
1142 unsigned long arg)
1143 {
1144 // Index to mixer_src[] is value of AC97 Input Mux Select Reg.
1145 // Value of array member is recording source Device ID Mask.
1146 static const unsigned int mixer_src[8] = {
1147 SOUND_MASK_MIC, SOUND_MASK_CD, 0, SOUND_MASK_LINE1,
1148 SOUND_MASK_LINE, SOUND_MASK_VOLUME, 0, 0
1149 };
1150
1151 // Index of mixtable1[] member is Device ID
1152 // and must be <= SOUND_MIXER_NRDEVICES.
1153 // Value of array member is index into s->mix.vol[]
1154 static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = {
1155 [SOUND_MIXER_PCM] = 1, // voice
1156 [SOUND_MIXER_LINE1] = 2, // AUX
1157 [SOUND_MIXER_CD] = 3, // CD
1158 [SOUND_MIXER_LINE] = 4, // Line
1159 [SOUND_MIXER_SYNTH] = 5, // FM
1160 [SOUND_MIXER_MIC] = 6, // Mic
1161 [SOUND_MIXER_SPEAKER] = 7, // Speaker
1162 [SOUND_MIXER_RECLEV] = 8, // Recording level
1163 [SOUND_MIXER_VOLUME] = 9 // Master Volume
1164 };
1165
1166 static const unsigned mixreg[] = {
1167 AC97_PCMOUT_VOL,
1168 AC97_AUX_VOL,
1169 AC97_CD_VOL,
1170 AC97_LINEIN_VOL
1171 };
1172 unsigned char l, r, rl, rr, vidx;
1173 unsigned char attentbl[11] =
1174 { 63, 42, 26, 17, 14, 11, 8, 6, 4, 2, 0 };
1175 unsigned temp1;
1176 int i, val;
1177
1178 VALIDATE_STATE(s);
1179 CS_DBGOUT(CS_FUNCTION, 4, printk(KERN_INFO
1180 "cs4297a: mixer_ioctl(): s=0x%.8x cmd=0x%.8x\n",
1181 (unsigned) s, cmd));
1182 #if CSDEBUG
1183 cs_printioctl(cmd);
1184 #endif
1185 #if CSDEBUG_INTERFACE
1186
1187 if ((cmd == SOUND_MIXER_CS_GETDBGMASK) ||
1188 (cmd == SOUND_MIXER_CS_SETDBGMASK) ||
1189 (cmd == SOUND_MIXER_CS_GETDBGLEVEL) ||
1190 (cmd == SOUND_MIXER_CS_SETDBGLEVEL))
1191 {
1192 switch (cmd) {
1193
1194 case SOUND_MIXER_CS_GETDBGMASK:
1195 return put_user(cs_debugmask,
1196 (unsigned long *) arg);
1197
1198 case SOUND_MIXER_CS_GETDBGLEVEL:
1199 return put_user(cs_debuglevel,
1200 (unsigned long *) arg);
1201
1202 case SOUND_MIXER_CS_SETDBGMASK:
1203 if (get_user(val, (unsigned long *) arg))
1204 return -EFAULT;
1205 cs_debugmask = val;
1206 return 0;
1207
1208 case SOUND_MIXER_CS_SETDBGLEVEL:
1209 if (get_user(val, (unsigned long *) arg))
1210 return -EFAULT;
1211 cs_debuglevel = val;
1212 return 0;
1213 default:
1214 CS_DBGOUT(CS_ERROR, 1, printk(KERN_INFO
1215 "cs4297a: mixer_ioctl(): ERROR unknown debug cmd\n"));
1216 return 0;
1217 }
1218 }
1219 #endif
1220
1221 if (cmd == SOUND_MIXER_PRIVATE1) {
1222 return -EINVAL;
1223 }
1224 if (cmd == SOUND_MIXER_PRIVATE2) {
1225 // enable/disable/query spatializer
1226 if (get_user(val, (int *) arg))
1227 return -EFAULT;
1228 if (val != -1) {
1229 temp1 = (val & 0x3f) >> 2;
1230 cs4297a_write_ac97(s, AC97_3D_CONTROL, temp1);
1231 cs4297a_read_ac97(s, AC97_GENERAL_PURPOSE,
1232 &temp1);
1233 cs4297a_write_ac97(s, AC97_GENERAL_PURPOSE,
1234 temp1 | 0x2000);
1235 }
1236 cs4297a_read_ac97(s, AC97_3D_CONTROL, &temp1);
1237 return put_user((temp1 << 2) | 3, (int *) arg);
1238 }
1239 if (cmd == SOUND_MIXER_INFO) {
1240 mixer_info info;
1241 strncpy(info.id, "CS4297a", sizeof(info.id));
1242 strncpy(info.name, "Crystal CS4297a", sizeof(info.name));
1243 info.modify_counter = s->mix.modcnt;
1244 if (copy_to_user((void *) arg, &info, sizeof(info)))
1245 return -EFAULT;
1246 return 0;
1247 }
1248 if (cmd == SOUND_OLD_MIXER_INFO) {
1249 _old_mixer_info info;
1250 strncpy(info.id, "CS4297a", sizeof(info.id));
1251 strncpy(info.name, "Crystal CS4297a", sizeof(info.name));
1252 if (copy_to_user((void *) arg, &info, sizeof(info)))
1253 return -EFAULT;
1254 return 0;
1255 }
1256 if (cmd == OSS_GETVERSION)
1257 return put_user(SOUND_VERSION, (int *) arg);
1258
1259 if (_IOC_TYPE(cmd) != 'M' || _SIOC_SIZE(cmd) != sizeof(int))
1260 return -EINVAL;
1261
1262 // If ioctl has only the SIOC_READ bit(bit 31)
1263 // on, process the only-read commands.
1264 if (_SIOC_DIR(cmd) == _SIOC_READ) {
1265 switch (_IOC_NR(cmd)) {
1266 case SOUND_MIXER_RECSRC: // Arg contains a bit for each recording source
1267 cs4297a_read_ac97(s, AC97_RECORD_SELECT,
1268 &temp1);
1269 return put_user(mixer_src[temp1 & 7], (int *) arg);
1270
1271 case SOUND_MIXER_DEVMASK: // Arg contains a bit for each supported device
1272 return put_user(SOUND_MASK_PCM | SOUND_MASK_LINE |
1273 SOUND_MASK_VOLUME | SOUND_MASK_RECLEV,
1274 (int *) arg);
1275
1276 case SOUND_MIXER_RECMASK: // Arg contains a bit for each supported recording source
1277 return put_user(SOUND_MASK_LINE | SOUND_MASK_VOLUME,
1278 (int *) arg);
1279
1280 case SOUND_MIXER_STEREODEVS: // Mixer channels supporting stereo
1281 return put_user(SOUND_MASK_PCM | SOUND_MASK_LINE |
1282 SOUND_MASK_VOLUME | SOUND_MASK_RECLEV,
1283 (int *) arg);
1284
1285 case SOUND_MIXER_CAPS:
1286 return put_user(SOUND_CAP_EXCL_INPUT, (int *) arg);
1287
1288 default:
1289 i = _IOC_NR(cmd);
1290 if (i >= SOUND_MIXER_NRDEVICES
1291 || !(vidx = mixtable1[i]))
1292 return -EINVAL;
1293 return put_user(s->mix.vol[vidx - 1], (int *) arg);
1294 }
1295 }
1296 // If ioctl doesn't have both the SIOC_READ and
1297 // the SIOC_WRITE bit set, return invalid.
1298 if (_SIOC_DIR(cmd) != (_SIOC_READ | _SIOC_WRITE))
1299 return -EINVAL;
1300
1301 // Increment the count of volume writes.
1302 s->mix.modcnt++;
1303
1304 // Isolate the command; it must be a write.
1305 switch (_IOC_NR(cmd)) {
1306
1307 case SOUND_MIXER_RECSRC: // Arg contains a bit for each recording source
1308 if (get_user(val, (int *) arg))
1309 return -EFAULT;
1310 i = hweight32(val); // i = # bits on in val.
1311 if (i != 1) // One & only 1 bit must be on.
1312 return 0;
1313 for (i = 0; i < sizeof(mixer_src) / sizeof(int); i++) {
1314 if (val == mixer_src[i]) {
1315 temp1 = (i << 8) | i;
1316 cs4297a_write_ac97(s,
1317 AC97_RECORD_SELECT,
1318 temp1);
1319 return 0;
1320 }
1321 }
1322 return 0;
1323
1324 case SOUND_MIXER_VOLUME:
1325 if (get_user(val, (int *) arg))
1326 return -EFAULT;
1327 l = val & 0xff;
1328 if (l > 100)
1329 l = 100; // Max soundcard.h vol is 100.
1330 if (l < 6) {
1331 rl = 63;
1332 l = 0;
1333 } else
1334 rl = attentbl[(10 * l) / 100]; // Convert 0-100 vol to 63-0 atten.
1335
1336 r = (val >> 8) & 0xff;
1337 if (r > 100)
1338 r = 100; // Max right volume is 100, too
1339 if (r < 6) {
1340 rr = 63;
1341 r = 0;
1342 } else
1343 rr = attentbl[(10 * r) / 100]; // Convert volume to attenuation.
1344
1345 if ((rl > 60) && (rr > 60)) // If both l & r are 'low',
1346 temp1 = 0x8000; // turn on the mute bit.
1347 else
1348 temp1 = 0;
1349
1350 temp1 |= (rl << 8) | rr;
1351
1352 cs4297a_write_ac97(s, AC97_MASTER_VOL_STEREO, temp1);
1353 cs4297a_write_ac97(s, AC97_PHONE_VOL, temp1);
1354
1355 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1356 s->mix.vol[8] = ((unsigned int) r << 8) | l;
1357 #else
1358 s->mix.vol[8] = val;
1359 #endif
1360 return put_user(s->mix.vol[8], (int *) arg);
1361
1362 case SOUND_MIXER_SPEAKER:
1363 if (get_user(val, (int *) arg))
1364 return -EFAULT;
1365 l = val & 0xff;
1366 if (l > 100)
1367 l = 100;
1368 if (l < 3) {
1369 rl = 0;
1370 l = 0;
1371 } else {
1372 rl = (l * 2 - 5) / 13; // Convert 0-100 range to 0-15.
1373 l = (rl * 13 + 5) / 2;
1374 }
1375
1376 if (rl < 3) {
1377 temp1 = 0x8000;
1378 rl = 0;
1379 } else
1380 temp1 = 0;
1381 rl = 15 - rl; // Convert volume to attenuation.
1382 temp1 |= rl << 1;
1383 cs4297a_write_ac97(s, AC97_PCBEEP_VOL, temp1);
1384
1385 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1386 s->mix.vol[6] = l << 8;
1387 #else
1388 s->mix.vol[6] = val;
1389 #endif
1390 return put_user(s->mix.vol[6], (int *) arg);
1391
1392 case SOUND_MIXER_RECLEV:
1393 if (get_user(val, (int *) arg))
1394 return -EFAULT;
1395 l = val & 0xff;
1396 if (l > 100)
1397 l = 100;
1398 r = (val >> 8) & 0xff;
1399 if (r > 100)
1400 r = 100;
1401 rl = (l * 2 - 5) / 13; // Convert 0-100 scale to 0-15.
1402 rr = (r * 2 - 5) / 13;
1403 if (rl < 3 && rr < 3)
1404 temp1 = 0x8000;
1405 else
1406 temp1 = 0;
1407
1408 temp1 = temp1 | (rl << 8) | rr;
1409 cs4297a_write_ac97(s, AC97_RECORD_GAIN, temp1);
1410
1411 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1412 s->mix.vol[7] = ((unsigned int) r << 8) | l;
1413 #else
1414 s->mix.vol[7] = val;
1415 #endif
1416 return put_user(s->mix.vol[7], (int *) arg);
1417
1418 case SOUND_MIXER_MIC:
1419 if (get_user(val, (int *) arg))
1420 return -EFAULT;
1421 l = val & 0xff;
1422 if (l > 100)
1423 l = 100;
1424 if (l < 1) {
1425 l = 0;
1426 rl = 0;
1427 } else {
1428 rl = ((unsigned) l * 5 - 4) / 16; // Convert 0-100 range to 0-31.
1429 l = (rl * 16 + 4) / 5;
1430 }
1431 cs4297a_read_ac97(s, AC97_MIC_VOL, &temp1);
1432 temp1 &= 0x40; // Isolate 20db gain bit.
1433 if (rl < 3) {
1434 temp1 |= 0x8000;
1435 rl = 0;
1436 }
1437 rl = 31 - rl; // Convert volume to attenuation.
1438 temp1 |= rl;
1439 cs4297a_write_ac97(s, AC97_MIC_VOL, temp1);
1440
1441 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1442 s->mix.vol[5] = val << 8;
1443 #else
1444 s->mix.vol[5] = val;
1445 #endif
1446 return put_user(s->mix.vol[5], (int *) arg);
1447
1448
1449 case SOUND_MIXER_SYNTH:
1450 if (get_user(val, (int *) arg))
1451 return -EFAULT;
1452 l = val & 0xff;
1453 if (l > 100)
1454 l = 100;
1455 if (get_user(val, (int *) arg))
1456 return -EFAULT;
1457 r = (val >> 8) & 0xff;
1458 if (r > 100)
1459 r = 100;
1460 rl = (l * 2 - 11) / 3; // Convert 0-100 range to 0-63.
1461 rr = (r * 2 - 11) / 3;
1462 if (rl < 3) // If l is low, turn on
1463 temp1 = 0x0080; // the mute bit.
1464 else
1465 temp1 = 0;
1466
1467 rl = 63 - rl; // Convert vol to attenuation.
1468 // writel(temp1 | rl, s->pBA0 + FMLVC);
1469 if (rr < 3) // If rr is low, turn on
1470 temp1 = 0x0080; // the mute bit.
1471 else
1472 temp1 = 0;
1473 rr = 63 - rr; // Convert vol to attenuation.
1474 // writel(temp1 | rr, s->pBA0 + FMRVC);
1475
1476 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1477 s->mix.vol[4] = (r << 8) | l;
1478 #else
1479 s->mix.vol[4] = val;
1480 #endif
1481 return put_user(s->mix.vol[4], (int *) arg);
1482
1483
1484 default:
1485 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
1486 "cs4297a: mixer_ioctl(): default\n"));
1487
1488 i = _IOC_NR(cmd);
1489 if (i >= SOUND_MIXER_NRDEVICES || !(vidx = mixtable1[i]))
1490 return -EINVAL;
1491 if (get_user(val, (int *) arg))
1492 return -EFAULT;
1493 l = val & 0xff;
1494 if (l > 100)
1495 l = 100;
1496 if (l < 1) {
1497 l = 0;
1498 rl = 31;
1499 } else
1500 rl = (attentbl[(l * 10) / 100]) >> 1;
1501
1502 r = (val >> 8) & 0xff;
1503 if (r > 100)
1504 r = 100;
1505 if (r < 1) {
1506 r = 0;
1507 rr = 31;
1508 } else
1509 rr = (attentbl[(r * 10) / 100]) >> 1;
1510 if ((rl > 30) && (rr > 30))
1511 temp1 = 0x8000;
1512 else
1513 temp1 = 0;
1514 temp1 = temp1 | (rl << 8) | rr;
1515 cs4297a_write_ac97(s, mixreg[vidx - 1], temp1);
1516
1517 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1518 s->mix.vol[vidx - 1] = ((unsigned int) r << 8) | l;
1519 #else
1520 s->mix.vol[vidx - 1] = val;
1521 #endif
1522 return put_user(s->mix.vol[vidx - 1], (int *) arg);
1523 }
1524 }
1525
1526
1527 // ---------------------------------------------------------------------
1528
1529 static loff_t cs4297a_llseek(struct file *file, loff_t offset, int origin)
1530 {
1531 return -ESPIPE;
1532 }
1533
1534
1535 // ---------------------------------------------------------------------
1536
1537 static int cs4297a_open_mixdev(struct inode *inode, struct file *file)
1538 {
1539 int minor = MINOR(inode->i_rdev);
1540 struct cs4297a_state *s=NULL;
1541 struct list_head *entry;
1542
1543 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 4,
1544 printk(KERN_INFO "cs4297a: cs4297a_open_mixdev()+\n"));
1545
1546 list_for_each(entry, &cs4297a_devs)
1547 {
1548 s = list_entry(entry, struct cs4297a_state, list);
1549 if(s->dev_mixer == minor)
1550 break;
1551 }
1552 if (!s)
1553 {
1554 CS_DBGOUT(CS_FUNCTION | CS_OPEN | CS_ERROR, 2,
1555 printk(KERN_INFO "cs4297a: cs4297a_open_mixdev()- -ENODEV\n"));
1556 return -ENODEV;
1557 }
1558 VALIDATE_STATE(s);
1559 file->private_data = s;
1560 MOD_INC_USE_COUNT;
1561
1562 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 4,
1563 printk(KERN_INFO "cs4297a: cs4297a_open_mixdev()- 0\n"));
1564
1565 return 0;
1566 }
1567
1568
1569 static int cs4297a_release_mixdev(struct inode *inode, struct file *file)
1570 {
1571 struct cs4297a_state *s =
1572 (struct cs4297a_state *) file->private_data;
1573
1574 VALIDATE_STATE(s);
1575 MOD_DEC_USE_COUNT;
1576 return 0;
1577 }
1578
1579
1580 static int cs4297a_ioctl_mixdev(struct inode *inode, struct file *file,
1581 unsigned int cmd, unsigned long arg)
1582 {
1583 return mixer_ioctl((struct cs4297a_state *) file->private_data, cmd,
1584 arg);
1585 }
1586
1587
1588 // ******************************************************************************************
1589 // Mixer file operations struct.
1590 // ******************************************************************************************
1591 static /*const */ struct file_operations cs4297a_mixer_fops = {
1592 llseek:cs4297a_llseek,
1593 ioctl:cs4297a_ioctl_mixdev,
1594 open:cs4297a_open_mixdev,
1595 release:cs4297a_release_mixdev,
1596 };
1597
1598 // ---------------------------------------------------------------------
1599
1600
1601 static int drain_adc(struct cs4297a_state *s, int nonblock)
1602 {
1603 /* This routine serves no purpose currently - any samples
1604 sitting in the receive queue will just be processed by the
1605 background consumer. This would be different if DMA
1606 actually stopped when there were no clients. */
1607 return 0;
1608 }
1609
1610 static int drain_dac(struct cs4297a_state *s, int nonblock)
1611 {
1612 DECLARE_WAITQUEUE(wait, current);
1613 unsigned long flags;
1614 unsigned hwptr;
1615 unsigned tmo;
1616 int count;
1617
1618 if (s->dma_dac.mapped)
1619 return 0;
1620 if (nonblock)
1621 return -EBUSY;
1622 add_wait_queue(&s->dma_dac.wait, &wait);
1623 while ((count = in64(SS_CSR(R_SER_DMA_DSCR_COUNT_TX))) ||
1624 (s->dma_dac.count > 0)) {
1625 if (!signal_pending(current)) {
1626 set_current_state(TASK_INTERRUPTIBLE);
1627 /* XXXKW is this calculation working? */
1628 tmo = ((count * FRAME_TX_US) * HZ) / 1000000;
1629 schedule_timeout(tmo + 1);
1630 } else {
1631 /* XXXKW do I care if there is a signal pending? */
1632 }
1633 }
1634 spin_lock_irqsave(&s->lock, flags);
1635 /* Reset the bookkeeping */
1636 hwptr = (int)(((in64(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
1637 s->dma_dac.descrtab_phys) / sizeof(serdma_descr_t));
1638 s->dma_dac.hwptr = s->dma_dac.swptr = hwptr;
1639 spin_unlock_irqrestore(&s->lock, flags);
1640 remove_wait_queue(&s->dma_dac.wait, &wait);
1641 current->state = TASK_RUNNING;
1642 return 0;
1643 }
1644
1645
1646 // ---------------------------------------------------------------------
1647
1648 static ssize_t cs4297a_read(struct file *file, char *buffer, size_t count,
1649 loff_t * ppos)
1650 {
1651 struct cs4297a_state *s =
1652 (struct cs4297a_state *) file->private_data;
1653 ssize_t ret;
1654 unsigned long flags;
1655 int cnt, count_fr, cnt_by;
1656 unsigned copied = 0;
1657
1658 CS_DBGOUT(CS_FUNCTION | CS_WAVE_READ, 2,
1659 printk(KERN_INFO "cs4297a: cs4297a_read()+ %d \n", count));
1660
1661 VALIDATE_STATE(s);
1662 if (ppos != &file->f_pos)
1663 return -ESPIPE;
1664 if (s->dma_adc.mapped)
1665 return -ENXIO;
1666 if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
1667 return ret;
1668 if (!access_ok(VERIFY_WRITE, buffer, count))
1669 return -EFAULT;
1670 ret = 0;
1671 //
1672 // "count" is the amount of bytes to read (from app), is decremented each loop
1673 // by the amount of bytes that have been returned to the user buffer.
1674 // "cnt" is the running total of each read from the buffer (changes each loop)
1675 // "buffer" points to the app's buffer
1676 // "ret" keeps a running total of the amount of bytes that have been copied
1677 // to the user buffer.
1678 // "copied" is the total bytes copied into the user buffer for each loop.
1679 //
1680 while (count > 0) {
1681 CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO
1682 "_read() count>0 count=%d .count=%d .swptr=%d .hwptr=%d \n",
1683 count, s->dma_adc.count,
1684 s->dma_adc.swptr, s->dma_adc.hwptr));
1685 spin_lock_irqsave(&s->lock, flags);
1686
1687 /* cnt will be the number of available samples (16-bit
1688 stereo); it starts out as the maxmimum consequetive
1689 samples */
1690 cnt = (s->dma_adc.sb_end - s->dma_adc.sb_swptr) / 2;
1691 count_fr = s->dma_adc.count / FRAME_SAMPLE_BYTES;
1692
1693 // dma_adc.count is the current total bytes that have not been read.
1694 // if the amount of unread bytes from the current sw pointer to the
1695 // end of the buffer is greater than the current total bytes that
1696 // have not been read, then set the "cnt" (unread bytes) to the
1697 // amount of unread bytes.
1698
1699 if (count_fr < cnt)
1700 cnt = count_fr;
1701 cnt_by = cnt * FRAME_SAMPLE_BYTES;
1702 spin_unlock_irqrestore(&s->lock, flags);
1703 //
1704 // if we are converting from 8/16 then we need to copy
1705 // twice the number of 16 bit bytes then 8 bit bytes.
1706 //
1707 if (s->conversion) {
1708 if (cnt_by > (count * 2)) {
1709 cnt = (count * 2) / FRAME_SAMPLE_BYTES;
1710 cnt_by = count * 2;
1711 }
1712 } else {
1713 if (cnt_by > count) {
1714 cnt = count / FRAME_SAMPLE_BYTES;
1715 cnt_by = count;
1716 }
1717 }
1718 //
1719 // "cnt" NOW is the smaller of the amount that will be read,
1720 // and the amount that is requested in this read (or partial).
1721 // if there are no bytes in the buffer to read, then start the
1722 // ADC and wait for the interrupt handler to wake us up.
1723 //
1724 if (cnt <= 0) {
1725
1726 // start up the dma engine and then continue back to the top of
1727 // the loop when wake up occurs.
1728 start_adc(s);
1729 if (file->f_flags & O_NONBLOCK)
1730 return ret ? ret : -EAGAIN;
1731 interruptible_sleep_on(&s->dma_adc.wait);
1732 if (signal_pending(current))
1733 return ret ? ret : -ERESTARTSYS;
1734 continue;
1735 }
1736 // there are bytes in the buffer to read.
1737 // copy from the hw buffer over to the user buffer.
1738 // user buffer is designated by "buffer"
1739 // virtual address to copy from is dma_buf+swptr
1740 // the "cnt" is the number of bytes to read.
1741
1742 CS_DBGOUT(CS_WAVE_READ, 2, printk(KERN_INFO
1743 "_read() copy_to cnt=%d count=%d ", cnt_by, count));
1744 CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO
1745 " .sbufsz=%d .count=%d buffer=0x%.8x ret=%d\n",
1746 s->dma_adc.sbufsz, s->dma_adc.count,
1747 (unsigned) buffer, ret));
1748
1749 if (copy_to_user (buffer, ((void *)s->dma_adc.sb_swptr), cnt_by))
1750 return ret ? ret : -EFAULT;
1751 copied = cnt_by;
1752
1753 /* Return the descriptors */
1754 spin_lock_irqsave(&s->lock, flags);
1755 CS_DBGOUT(CS_FUNCTION, 2,
1756 printk(KERN_INFO "cs4297a: upd_rcv sw->hw %x/%x\n", s->dma_adc.swptr, s->dma_adc.hwptr));
1757 s->dma_adc.count -= cnt_by;
1758 s->dma_adc.sb_swptr += cnt * 2;
1759 if (s->dma_adc.sb_swptr == s->dma_adc.sb_end)
1760 s->dma_adc.sb_swptr = s->dma_adc.sample_buf;
1761 spin_unlock_irqrestore(&s->lock, flags);
1762 count -= copied;
1763 buffer += copied;
1764 ret += copied;
1765 start_adc(s);
1766 }
1767 CS_DBGOUT(CS_FUNCTION | CS_WAVE_READ, 2,
1768 printk(KERN_INFO "cs4297a: cs4297a_read()- %d\n", ret));
1769 return ret;
1770 }
1771
1772
1773 static ssize_t cs4297a_write(struct file *file, const char *buffer,
1774 size_t count, loff_t * ppos)
1775 {
1776 struct cs4297a_state *s =
1777 (struct cs4297a_state *) file->private_data;
1778 ssize_t ret;
1779 unsigned long flags;
1780 unsigned swptr, hwptr;
1781 int cnt;
1782
1783 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE, 2,
1784 printk(KERN_INFO "cs4297a: cs4297a_write()+ count=%d\n",
1785 count));
1786 VALIDATE_STATE(s);
1787
1788 if (ppos != &file->f_pos)
1789 return -ESPIPE;
1790 if (s->dma_dac.mapped)
1791 return -ENXIO;
1792 if (!s->dma_dac.ready && (ret = prog_dmabuf_dac(s)))
1793 return ret;
1794 if (!access_ok(VERIFY_READ, buffer, count))
1795 return -EFAULT;
1796 ret = 0;
1797 while (count > 0) {
1798 serdma_t *d = &s->dma_dac;
1799 int copy_cnt;
1800 u32 *s_tmpl;
1801 u32 *t_tmpl;
1802 u32 left, right;
1803 /* XXXKW check system endian here ... */
1804 int swap = (s->prop_dac.fmt == AFMT_S16_LE) || (s->prop_dac.fmt == AFMT_U16_LE);
1805
1806 /* XXXXXX this is broken for BLOAT_FACTOR */
1807 spin_lock_irqsave(&s->lock, flags);
1808 if (d->count < 0) {
1809 d->count = 0;
1810 d->swptr = d->hwptr;
1811 }
1812 if (d->underrun) {
1813 d->underrun = 0;
1814 hwptr = (unsigned) (((in64(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
1815 d->descrtab_phys) / sizeof(serdma_descr_t));
1816 d->swptr = d->hwptr = hwptr;
1817 }
1818 swptr = d->swptr;
1819 cnt = d->sbufsz - (swptr * FRAME_SAMPLE_BYTES);
1820 /* Will this write fill up the buffer? */
1821 if (d->count + cnt > d->sbufsz)
1822 cnt = d->sbufsz - d->count;
1823 spin_unlock_irqrestore(&s->lock, flags);
1824 if (cnt > count)
1825 cnt = count;
1826 if (cnt <= 0) {
1827 start_dac(s);
1828 if (file->f_flags & O_NONBLOCK)
1829 return ret ? ret : -EAGAIN;
1830 interruptible_sleep_on(&d->wait);
1831 if (signal_pending(current))
1832 return ret ? ret : -ERESTARTSYS;
1833 continue;
1834 }
1835 if (copy_from_user(d->sample_buf, buffer, cnt))
1836 return ret ? ret : -EFAULT;
1837
1838 copy_cnt = cnt;
1839 s_tmpl = (u32 *)d->sample_buf;
1840 t_tmpl = (u32 *)(d->dma_buf + (swptr * 4));
1841
1842 /* XXXKW assuming 16-bit stereo! */
1843 do {
1844 t_tmpl[0] = 0x98000000;
1845 left = s_tmpl[0] >> 16;
1846 if (left & 0x8000)
1847 left |= 0xf0000;
1848 right = s_tmpl[0] & 0xffff;
1849 if (right & 0x8000)
1850 right |= 0xf0000;
1851 if (swap) {
1852 t_tmpl[1] = left & 0xff;
1853 t_tmpl[2] = ((left & 0xff00) << 16) | ((right & 0xff) << 12) |
1854 ((right & 0xff00) >> 4);
1855 } else {
1856 t_tmpl[1] = left >> 8;
1857 t_tmpl[2] = ((left & 0xff) << 24) | (right << 4);
1858 }
1859 s_tmpl++;
1860 t_tmpl += 8;
1861 copy_cnt -= 4;
1862 } while (copy_cnt);
1863
1864 /* Mux in any pending read/write accesses */
1865 if (s->reg_request) {
1866 *(u64 *)(d->dma_buf + (swptr * 4)) |= s->reg_request;
1867 s->reg_request = 0;
1868 wake_up(&s->dma_dac.reg_wait);
1869 }
1870
1871 CS_DBGOUT(CS_WAVE_WRITE, 4,
1872 printk(KERN_INFO
1873 "cs4297a: copy in %d to swptr %x\n", cnt, swptr));
1874
1875 swptr = (swptr + (cnt/FRAME_SAMPLE_BYTES)) % d->ringsz;
1876 out64(cnt/FRAME_SAMPLE_BYTES, SS_CSR(R_SER_DMA_DSCR_COUNT_TX));
1877 spin_lock_irqsave(&s->lock, flags);
1878 d->swptr = swptr;
1879 d->count += cnt;
1880 d->endcleared = 0;
1881 spin_unlock_irqrestore(&s->lock, flags);
1882 count -= cnt;
1883 buffer += cnt;
1884 ret += cnt;
1885 start_dac(s);
1886 }
1887 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE, 2,
1888 printk(KERN_INFO "cs4297a: cs4297a_write()- %d\n", ret));
1889 return ret;
1890 }
1891
1892
1893 static unsigned int cs4297a_poll(struct file *file,
1894 struct poll_table_struct *wait)
1895 {
1896 struct cs4297a_state *s =
1897 (struct cs4297a_state *) file->private_data;
1898 unsigned long flags;
1899 unsigned int mask = 0;
1900
1901 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
1902 printk(KERN_INFO "cs4297a: cs4297a_poll()+\n"));
1903 VALIDATE_STATE(s);
1904 if (file->f_mode & FMODE_WRITE) {
1905 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
1906 printk(KERN_INFO
1907 "cs4297a: cs4297a_poll() wait on FMODE_WRITE\n"));
1908 if(!s->dma_dac.ready && prog_dmabuf_dac(s))
1909 return 0;
1910 poll_wait(file, &s->dma_dac.wait, wait);
1911 }
1912 if (file->f_mode & FMODE_READ) {
1913 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
1914 printk(KERN_INFO
1915 "cs4297a: cs4297a_poll() wait on FMODE_READ\n"));
1916 if(!s->dma_dac.ready && prog_dmabuf_adc(s))
1917 return 0;
1918 poll_wait(file, &s->dma_adc.wait, wait);
1919 }
1920 spin_lock_irqsave(&s->lock, flags);
1921 cs4297a_update_ptr(s,CS_FALSE);
1922 if (file->f_mode & FMODE_WRITE) {
1923 if (s->dma_dac.mapped) {
1924 if (s->dma_dac.count >=
1925 (signed) s->dma_dac.fragsize) {
1926 if (s->dma_dac.wakeup)
1927 mask |= POLLOUT | POLLWRNORM;
1928 else
1929 mask = 0;
1930 s->dma_dac.wakeup = 0;
1931 }
1932 } else {
1933 if ((signed) (s->dma_dac.sbufsz/2) >= s->dma_dac.count)
1934 mask |= POLLOUT | POLLWRNORM;
1935 }
1936 } else if (file->f_mode & FMODE_READ) {
1937 if (s->dma_adc.mapped) {
1938 if (s->dma_adc.count >= (signed) s->dma_adc.fragsize)
1939 mask |= POLLIN | POLLRDNORM;
1940 } else {
1941 if (s->dma_adc.count > 0)
1942 mask |= POLLIN | POLLRDNORM;
1943 }
1944 }
1945 spin_unlock_irqrestore(&s->lock, flags);
1946 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
1947 printk(KERN_INFO "cs4297a: cs4297a_poll()- 0x%.8x\n",
1948 mask));
1949 return mask;
1950 }
1951
1952
1953 static int cs4297a_mmap(struct file *file, struct vm_area_struct *vma)
1954 {
1955 /* XXXKW currently no mmap support */
1956 return -EINVAL;
1957 return 0;
1958 }
1959
1960
1961 static int cs4297a_ioctl(struct inode *inode, struct file *file,
1962 unsigned int cmd, unsigned long arg)
1963 {
1964 struct cs4297a_state *s =
1965 (struct cs4297a_state *) file->private_data;
1966 unsigned long flags;
1967 audio_buf_info abinfo;
1968 count_info cinfo;
1969 int val, mapped, ret;
1970
1971 CS_DBGOUT(CS_FUNCTION|CS_IOCTL, 4, printk(KERN_INFO
1972 "cs4297a: cs4297a_ioctl(): file=0x%.8x cmd=0x%.8x\n",
1973 (unsigned) file, cmd));
1974 #if CSDEBUG
1975 cs_printioctl(cmd);
1976 #endif
1977 VALIDATE_STATE(s);
1978 mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
1979 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1980 switch (cmd) {
1981 case OSS_GETVERSION:
1982 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
1983 "cs4297a: cs4297a_ioctl(): SOUND_VERSION=0x%.8x\n",
1984 SOUND_VERSION));
1985 return put_user(SOUND_VERSION, (int *) arg);
1986
1987 case SNDCTL_DSP_SYNC:
1988 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
1989 "cs4297a: cs4297a_ioctl(): DSP_SYNC\n"));
1990 if (file->f_mode & FMODE_WRITE)
1991 return drain_dac(s,
1992 0 /*file->f_flags & O_NONBLOCK */
1993 );
1994 return 0;
1995
1996 case SNDCTL_DSP_SETDUPLEX:
1997 return 0;
1998
1999 case SNDCTL_DSP_GETCAPS:
2000 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME |
2001 DSP_CAP_TRIGGER | DSP_CAP_MMAP,
2002 (int *) arg);
2003
2004 case SNDCTL_DSP_RESET:
2005 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
2006 "cs4297a: cs4297a_ioctl(): DSP_RESET\n"));
2007 if (file->f_mode & FMODE_WRITE) {
2008 stop_dac(s);
2009 synchronize_irq();
2010 s->dma_dac.count = s->dma_dac.total_bytes =
2011 s->dma_dac.blocks = s->dma_dac.wakeup = 0;
2012 s->dma_dac.swptr = s->dma_dac.hwptr =
2013 (int)(((in64(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
2014 s->dma_dac.descrtab_phys) / sizeof(serdma_descr_t));
2015 }
2016 if (file->f_mode & FMODE_READ) {
2017 stop_adc(s);
2018 synchronize_irq();
2019 s->dma_adc.count = s->dma_adc.total_bytes =
2020 s->dma_adc.blocks = s->dma_dac.wakeup = 0;
2021 s->dma_adc.swptr = s->dma_adc.hwptr =
2022 (int)(((in64(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) -
2023 s->dma_adc.descrtab_phys) / sizeof(serdma_descr_t));
2024 }
2025 return 0;
2026
2027 case SNDCTL_DSP_SPEED:
2028 if (get_user(val, (int *) arg))
2029 return -EFAULT;
2030 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2031 "cs4297a: cs4297a_ioctl(): DSP_SPEED val=%d -> 48000\n", val));
2032 val = 48000;
2033 return put_user(val, (int *) arg);
2034
2035 case SNDCTL_DSP_STEREO:
2036 if (get_user(val, (int *) arg))
2037 return -EFAULT;
2038 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2039 "cs4297a: cs4297a_ioctl(): DSP_STEREO val=%d\n", val));
2040 if (file->f_mode & FMODE_READ) {
2041 stop_adc(s);
2042 s->dma_adc.ready = 0;
2043 s->prop_adc.channels = val ? 2 : 1;
2044 }
2045 if (file->f_mode & FMODE_WRITE) {
2046 stop_dac(s);
2047 s->dma_dac.ready = 0;
2048 s->prop_dac.channels = val ? 2 : 1;
2049 }
2050 return 0;
2051
2052 case SNDCTL_DSP_CHANNELS:
2053 if (get_user(val, (int *) arg))
2054 return -EFAULT;
2055 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2056 "cs4297a: cs4297a_ioctl(): DSP_CHANNELS val=%d\n",
2057 val));
2058 if (val != 0) {
2059 if (file->f_mode & FMODE_READ) {
2060 stop_adc(s);
2061 s->dma_adc.ready = 0;
2062 if (val >= 2)
2063 s->prop_adc.channels = 2;
2064 else
2065 s->prop_adc.channels = 1;
2066 }
2067 if (file->f_mode & FMODE_WRITE) {
2068 stop_dac(s);
2069 s->dma_dac.ready = 0;
2070 if (val >= 2)
2071 s->prop_dac.channels = 2;
2072 else
2073 s->prop_dac.channels = 1;
2074 }
2075 }
2076
2077 if (file->f_mode & FMODE_WRITE)
2078 val = s->prop_dac.channels;
2079 else if (file->f_mode & FMODE_READ)
2080 val = s->prop_adc.channels;
2081
2082 return put_user(val, (int *) arg);
2083
2084 case SNDCTL_DSP_GETFMTS: // Returns a mask
2085 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2086 "cs4297a: cs4297a_ioctl(): DSP_GETFMT val=0x%.8x\n",
2087 AFMT_S16_LE | AFMT_U16_LE | AFMT_S8 |
2088 AFMT_U8));
2089 return put_user(AFMT_S16_LE | AFMT_U16_LE | AFMT_S8 |
2090 AFMT_U8, (int *) arg);
2091
2092 case SNDCTL_DSP_SETFMT:
2093 if (get_user(val, (int *) arg))
2094 return -EFAULT;
2095 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2096 "cs4297a: cs4297a_ioctl(): DSP_SETFMT val=0x%.8x\n",
2097 val));
2098 if (val != AFMT_QUERY) {
2099 if (file->f_mode & FMODE_READ) {
2100 stop_adc(s);
2101 s->dma_adc.ready = 0;
2102 if (val != AFMT_S16_LE
2103 && val != AFMT_U16_LE && val != AFMT_S8
2104 && val != AFMT_U8)
2105 val = AFMT_U8;
2106 s->prop_adc.fmt = val;
2107 s->prop_adc.fmt_original = s->prop_adc.fmt;
2108 }
2109 if (file->f_mode & FMODE_WRITE) {
2110 stop_dac(s);
2111 s->dma_dac.ready = 0;
2112 if (val != AFMT_S16_LE
2113 && val != AFMT_U16_LE && val != AFMT_S8
2114 && val != AFMT_U8)
2115 val = AFMT_U8;
2116 s->prop_dac.fmt = val;
2117 s->prop_dac.fmt_original = s->prop_dac.fmt;
2118 }
2119 } else {
2120 if (file->f_mode & FMODE_WRITE)
2121 val = s->prop_dac.fmt_original;
2122 else if (file->f_mode & FMODE_READ)
2123 val = s->prop_adc.fmt_original;
2124 }
2125 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2126 "cs4297a: cs4297a_ioctl(): DSP_SETFMT return val=0x%.8x\n",
2127 val));
2128 return put_user(val, (int *) arg);
2129
2130 case SNDCTL_DSP_POST:
2131 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
2132 "cs4297a: cs4297a_ioctl(): DSP_POST\n"));
2133 return 0;
2134
2135 case SNDCTL_DSP_GETTRIGGER:
2136 val = 0;
2137 if (file->f_mode & s->ena & FMODE_READ)
2138 val |= PCM_ENABLE_INPUT;
2139 if (file->f_mode & s->ena & FMODE_WRITE)
2140 val |= PCM_ENABLE_OUTPUT;
2141 return put_user(val, (int *) arg);
2142
2143 case SNDCTL_DSP_SETTRIGGER:
2144 if (get_user(val, (int *) arg))
2145 return -EFAULT;
2146 if (file->f_mode & FMODE_READ) {
2147 if (val & PCM_ENABLE_INPUT) {
2148 if (!s->dma_adc.ready
2149 && (ret = prog_dmabuf_adc(s)))
2150 return ret;
2151 start_adc(s);
2152 } else
2153 stop_adc(s);
2154 }
2155 if (file->f_mode & FMODE_WRITE) {
2156 if (val & PCM_ENABLE_OUTPUT) {
2157 if (!s->dma_dac.ready
2158 && (ret = prog_dmabuf_dac(s)))
2159 return ret;
2160 start_dac(s);
2161 } else
2162 stop_dac(s);
2163 }
2164 return 0;
2165
2166 case SNDCTL_DSP_GETOSPACE:
2167 if (!(file->f_mode & FMODE_WRITE))
2168 return -EINVAL;
2169 if (!s->dma_dac.ready && (val = prog_dmabuf_dac(s)))
2170 return val;
2171 spin_lock_irqsave(&s->lock, flags);
2172 cs4297a_update_ptr(s,CS_FALSE);
2173 abinfo.fragsize = s->dma_dac.fragsize;
2174 if (s->dma_dac.mapped)
2175 abinfo.bytes = s->dma_dac.sbufsz;
2176 else
2177 abinfo.bytes =
2178 s->dma_dac.sbufsz - s->dma_dac.count;
2179 abinfo.fragstotal = s->dma_dac.numfrag;
2180 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
2181 CS_DBGOUT(CS_FUNCTION | CS_PARMS, 4, printk(KERN_INFO
2182 "cs4297a: cs4297a_ioctl(): GETOSPACE .fragsize=%d .bytes=%d .fragstotal=%d .fragments=%d\n",
2183 abinfo.fragsize,abinfo.bytes,abinfo.fragstotal,
2184 abinfo.fragments));
2185 spin_unlock_irqrestore(&s->lock, flags);
2186 return copy_to_user((void *) arg, &abinfo,
2187 sizeof(abinfo)) ? -EFAULT : 0;
2188
2189 case SNDCTL_DSP_GETISPACE:
2190 if (!(file->f_mode & FMODE_READ))
2191 return -EINVAL;
2192 if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s)))
2193 return val;
2194 spin_lock_irqsave(&s->lock, flags);
2195 cs4297a_update_ptr(s,CS_FALSE);
2196 if (s->conversion) {
2197 abinfo.fragsize = s->dma_adc.fragsize / 2;
2198 abinfo.bytes = s->dma_adc.count / 2;
2199 abinfo.fragstotal = s->dma_adc.numfrag;
2200 abinfo.fragments =
2201 abinfo.bytes >> (s->dma_adc.fragshift - 1);
2202 } else {
2203 abinfo.fragsize = s->dma_adc.fragsize;
2204 abinfo.bytes = s->dma_adc.count;
2205 abinfo.fragstotal = s->dma_adc.numfrag;
2206 abinfo.fragments =
2207 abinfo.bytes >> s->dma_adc.fragshift;
2208 }
2209 spin_unlock_irqrestore(&s->lock, flags);
2210 return copy_to_user((void *) arg, &abinfo,
2211 sizeof(abinfo)) ? -EFAULT : 0;
2212
2213 case SNDCTL_DSP_NONBLOCK:
2214 file->f_flags |= O_NONBLOCK;
2215 return 0;
2216
2217 case SNDCTL_DSP_GETODELAY:
2218 if (!(file->f_mode & FMODE_WRITE))
2219 return -EINVAL;
2220 if(!s->dma_dac.ready && prog_dmabuf_dac(s))
2221 return 0;
2222 spin_lock_irqsave(&s->lock, flags);
2223 cs4297a_update_ptr(s,CS_FALSE);
2224 val = s->dma_dac.count;
2225 spin_unlock_irqrestore(&s->lock, flags);
2226 return put_user(val, (int *) arg);
2227
2228 case SNDCTL_DSP_GETIPTR:
2229 if (!(file->f_mode & FMODE_READ))
2230 return -EINVAL;
2231 if(!s->dma_adc.ready && prog_dmabuf_adc(s))
2232 return 0;
2233 spin_lock_irqsave(&s->lock, flags);
2234 cs4297a_update_ptr(s,CS_FALSE);
2235 cinfo.bytes = s->dma_adc.total_bytes;
2236 if (s->dma_adc.mapped) {
2237 cinfo.blocks =
2238 (cinfo.bytes >> s->dma_adc.fragshift) -
2239 s->dma_adc.blocks;
2240 s->dma_adc.blocks =
2241 cinfo.bytes >> s->dma_adc.fragshift;
2242 } else {
2243 if (s->conversion) {
2244 cinfo.blocks =
2245 s->dma_adc.count /
2246 2 >> (s->dma_adc.fragshift - 1);
2247 } else
2248 cinfo.blocks =
2249 s->dma_adc.count >> s->dma_adc.
2250 fragshift;
2251 }
2252 if (s->conversion)
2253 cinfo.ptr = s->dma_adc.hwptr / 2;
2254 else
2255 cinfo.ptr = s->dma_adc.hwptr;
2256 if (s->dma_adc.mapped)
2257 s->dma_adc.count &= s->dma_adc.fragsize - 1;
2258 spin_unlock_irqrestore(&s->lock, flags);
2259 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
2260
2261 case SNDCTL_DSP_GETOPTR:
2262 if (!(file->f_mode & FMODE_WRITE))
2263 return -EINVAL;
2264 if(!s->dma_dac.ready && prog_dmabuf_dac(s))
2265 return 0;
2266 spin_lock_irqsave(&s->lock, flags);
2267 cs4297a_update_ptr(s,CS_FALSE);
2268 cinfo.bytes = s->dma_dac.total_bytes;
2269 if (s->dma_dac.mapped) {
2270 cinfo.blocks =
2271 (cinfo.bytes >> s->dma_dac.fragshift) -
2272 s->dma_dac.blocks;
2273 s->dma_dac.blocks =
2274 cinfo.bytes >> s->dma_dac.fragshift;
2275 } else {
2276 cinfo.blocks =
2277 s->dma_dac.count >> s->dma_dac.fragshift;
2278 }
2279 cinfo.ptr = s->dma_dac.hwptr;
2280 if (s->dma_dac.mapped)
2281 s->dma_dac.count &= s->dma_dac.fragsize - 1;
2282 spin_unlock_irqrestore(&s->lock, flags);
2283 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
2284
2285 case SNDCTL_DSP_GETBLKSIZE:
2286 if (file->f_mode & FMODE_WRITE) {
2287 if ((val = prog_dmabuf_dac(s)))
2288 return val;
2289 return put_user(s->dma_dac.fragsize, (int *) arg);
2290 }
2291 if ((val = prog_dmabuf_adc(s)))
2292 return val;
2293 if (s->conversion)
2294 return put_user(s->dma_adc.fragsize / 2,
2295 (int *) arg);
2296 else
2297 return put_user(s->dma_adc.fragsize, (int *) arg);
2298
2299 case SNDCTL_DSP_SETFRAGMENT:
2300 if (get_user(val, (int *) arg))
2301 return -EFAULT;
2302 return 0; // Say OK, but do nothing.
2303
2304 case SNDCTL_DSP_SUBDIVIDE:
2305 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision)
2306 || (file->f_mode & FMODE_WRITE
2307 && s->dma_dac.subdivision)) return -EINVAL;
2308 if (get_user(val, (int *) arg))
2309 return -EFAULT;
2310 if (val != 1 && val != 2 && val != 4)
2311 return -EINVAL;
2312 if (file->f_mode & FMODE_READ)
2313 s->dma_adc.subdivision = val;
2314 else if (file->f_mode & FMODE_WRITE)
2315 s->dma_dac.subdivision = val;
2316 return 0;
2317
2318 case SOUND_PCM_READ_RATE:
2319 if (file->f_mode & FMODE_READ)
2320 return put_user(s->prop_adc.rate, (int *) arg);
2321 else if (file->f_mode & FMODE_WRITE)
2322 return put_user(s->prop_dac.rate, (int *) arg);
2323
2324 case SOUND_PCM_READ_CHANNELS:
2325 if (file->f_mode & FMODE_READ)
2326 return put_user(s->prop_adc.channels, (int *) arg);
2327 else if (file->f_mode & FMODE_WRITE)
2328 return put_user(s->prop_dac.channels, (int *) arg);
2329
2330 case SOUND_PCM_READ_BITS:
2331 if (file->f_mode & FMODE_READ)
2332 return
2333 put_user(
2334 (s->prop_adc.
2335 fmt & (AFMT_S8 | AFMT_U8)) ? 8 : 16,
2336 (int *) arg);
2337 else if (file->f_mode & FMODE_WRITE)
2338 return
2339 put_user(
2340 (s->prop_dac.
2341 fmt & (AFMT_S8 | AFMT_U8)) ? 8 : 16,
2342 (int *) arg);
2343
2344 case SOUND_PCM_WRITE_FILTER:
2345 case SNDCTL_DSP_SETSYNCRO:
2346 case SOUND_PCM_READ_FILTER:
2347 return -EINVAL;
2348 }
2349 return mixer_ioctl(s, cmd, arg);
2350 }
2351
2352
2353 static int cs4297a_release(struct inode *inode, struct file *file)
2354 {
2355 struct cs4297a_state *s =
2356 (struct cs4297a_state *) file->private_data;
2357
2358 CS_DBGOUT(CS_FUNCTION | CS_RELEASE, 2, printk(KERN_INFO
2359 "cs4297a: cs4297a_release(): inode=0x%.8x file=0x%.8x f_mode=0x%x\n",
2360 (unsigned) inode, (unsigned) file, file->f_mode));
2361 VALIDATE_STATE(s);
2362
2363 if (file->f_mode & FMODE_WRITE) {
2364 drain_dac(s, file->f_flags & O_NONBLOCK);
2365 down(&s->open_sem_dac);
2366 stop_dac(s);
2367 dealloc_dmabuf(s, &s->dma_dac);
2368 s->open_mode &= ~FMODE_WRITE;
2369 up(&s->open_sem_dac);
2370 wake_up(&s->open_wait_dac);
2371 MOD_DEC_USE_COUNT;
2372 }
2373 if (file->f_mode & FMODE_READ) {
2374 drain_adc(s, file->f_flags & O_NONBLOCK);
2375 down(&s->open_sem_adc);
2376 stop_adc(s);
2377 dealloc_dmabuf(s, &s->dma_adc);
2378 s->open_mode &= ~FMODE_READ;
2379 up(&s->open_sem_adc);
2380 wake_up(&s->open_wait_adc);
2381 MOD_DEC_USE_COUNT;
2382 }
2383 return 0;
2384 }
2385
2386 static int cs4297a_open(struct inode *inode, struct file *file)
2387 {
2388 int minor = MINOR(inode->i_rdev);
2389 struct cs4297a_state *s=NULL;
2390 struct list_head *entry;
2391
2392 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
2393 "cs4297a: cs4297a_open(): inode=0x%.8x file=0x%.8x f_mode=0x%x\n",
2394 (unsigned) inode, (unsigned) file, file->f_mode));
2395 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
2396 "cs4297a: status = %08x\n", (int)in64(SS_CSR(R_SER_STATUS_DEBUG))));
2397
2398 list_for_each(entry, &cs4297a_devs)
2399 {
2400 s = list_entry(entry, struct cs4297a_state, list);
2401
2402 if (!((s->dev_audio ^ minor) & ~0xf))
2403 break;
2404 }
2405 if (entry == &cs4297a_devs)
2406 return -ENODEV;
2407 if (!s) {
2408 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
2409 "cs4297a: cs4297a_open(): Error - unable to find audio state struct\n"));
2410 return -ENODEV;
2411 }
2412 VALIDATE_STATE(s);
2413 file->private_data = s;
2414
2415 // wait for device to become free
2416 if (!(file->f_mode & (FMODE_WRITE | FMODE_READ))) {
2417 CS_DBGOUT(CS_FUNCTION | CS_OPEN | CS_ERROR, 2, printk(KERN_INFO
2418 "cs4297a: cs4297a_open(): Error - must open READ and/or WRITE\n"));
2419 return -ENODEV;
2420 }
2421 if (file->f_mode & FMODE_WRITE) {
2422 if (in64(SS_CSR(R_SER_DMA_DSCR_COUNT_TX)) != 0) {
2423 printk(KERN_ERR "cs4297a: TX pipe needs to drain\n");
2424 while (in64(SS_CSR(R_SER_DMA_DSCR_COUNT_TX)))
2425 ;
2426 }
2427
2428 down(&s->open_sem_dac);
2429 while (s->open_mode & FMODE_WRITE) {
2430 if (file->f_flags & O_NONBLOCK) {
2431 up(&s->open_sem_dac);
2432 return -EBUSY;
2433 }
2434 up(&s->open_sem_dac);
2435 interruptible_sleep_on(&s->open_wait_dac);
2436
2437 if (signal_pending(current)) {
2438 printk("open - sig pending\n");
2439 return -ERESTARTSYS;
2440 }
2441 down(&s->open_sem_dac);
2442 }
2443 }
2444 if (file->f_mode & FMODE_READ) {
2445 down(&s->open_sem_adc);
2446 while (s->open_mode & FMODE_READ) {
2447 if (file->f_flags & O_NONBLOCK) {
2448 up(&s->open_sem_adc);
2449 return -EBUSY;
2450 }
2451 up(&s->open_sem_adc);
2452 interruptible_sleep_on(&s->open_wait_adc);
2453
2454 if (signal_pending(current)) {
2455 printk("open - sig pending\n");
2456 return -ERESTARTSYS;
2457 }
2458 down(&s->open_sem_adc);
2459 }
2460 }
2461 s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
2462 if (file->f_mode & FMODE_READ) {
2463 s->prop_adc.fmt = AFMT_S16_BE;
2464 s->prop_adc.fmt_original = s->prop_adc.fmt;
2465 s->prop_adc.channels = 2;
2466 s->prop_adc.rate = 48000;
2467 s->conversion = 0;
2468 s->ena &= ~FMODE_READ;
2469 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags =
2470 s->dma_adc.subdivision = 0;
2471 up(&s->open_sem_adc);
2472 MOD_INC_USE_COUNT;
2473
2474 if (prog_dmabuf_adc(s)) {
2475 CS_DBGOUT(CS_OPEN | CS_ERROR, 2, printk(KERN_ERR
2476 "cs4297a: adc Program dmabufs failed.\n"));
2477 cs4297a_release(inode, file);
2478 return -ENOMEM;
2479 }
2480 }
2481 if (file->f_mode & FMODE_WRITE) {
2482 s->prop_dac.fmt = AFMT_S16_BE;
2483 s->prop_dac.fmt_original = s->prop_dac.fmt;
2484 s->prop_dac.channels = 2;
2485 s->prop_dac.rate = 48000;
2486 s->conversion = 0;
2487 s->ena &= ~FMODE_WRITE;
2488 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags =
2489 s->dma_dac.subdivision = 0;
2490 up(&s->open_sem_dac);
2491 MOD_INC_USE_COUNT;
2492
2493 if (prog_dmabuf_dac(s)) {
2494 CS_DBGOUT(CS_OPEN | CS_ERROR, 2, printk(KERN_ERR
2495 "cs4297a: dac Program dmabufs failed.\n"));
2496 cs4297a_release(inode, file);
2497 return -ENOMEM;
2498 }
2499 }
2500 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2,
2501 printk(KERN_INFO "cs4297a: cs4297a_open()- 0\n"));
2502 return 0;
2503 }
2504
2505
2506 // ******************************************************************************************
2507 // Wave (audio) file operations struct.
2508 // ******************************************************************************************
2509 static /*const */ struct file_operations cs4297a_audio_fops = {
2510 llseek:cs4297a_llseek,
2511 read:cs4297a_read,
2512 write:cs4297a_write,
2513 poll:cs4297a_poll,
2514 ioctl:cs4297a_ioctl,
2515 mmap:cs4297a_mmap,
2516 open:cs4297a_open,
2517 release:cs4297a_release,
2518 };
2519
2520 static void cs4297a_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2521 {
2522 struct cs4297a_state *s = (struct cs4297a_state *) dev_id;
2523 u32 status;
2524
2525 status = in64(SS_CSR(R_SER_STATUS_DEBUG));
2526
2527 CS_DBGOUT(CS_INTERRUPT, 6, printk(KERN_INFO
2528 "cs4297a: cs4297a_interrupt() HISR=0x%.8x\n", status));
2529
2530 #if 0
2531 /* XXXKW what check *should* be done here? */
2532 if (!(status & (M_SYNCSER_RX_EOP_COUNT | M_SYNCSER_RX_OVERRUN | M_SYNCSER_RX_SYNC_ERR))) {
2533 status = in64(SS_CSR(R_SER_STATUS));
2534 printk(KERN_ERR "cs4297a: unexpected interrupt (status %08x)\n", status);
2535 return;
2536 }
2537 #endif
2538
2539 if (status & M_SYNCSER_RX_SYNC_ERR) {
2540 status = in64(SS_CSR(R_SER_STATUS));
2541 printk(KERN_ERR "cs4297a: rx sync error (status %08x)\n", status);
2542 return;
2543 }
2544
2545 if (status & M_SYNCSER_RX_OVERRUN) {
2546 int newptr, i;
2547 s->stats.rx_ovrrn++;
2548 printk(KERN_ERR "cs4297a: receive FIFO overrun\n");
2549
2550 /* Fix things up: get the receive descriptor pool
2551 clean and give them back to the hardware */
2552 while (in64(SS_CSR(R_SER_DMA_DSCR_COUNT_RX)))
2553 ;
2554 newptr = (unsigned) (((in64(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) -
2555 s->dma_adc.descrtab_phys) / sizeof(serdma_descr_t));
2556 for (i=0; i<DMA_DESCR; i++) {
2557 s->dma_adc.descrtab[i].descr_a &= ~M_DMA_SERRX_SOP;
2558 }
2559 s->dma_adc.swptr = s->dma_adc.hwptr = newptr;
2560 s->dma_adc.count = 0;
2561 s->dma_adc.sb_swptr = s->dma_adc.sb_hwptr = s->dma_adc.sample_buf;
2562 out64(DMA_DESCR, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
2563 }
2564
2565 spin_lock(&s->lock);
2566 cs4297a_update_ptr(s,CS_TRUE);
2567 spin_unlock(&s->lock);
2568
2569 CS_DBGOUT(CS_INTERRUPT, 6, printk(KERN_INFO
2570 "cs4297a: cs4297a_interrupt()-\n"));
2571 }
2572
2573 #if 0
2574 static struct initvol {
2575 int mixch;
2576 int vol;
2577 } initvol[] __initdata = {
2578
2579 {SOUND_MIXER_WRITE_VOLUME, 0x4040},
2580 {SOUND_MIXER_WRITE_PCM, 0x4040},
2581 {SOUND_MIXER_WRITE_SYNTH, 0x4040},
2582 {SOUND_MIXER_WRITE_CD, 0x4040},
2583 {SOUND_MIXER_WRITE_LINE, 0x4040},
2584 {SOUND_MIXER_WRITE_LINE1, 0x4040},
2585 {SOUND_MIXER_WRITE_RECLEV, 0x0000},
2586 {SOUND_MIXER_WRITE_SPEAKER, 0x4040},
2587 {SOUND_MIXER_WRITE_MIC, 0x0000}
2588 };
2589 #endif
2590
2591 static int __init cs4297a_init(void)
2592 {
2593 struct cs4297a_state *s;
2594 u32 pwr, id;
2595 mm_segment_t fs;
2596 int rval;
2597 #ifndef CONFIG_BCM_CS4297A_CSWARM
2598 u64 cfg;
2599 int mdio_val;
2600 #endif
2601
2602 CS_DBGOUT(CS_INIT | CS_FUNCTION, 2, printk(KERN_INFO
2603 "cs4297a: cs4297a_init_module()+ \n"));
2604
2605 #ifndef CONFIG_BCM_CS4297A_CSWARM
2606 mdio_val = in64(KSEG1 + A_MAC_REGISTER(2, R_MAC_MDIO)) &
2607 (M_MAC_MDIO_DIR|M_MAC_MDIO_OUT);
2608
2609 /* Check syscfg for synchronous serial on port 1 */
2610 cfg = in64(KSEG1 + A_SCD_SYSTEM_CFG);
2611 if (!(cfg & M_SYS_SER1_ENABLE)) {
2612 out64(cfg | M_SYS_SER1_ENABLE, KSEG1+A_SCD_SYSTEM_CFG);
2613 cfg = in64(KSEG1 + A_SCD_SYSTEM_CFG);
2614 if (!(cfg & M_SYS_SER1_ENABLE)) {
2615 printk(KERN_INFO "cs4297a: serial port 1 not configured for synchronous operation\n");
2616 return -1;
2617 }
2618
2619 printk(KERN_INFO "cs4297a: serial port 1 switching to synchronous operation\n");
2620
2621 /* Force the codec (on SWARM) to reset by clearing
2622 GENO, preserving MDIO (no effect on CSWARM) */
2623 out64(mdio_val, KSEG1+A_MAC_REGISTER(2, R_MAC_MDIO));
2624 udelay(10);
2625 }
2626
2627 /* Now set GENO */
2628 out64(mdio_val | M_MAC_GENC, KSEG1+A_MAC_REGISTER(2, R_MAC_MDIO));
2629 /* Give the codec some time to finish resetting (start the bit clock) */
2630 udelay(100);
2631 #endif
2632
2633 if (!(s = kmalloc(sizeof(struct cs4297a_state), GFP_KERNEL))) {
2634 CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
2635 "cs4297a: probe() no memory for state struct.\n"));
2636 return -1;
2637 }
2638 memset(s, 0, sizeof(struct cs4297a_state));
2639 s->magic = CS4297a_MAGIC;
2640 init_waitqueue_head(&s->dma_adc.wait);
2641 init_waitqueue_head(&s->dma_dac.wait);
2642 init_waitqueue_head(&s->dma_adc.reg_wait);
2643 init_waitqueue_head(&s->dma_dac.reg_wait);
2644 init_waitqueue_head(&s->open_wait);
2645 init_waitqueue_head(&s->open_wait_adc);
2646 init_waitqueue_head(&s->open_wait_dac);
2647 init_MUTEX(&s->open_sem_adc);
2648 init_MUTEX(&s->open_sem_dac);
2649 spin_lock_init(&s->lock);
2650
2651 s->irq = K_INT_SER_1;
2652
2653 if (request_irq
2654 (s->irq, cs4297a_interrupt, 0, "Crystal CS4297a", s)) {
2655 CS_DBGOUT(CS_INIT | CS_ERROR, 1,
2656 printk(KERN_ERR "cs4297a: irq %u in use\n", s->irq));
2657 goto err_irq;
2658 }
2659 if ((s->dev_audio = register_sound_dsp(&cs4297a_audio_fops, -1)) <
2660 0) {
2661 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
2662 "cs4297a: probe() register_sound_dsp() failed.\n"));
2663 goto err_dev1;
2664 }
2665 if ((s->dev_mixer = register_sound_mixer(&cs4297a_mixer_fops, -1)) <
2666 0) {
2667 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
2668 "cs4297a: probe() register_sound_mixer() failed.\n"));
2669 goto err_dev2;
2670 }
2671
2672 if (ser_init(s) || dma_init(s)) {
2673 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
2674 "cs4297a: ser_init failed.\n"));
2675 goto err_dev3;
2676 }
2677
2678 do {
2679 udelay(4000);
2680 rval = cs4297a_read_ac97(s, AC97_POWER_CONTROL, &pwr);
2681 } while (!rval && (pwr != 0xf));
2682
2683 if (!rval) {
2684 fs = get_fs();
2685 set_fs(KERNEL_DS);
2686 #if 0
2687 val = SOUND_MASK_LINE;
2688 mixer_ioctl(s, SOUND_MIXER_WRITE_RECSRC, (unsigned long) &val);
2689 for (i = 0; i < sizeof(initvol) / sizeof(initvol[0]); i++) {
2690 val = initvol[i].vol;
2691 mixer_ioctl(s, initvol[i].mixch, (unsigned long) &val);
2692 }
2693 // cs4297a_write_ac97(s, 0x18, 0x0808);
2694 #else
2695 // cs4297a_write_ac97(s, 0x5e, 0x180);
2696 cs4297a_write_ac97(s, 0x02, 0x0808);
2697 cs4297a_write_ac97(s, 0x18, 0x0808);
2698 #endif
2699 set_fs(fs);
2700
2701 list_add(&s->list, &cs4297a_devs);
2702
2703 cs4297a_read_ac97(s, AC97_VENDOR_ID1, &id);
2704
2705 printk(KERN_INFO "cs4297a: initialized (vendor id = %x)\n", id);
2706
2707 CS_DBGOUT(CS_INIT | CS_FUNCTION, 2,
2708 printk(KERN_INFO "cs4297a: cs4297a_init_module()-\n"));
2709
2710 return 0;
2711 }
2712
2713 err_dev3:
2714 unregister_sound_mixer(s->dev_mixer);
2715 err_dev2:
2716 unregister_sound_dsp(s->dev_audio);
2717 err_dev1:
2718 free_irq(s->irq, s);
2719 err_irq:
2720 kfree(s);
2721
2722 printk(KERN_INFO "cs4297a: initialization failed\n");
2723
2724 return -1;
2725 }
2726
2727 static void __exit cs4297a_cleanup(void)
2728 {
2729 /*
2730 XXXKW
2731 disable_irq, free_irq
2732 drain DMA queue
2733 disable DMA
2734 disable TX/RX
2735 free memory
2736 */
2737 CS_DBGOUT(CS_INIT | CS_FUNCTION, 2,
2738 printk(KERN_INFO "cs4297a: cleanup_cs4297a() finished\n"));
2739 }
2740
2741 // ---------------------------------------------------------------------
2742
2743 EXPORT_NO_SYMBOLS;
2744
2745 MODULE_AUTHOR("Kip Walker, kwalker@broadcom.com");
2746 MODULE_DESCRIPTION("Cirrus Logic CS4297a Driver for Broadcom SWARM board");
2747
2748 // ---------------------------------------------------------------------
2749
2750 module_init(cs4297a_init);
2751 module_exit(cs4297a_cleanup);
Mirror of the linux-mips.org kernel tree