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Pull one more egcs 1.1.2 workaround.
[linux-2.6/linux-mips.git] / sound / oss / ite8172.c
blob26a27580a4f084314451cca5c8c60200fd4f4630
1 /*
2 * ite8172.c -- ITE IT8172G Sound Driver.
3 *
4 * Copyright 2001 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc.
6 * stevel@mvista.com or source@mvista.com
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 *
28 *
29 * Module command line parameters:
30 *
31 * Supported devices:
32 * /dev/dsp standard OSS /dev/dsp device
33 * /dev/mixer standard OSS /dev/mixer device
34 *
35 * Notes:
36 *
37 * 1. Much of the OSS buffer allocation, ioctl's, and mmap'ing are
38 * taken, slightly modified or not at all, from the ES1371 driver,
39 * so refer to the credits in es1371.c for those. The rest of the
40 * code (probe, open, read, write, the ISR, etc.) is new.
41 * 2. The following support is untested:
42 * * Memory mapping the audio buffers, and the ioctl controls that go
43 * with it.
44 * * S/PDIF output.
45 * * I2S support.
46 * 3. The following is not supported:
47 * * legacy audio mode.
48 * 4. Support for volume button interrupts is implemented but doesn't
49 * work yet.
50 *
51 * Revision history
52 * 02.08.2001 Initial release
53 * 06.22.2001 Added I2S support
54 */
55 #include <linux/version.h>
56 #include <linux/module.h>
57 #include <linux/string.h>
58 #include <linux/ioport.h>
59 #include <linux/sched.h>
60 #include <linux/delay.h>
61 #include <linux/sound.h>
62 #include <linux/slab.h>
63 #include <linux/soundcard.h>
64 #include <linux/pci.h>
65 #include <linux/init.h>
66 #include <linux/poll.h>
67 #include <linux/bitops.h>
68 #include <linux/proc_fs.h>
69 #include <linux/spinlock.h>
70 #include <linux/smp_lock.h>
71 #include <linux/ac97_codec.h>
72 #include <linux/wrapper.h>
73 #include <asm/io.h>
74 #include <asm/dma.h>
75 #include <asm/uaccess.h>
76 #include <asm/hardirq.h>
77 #include <asm/it8172/it8172.h>
78
79 /* --------------------------------------------------------------------- */
80
81 #undef OSS_DOCUMENTED_MIXER_SEMANTICS
82 #define IT8172_DEBUG
83 #undef IT8172_VERBOSE_DEBUG
84 #define DBG(x) {}
85
86 #define IT8172_MODULE_NAME "IT8172 audio"
87 #define PFX IT8172_MODULE_NAME
88
89 #ifdef IT8172_DEBUG
90 #define dbg(format, arg...) printk(KERN_DEBUG PFX ": " format "\n" , ## arg)
91 #else
92 #define dbg(format, arg...) do {} while (0)
93 #endif
94 #define err(format, arg...) printk(KERN_ERR PFX ": " format "\n" , ## arg)
95 #define info(format, arg...) printk(KERN_INFO PFX ": " format "\n" , ## arg)
96 #define warn(format, arg...) printk(KERN_WARNING PFX ": " format "\n" , ## arg)
97
98
99 static const unsigned sample_shift[] = { 0, 1, 1, 2 };
100
101
102 /*
103 * Audio Controller register bit definitions follow. See
104 * include/asm/it8172/it8172.h for register offsets.
105 */
106
107 /* PCM Out Volume Reg */
108 #define PCMOV_PCMOM (1<<15) /* PCM Out Mute default 1: mute */
109 #define PCMOV_PCMRCG_BIT 8 /* PCM Right channel Gain */
110 #define PCMOV_PCMRCG_MASK (0x1f<<PCMOV_PCMRCG_BIT)
111 #define PCMOV_PCMLCG_BIT 0 /* PCM Left channel gain */
112 #define PCMOV_PCMLCG_MASK 0x1f
113
114 /* FM Out Volume Reg */
115 #define FMOV_FMOM (1<<15) /* FM Out Mute default 1: mute */
116 #define FMOV_FMRCG_BIT 8 /* FM Right channel Gain */
117 #define FMOV_FMRCG_MASK (0x1f<<FMOV_FMRCG_BIT)
118 #define FMOV_FMLCG_BIT 0 /* FM Left channel gain */
119 #define FMOV_FMLCG_MASK 0x1f
120
121 /* I2S Out Volume Reg */
122 #define I2SV_I2SOM (1<<15) /* I2S Out Mute default 1: mute */
123 #define I2SV_I2SRCG_BIT 8 /* I2S Right channel Gain */
124 #define I2SV_I2SRCG_MASK (0x1f<<I2SV_I2SRCG_BIT)
125 #define I2SV_I2SLCG_BIT 0 /* I2S Left channel gain */
126 #define I2SV_I2SLCG_MASK 0x1f
127
128 /* Digital Recording Source Select Reg */
129 #define DRSS_BIT 0
130 #define DRSS_MASK 0x07
131 #define DRSS_AC97_PRIM 0
132 #define DRSS_FM 1
133 #define DRSS_I2S 2
134 #define DRSS_PCM 3
135 #define DRSS_AC97_SEC 4
136
137 /* Playback/Capture Channel Control Registers */
138 #define CC_SM (1<<15) /* Stereo, Mone 0: mono 1: stereo */
139 #define CC_DF (1<<14) /* Data Format 0: 8 bit 1: 16 bit */
140 #define CC_FMT_BIT 14
141 #define CC_FMT_MASK (0x03<<CC_FMT_BIT)
142 #define CC_CF_BIT 12 /* Channel format (Playback only) */
143 #define CC_CF_MASK (0x03<<CC_CF_BIT)
144 #define CC_CF_2 0
145 #define CC_CF_4 (1<<CC_CF_BIT)
146 #define CC_CF_6 (2<<CC_CF_BIT)
147 #define CC_SR_BIT 8 /* sample Rate */
148 #define CC_SR_MASK (0x0f<<CC_SR_BIT)
149 #define CC_SR_5500 0
150 #define CC_SR_8000 (1<<CC_SR_BIT)
151 #define CC_SR_9600 (2<<CC_SR_BIT)
152 #define CC_SR_11025 (3<<CC_SR_BIT)
153 #define CC_SR_16000 (4<<CC_SR_BIT)
154 #define CC_SR_19200 (5<<CC_SR_BIT)
155 #define CC_SR_22050 (6<<CC_SR_BIT)
156 #define CC_SR_32000 (7<<CC_SR_BIT)
157 #define CC_SR_38400 (8<<CC_SR_BIT)
158 #define CC_SR_44100 (9<<CC_SR_BIT)
159 #define CC_SR_48000 (10<<CC_SR_BIT)
160 #define CC_CSP (1<<7) /* Channel stop
161 * 0: End of Current buffer
162 * 1: Immediately stop when rec stop */
163 #define CC_CP (1<<6) /* Channel pause 0: normal, 1: pause */
164 #define CC_CA (1<<5) /* Channel Action 0: Stop , 1: start */
165 #define CC_CB2L (1<<2) /* Cur. buf. 2 xfr is last 0: No, 1: Yes */
166 #define CC_CB1L (1<<1) /* Cur. buf. 1 xfr is last 0: No, 1: Yes */
167 #define CC_DE 1 /* DFC/DFIFO Data Empty 1: empty, 0: not empty
168 * (Playback only)
169 */
170
171 /* Codec Control Reg */
172 #define CODECC_GME (1<<9) /* AC97 GPIO Mode enable */
173 #define CODECC_ATM (1<<8) /* AC97 ATE test mode 0: test 1: normal */
174 #define CODECC_WR (1<<6) /* AC97 Warn reset 1: warm reset , 0: Normal */
175 #define CODECC_CR (1<<5) /* AC97 Cold reset 1: Cold reset , 0: Normal */
176
177
178 /* I2S Control Reg */
179 #define I2SMC_SR_BIT 6 /* I2S Sampling rate
180 * 00: 48KHz, 01: 44.1 KHz, 10: 32 32 KHz */
181 #define I2SMC_SR_MASK (0x03<<I2SMC_SR_BIT)
182 #define I2SMC_SR_48000 0
183 #define I2SMC_SR_44100 (1<<I2SMC_SR_BIT)
184 #define I2SMC_SR_32000 (2<<I2SMC_SR_BIT)
185 #define I2SMC_SRSS (1<<5) /* Sample Rate Source Select 1:S/W, 0: H/W */
186 #define I2SMC_I2SF_BIT 0 /* I2S Format */
187 #define I2SMC_I2SF_MASK 0x03
188 #define I2SMC_I2SF_DAC 0
189 #define I2SMC_I2SF_ADC 2
190 #define I2SMC_I2SF_I2S 3
191
192
193 /* Volume up, Down, Mute */
194 #define VS_VMP (1<<2) /* Volume mute 1: pushed, 0: not */
195 #define VS_VDP (1<<1) /* Volume Down 1: pushed, 0: not */
196 #define VS_VUP 1 /* Volime Up 1: pushed, 0: not */
197
198 /* SRC, Mixer test control/DFC status reg */
199 #define SRCS_DPUSC (1<<5) /* DFC Playback underrun Status/clear */
200 #define SRCS_DCOSC (1<<4) /* DFC Capture Overrun Status/clear */
201 #define SRCS_SIS (1<<3) /* SRC input select 1: Mixer, 0: Codec I/F */
202 #define SRCS_CDIS_BIT 0 /* Codec Data Input Select */
203 #define SRCS_CDIS_MASK 0x07
204 #define SRCS_CDIS_MIXER 0
205 #define SRCS_CDIS_PCM 1
206 #define SRCS_CDIS_I2S 2
207 #define SRCS_CDIS_FM 3
208 #define SRCS_CDIS_DFC 4
209
210
211 /* Codec Index Reg command Port */
212 #define CIRCP_CID_BIT 10
213 #define CIRCP_CID_MASK (0x03<<CIRCP_CID_BIT)
214 #define CIRCP_CPS (1<<9) /* Command Port Status 0: ready, 1: busy */
215 #define CIRCP_DPVF (1<<8) /* Data Port Valid Flag 0: invalis, 1: valid */
216 #define CIRCP_RWC (1<<7) /* Read/write command */
217 #define CIRCP_CIA_BIT 0
218 #define CIRCP_CIA_MASK 0x007F /* Codec Index Address */
219
220 /* Test Mode Control/Test group Select Control */
221
222 /* General Control Reg */
223 #define GC_VDC_BIT 6 /* Volume Division Control */
224 #define GC_VDC_MASK (0x03<<GC_VDC_BIT)
225 #define GC_VDC_NONE 0
226 #define GC_VDC_DIV2 (1<<GC_VDC_BIT)
227 #define GC_VDC_DIV4 (2<<GC_VDC_BIT)
228 #define GC_SOE (1<<2) /* S/PDIF Output enable */
229 #define GC_SWR 1 /* Software warn reset */
230
231 /* Interrupt mask Control Reg */
232 #define IMC_VCIM (1<<6) /* Volume CNTL interrupt mask */
233 #define IMC_CCIM (1<<1) /* Capture Chan. iterrupt mask */
234 #define IMC_PCIM 1 /* Playback Chan. interrupt mask */
235
236 /* Interrupt status/clear reg */
237 #define ISC_VCI (1<<6) /* Volume CNTL interrupt 1: clears */
238 #define ISC_CCI (1<<1) /* Capture Chan. interrupt 1: clears */
239 #define ISC_PCI 1 /* Playback Chan. interrupt 1: clears */
240
241 /* misc stuff */
242 #define POLL_COUNT 0x5000
243
244
245 /* --------------------------------------------------------------------- */
246
247 /*
248 * Define DIGITAL1 as the I2S channel, since it is not listed in
249 * soundcard.h.
250 */
251 #define SOUND_MIXER_I2S SOUND_MIXER_DIGITAL1
252 #define SOUND_MASK_I2S SOUND_MASK_DIGITAL1
253 #define SOUND_MIXER_READ_I2S MIXER_READ(SOUND_MIXER_I2S)
254 #define SOUND_MIXER_WRITE_I2S MIXER_WRITE(SOUND_MIXER_I2S)
255
256 /* --------------------------------------------------------------------- */
257
258 struct it8172_state {
259 /* list of it8172 devices */
260 struct list_head devs;
261
262 /* the corresponding pci_dev structure */
263 struct pci_dev *dev;
264
265 /* soundcore stuff */
266 int dev_audio;
267
268 /* hardware resources */
269 unsigned long io;
270 unsigned int irq;
271
272 /* PCI ID's */
273 u16 vendor;
274 u16 device;
275 u8 rev; /* the chip revision */
276
277 /* options */
278 int spdif_volume; /* S/PDIF output is enabled if != -1 */
279 int i2s_volume; /* current I2S out volume, in OSS format */
280 int i2s_recording;/* 1 = recording from I2S, 0 = not */
281
282 #ifdef IT8172_DEBUG
283 /* debug /proc entry */
284 struct proc_dir_entry *ps;
285 struct proc_dir_entry *ac97_ps;
286 #endif /* IT8172_DEBUG */
287
288 struct ac97_codec codec;
289
290 unsigned short pcc, capcc;
291 unsigned dacrate, adcrate;
292
293 spinlock_t lock;
294 struct semaphore open_sem;
295 mode_t open_mode;
296 wait_queue_head_t open_wait;
297
298 struct dmabuf {
299 void *rawbuf;
300 dma_addr_t dmaaddr;
301 unsigned buforder;
302 unsigned numfrag;
303 unsigned fragshift;
304 void* nextIn;
305 void* nextOut;
306 int count;
307 int curBufPtr;
308 unsigned total_bytes;
309 unsigned error; /* over/underrun */
310 wait_queue_head_t wait;
311 /* redundant, but makes calculations easier */
312 unsigned fragsize;
313 unsigned dmasize;
314 unsigned fragsamples;
315 /* OSS stuff */
316 unsigned mapped:1;
317 unsigned ready:1;
318 unsigned stopped:1;
319 unsigned ossfragshift;
320 int ossmaxfrags;
321 unsigned subdivision;
322 } dma_dac, dma_adc;
323 };
324
325 /* --------------------------------------------------------------------- */
326
327 static LIST_HEAD(devs);
328
329 /* --------------------------------------------------------------------- */
330
331 static inline unsigned ld2(unsigned int x)
332 {
333 unsigned r = 0;
334
335 if (x >= 0x10000) {
336 x >>= 16;
337 r += 16;
338 }
339 if (x >= 0x100) {
340 x >>= 8;
341 r += 8;
342 }
343 if (x >= 0x10) {
344 x >>= 4;
345 r += 4;
346 }
347 if (x >= 4) {
348 x >>= 2;
349 r += 2;
350 }
351 if (x >= 2)
352 r++;
353 return r;
354 }
355
356 /* --------------------------------------------------------------------- */
357
358 static void it8172_delay(int msec)
359 {
360 unsigned long tmo;
361 signed long tmo2;
362
363 if (in_interrupt())
364 return;
365
366 tmo = jiffies + (msec*HZ)/1000;
367 for (;;) {
368 tmo2 = tmo - jiffies;
369 if (tmo2 <= 0)
370 break;
371 schedule_timeout(tmo2);
372 }
373 }
374
375
376 static unsigned short
377 get_compat_rate(unsigned* rate)
378 {
379 unsigned rate_out = *rate;
380 unsigned short sr;
381
382 if (rate_out >= 46050) {
383 sr = CC_SR_48000; rate_out = 48000;
384 } else if (rate_out >= 41250) {
385 sr = CC_SR_44100; rate_out = 44100;
386 } else if (rate_out >= 35200) {
387 sr = CC_SR_38400; rate_out = 38400;
388 } else if (rate_out >= 27025) {
389 sr = CC_SR_32000; rate_out = 32000;
390 } else if (rate_out >= 20625) {
391 sr = CC_SR_22050; rate_out = 22050;
392 } else if (rate_out >= 17600) {
393 sr = CC_SR_19200; rate_out = 19200;
394 } else if (rate_out >= 13513) {
395 sr = CC_SR_16000; rate_out = 16000;
396 } else if (rate_out >= 10313) {
397 sr = CC_SR_11025; rate_out = 11025;
398 } else if (rate_out >= 8800) {
399 sr = CC_SR_9600; rate_out = 9600;
400 } else if (rate_out >= 6750) {
401 sr = CC_SR_8000; rate_out = 8000;
402 } else {
403 sr = CC_SR_5500; rate_out = 5500;
404 }
405
406 *rate = rate_out;
407 return sr;
408 }
409
410 static void set_adc_rate(struct it8172_state *s, unsigned rate)
411 {
412 unsigned long flags;
413 unsigned short sr;
414
415 sr = get_compat_rate(&rate);
416
417 spin_lock_irqsave(&s->lock, flags);
418 s->capcc &= ~CC_SR_MASK;
419 s->capcc |= sr;
420 outw(s->capcc, s->io+IT_AC_CAPCC);
421 spin_unlock_irqrestore(&s->lock, flags);
422
423 s->adcrate = rate;
424 }
425
426
427 static void set_dac_rate(struct it8172_state *s, unsigned rate)
428 {
429 unsigned long flags;
430 unsigned short sr;
431
432 sr = get_compat_rate(&rate);
433
434 spin_lock_irqsave(&s->lock, flags);
435 s->pcc &= ~CC_SR_MASK;
436 s->pcc |= sr;
437 outw(s->pcc, s->io+IT_AC_PCC);
438 spin_unlock_irqrestore(&s->lock, flags);
439
440 s->dacrate = rate;
441 }
442
443
444 /* --------------------------------------------------------------------- */
445
446 static u16 rdcodec(struct ac97_codec *codec, u8 addr)
447 {
448 struct it8172_state *s = (struct it8172_state *)codec->private_data;
449 unsigned long flags;
450 unsigned short circp, data;
451 int i;
452
453 spin_lock_irqsave(&s->lock, flags);
454
455 for (i = 0; i < POLL_COUNT; i++)
456 if (!(inw(s->io+IT_AC_CIRCP) & CIRCP_CPS))
457 break;
458 if (i == POLL_COUNT)
459 err("rdcodec: codec ready poll expired!");
460
461 circp = addr & CIRCP_CIA_MASK;
462 circp |= (codec->id << CIRCP_CID_BIT);
463 circp |= CIRCP_RWC; // read command
464 outw(circp, s->io+IT_AC_CIRCP);
465
466 /* now wait for the data */
467 for (i = 0; i < POLL_COUNT; i++)
468 if (inw(s->io+IT_AC_CIRCP) & CIRCP_DPVF)
469 break;
470 if (i == POLL_COUNT)
471 err("rdcodec: read poll expired!");
472
473 data = inw(s->io+IT_AC_CIRDP);
474 spin_unlock_irqrestore(&s->lock, flags);
475
476 return data;
477 }
478
479
480 static void wrcodec(struct ac97_codec *codec, u8 addr, u16 data)
481 {
482 struct it8172_state *s = (struct it8172_state *)codec->private_data;
483 unsigned long flags;
484 unsigned short circp;
485 int i;
486
487 spin_lock_irqsave(&s->lock, flags);
488
489 for (i = 0; i < POLL_COUNT; i++)
490 if (!(inw(s->io+IT_AC_CIRCP) & CIRCP_CPS))
491 break;
492 if (i == POLL_COUNT)
493 err("wrcodec: codec ready poll expired!");
494
495 circp = addr & CIRCP_CIA_MASK;
496 circp |= (codec->id << CIRCP_CID_BIT);
497 circp &= ~CIRCP_RWC; // write command
498
499 outw(data, s->io+IT_AC_CIRDP); // send data first
500 outw(circp, s->io+IT_AC_CIRCP);
501
502 spin_unlock_irqrestore(&s->lock, flags);
503 }
504
505
506 static void waitcodec(struct ac97_codec *codec)
507 {
508 unsigned short temp;
509
510 /* codec_wait is used to wait for a ready state after
511 an AC97_RESET. */
512 it8172_delay(10);
513
514 temp = rdcodec(codec, 0x26);
515
516 // If power down, power up
517 if (temp & 0x3f00) {
518 // Power on
519 wrcodec(codec, 0x26, 0);
520 it8172_delay(100);
521 // Reread
522 temp = rdcodec(codec, 0x26);
523 }
524
525 // Check if Codec REF,ANL,DAC,ADC ready***/
526 if ((temp & 0x3f0f) != 0x000f) {
527 err("codec reg 26 status (0x%x) not ready!!", temp);
528 return;
529 }
530 }
531
532
533 /* --------------------------------------------------------------------- */
534
535 static inline void stop_adc(struct it8172_state *s)
536 {
537 struct dmabuf* db = &s->dma_adc;
538 unsigned long flags;
539 unsigned char imc;
540
541 if (db->stopped)
542 return;
543
544 spin_lock_irqsave(&s->lock, flags);
545
546 s->capcc &= ~(CC_CA | CC_CP | CC_CB2L | CC_CB1L);
547 s->capcc |= CC_CSP;
548 outw(s->capcc, s->io+IT_AC_CAPCC);
549
550 // disable capture interrupt
551 imc = inb(s->io+IT_AC_IMC);
552 outb(imc | IMC_CCIM, s->io+IT_AC_IMC);
553
554 db->stopped = 1;
555
556 spin_unlock_irqrestore(&s->lock, flags);
557 }
558
559 static inline void stop_dac(struct it8172_state *s)
560 {
561 struct dmabuf* db = &s->dma_dac;
562 unsigned long flags;
563 unsigned char imc;
564
565 if (db->stopped)
566 return;
567
568 spin_lock_irqsave(&s->lock, flags);
569
570 s->pcc &= ~(CC_CA | CC_CP | CC_CB2L | CC_CB1L);
571 s->pcc |= CC_CSP;
572 outw(s->pcc, s->io+IT_AC_PCC);
573
574 // disable playback interrupt
575 imc = inb(s->io+IT_AC_IMC);
576 outb(imc | IMC_PCIM, s->io+IT_AC_IMC);
577
578 db->stopped = 1;
579
580 spin_unlock_irqrestore(&s->lock, flags);
581 }
582
583 static void start_dac(struct it8172_state *s)
584 {
585 struct dmabuf* db = &s->dma_dac;
586 unsigned long flags;
587 unsigned char imc;
588 unsigned long buf1, buf2;
589
590 if (!db->stopped)
591 return;
592
593 spin_lock_irqsave(&s->lock, flags);
594
595 // reset Buffer 1 and 2 pointers to nextOut and nextOut+fragsize
596 buf1 = virt_to_bus(db->nextOut);
597 buf2 = buf1 + db->fragsize;
598 if (buf2 >= db->dmaaddr + db->dmasize)
599 buf2 -= db->dmasize;
600
601 outl(buf1, s->io+IT_AC_PCB1STA);
602 outl(buf2, s->io+IT_AC_PCB2STA);
603 db->curBufPtr = IT_AC_PCB1STA;
604
605 // enable playback interrupt
606 imc = inb(s->io+IT_AC_IMC);
607 outb(imc & ~IMC_PCIM, s->io+IT_AC_IMC);
608
609 s->pcc &= ~(CC_CSP | CC_CP | CC_CB2L | CC_CB1L);
610 s->pcc |= CC_CA;
611 outw(s->pcc, s->io+IT_AC_PCC);
612
613 db->stopped = 0;
614
615 spin_unlock_irqrestore(&s->lock, flags);
616 }
617
618 static void start_adc(struct it8172_state *s)
619 {
620 struct dmabuf* db = &s->dma_adc;
621 unsigned long flags;
622 unsigned char imc;
623 unsigned long buf1, buf2;
624
625 if (!db->stopped)
626 return;
627
628 spin_lock_irqsave(&s->lock, flags);
629
630 // reset Buffer 1 and 2 pointers to nextIn and nextIn+fragsize
631 buf1 = virt_to_bus(db->nextIn);
632 buf2 = buf1 + db->fragsize;
633 if (buf2 >= db->dmaaddr + db->dmasize)
634 buf2 -= db->dmasize;
635
636 outl(buf1, s->io+IT_AC_CAPB1STA);
637 outl(buf2, s->io+IT_AC_CAPB2STA);
638 db->curBufPtr = IT_AC_CAPB1STA;
639
640 // enable capture interrupt
641 imc = inb(s->io+IT_AC_IMC);
642 outb(imc & ~IMC_CCIM, s->io+IT_AC_IMC);
643
644 s->capcc &= ~(CC_CSP | CC_CP | CC_CB2L | CC_CB1L);
645 s->capcc |= CC_CA;
646 outw(s->capcc, s->io+IT_AC_CAPCC);
647
648 db->stopped = 0;
649
650 spin_unlock_irqrestore(&s->lock, flags);
651 }
652
653 /* --------------------------------------------------------------------- */
654
655 #define DMABUF_DEFAULTORDER (17-PAGE_SHIFT)
656 #define DMABUF_MINORDER 1
657
658 static inline void dealloc_dmabuf(struct it8172_state *s, struct dmabuf *db)
659 {
660 struct page *page, *pend;
661
662 if (db->rawbuf) {
663 /* undo marking the pages as reserved */
664 pend = virt_to_page(db->rawbuf +
665 (PAGE_SIZE << db->buforder) - 1);
666 for (page = virt_to_page(db->rawbuf); page <= pend; page++)
667 mem_map_unreserve(page);
668 pci_free_consistent(s->dev, PAGE_SIZE << db->buforder,
669 db->rawbuf, db->dmaaddr);
670 }
671 db->rawbuf = db->nextIn = db->nextOut = NULL;
672 db->mapped = db->ready = 0;
673 }
674
675 static int prog_dmabuf(struct it8172_state *s, struct dmabuf *db,
676 unsigned rate, unsigned fmt, unsigned reg)
677 {
678 int order;
679 unsigned bytepersec;
680 unsigned bufs;
681 struct page *page, *pend;
682
683 if (!db->rawbuf) {
684 db->ready = db->mapped = 0;
685 for (order = DMABUF_DEFAULTORDER;
686 order >= DMABUF_MINORDER; order--)
687 if ((db->rawbuf =
688 pci_alloc_consistent(s->dev,
689 PAGE_SIZE << order,
690 &db->dmaaddr)))
691 break;
692 if (!db->rawbuf)
693 return -ENOMEM;
694 db->buforder = order;
695 /* now mark the pages as reserved;
696 otherwise remap_page_range doesn't do what we want */
697 pend = virt_to_page(db->rawbuf +
698 (PAGE_SIZE << db->buforder) - 1);
699 for (page = virt_to_page(db->rawbuf); page <= pend; page++)
700 mem_map_reserve(page);
701 }
702
703 db->count = 0;
704 db->nextIn = db->nextOut = db->rawbuf;
705
706 bytepersec = rate << sample_shift[fmt];
707 bufs = PAGE_SIZE << db->buforder;
708 if (db->ossfragshift) {
709 if ((1000 << db->ossfragshift) < bytepersec)
710 db->fragshift = ld2(bytepersec/1000);
711 else
712 db->fragshift = db->ossfragshift;
713 } else {
714 db->fragshift = ld2(bytepersec/100/(db->subdivision ?
715 db->subdivision : 1));
716 if (db->fragshift < 3)
717 db->fragshift = 3;
718 }
719 db->numfrag = bufs >> db->fragshift;
720 while (db->numfrag < 4 && db->fragshift > 3) {
721 db->fragshift--;
722 db->numfrag = bufs >> db->fragshift;
723 }
724 db->fragsize = 1 << db->fragshift;
725 if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
726 db->numfrag = db->ossmaxfrags;
727 db->fragsamples = db->fragsize >> sample_shift[fmt];
728 db->dmasize = db->numfrag << db->fragshift;
729 memset(db->rawbuf, (fmt & (CC_DF>>CC_FMT_BIT)) ? 0 : 0x80, bufs);
730
731 #ifdef IT8172_VERBOSE_DEBUG
732 dbg("rate=%d, fragsize=%d, numfrag=%d, dmasize=%d",
733 rate, db->fragsize, db->numfrag, db->dmasize);
734 #endif
735
736 // set data length register
737 outw(db->fragsize, s->io+reg+2);
738 db->ready = 1;
739
740 return 0;
741 }
742
743 static inline int prog_dmabuf_adc(struct it8172_state *s)
744 {
745 stop_adc(s);
746 return prog_dmabuf(s, &s->dma_adc, s->adcrate,
747 (s->capcc & CC_FMT_MASK) >> CC_FMT_BIT,
748 IT_AC_CAPCC);
749 }
750
751 static inline int prog_dmabuf_dac(struct it8172_state *s)
752 {
753 stop_dac(s);
754 return prog_dmabuf(s, &s->dma_dac, s->dacrate,
755 (s->pcc & CC_FMT_MASK) >> CC_FMT_BIT,
756 IT_AC_PCC);
757 }
758
759
760 /* hold spinlock for the following! */
761
762 static void it8172_interrupt(int irq, void *dev_id, struct pt_regs *regs)
763 {
764 struct it8172_state *s = (struct it8172_state *)dev_id;
765 struct dmabuf* dac = &s->dma_dac;
766 struct dmabuf* adc = &s->dma_adc;
767 unsigned char isc, vs;
768 unsigned short vol, mute;
769 unsigned long newptr;
770
771 spin_lock(&s->lock);
772
773 isc = inb(s->io+IT_AC_ISC);
774
775 /* fastpath out, to ease interrupt sharing */
776 if (!(isc & (ISC_VCI | ISC_CCI | ISC_PCI))) {
777 spin_unlock(&s->lock);
778 return;
779 }
780
781 /* clear audio interrupts first */
782 outb(isc | ISC_VCI | ISC_CCI | ISC_PCI, s->io+IT_AC_ISC);
783
784 /* handle volume button events (ignore if S/PDIF enabled) */
785 if ((isc & ISC_VCI) && s->spdif_volume == -1) {
786 vs = inb(s->io+IT_AC_VS);
787 outb(0, s->io+IT_AC_VS);
788 vol = inw(s->io+IT_AC_PCMOV);
789 mute = vol & PCMOV_PCMOM;
790 vol &= PCMOV_PCMLCG_MASK;
791 if ((vs & VS_VUP) && vol > 0)
792 vol--;
793 if ((vs & VS_VDP) && vol < 0x1f)
794 vol++;
795 vol |= (vol << PCMOV_PCMRCG_BIT);
796 if (vs & VS_VMP)
797 vol |= (mute ^ PCMOV_PCMOM);
798 outw(vol, s->io+IT_AC_PCMOV);
799 }
800
801 /* update capture pointers */
802 if (isc & ISC_CCI) {
803 if (adc->count > adc->dmasize - adc->fragsize) {
804 // Overrun. Stop ADC and log the error
805 stop_adc(s);
806 adc->error++;
807 dbg("adc overrun");
808 } else {
809 newptr = virt_to_bus(adc->nextIn) + 2*adc->fragsize;
810 if (newptr >= adc->dmaaddr + adc->dmasize)
811 newptr -= adc->dmasize;
812
813 outl(newptr, s->io+adc->curBufPtr);
814 adc->curBufPtr = (adc->curBufPtr == IT_AC_CAPB1STA) ?
815 IT_AC_CAPB2STA : IT_AC_CAPB1STA;
816
817 adc->nextIn += adc->fragsize;
818 if (adc->nextIn >= adc->rawbuf + adc->dmasize)
819 adc->nextIn -= adc->dmasize;
820
821 adc->count += adc->fragsize;
822 adc->total_bytes += adc->fragsize;
823
824 /* wake up anybody listening */
825 if (waitqueue_active(&adc->wait))
826 wake_up_interruptible(&adc->wait);
827 }
828 }
829
830 /* update playback pointers */
831 if (isc & ISC_PCI) {
832 newptr = virt_to_bus(dac->nextOut) + 2*dac->fragsize;
833 if (newptr >= dac->dmaaddr + dac->dmasize)
834 newptr -= dac->dmasize;
835
836 outl(newptr, s->io+dac->curBufPtr);
837 dac->curBufPtr = (dac->curBufPtr == IT_AC_PCB1STA) ?
838 IT_AC_PCB2STA : IT_AC_PCB1STA;
839
840 dac->nextOut += dac->fragsize;
841 if (dac->nextOut >= dac->rawbuf + dac->dmasize)
842 dac->nextOut -= dac->dmasize;
843
844 dac->count -= dac->fragsize;
845 dac->total_bytes += dac->fragsize;
846
847 /* wake up anybody listening */
848 if (waitqueue_active(&dac->wait))
849 wake_up_interruptible(&dac->wait);
850
851 if (dac->count <= 0)
852 stop_dac(s);
853 }
854
855 spin_unlock(&s->lock);
856 }
857
858 /* --------------------------------------------------------------------- */
859
860 static int it8172_open_mixdev(struct inode *inode, struct file *file)
861 {
862 int minor = minor(inode->i_rdev);
863 struct list_head *list;
864 struct it8172_state *s;
865
866 for (list = devs.next; ; list = list->next) {
867 if (list == &devs)
868 return -ENODEV;
869 s = list_entry(list, struct it8172_state, devs);
870 if (s->codec.dev_mixer == minor)
871 break;
872 }
873 file->private_data = s;
874 return 0;
875 }
876
877 static int it8172_release_mixdev(struct inode *inode, struct file *file)
878 {
879 return 0;
880 }
881
882
883 static u16
884 cvt_ossvol(unsigned int gain)
885 {
886 u16 ret;
887
888 if (gain == 0)
889 return 0;
890
891 if (gain > 100)
892 gain = 100;
893
894 ret = (100 - gain + 32) / 4;
895 ret = ret > 31 ? 31 : ret;
896 return ret;
897 }
898
899
900 static int mixdev_ioctl(struct ac97_codec *codec, unsigned int cmd,
901 unsigned long arg)
902 {
903 struct it8172_state *s = (struct it8172_state *)codec->private_data;
904 unsigned int left, right;
905 unsigned long flags;
906 int val;
907 u16 vol;
908
909 /*
910 * When we are in S/PDIF mode, we want to disable any analog output so
911 * we filter the master/PCM channel volume ioctls.
912 *
913 * Also filter I2S channel, which AC'97 knows nothing about.
914 */
915
916 switch (cmd) {
917 case SOUND_MIXER_WRITE_VOLUME:
918 // if not in S/PDIF mode, pass to AC'97
919 if (s->spdif_volume == -1)
920 break;
921 return 0;
922 case SOUND_MIXER_WRITE_PCM:
923 // if not in S/PDIF mode, pass to AC'97
924 if (s->spdif_volume == -1)
925 break;
926 if (get_user(val, (int *)arg))
927 return -EFAULT;
928 right = ((val >> 8) & 0xff);
929 left = (val & 0xff);
930 if (right > 100)
931 right = 100;
932 if (left > 100)
933 left = 100;
934 s->spdif_volume = (right << 8) | left;
935 vol = cvt_ossvol(left);
936 vol |= (cvt_ossvol(right) << PCMOV_PCMRCG_BIT);
937 if (vol == 0)
938 vol = PCMOV_PCMOM; // mute
939 spin_lock_irqsave(&s->lock, flags);
940 outw(vol, s->io+IT_AC_PCMOV);
941 spin_unlock_irqrestore(&s->lock, flags);
942 return put_user(s->spdif_volume, (int *)arg);
943 case SOUND_MIXER_READ_PCM:
944 // if not in S/PDIF mode, pass to AC'97
945 if (s->spdif_volume == -1)
946 break;
947 return put_user(s->spdif_volume, (int *)arg);
948 case SOUND_MIXER_WRITE_I2S:
949 if (get_user(val, (int *)arg))
950 return -EFAULT;
951 right = ((val >> 8) & 0xff);
952 left = (val & 0xff);
953 if (right > 100)
954 right = 100;
955 if (left > 100)
956 left = 100;
957 s->i2s_volume = (right << 8) | left;
958 vol = cvt_ossvol(left);
959 vol |= (cvt_ossvol(right) << I2SV_I2SRCG_BIT);
960 if (vol == 0)
961 vol = I2SV_I2SOM; // mute
962 outw(vol, s->io+IT_AC_I2SV);
963 return put_user(s->i2s_volume, (int *)arg);
964 case SOUND_MIXER_READ_I2S:
965 return put_user(s->i2s_volume, (int *)arg);
966 case SOUND_MIXER_WRITE_RECSRC:
967 if (get_user(val, (int *)arg))
968 return -EFAULT;
969 if (val & SOUND_MASK_I2S) {
970 s->i2s_recording = 1;
971 outb(DRSS_I2S, s->io+IT_AC_DRSS);
972 return 0;
973 } else {
974 s->i2s_recording = 0;
975 outb(DRSS_AC97_PRIM, s->io+IT_AC_DRSS);
976 // now let AC'97 select record source
977 break;
978 }
979 case SOUND_MIXER_READ_RECSRC:
980 if (s->i2s_recording)
981 return put_user(SOUND_MASK_I2S, (int *)arg);
982 else
983 // let AC'97 report recording source
984 break;
985 }
986
987 return codec->mixer_ioctl(codec, cmd, arg);
988 }
989
990 static int it8172_ioctl_mixdev(struct inode *inode, struct file *file,
991 unsigned int cmd, unsigned long arg)
992 {
993 struct it8172_state *s = (struct it8172_state *)file->private_data;
994 struct ac97_codec *codec = &s->codec;
995
996 return mixdev_ioctl(codec, cmd, arg);
997 }
998
999 static /*const*/ struct file_operations it8172_mixer_fops = {
1000 .owner = THIS_MODULE,
1001 .llseek = no_llseek,
1002 .ioctl = it8172_ioctl_mixdev,
1003 .open = it8172_open_mixdev,
1004 .release = it8172_release_mixdev,
1005 };
1006
1007 /* --------------------------------------------------------------------- */
1008
1009 static int drain_dac(struct it8172_state *s, int nonblock)
1010 {
1011 unsigned long flags;
1012 int count, tmo;
1013
1014 if (s->dma_dac.mapped || !s->dma_dac.ready || s->dma_dac.stopped)
1015 return 0;
1016
1017 for (;;) {
1018 spin_lock_irqsave(&s->lock, flags);
1019 count = s->dma_dac.count;
1020 spin_unlock_irqrestore(&s->lock, flags);
1021 if (count <= 0)
1022 break;
1023 if (signal_pending(current))
1024 break;
1025 //if (nonblock)
1026 //return -EBUSY;
1027 tmo = 1000 * count / s->dacrate;
1028 tmo >>= sample_shift[(s->pcc & CC_FMT_MASK) >> CC_FMT_BIT];
1029 it8172_delay(tmo);
1030 }
1031 if (signal_pending(current))
1032 return -ERESTARTSYS;
1033 return 0;
1034 }
1035
1036 /* --------------------------------------------------------------------- */
1037
1038
1039 /*
1040 * Copy audio data to/from user buffer from/to dma buffer, taking care
1041 * that we wrap when reading/writing the dma buffer. Returns actual byte
1042 * count written to or read from the dma buffer.
1043 */
1044 static int copy_dmabuf_user(struct dmabuf *db, char* userbuf,
1045 int count, int to_user)
1046 {
1047 char* bufptr = to_user ? db->nextOut : db->nextIn;
1048 char* bufend = db->rawbuf + db->dmasize;
1049
1050 if (bufptr + count > bufend) {
1051 int partial = (int)(bufend - bufptr);
1052 if (to_user) {
1053 if (copy_to_user(userbuf, bufptr, partial))
1054 return -EFAULT;
1055 if (copy_to_user(userbuf + partial, db->rawbuf,
1056 count - partial))
1057 return -EFAULT;
1058 } else {
1059 if (copy_from_user(bufptr, userbuf, partial))
1060 return -EFAULT;
1061 if (copy_from_user(db->rawbuf,
1062 userbuf + partial,
1063 count - partial))
1064 return -EFAULT;
1065 }
1066 } else {
1067 if (to_user) {
1068 if (copy_to_user(userbuf, bufptr, count))
1069 return -EFAULT;
1070 } else {
1071 if (copy_from_user(bufptr, userbuf, count))
1072 return -EFAULT;
1073 }
1074 }
1075
1076 return count;
1077 }
1078
1079
1080 static ssize_t it8172_read(struct file *file, char *buffer,
1081 size_t count, loff_t *ppos)
1082 {
1083 struct it8172_state *s = (struct it8172_state *)file->private_data;
1084 struct dmabuf *db = &s->dma_adc;
1085 ssize_t ret;
1086 unsigned long flags;
1087 int cnt, remainder, avail;
1088
1089 if (ppos != &file->f_pos)
1090 return -ESPIPE;
1091 if (db->mapped)
1092 return -ENXIO;
1093 if (!access_ok(VERIFY_WRITE, buffer, count))
1094 return -EFAULT;
1095 ret = 0;
1096
1097 while (count > 0) {
1098 // wait for samples in capture buffer
1099 do {
1100 spin_lock_irqsave(&s->lock, flags);
1101 if (db->stopped)
1102 start_adc(s);
1103 avail = db->count;
1104 spin_unlock_irqrestore(&s->lock, flags);
1105 if (avail <= 0) {
1106 if (file->f_flags & O_NONBLOCK) {
1107 if (!ret)
1108 ret = -EAGAIN;
1109 return ret;
1110 }
1111 interruptible_sleep_on(&db->wait);
1112 if (signal_pending(current)) {
1113 if (!ret)
1114 ret = -ERESTARTSYS;
1115 return ret;
1116 }
1117 }
1118 } while (avail <= 0);
1119
1120 // copy from nextOut to user
1121 if ((cnt = copy_dmabuf_user(db, buffer, count > avail ?
1122 avail : count, 1)) < 0) {
1123 if (!ret)
1124 ret = -EFAULT;
1125 return ret;
1126 }
1127
1128 spin_lock_irqsave(&s->lock, flags);
1129 db->count -= cnt;
1130 spin_unlock_irqrestore(&s->lock, flags);
1131
1132 db->nextOut += cnt;
1133 if (db->nextOut >= db->rawbuf + db->dmasize)
1134 db->nextOut -= db->dmasize;
1135
1136 count -= cnt;
1137 buffer += cnt;
1138 ret += cnt;
1139 } // while (count > 0)
1140
1141 /*
1142 * See if the dma buffer count after this read call is
1143 * aligned on a fragsize boundary. If not, read from
1144 * buffer until we reach a boundary, and let's hope this
1145 * is just the last remainder of an audio record. If not
1146 * it means the user is not reading in fragsize chunks, in
1147 * which case it's his/her fault that there are audio gaps
1148 * in their record.
1149 */
1150 spin_lock_irqsave(&s->lock, flags);
1151 remainder = db->count % db->fragsize;
1152 if (remainder) {
1153 db->nextOut += remainder;
1154 if (db->nextOut >= db->rawbuf + db->dmasize)
1155 db->nextOut -= db->dmasize;
1156 db->count -= remainder;
1157 }
1158 spin_unlock_irqrestore(&s->lock, flags);
1159
1160 return ret;
1161 }
1162
1163 static ssize_t it8172_write(struct file *file, const char *buffer,
1164 size_t count, loff_t *ppos)
1165 {
1166 struct it8172_state *s = (struct it8172_state *)file->private_data;
1167 struct dmabuf *db = &s->dma_dac;
1168 ssize_t ret;
1169 unsigned long flags;
1170 int cnt, remainder, avail;
1171
1172 if (ppos != &file->f_pos)
1173 return -ESPIPE;
1174 if (db->mapped)
1175 return -ENXIO;
1176 if (!access_ok(VERIFY_READ, buffer, count))
1177 return -EFAULT;
1178 ret = 0;
1179
1180 while (count > 0) {
1181 // wait for space in playback buffer
1182 do {
1183 spin_lock_irqsave(&s->lock, flags);
1184 avail = db->dmasize - db->count;
1185 spin_unlock_irqrestore(&s->lock, flags);
1186 if (avail <= 0) {
1187 if (file->f_flags & O_NONBLOCK) {
1188 if (!ret)
1189 ret = -EAGAIN;
1190 return ret;
1191 }
1192 interruptible_sleep_on(&db->wait);
1193 if (signal_pending(current)) {
1194 if (!ret)
1195 ret = -ERESTARTSYS;
1196 return ret;
1197 }
1198 }
1199 } while (avail <= 0);
1200
1201 // copy to nextIn
1202 if ((cnt = copy_dmabuf_user(db, (char*)buffer,
1203 count > avail ?
1204 avail : count, 0)) < 0) {
1205 if (!ret)
1206 ret = -EFAULT;
1207 return ret;
1208 }
1209
1210 spin_lock_irqsave(&s->lock, flags);
1211 db->count += cnt;
1212 if (db->stopped)
1213 start_dac(s);
1214 spin_unlock_irqrestore(&s->lock, flags);
1215
1216 db->nextIn += cnt;
1217 if (db->nextIn >= db->rawbuf + db->dmasize)
1218 db->nextIn -= db->dmasize;
1219
1220 count -= cnt;
1221 buffer += cnt;
1222 ret += cnt;
1223 } // while (count > 0)
1224
1225 /*
1226 * See if the dma buffer count after this write call is
1227 * aligned on a fragsize boundary. If not, fill buffer
1228 * with silence to the next boundary, and let's hope this
1229 * is just the last remainder of an audio playback. If not
1230 * it means the user is not sending us fragsize chunks, in
1231 * which case it's his/her fault that there are audio gaps
1232 * in their playback.
1233 */
1234 spin_lock_irqsave(&s->lock, flags);
1235 remainder = db->count % db->fragsize;
1236 if (remainder) {
1237 int fill_cnt = db->fragsize - remainder;
1238 memset(db->nextIn, 0, fill_cnt);
1239 db->nextIn += fill_cnt;
1240 if (db->nextIn >= db->rawbuf + db->dmasize)
1241 db->nextIn -= db->dmasize;
1242 db->count += fill_cnt;
1243 }
1244 spin_unlock_irqrestore(&s->lock, flags);
1245
1246 return ret;
1247 }
1248
1249 /* No kernel lock - we have our own spinlock */
1250 static unsigned int it8172_poll(struct file *file,
1251 struct poll_table_struct *wait)
1252 {
1253 struct it8172_state *s = (struct it8172_state *)file->private_data;
1254 unsigned long flags;
1255 unsigned int mask = 0;
1256
1257 if (file->f_mode & FMODE_WRITE) {
1258 if (!s->dma_dac.ready)
1259 return 0;
1260 poll_wait(file, &s->dma_dac.wait, wait);
1261 }
1262 if (file->f_mode & FMODE_READ) {
1263 if (!s->dma_adc.ready)
1264 return 0;
1265 poll_wait(file, &s->dma_adc.wait, wait);
1266 }
1267
1268 spin_lock_irqsave(&s->lock, flags);
1269 if (file->f_mode & FMODE_READ) {
1270 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
1271 mask |= POLLIN | POLLRDNORM;
1272 }
1273 if (file->f_mode & FMODE_WRITE) {
1274 if (s->dma_dac.mapped) {
1275 if (s->dma_dac.count >= (signed)s->dma_dac.fragsize)
1276 mask |= POLLOUT | POLLWRNORM;
1277 } else {
1278 if ((signed)s->dma_dac.dmasize >=
1279 s->dma_dac.count + (signed)s->dma_dac.fragsize)
1280 mask |= POLLOUT | POLLWRNORM;
1281 }
1282 }
1283 spin_unlock_irqrestore(&s->lock, flags);
1284 return mask;
1285 }
1286
1287 static int it8172_mmap(struct file *file, struct vm_area_struct *vma)
1288 {
1289 struct it8172_state *s = (struct it8172_state *)file->private_data;
1290 struct dmabuf *db;
1291 unsigned long size;
1292
1293 lock_kernel();
1294 if (vma->vm_flags & VM_WRITE)
1295 db = &s->dma_dac;
1296 else if (vma->vm_flags & VM_READ)
1297 db = &s->dma_adc;
1298 else {
1299 unlock_kernel();
1300 return -EINVAL;
1301 }
1302 if (vma->vm_pgoff != 0) {
1303 unlock_kernel();
1304 return -EINVAL;
1305 }
1306 size = vma->vm_end - vma->vm_start;
1307 if (size > (PAGE_SIZE << db->buforder)) {
1308 unlock_kernel();
1309 return -EINVAL;
1310 }
1311 if (remap_page_range(vma, vma->vm_start, virt_to_phys(db->rawbuf),
1312 size, vma->vm_page_prot)) {
1313 unlock_kernel();
1314 return -EAGAIN;
1315 }
1316 db->mapped = 1;
1317 unlock_kernel();
1318 return 0;
1319 }
1320
1321
1322 #ifdef IT8172_VERBOSE_DEBUG
1323 static struct ioctl_str_t {
1324 unsigned int cmd;
1325 const char* str;
1326 } ioctl_str[] = {
1327 {SNDCTL_DSP_RESET, "SNDCTL_DSP_RESET"},
1328 {SNDCTL_DSP_SYNC, "SNDCTL_DSP_SYNC"},
1329 {SNDCTL_DSP_SPEED, "SNDCTL_DSP_SPEED"},
1330 {SNDCTL_DSP_STEREO, "SNDCTL_DSP_STEREO"},
1331 {SNDCTL_DSP_GETBLKSIZE, "SNDCTL_DSP_GETBLKSIZE"},
1332 {SNDCTL_DSP_SAMPLESIZE, "SNDCTL_DSP_SAMPLESIZE"},
1333 {SNDCTL_DSP_CHANNELS, "SNDCTL_DSP_CHANNELS"},
1334 {SOUND_PCM_WRITE_CHANNELS, "SOUND_PCM_WRITE_CHANNELS"},
1335 {SOUND_PCM_WRITE_FILTER, "SOUND_PCM_WRITE_FILTER"},
1336 {SNDCTL_DSP_POST, "SNDCTL_DSP_POST"},
1337 {SNDCTL_DSP_SUBDIVIDE, "SNDCTL_DSP_SUBDIVIDE"},
1338 {SNDCTL_DSP_SETFRAGMENT, "SNDCTL_DSP_SETFRAGMENT"},
1339 {SNDCTL_DSP_GETFMTS, "SNDCTL_DSP_GETFMTS"},
1340 {SNDCTL_DSP_SETFMT, "SNDCTL_DSP_SETFMT"},
1341 {SNDCTL_DSP_GETOSPACE, "SNDCTL_DSP_GETOSPACE"},
1342 {SNDCTL_DSP_GETISPACE, "SNDCTL_DSP_GETISPACE"},
1343 {SNDCTL_DSP_NONBLOCK, "SNDCTL_DSP_NONBLOCK"},
1344 {SNDCTL_DSP_GETCAPS, "SNDCTL_DSP_GETCAPS"},
1345 {SNDCTL_DSP_GETTRIGGER, "SNDCTL_DSP_GETTRIGGER"},
1346 {SNDCTL_DSP_SETTRIGGER, "SNDCTL_DSP_SETTRIGGER"},
1347 {SNDCTL_DSP_GETIPTR, "SNDCTL_DSP_GETIPTR"},
1348 {SNDCTL_DSP_GETOPTR, "SNDCTL_DSP_GETOPTR"},
1349 {SNDCTL_DSP_MAPINBUF, "SNDCTL_DSP_MAPINBUF"},
1350 {SNDCTL_DSP_MAPOUTBUF, "SNDCTL_DSP_MAPOUTBUF"},
1351 {SNDCTL_DSP_SETSYNCRO, "SNDCTL_DSP_SETSYNCRO"},
1352 {SNDCTL_DSP_SETDUPLEX, "SNDCTL_DSP_SETDUPLEX"},
1353 {SNDCTL_DSP_GETODELAY, "SNDCTL_DSP_GETODELAY"},
1354 {SNDCTL_DSP_GETCHANNELMASK, "SNDCTL_DSP_GETCHANNELMASK"},
1355 {SNDCTL_DSP_BIND_CHANNEL, "SNDCTL_DSP_BIND_CHANNEL"},
1356 {OSS_GETVERSION, "OSS_GETVERSION"},
1357 {SOUND_PCM_READ_RATE, "SOUND_PCM_READ_RATE"},
1358 {SOUND_PCM_READ_CHANNELS, "SOUND_PCM_READ_CHANNELS"},
1359 {SOUND_PCM_READ_BITS, "SOUND_PCM_READ_BITS"},
1360 {SOUND_PCM_READ_FILTER, "SOUND_PCM_READ_FILTER"}
1361 };
1362 #endif
1363
1364 static int it8172_ioctl(struct inode *inode, struct file *file,
1365 unsigned int cmd, unsigned long arg)
1366 {
1367 struct it8172_state *s = (struct it8172_state *)file->private_data;
1368 unsigned long flags;
1369 audio_buf_info abinfo;
1370 count_info cinfo;
1371 int count;
1372 int val, mapped, ret, diff;
1373
1374 mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
1375 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1376
1377 #ifdef IT8172_VERBOSE_DEBUG
1378 for (count=0; count<sizeof(ioctl_str)/sizeof(ioctl_str[0]); count++) {
1379 if (ioctl_str[count].cmd == cmd)
1380 break;
1381 }
1382 if (count < sizeof(ioctl_str)/sizeof(ioctl_str[0]))
1383 dbg("ioctl %s, arg=0x%08x",
1384 ioctl_str[count].str, (unsigned int)arg);
1385 else
1386 dbg("ioctl unknown, 0x%x", cmd);
1387 #endif
1388
1389 switch (cmd) {
1390 case OSS_GETVERSION:
1391 return put_user(SOUND_VERSION, (int *)arg);
1392
1393 case SNDCTL_DSP_SYNC:
1394 if (file->f_mode & FMODE_WRITE)
1395 return drain_dac(s, file->f_flags & O_NONBLOCK);
1396 return 0;
1397
1398 case SNDCTL_DSP_SETDUPLEX:
1399 return 0;
1400
1401 case SNDCTL_DSP_GETCAPS:
1402 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME |
1403 DSP_CAP_TRIGGER | DSP_CAP_MMAP, (int *)arg);
1404
1405 case SNDCTL_DSP_RESET:
1406 if (file->f_mode & FMODE_WRITE) {
1407 stop_dac(s);
1408 synchronize_irq(s->irq);
1409 s->dma_dac.count = s->dma_dac.total_bytes = 0;
1410 s->dma_dac.nextIn = s->dma_dac.nextOut =
1411 s->dma_dac.rawbuf;
1412 }
1413 if (file->f_mode & FMODE_READ) {
1414 stop_adc(s);
1415 synchronize_irq(s->irq);
1416 s->dma_adc.count = s->dma_adc.total_bytes = 0;
1417 s->dma_adc.nextIn = s->dma_adc.nextOut =
1418 s->dma_adc.rawbuf;
1419 }
1420 return 0;
1421
1422 case SNDCTL_DSP_SPEED:
1423 if (get_user(val, (int *)arg))
1424 return -EFAULT;
1425 if (val >= 0) {
1426 if (file->f_mode & FMODE_READ) {
1427 stop_adc(s);
1428 set_adc_rate(s, val);
1429 if ((ret = prog_dmabuf_adc(s)))
1430 return ret;
1431 }
1432 if (file->f_mode & FMODE_WRITE) {
1433 stop_dac(s);
1434 set_dac_rate(s, val);
1435 if ((ret = prog_dmabuf_dac(s)))
1436 return ret;
1437 }
1438 }
1439 return put_user((file->f_mode & FMODE_READ) ?
1440 s->adcrate : s->dacrate, (int *)arg);
1441
1442 case SNDCTL_DSP_STEREO:
1443 if (get_user(val, (int *)arg))
1444 return -EFAULT;
1445 if (file->f_mode & FMODE_READ) {
1446 stop_adc(s);
1447 if (val)
1448 s->capcc |= CC_SM;
1449 else
1450 s->capcc &= ~CC_SM;
1451 outw(s->capcc, s->io+IT_AC_CAPCC);
1452 if ((ret = prog_dmabuf_adc(s)))
1453 return ret;
1454 }
1455 if (file->f_mode & FMODE_WRITE) {
1456 stop_dac(s);
1457 if (val)
1458 s->pcc |= CC_SM;
1459 else
1460 s->pcc &= ~CC_SM;
1461 outw(s->pcc, s->io+IT_AC_PCC);
1462 if ((ret = prog_dmabuf_dac(s)))
1463 return ret;
1464 }
1465 return 0;
1466
1467 case SNDCTL_DSP_CHANNELS:
1468 if (get_user(val, (int *)arg))
1469 return -EFAULT;
1470 if (val != 0) {
1471 if (file->f_mode & FMODE_READ) {
1472 stop_adc(s);
1473 if (val >= 2) {
1474 val = 2;
1475 s->capcc |= CC_SM;
1476 }
1477 else
1478 s->capcc &= ~CC_SM;
1479 outw(s->capcc, s->io+IT_AC_CAPCC);
1480 if ((ret = prog_dmabuf_adc(s)))
1481 return ret;
1482 }
1483 if (file->f_mode & FMODE_WRITE) {
1484 stop_dac(s);
1485 switch (val) {
1486 case 1:
1487 s->pcc &= ~CC_SM;
1488 break;
1489 case 2:
1490 s->pcc |= CC_SM;
1491 break;
1492 default:
1493 // FIX! support multichannel???
1494 val = 2;
1495 s->pcc |= CC_SM;
1496 break;
1497 }
1498 outw(s->pcc, s->io+IT_AC_PCC);
1499 if ((ret = prog_dmabuf_dac(s)))
1500 return ret;
1501 }
1502 }
1503 return put_user(val, (int *)arg);
1504
1505 case SNDCTL_DSP_GETFMTS: /* Returns a mask */
1506 return put_user(AFMT_S16_LE|AFMT_U8, (int *)arg);
1507
1508 case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
1509 if (get_user(val, (int *)arg))
1510 return -EFAULT;
1511 if (val != AFMT_QUERY) {
1512 if (file->f_mode & FMODE_READ) {
1513 stop_adc(s);
1514 if (val == AFMT_S16_LE)
1515 s->capcc |= CC_DF;
1516 else {
1517 val = AFMT_U8;
1518 s->capcc &= ~CC_DF;
1519 }
1520 outw(s->capcc, s->io+IT_AC_CAPCC);
1521 if ((ret = prog_dmabuf_adc(s)))
1522 return ret;
1523 }
1524 if (file->f_mode & FMODE_WRITE) {
1525 stop_dac(s);
1526 if (val == AFMT_S16_LE)
1527 s->pcc |= CC_DF;
1528 else {
1529 val = AFMT_U8;
1530 s->pcc &= ~CC_DF;
1531 }
1532 outw(s->pcc, s->io+IT_AC_PCC);
1533 if ((ret = prog_dmabuf_dac(s)))
1534 return ret;
1535 }
1536 } else {
1537 if (file->f_mode & FMODE_READ)
1538 val = (s->capcc & CC_DF) ?
1539 AFMT_S16_LE : AFMT_U8;
1540 else
1541 val = (s->pcc & CC_DF) ?
1542 AFMT_S16_LE : AFMT_U8;
1543 }
1544 return put_user(val, (int *)arg);
1545
1546 case SNDCTL_DSP_POST:
1547 return 0;
1548
1549 case SNDCTL_DSP_GETTRIGGER:
1550 val = 0;
1551 spin_lock_irqsave(&s->lock, flags);
1552 if (file->f_mode & FMODE_READ && !s->dma_adc.stopped)
1553 val |= PCM_ENABLE_INPUT;
1554 if (file->f_mode & FMODE_WRITE && !s->dma_dac.stopped)
1555 val |= PCM_ENABLE_OUTPUT;
1556 spin_unlock_irqrestore(&s->lock, flags);
1557 return put_user(val, (int *)arg);
1558
1559 case SNDCTL_DSP_SETTRIGGER:
1560 if (get_user(val, (int *)arg))
1561 return -EFAULT;
1562 if (file->f_mode & FMODE_READ) {
1563 if (val & PCM_ENABLE_INPUT)
1564 start_adc(s);
1565 else
1566 stop_adc(s);
1567 }
1568 if (file->f_mode & FMODE_WRITE) {
1569 if (val & PCM_ENABLE_OUTPUT)
1570 start_dac(s);
1571 else
1572 stop_dac(s);
1573 }
1574 return 0;
1575
1576 case SNDCTL_DSP_GETOSPACE:
1577 if (!(file->f_mode & FMODE_WRITE))
1578 return -EINVAL;
1579 abinfo.fragsize = s->dma_dac.fragsize;
1580 spin_lock_irqsave(&s->lock, flags);
1581 count = s->dma_dac.count;
1582 if (!s->dma_dac.stopped)
1583 count -= (s->dma_dac.fragsize -
1584 inw(s->io+IT_AC_PCDL));
1585 spin_unlock_irqrestore(&s->lock, flags);
1586 if (count < 0)
1587 count = 0;
1588 abinfo.bytes = s->dma_dac.dmasize - count;
1589 abinfo.fragstotal = s->dma_dac.numfrag;
1590 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
1591 return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ?
1592 -EFAULT : 0;
1593
1594 case SNDCTL_DSP_GETISPACE:
1595 if (!(file->f_mode & FMODE_READ))
1596 return -EINVAL;
1597 abinfo.fragsize = s->dma_adc.fragsize;
1598 spin_lock_irqsave(&s->lock, flags);
1599 count = s->dma_adc.count;
1600 if (!s->dma_adc.stopped)
1601 count += (s->dma_adc.fragsize -
1602 inw(s->io+IT_AC_CAPCDL));
1603 spin_unlock_irqrestore(&s->lock, flags);
1604 if (count < 0)
1605 count = 0;
1606 abinfo.bytes = count;
1607 abinfo.fragstotal = s->dma_adc.numfrag;
1608 abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
1609 return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ?
1610 -EFAULT : 0;
1611
1612 case SNDCTL_DSP_NONBLOCK:
1613 file->f_flags |= O_NONBLOCK;
1614 return 0;
1615
1616 case SNDCTL_DSP_GETODELAY:
1617 if (!(file->f_mode & FMODE_WRITE))
1618 return -EINVAL;
1619 spin_lock_irqsave(&s->lock, flags);
1620 count = s->dma_dac.count;
1621 if (!s->dma_dac.stopped)
1622 count -= (s->dma_dac.fragsize -
1623 inw(s->io+IT_AC_PCDL));
1624 spin_unlock_irqrestore(&s->lock, flags);
1625 if (count < 0)
1626 count = 0;
1627 return put_user(count, (int *)arg);
1628
1629 case SNDCTL_DSP_GETIPTR:
1630 if (!(file->f_mode & FMODE_READ))
1631 return -EINVAL;
1632 spin_lock_irqsave(&s->lock, flags);
1633 cinfo.bytes = s->dma_adc.total_bytes;
1634 count = s->dma_adc.count;
1635 if (!s->dma_adc.stopped) {
1636 diff = s->dma_adc.fragsize - inw(s->io+IT_AC_CAPCDL);
1637 count += diff;
1638 cinfo.bytes += diff;
1639 cinfo.ptr = inl(s->io+s->dma_adc.curBufPtr) -
1640 s->dma_adc.dmaaddr;
1641 } else
1642 cinfo.ptr = virt_to_bus(s->dma_adc.nextIn) -
1643 s->dma_adc.dmaaddr;
1644 if (s->dma_adc.mapped)
1645 s->dma_adc.count &= s->dma_adc.fragsize-1;
1646 spin_unlock_irqrestore(&s->lock, flags);
1647 if (count < 0)
1648 count = 0;
1649 cinfo.blocks = count >> s->dma_adc.fragshift;
1650 if (copy_to_user((void *)arg, &cinfo, sizeof(cinfo)))
1651 return -EFAULT;
1652 return 0;
1653
1654 case SNDCTL_DSP_GETOPTR:
1655 if (!(file->f_mode & FMODE_READ))
1656 return -EINVAL;
1657 spin_lock_irqsave(&s->lock, flags);
1658 cinfo.bytes = s->dma_dac.total_bytes;
1659 count = s->dma_dac.count;
1660 if (!s->dma_dac.stopped) {
1661 diff = s->dma_dac.fragsize - inw(s->io+IT_AC_CAPCDL);
1662 count -= diff;
1663 cinfo.bytes += diff;
1664 cinfo.ptr = inl(s->io+s->dma_dac.curBufPtr) -
1665 s->dma_dac.dmaaddr;
1666 } else
1667 cinfo.ptr = virt_to_bus(s->dma_dac.nextOut) -
1668 s->dma_dac.dmaaddr;
1669 if (s->dma_dac.mapped)
1670 s->dma_dac.count &= s->dma_dac.fragsize-1;
1671 spin_unlock_irqrestore(&s->lock, flags);
1672 if (count < 0)
1673 count = 0;
1674 cinfo.blocks = count >> s->dma_dac.fragshift;
1675 if (copy_to_user((void *)arg, &cinfo, sizeof(cinfo)))
1676 return -EFAULT;
1677 return 0;
1678
1679 case SNDCTL_DSP_GETBLKSIZE:
1680 if (file->f_mode & FMODE_WRITE)
1681 return put_user(s->dma_dac.fragsize, (int *)arg);
1682 else
1683 return put_user(s->dma_adc.fragsize, (int *)arg);
1684
1685 case SNDCTL_DSP_SETFRAGMENT:
1686 if (get_user(val, (int *)arg))
1687 return -EFAULT;
1688 if (file->f_mode & FMODE_READ) {
1689 stop_adc(s);
1690 s->dma_adc.ossfragshift = val & 0xffff;
1691 s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
1692 if (s->dma_adc.ossfragshift < 4)
1693 s->dma_adc.ossfragshift = 4;
1694 if (s->dma_adc.ossfragshift > 15)
1695 s->dma_adc.ossfragshift = 15;
1696 if (s->dma_adc.ossmaxfrags < 4)
1697 s->dma_adc.ossmaxfrags = 4;
1698 if ((ret = prog_dmabuf_adc(s)))
1699 return ret;
1700 }
1701 if (file->f_mode & FMODE_WRITE) {
1702 stop_dac(s);
1703 s->dma_dac.ossfragshift = val & 0xffff;
1704 s->dma_dac.ossmaxfrags = (val >> 16) & 0xffff;
1705 if (s->dma_dac.ossfragshift < 4)
1706 s->dma_dac.ossfragshift = 4;
1707 if (s->dma_dac.ossfragshift > 15)
1708 s->dma_dac.ossfragshift = 15;
1709 if (s->dma_dac.ossmaxfrags < 4)
1710 s->dma_dac.ossmaxfrags = 4;
1711 if ((ret = prog_dmabuf_dac(s)))
1712 return ret;
1713 }
1714 return 0;
1715
1716 case SNDCTL_DSP_SUBDIVIDE:
1717 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
1718 (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision))
1719 return -EINVAL;
1720 if (get_user(val, (int *)arg))
1721 return -EFAULT;
1722 if (val != 1 && val != 2 && val != 4)
1723 return -EINVAL;
1724 if (file->f_mode & FMODE_READ) {
1725 stop_adc(s);
1726 s->dma_adc.subdivision = val;
1727 if ((ret = prog_dmabuf_adc(s)))
1728 return ret;
1729 }
1730 if (file->f_mode & FMODE_WRITE) {
1731 stop_dac(s);
1732 s->dma_dac.subdivision = val;
1733 if ((ret = prog_dmabuf_dac(s)))
1734 return ret;
1735 }
1736 return 0;
1737
1738 case SOUND_PCM_READ_RATE:
1739 return put_user((file->f_mode & FMODE_READ) ?
1740 s->adcrate : s->dacrate, (int *)arg);
1741
1742 case SOUND_PCM_READ_CHANNELS:
1743 if (file->f_mode & FMODE_READ)
1744 return put_user((s->capcc & CC_SM) ? 2 : 1,
1745 (int *)arg);
1746 else
1747 return put_user((s->pcc & CC_SM) ? 2 : 1,
1748 (int *)arg);
1749
1750 case SOUND_PCM_READ_BITS:
1751 if (file->f_mode & FMODE_READ)
1752 return put_user((s->capcc & CC_DF) ? 16 : 8,
1753 (int *)arg);
1754 else
1755 return put_user((s->pcc & CC_DF) ? 16 : 8,
1756 (int *)arg);
1757
1758 case SOUND_PCM_WRITE_FILTER:
1759 case SNDCTL_DSP_SETSYNCRO:
1760 case SOUND_PCM_READ_FILTER:
1761 return -EINVAL;
1762 }
1763
1764 return mixdev_ioctl(&s->codec, cmd, arg);
1765 }
1766
1767
1768 static int it8172_open(struct inode *inode, struct file *file)
1769 {
1770 int minor = minor(inode->i_rdev);
1771 DECLARE_WAITQUEUE(wait, current);
1772 unsigned long flags;
1773 struct list_head *list;
1774 struct it8172_state *s;
1775 int ret;
1776
1777 #ifdef IT8172_VERBOSE_DEBUG
1778 if (file->f_flags & O_NONBLOCK)
1779 dbg(__FUNCTION__ ": non-blocking");
1780 else
1781 dbg(__FUNCTION__ ": blocking");
1782 #endif
1783
1784 for (list = devs.next; ; list = list->next) {
1785 if (list == &devs)
1786 return -ENODEV;
1787 s = list_entry(list, struct it8172_state, devs);
1788 if (!((s->dev_audio ^ minor) & ~0xf))
1789 break;
1790 }
1791 file->private_data = s;
1792 /* wait for device to become free */
1793 down(&s->open_sem);
1794 while (s->open_mode & file->f_mode) {
1795 if (file->f_flags & O_NONBLOCK) {
1796 up(&s->open_sem);
1797 return -EBUSY;
1798 }
1799 add_wait_queue(&s->open_wait, &wait);
1800 __set_current_state(TASK_INTERRUPTIBLE);
1801 up(&s->open_sem);
1802 schedule();
1803 remove_wait_queue(&s->open_wait, &wait);
1804 set_current_state(TASK_RUNNING);
1805 if (signal_pending(current))
1806 return -ERESTARTSYS;
1807 down(&s->open_sem);
1808 }
1809
1810 spin_lock_irqsave(&s->lock, flags);
1811
1812 if (file->f_mode & FMODE_READ) {
1813 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags =
1814 s->dma_adc.subdivision = s->dma_adc.total_bytes = 0;
1815 s->capcc &= ~(CC_SM | CC_DF);
1816 set_adc_rate(s, 8000);
1817 if ((minor & 0xf) == SND_DEV_DSP16)
1818 s->capcc |= CC_DF;
1819 outw(s->capcc, s->io+IT_AC_CAPCC);
1820 if ((ret = prog_dmabuf_adc(s))) {
1821 spin_unlock_irqrestore(&s->lock, flags);
1822 return ret;
1823 }
1824 }
1825 if (file->f_mode & FMODE_WRITE) {
1826 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags =
1827 s->dma_dac.subdivision = s->dma_dac.total_bytes = 0;
1828 s->pcc &= ~(CC_SM | CC_DF);
1829 set_dac_rate(s, 8000);
1830 if ((minor & 0xf) == SND_DEV_DSP16)
1831 s->pcc |= CC_DF;
1832 outw(s->pcc, s->io+IT_AC_PCC);
1833 if ((ret = prog_dmabuf_dac(s))) {
1834 spin_unlock_irqrestore(&s->lock, flags);
1835 return ret;
1836 }
1837 }
1838
1839 spin_unlock_irqrestore(&s->lock, flags);
1840
1841 s->open_mode |= (file->f_mode & (FMODE_READ | FMODE_WRITE));
1842 up(&s->open_sem);
1843 return 0;
1844 }
1845
1846 static int it8172_release(struct inode *inode, struct file *file)
1847 {
1848 struct it8172_state *s = (struct it8172_state *)file->private_data;
1849
1850 #ifdef IT8172_VERBOSE_DEBUG
1851 dbg(__FUNCTION__);
1852 #endif
1853 lock_kernel();
1854 if (file->f_mode & FMODE_WRITE)
1855 drain_dac(s, file->f_flags & O_NONBLOCK);
1856 down(&s->open_sem);
1857 if (file->f_mode & FMODE_WRITE) {
1858 stop_dac(s);
1859 dealloc_dmabuf(s, &s->dma_dac);
1860 }
1861 if (file->f_mode & FMODE_READ) {
1862 stop_adc(s);
1863 dealloc_dmabuf(s, &s->dma_adc);
1864 }
1865 s->open_mode &= ((~file->f_mode) & (FMODE_READ|FMODE_WRITE));
1866 up(&s->open_sem);
1867 wake_up(&s->open_wait);
1868 unlock_kernel();
1869 return 0;
1870 }
1871
1872 static /*const*/ struct file_operations it8172_audio_fops = {
1873 .owner = THIS_MODULE,
1874 .llseek = no_llseek,
1875 .read = it8172_read,
1876 .write = it8172_write,
1877 .poll = it8172_poll,
1878 .ioctl = it8172_ioctl,
1879 .mmap = it8172_mmap,
1880 .open = it8172_open,
1881 .release = it8172_release,
1882 };
1883
1884
1885 /* --------------------------------------------------------------------- */
1886
1887
1888 /* --------------------------------------------------------------------- */
1889
1890 /*
1891 * for debugging purposes, we'll create a proc device that dumps the
1892 * CODEC chipstate
1893 */
1894
1895 #ifdef IT8172_DEBUG
1896 static int proc_it8172_dump (char *buf, char **start, off_t fpos,
1897 int length, int *eof, void *data)
1898 {
1899 struct it8172_state *s;
1900 int cnt, len = 0;
1901
1902 if (list_empty(&devs))
1903 return 0;
1904 s = list_entry(devs.next, struct it8172_state, devs);
1905
1906 /* print out header */
1907 len += sprintf(buf + len, "\n\t\tIT8172 Audio Debug\n\n");
1908
1909 // print out digital controller state
1910 len += sprintf (buf + len, "IT8172 Audio Controller registers\n");
1911 len += sprintf (buf + len, "---------------------------------\n");
1912 cnt=0;
1913 while (cnt < 0x72) {
1914 if (cnt == IT_AC_PCB1STA || cnt == IT_AC_PCB2STA ||
1915 cnt == IT_AC_CAPB1STA || cnt == IT_AC_CAPB2STA ||
1916 cnt == IT_AC_PFDP) {
1917 len+= sprintf (buf + len, "reg %02x = %08x\n",
1918 cnt, inl(s->io+cnt));
1919 cnt += 4;
1920 } else {
1921 len+= sprintf (buf + len, "reg %02x = %04x\n",
1922 cnt, inw(s->io+cnt));
1923 cnt += 2;
1924 }
1925 }
1926
1927 /* print out CODEC state */
1928 len += sprintf (buf + len, "\nAC97 CODEC registers\n");
1929 len += sprintf (buf + len, "----------------------\n");
1930 for (cnt=0; cnt <= 0x7e; cnt = cnt +2)
1931 len+= sprintf (buf + len, "reg %02x = %04x\n",
1932 cnt, rdcodec(&s->codec, cnt));
1933
1934 if (fpos >=len){
1935 *start = buf;
1936 *eof =1;
1937 return 0;
1938 }
1939 *start = buf + fpos;
1940 if ((len -= fpos) > length)
1941 return length;
1942 *eof =1;
1943 return len;
1944
1945 }
1946 #endif /* IT8172_DEBUG */
1947
1948 /* --------------------------------------------------------------------- */
1949
1950 /* maximum number of devices; only used for command line params */
1951 #define NR_DEVICE 5
1952
1953 static int spdif[NR_DEVICE] = { 0, };
1954 static int i2s_fmt[NR_DEVICE] = { 0, };
1955
1956 static unsigned int devindex = 0;
1957
1958 MODULE_PARM(spdif, "1-" __MODULE_STRING(NR_DEVICE) "i");
1959 MODULE_PARM_DESC(spdif, "if 1 the S/PDIF digital output is enabled");
1960 MODULE_PARM(i2s_fmt, "1-" __MODULE_STRING(NR_DEVICE) "i");
1961 MODULE_PARM_DESC(i2s_fmt, "the format of I2S");
1962
1963 MODULE_AUTHOR("Monta Vista Software, stevel@mvista.com");
1964 MODULE_DESCRIPTION("IT8172 Audio Driver");
1965
1966 /* --------------------------------------------------------------------- */
1967
1968 static int __devinit it8172_probe(struct pci_dev *pcidev,
1969 const struct pci_device_id *pciid)
1970 {
1971 struct it8172_state *s;
1972 int i, val;
1973 unsigned short pcisr, vol;
1974 unsigned char legacy, imc;
1975 char proc_str[80];
1976
1977 if (pcidev->irq == 0)
1978 return -1;
1979
1980 if (!(s = kmalloc(sizeof(struct it8172_state), GFP_KERNEL))) {
1981 err("alloc of device struct failed");
1982 return -1;
1983 }
1984
1985 memset(s, 0, sizeof(struct it8172_state));
1986 init_waitqueue_head(&s->dma_adc.wait);
1987 init_waitqueue_head(&s->dma_dac.wait);
1988 init_waitqueue_head(&s->open_wait);
1989 init_MUTEX(&s->open_sem);
1990 spin_lock_init(&s->lock);
1991 s->dev = pcidev;
1992 s->io = pci_resource_start(pcidev, 0);
1993 s->irq = pcidev->irq;
1994 s->vendor = pcidev->vendor;
1995 s->device = pcidev->device;
1996 pci_read_config_byte(pcidev, PCI_REVISION_ID, &s->rev);
1997 s->codec.private_data = s;
1998 s->codec.id = 0;
1999 s->codec.codec_read = rdcodec;
2000 s->codec.codec_write = wrcodec;
2001 s->codec.codec_wait = waitcodec;
2002
2003 if (!request_region(s->io, pci_resource_len(pcidev,0),
2004 IT8172_MODULE_NAME)) {
2005 err("io ports %#lx->%#lx in use",
2006 s->io, s->io + pci_resource_len(pcidev,0)-1);
2007 goto err_region;
2008 }
2009 if (request_irq(s->irq, it8172_interrupt, SA_INTERRUPT,
2010 IT8172_MODULE_NAME, s)) {
2011 err("irq %u in use", s->irq);
2012 goto err_irq;
2013 }
2014
2015 info("IO at %#lx, IRQ %d", s->io, s->irq);
2016
2017 /* register devices */
2018 if ((s->dev_audio = register_sound_dsp(&it8172_audio_fops, -1)) < 0)
2019 goto err_dev1;
2020 if ((s->codec.dev_mixer =
2021 register_sound_mixer(&it8172_mixer_fops, -1)) < 0)
2022 goto err_dev2;
2023
2024 #ifdef IT8172_DEBUG
2025 /* intialize the debug proc device */
2026 s->ps = create_proc_read_entry(IT8172_MODULE_NAME, 0, NULL,
2027 proc_it8172_dump, NULL);
2028 #endif /* IT8172_DEBUG */
2029
2030 /*
2031 * Reset the Audio device using the IT8172 PCI Reset register. This
2032 * creates an audible double click on a speaker connected to Line-out.
2033 */
2034 IT_IO_READ16(IT_PM_PCISR, pcisr);
2035 pcisr |= IT_PM_PCISR_ACSR;
2036 IT_IO_WRITE16(IT_PM_PCISR, pcisr);
2037 /* wait up to 100msec for reset to complete */
2038 for (i=0; pcisr & IT_PM_PCISR_ACSR; i++) {
2039 it8172_delay(10);
2040 if (i == 10)
2041 break;
2042 IT_IO_READ16(IT_PM_PCISR, pcisr);
2043 }
2044 if (i == 10) {
2045 err("chip reset timeout!");
2046 goto err_dev3;
2047 }
2048
2049 /* enable pci io and bus mastering */
2050 if (pci_enable_device(pcidev))
2051 goto err_dev3;
2052 pci_set_master(pcidev);
2053
2054 /* get out of legacy mode */
2055 pci_read_config_byte (pcidev, 0x40, &legacy);
2056 pci_write_config_byte (pcidev, 0x40, legacy & ~1);
2057
2058 s->spdif_volume = -1;
2059 /* check to see if s/pdif mode is being requested */
2060 if (spdif[devindex]) {
2061 info("enabling S/PDIF output");
2062 s->spdif_volume = 0;
2063 outb(GC_SOE, s->io+IT_AC_GC);
2064 } else {
2065 info("disabling S/PDIF output");
2066 outb(0, s->io+IT_AC_GC);
2067 }
2068
2069 /* check to see if I2S format requested */
2070 if (i2s_fmt[devindex]) {
2071 info("setting I2S format to 0x%02x", i2s_fmt[devindex]);
2072 outb(i2s_fmt[devindex], s->io+IT_AC_I2SMC);
2073 } else {
2074 outb(I2SMC_I2SF_I2S, s->io+IT_AC_I2SMC);
2075 }
2076
2077 /* cold reset the AC97 */
2078 outw(CODECC_CR, s->io+IT_AC_CODECC);
2079 udelay(1000);
2080 outw(0, s->io+IT_AC_CODECC);
2081 /* need to delay around 500msec(bleech) to give
2082 some CODECs enough time to wakeup */
2083 it8172_delay(500);
2084
2085 /* AC97 warm reset to start the bitclk */
2086 outw(CODECC_WR, s->io+IT_AC_CODECC);
2087 udelay(1000);
2088 outw(0, s->io+IT_AC_CODECC);
2089
2090 /* codec init */
2091 if (!ac97_probe_codec(&s->codec))
2092 goto err_dev3;
2093
2094 /* add I2S as allowable recording source */
2095 s->codec.record_sources |= SOUND_MASK_I2S;
2096
2097 /* Enable Volume button interrupts */
2098 imc = inb(s->io+IT_AC_IMC);
2099 outb(imc & ~IMC_VCIM, s->io+IT_AC_IMC);
2100
2101 /* Un-mute PCM and FM out on the controller */
2102 vol = inw(s->io+IT_AC_PCMOV);
2103 outw(vol & ~PCMOV_PCMOM, s->io+IT_AC_PCMOV);
2104 vol = inw(s->io+IT_AC_FMOV);
2105 outw(vol & ~FMOV_FMOM, s->io+IT_AC_FMOV);
2106
2107 /* set channel defaults to 8-bit, mono, 8 Khz */
2108 s->pcc = 0;
2109 s->capcc = 0;
2110 set_dac_rate(s, 8000);
2111 set_adc_rate(s, 8000);
2112
2113 /* set mic to be the recording source */
2114 val = SOUND_MASK_MIC;
2115 mixdev_ioctl(&s->codec, SOUND_MIXER_WRITE_RECSRC,
2116 (unsigned long)&val);
2117
2118 /* mute AC'97 master and PCM when in S/PDIF mode */
2119 if (s->spdif_volume != -1) {
2120 val = 0x0000;
2121 s->codec.mixer_ioctl(&s->codec, SOUND_MIXER_WRITE_VOLUME,
2122 (unsigned long)&val);
2123 s->codec.mixer_ioctl(&s->codec, SOUND_MIXER_WRITE_PCM,
2124 (unsigned long)&val);
2125 }
2126
2127 #ifdef IT8172_DEBUG
2128 sprintf(proc_str, "driver/%s/%d/ac97", IT8172_MODULE_NAME,
2129 s->codec.id);
2130 s->ac97_ps = create_proc_read_entry (proc_str, 0, NULL,
2131 ac97_read_proc, &s->codec);
2132 #endif
2133
2134 /* store it in the driver field */
2135 pci_set_drvdata(pcidev, s);
2136 pcidev->dma_mask = 0xffffffff;
2137 /* put it into driver list */
2138 list_add_tail(&s->devs, &devs);
2139 /* increment devindex */
2140 if (devindex < NR_DEVICE-1)
2141 devindex++;
2142 return 0;
2143
2144 err_dev3:
2145 unregister_sound_mixer(s->codec.dev_mixer);
2146 err_dev2:
2147 unregister_sound_dsp(s->dev_audio);
2148 err_dev1:
2149 err("cannot register misc device");
2150 free_irq(s->irq, s);
2151 err_irq:
2152 release_region(s->io, pci_resource_len(pcidev,0));
2153 err_region:
2154 kfree(s);
2155 return -1;
2156 }
2157
2158 static void __devinit it8172_remove(struct pci_dev *dev)
2159 {
2160 struct it8172_state *s = pci_get_drvdata(dev);
2161
2162 if (!s)
2163 return;
2164 list_del(&s->devs);
2165 #ifdef IT8172_DEBUG
2166 if (s->ps)
2167 remove_proc_entry(IT8172_MODULE_NAME, NULL);
2168 #endif /* IT8172_DEBUG */
2169 synchronize_irq(s->irq);
2170 free_irq(s->irq, s);
2171 release_region(s->io, pci_resource_len(dev,0));
2172 unregister_sound_dsp(s->dev_audio);
2173 unregister_sound_mixer(s->codec.dev_mixer);
2174 kfree(s);
2175 pci_set_drvdata(dev, NULL);
2176 }
2177
2178
2179
2180 static struct pci_device_id id_table[] __devinitdata = {
2181 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_IT8172G_AUDIO, PCI_ANY_ID,
2182 PCI_ANY_ID, 0, 0 },
2183 { 0, }
2184 };
2185
2186 MODULE_DEVICE_TABLE(pci, id_table);
2187
2188 static struct pci_driver it8172_driver = {
2189 .name = IT8172_MODULE_NAME,
2190 .id_table = id_table,
2191 .probe = it8172_probe,
2192 .remove = it8172_remove
2193 };
2194
2195 static int __init init_it8172(void)
2196 {
2197 if (!pci_present()) /* No PCI bus in this machine! */
2198 return -ENODEV;
2199 info("version v0.5 time " __TIME__ " " __DATE__);
2200 return pci_module_init(&it8172_driver);
2201 }
2202
2203 static void __exit cleanup_it8172(void)
2204 {
2205 info("unloading");
2206 pci_unregister_driver(&it8172_driver);
2207 }
2208
2209 module_init(init_it8172);
2210 module_exit(cleanup_it8172);
2211
2212 /* --------------------------------------------------------------------- */
2213
2214 #ifndef MODULE
2215
2216 /* format is: it8172=[spdif],[i2s:<I2S format>] */
2217
2218 static int __init it8172_setup(char *options)
2219 {
2220 char* this_opt;
2221 static unsigned __initdata nr_dev = 0;
2222
2223 if (nr_dev >= NR_DEVICE)
2224 return 0;
2225
2226 if (!options || !*options)
2227 return 0;
2228
2229 for(this_opt=strtok(options, ",");
2230 this_opt; this_opt=strtok(NULL, ",")) {
2231 if (!strncmp(this_opt, "spdif", 5)) {
2232 spdif[nr_dev] = 1;
2233 } else if (!strncmp(this_opt, "i2s:", 4)) {
2234 if (!strncmp(this_opt+4, "dac", 3))
2235 i2s_fmt[nr_dev] = I2SMC_I2SF_DAC;
2236 else if (!strncmp(this_opt+4, "adc", 3))
2237 i2s_fmt[nr_dev] = I2SMC_I2SF_ADC;
2238 else if (!strncmp(this_opt+4, "i2s", 3))
2239 i2s_fmt[nr_dev] = I2SMC_I2SF_I2S;
2240 }
2241 }
2242
2243 nr_dev++;
2244 return 1;
2245 }
2246
2247 __setup("it8172=", it8172_setup);
2248
2249 #endif /* MODULE */
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