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Pull one more egcs 1.1.2 workaround.
[linux-2.6/linux-mips.git] / sound / oss / esssolo1.c
blobe4c002f33521927970317525485ace3b61cf5ead
1 /****************************************************************************/
2
3 /*
4 * esssolo1.c -- ESS Technology Solo1 (ES1946) audio driver.
5 *
6 * Copyright (C) 1998-2001 Thomas Sailer (t.sailer@alumni.ethz.ch)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 * Module command line parameters:
23 * none so far
24 *
25 * Supported devices:
26 * /dev/dsp standard /dev/dsp device, (mostly) OSS compatible
27 * /dev/mixer standard /dev/mixer device, (mostly) OSS compatible
28 * /dev/midi simple MIDI UART interface, no ioctl
29 *
30 * Revision history
31 * 10.11.1998 0.1 Initial release (without any hardware)
32 * 22.03.1999 0.2 cinfo.blocks should be reset after GETxPTR ioctl.
33 * reported by Johan Maes <joma@telindus.be>
34 * return EAGAIN instead of EBUSY when O_NONBLOCK
35 * read/write cannot be executed
36 * 07.04.1999 0.3 implemented the following ioctl's: SOUND_PCM_READ_RATE,
37 * SOUND_PCM_READ_CHANNELS, SOUND_PCM_READ_BITS;
38 * Alpha fixes reported by Peter Jones <pjones@redhat.com>
39 * 15.06.1999 0.4 Fix bad allocation bug.
40 * Thanks to Deti Fliegl <fliegl@in.tum.de>
41 * 28.06.1999 0.5 Add pci_set_master
42 * 12.08.1999 0.6 Fix MIDI UART crashing the driver
43 * Changed mixer semantics from OSS documented
44 * behaviour to OSS "code behaviour".
45 * Recording might actually work now.
46 * The real DDMA controller address register is at PCI config
47 * 0x60, while the register at 0x18 is used as a placeholder
48 * register for BIOS address allocation. This register
49 * is supposed to be copied into 0x60, according
50 * to the Solo1 datasheet. When I do that, I can access
51 * the DDMA registers except the mask bit, which
52 * is stuck at 1. When I copy the contents of 0x18 +0x10
53 * to the DDMA base register, everything seems to work.
54 * The fun part is that the Windows Solo1 driver doesn't
55 * seem to do these tricks.
56 * Bugs remaining: plops and clicks when starting/stopping playback
57 * 31.08.1999 0.7 add spin_lock_init
58 * replaced current->state = x with set_current_state(x)
59 * 03.09.1999 0.8 change read semantics for MIDI to match
60 * OSS more closely; remove possible wakeup race
61 * 07.10.1999 0.9 Fix initialization; complain if sequencer writes time out
62 * Revised resource grabbing for the FM synthesizer
63 * 28.10.1999 0.10 More waitqueue races fixed
64 * 09.12.1999 0.11 Work around stupid Alpha port issue (virt_to_bus(kmalloc(GFP_DMA)) > 16M)
65 * Disabling recording on Alpha
66 * 12.01.2000 0.12 Prevent some ioctl's from returning bad count values on underrun/overrun;
67 * Tim Janik's BSE (Bedevilled Sound Engine) found this
68 * Integrated (aka redid 8-)) APM support patch by Zach Brown
69 * 07.02.2000 0.13 Use pci_alloc_consistent and pci_register_driver
70 * 19.02.2000 0.14 Use pci_dma_supported to determine if recording should be disabled
71 * 13.03.2000 0.15 Reintroduce initialization of a couple of PCI config space registers
72 * 21.11.2000 0.16 Initialize dma buffers in poll, otherwise poll may return a bogus mask
73 * 12.12.2000 0.17 More dma buffer initializations, patch from
74 * Tjeerd Mulder <tjeerd.mulder@fujitsu-siemens.com>
75 * 31.01.2001 0.18 Register/Unregister gameport, original patch from
76 * Nathaniel Daw <daw@cs.cmu.edu>
77 * Fix SETTRIGGER non OSS API conformity
78 * 10.03.2001 provide abs function, prevent picking up a bogus kernel macro
79 * for abs. Bug report by Andrew Morton <andrewm@uow.edu.au>
80 * 15.05.2001 pci_enable_device moved, return values in probe cleaned
81 * up. Marcus Meissner <mm@caldera.de>
82 * 22.05.2001 0.19 more cleanups, changed PM to PCI 2.4 style, got rid
83 * of global list of devices, using pci device data.
84 * Marcus Meissner <mm@caldera.de>
85 */
86
87 /*****************************************************************************/
88
89 #include <linux/version.h>
90 #include <linux/module.h>
91 #include <linux/string.h>
92 #include <linux/ioport.h>
93 #include <linux/sched.h>
94 #include <linux/delay.h>
95 #include <linux/sound.h>
96 #include <linux/slab.h>
97 #include <linux/soundcard.h>
98 #include <linux/pci.h>
99 #include <linux/bitops.h>
100 #include <asm/io.h>
101 #include <asm/dma.h>
102 #include <linux/init.h>
103 #include <linux/poll.h>
104 #include <linux/spinlock.h>
105 #include <linux/smp_lock.h>
106 #include <linux/wrapper.h>
107 #include <asm/uaccess.h>
108 #include <asm/hardirq.h>
109 #include <linux/gameport.h>
110
111 #include "dm.h"
112
113 /* --------------------------------------------------------------------- */
114
115 #undef OSS_DOCUMENTED_MIXER_SEMANTICS
116
117 /* --------------------------------------------------------------------- */
118
119 #ifndef PCI_VENDOR_ID_ESS
120 #define PCI_VENDOR_ID_ESS 0x125d
121 #endif
122 #ifndef PCI_DEVICE_ID_ESS_SOLO1
123 #define PCI_DEVICE_ID_ESS_SOLO1 0x1969
124 #endif
125
126 #define SOLO1_MAGIC ((PCI_VENDOR_ID_ESS<<16)|PCI_DEVICE_ID_ESS_SOLO1)
127
128 #define DDMABASE_OFFSET 0 /* chip bug workaround kludge */
129 #define DDMABASE_EXTENT 16
130
131 #define IOBASE_EXTENT 16
132 #define SBBASE_EXTENT 16
133 #define VCBASE_EXTENT (DDMABASE_EXTENT+DDMABASE_OFFSET)
134 #define MPUBASE_EXTENT 4
135 #define GPBASE_EXTENT 4
136 #define GAMEPORT_EXTENT 4
137
138 #define FMSYNTH_EXTENT 4
139
140 /* MIDI buffer sizes */
141
142 #define MIDIINBUF 256
143 #define MIDIOUTBUF 256
144
145 #define FMODE_MIDI_SHIFT 3
146 #define FMODE_MIDI_READ (FMODE_READ << FMODE_MIDI_SHIFT)
147 #define FMODE_MIDI_WRITE (FMODE_WRITE << FMODE_MIDI_SHIFT)
148
149 #define FMODE_DMFM 0x10
150
151 static struct pci_driver solo1_driver;
152
153 /* --------------------------------------------------------------------- */
154
155 struct solo1_state {
156 /* magic */
157 unsigned int magic;
158
159 /* the corresponding pci_dev structure */
160 struct pci_dev *dev;
161
162 /* soundcore stuff */
163 int dev_audio;
164 int dev_mixer;
165 int dev_midi;
166 int dev_dmfm;
167
168 /* hardware resources */
169 unsigned long iobase, sbbase, vcbase, ddmabase, mpubase; /* long for SPARC */
170 unsigned int irq;
171
172 /* mixer registers */
173 struct {
174 unsigned short vol[10];
175 unsigned int recsrc;
176 unsigned int modcnt;
177 unsigned short micpreamp;
178 } mix;
179
180 /* wave stuff */
181 unsigned fmt;
182 unsigned channels;
183 unsigned rate;
184 unsigned char clkdiv;
185 unsigned ena;
186
187 spinlock_t lock;
188 struct semaphore open_sem;
189 mode_t open_mode;
190 wait_queue_head_t open_wait;
191
192 struct dmabuf {
193 void *rawbuf;
194 dma_addr_t dmaaddr;
195 unsigned buforder;
196 unsigned numfrag;
197 unsigned fragshift;
198 unsigned hwptr, swptr;
199 unsigned total_bytes;
200 int count;
201 unsigned error; /* over/underrun */
202 wait_queue_head_t wait;
203 /* redundant, but makes calculations easier */
204 unsigned fragsize;
205 unsigned dmasize;
206 unsigned fragsamples;
207 /* OSS stuff */
208 unsigned mapped:1;
209 unsigned ready:1;
210 unsigned endcleared:1;
211 unsigned enabled:1;
212 unsigned ossfragshift;
213 int ossmaxfrags;
214 unsigned subdivision;
215 } dma_dac, dma_adc;
216
217 /* midi stuff */
218 struct {
219 unsigned ird, iwr, icnt;
220 unsigned ord, owr, ocnt;
221 wait_queue_head_t iwait;
222 wait_queue_head_t owait;
223 struct timer_list timer;
224 unsigned char ibuf[MIDIINBUF];
225 unsigned char obuf[MIDIOUTBUF];
226 } midi;
227
228 struct gameport gameport;
229 };
230
231 /* --------------------------------------------------------------------- */
232
233 static inline void write_seq(struct solo1_state *s, unsigned char data)
234 {
235 int i;
236 unsigned long flags;
237
238 /* the local_irq_save stunt is to send the data within the command window */
239 for (i = 0; i < 0xffff; i++) {
240 local_irq_save(flags);
241 if (!(inb(s->sbbase+0xc) & 0x80)) {
242 outb(data, s->sbbase+0xc);
243 local_irq_restore(flags);
244 return;
245 }
246 local_irq_restore(flags);
247 }
248 printk(KERN_ERR "esssolo1: write_seq timeout\n");
249 outb(data, s->sbbase+0xc);
250 }
251
252 static inline int read_seq(struct solo1_state *s, unsigned char *data)
253 {
254 int i;
255
256 if (!data)
257 return 0;
258 for (i = 0; i < 0xffff; i++)
259 if (inb(s->sbbase+0xe) & 0x80) {
260 *data = inb(s->sbbase+0xa);
261 return 1;
262 }
263 printk(KERN_ERR "esssolo1: read_seq timeout\n");
264 return 0;
265 }
266
267 static int inline reset_ctrl(struct solo1_state *s)
268 {
269 int i;
270
271 outb(3, s->sbbase+6); /* clear sequencer and FIFO */
272 udelay(10);
273 outb(0, s->sbbase+6);
274 for (i = 0; i < 0xffff; i++)
275 if (inb(s->sbbase+0xe) & 0x80)
276 if (inb(s->sbbase+0xa) == 0xaa) {
277 write_seq(s, 0xc6); /* enter enhanced mode */
278 return 1;
279 }
280 return 0;
281 }
282
283 static void write_ctrl(struct solo1_state *s, unsigned char reg, unsigned char data)
284 {
285 write_seq(s, reg);
286 write_seq(s, data);
287 }
288
289 #if 0 /* unused */
290 static unsigned char read_ctrl(struct solo1_state *s, unsigned char reg)
291 {
292 unsigned char r;
293
294 write_seq(s, 0xc0);
295 write_seq(s, reg);
296 read_seq(s, &r);
297 return r;
298 }
299 #endif /* unused */
300
301 static void write_mixer(struct solo1_state *s, unsigned char reg, unsigned char data)
302 {
303 outb(reg, s->sbbase+4);
304 outb(data, s->sbbase+5);
305 }
306
307 static unsigned char read_mixer(struct solo1_state *s, unsigned char reg)
308 {
309 outb(reg, s->sbbase+4);
310 return inb(s->sbbase+5);
311 }
312
313 /* --------------------------------------------------------------------- */
314
315 static inline unsigned ld2(unsigned int x)
316 {
317 unsigned r = 0;
318
319 if (x >= 0x10000) {
320 x >>= 16;
321 r += 16;
322 }
323 if (x >= 0x100) {
324 x >>= 8;
325 r += 8;
326 }
327 if (x >= 0x10) {
328 x >>= 4;
329 r += 4;
330 }
331 if (x >= 4) {
332 x >>= 2;
333 r += 2;
334 }
335 if (x >= 2)
336 r++;
337 return r;
338 }
339
340 /* --------------------------------------------------------------------- */
341
342 static inline void stop_dac(struct solo1_state *s)
343 {
344 unsigned long flags;
345
346 spin_lock_irqsave(&s->lock, flags);
347 s->ena &= ~FMODE_WRITE;
348 write_mixer(s, 0x78, 0x10);
349 spin_unlock_irqrestore(&s->lock, flags);
350 }
351
352 static void start_dac(struct solo1_state *s)
353 {
354 unsigned long flags;
355
356 spin_lock_irqsave(&s->lock, flags);
357 if (!(s->ena & FMODE_WRITE) && (s->dma_dac.mapped || s->dma_dac.count > 0) && s->dma_dac.ready) {
358 s->ena |= FMODE_WRITE;
359 write_mixer(s, 0x78, 0x12);
360 udelay(10);
361 write_mixer(s, 0x78, 0x13);
362 }
363 spin_unlock_irqrestore(&s->lock, flags);
364 }
365
366 static inline void stop_adc(struct solo1_state *s)
367 {
368 unsigned long flags;
369
370 spin_lock_irqsave(&s->lock, flags);
371 s->ena &= ~FMODE_READ;
372 write_ctrl(s, 0xb8, 0xe);
373 spin_unlock_irqrestore(&s->lock, flags);
374 }
375
376 static void start_adc(struct solo1_state *s)
377 {
378 unsigned long flags;
379
380 spin_lock_irqsave(&s->lock, flags);
381 if (!(s->ena & FMODE_READ) && (s->dma_adc.mapped || s->dma_adc.count < (signed)(s->dma_adc.dmasize - 2*s->dma_adc.fragsize))
382 && s->dma_adc.ready) {
383 s->ena |= FMODE_READ;
384 write_ctrl(s, 0xb8, 0xf);
385 #if 0
386 printk(KERN_DEBUG "solo1: DMAbuffer: 0x%08lx\n", (long)s->dma_adc.rawbuf);
387 printk(KERN_DEBUG "solo1: DMA: mask: 0x%02x cnt: 0x%04x addr: 0x%08x stat: 0x%02x\n",
388 inb(s->ddmabase+0xf), inw(s->ddmabase+4), inl(s->ddmabase), inb(s->ddmabase+8));
389 #endif
390 outb(0, s->ddmabase+0xd); /* master reset */
391 outb(1, s->ddmabase+0xf); /* mask */
392 outb(0x54/*0x14*/, s->ddmabase+0xb); /* DMA_MODE_READ | DMA_MODE_AUTOINIT */
393 outl(virt_to_bus(s->dma_adc.rawbuf), s->ddmabase);
394 outw(s->dma_adc.dmasize-1, s->ddmabase+4);
395 outb(0, s->ddmabase+0xf);
396 }
397 spin_unlock_irqrestore(&s->lock, flags);
398 #if 0
399 printk(KERN_DEBUG "solo1: start DMA: reg B8: 0x%02x SBstat: 0x%02x\n"
400 KERN_DEBUG "solo1: DMA: stat: 0x%02x cnt: 0x%04x mask: 0x%02x\n",
401 read_ctrl(s, 0xb8), inb(s->sbbase+0xc),
402 inb(s->ddmabase+8), inw(s->ddmabase+4), inb(s->ddmabase+0xf));
403 printk(KERN_DEBUG "solo1: A1: 0x%02x A2: 0x%02x A4: 0x%02x A5: 0x%02x A8: 0x%02x\n"
404 KERN_DEBUG "solo1: B1: 0x%02x B2: 0x%02x B4: 0x%02x B7: 0x%02x B8: 0x%02x B9: 0x%02x\n",
405 read_ctrl(s, 0xa1), read_ctrl(s, 0xa2), read_ctrl(s, 0xa4), read_ctrl(s, 0xa5), read_ctrl(s, 0xa8),
406 read_ctrl(s, 0xb1), read_ctrl(s, 0xb2), read_ctrl(s, 0xb4), read_ctrl(s, 0xb7), read_ctrl(s, 0xb8),
407 read_ctrl(s, 0xb9));
408 #endif
409 }
410
411 /* --------------------------------------------------------------------- */
412
413 #define DMABUF_DEFAULTORDER (15-PAGE_SHIFT)
414 #define DMABUF_MINORDER 1
415
416 static inline void dealloc_dmabuf(struct solo1_state *s, struct dmabuf *db)
417 {
418 struct page *page, *pend;
419
420 if (db->rawbuf) {
421 /* undo marking the pages as reserved */
422 pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
423 for (page = virt_to_page(db->rawbuf); page <= pend; page++)
424 mem_map_unreserve(page);
425 pci_free_consistent(s->dev, PAGE_SIZE << db->buforder, db->rawbuf, db->dmaaddr);
426 }
427 db->rawbuf = NULL;
428 db->mapped = db->ready = 0;
429 }
430
431 static int prog_dmabuf(struct solo1_state *s, struct dmabuf *db)
432 {
433 int order;
434 unsigned bytespersec;
435 unsigned bufs, sample_shift = 0;
436 struct page *page, *pend;
437
438 db->hwptr = db->swptr = db->total_bytes = db->count = db->error = db->endcleared = 0;
439 if (!db->rawbuf) {
440 db->ready = db->mapped = 0;
441 for (order = DMABUF_DEFAULTORDER; order >= DMABUF_MINORDER; order--)
442 if ((db->rawbuf = pci_alloc_consistent(s->dev, PAGE_SIZE << order, &db->dmaaddr)))
443 break;
444 if (!db->rawbuf)
445 return -ENOMEM;
446 db->buforder = order;
447 /* now mark the pages as reserved; otherwise remap_page_range doesn't do what we want */
448 pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
449 for (page = virt_to_page(db->rawbuf); page <= pend; page++)
450 mem_map_reserve(page);
451 }
452 if (s->fmt & (AFMT_S16_LE | AFMT_U16_LE))
453 sample_shift++;
454 if (s->channels > 1)
455 sample_shift++;
456 bytespersec = s->rate << sample_shift;
457 bufs = PAGE_SIZE << db->buforder;
458 if (db->ossfragshift) {
459 if ((1000 << db->ossfragshift) < bytespersec)
460 db->fragshift = ld2(bytespersec/1000);
461 else
462 db->fragshift = db->ossfragshift;
463 } else {
464 db->fragshift = ld2(bytespersec/100/(db->subdivision ? db->subdivision : 1));
465 if (db->fragshift < 3)
466 db->fragshift = 3;
467 }
468 db->numfrag = bufs >> db->fragshift;
469 while (db->numfrag < 4 && db->fragshift > 3) {
470 db->fragshift--;
471 db->numfrag = bufs >> db->fragshift;
472 }
473 db->fragsize = 1 << db->fragshift;
474 if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
475 db->numfrag = db->ossmaxfrags;
476 db->fragsamples = db->fragsize >> sample_shift;
477 db->dmasize = db->numfrag << db->fragshift;
478 db->enabled = 1;
479 return 0;
480 }
481
482 static inline int prog_dmabuf_adc(struct solo1_state *s)
483 {
484 unsigned long va;
485 int c;
486
487 stop_adc(s);
488 /* check if PCI implementation supports 24bit busmaster DMA */
489 if (s->dev->dma_mask > 0xffffff)
490 return -EIO;
491 if ((c = prog_dmabuf(s, &s->dma_adc)))
492 return c;
493 va = s->dma_adc.dmaaddr;
494 if ((va & ~((1<<24)-1)))
495 panic("solo1: buffer above 16M boundary");
496 outb(0, s->ddmabase+0xd); /* clear */
497 outb(1, s->ddmabase+0xf); /* mask */
498 /*outb(0, s->ddmabase+8);*/ /* enable (enable is active low!) */
499 outb(0x54, s->ddmabase+0xb); /* DMA_MODE_READ | DMA_MODE_AUTOINIT */
500 outl(va, s->ddmabase);
501 outw(s->dma_adc.dmasize-1, s->ddmabase+4);
502 c = - s->dma_adc.fragsamples;
503 write_ctrl(s, 0xa4, c);
504 write_ctrl(s, 0xa5, c >> 8);
505 outb(0, s->ddmabase+0xf);
506 s->dma_adc.ready = 1;
507 return 0;
508 }
509
510 static inline int prog_dmabuf_dac(struct solo1_state *s)
511 {
512 unsigned long va;
513 int c;
514
515 stop_dac(s);
516 if ((c = prog_dmabuf(s, &s->dma_dac)))
517 return c;
518 memset(s->dma_dac.rawbuf, (s->fmt & (AFMT_U8 | AFMT_U16_LE)) ? 0 : 0x80, s->dma_dac.dmasize); /* almost correct for U16 */
519 va = s->dma_dac.dmaaddr;
520 if ((va ^ (va + s->dma_dac.dmasize - 1)) & ~((1<<20)-1))
521 panic("solo1: buffer crosses 1M boundary");
522 outl(va, s->iobase);
523 /* warning: s->dma_dac.dmasize & 0xffff must not be zero! i.e. this limits us to a 32k buffer */
524 outw(s->dma_dac.dmasize, s->iobase+4);
525 c = - s->dma_dac.fragsamples;
526 write_mixer(s, 0x74, c);
527 write_mixer(s, 0x76, c >> 8);
528 outb(0xa, s->iobase+6);
529 s->dma_dac.ready = 1;
530 return 0;
531 }
532
533 static inline void clear_advance(void *buf, unsigned bsize, unsigned bptr, unsigned len, unsigned char c)
534 {
535 if (bptr + len > bsize) {
536 unsigned x = bsize - bptr;
537 memset(((char *)buf) + bptr, c, x);
538 bptr = 0;
539 len -= x;
540 }
541 memset(((char *)buf) + bptr, c, len);
542 }
543
544 /* call with spinlock held! */
545
546 static void solo1_update_ptr(struct solo1_state *s)
547 {
548 int diff;
549 unsigned hwptr;
550
551 /* update ADC pointer */
552 if (s->ena & FMODE_READ) {
553 hwptr = (s->dma_adc.dmasize - 1 - inw(s->ddmabase+4)) % s->dma_adc.dmasize;
554 diff = (s->dma_adc.dmasize + hwptr - s->dma_adc.hwptr) % s->dma_adc.dmasize;
555 s->dma_adc.hwptr = hwptr;
556 s->dma_adc.total_bytes += diff;
557 s->dma_adc.count += diff;
558 #if 0
559 printk(KERN_DEBUG "solo1: rd: hwptr %u swptr %u dmasize %u count %u\n",
560 s->dma_adc.hwptr, s->dma_adc.swptr, s->dma_adc.dmasize, s->dma_adc.count);
561 #endif
562 if (s->dma_adc.mapped) {
563 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
564 wake_up(&s->dma_adc.wait);
565 } else {
566 if (s->dma_adc.count > (signed)(s->dma_adc.dmasize - ((3 * s->dma_adc.fragsize) >> 1))) {
567 s->ena &= ~FMODE_READ;
568 write_ctrl(s, 0xb8, 0xe);
569 s->dma_adc.error++;
570 }
571 if (s->dma_adc.count > 0)
572 wake_up(&s->dma_adc.wait);
573 }
574 }
575 /* update DAC pointer */
576 if (s->ena & FMODE_WRITE) {
577 hwptr = (s->dma_dac.dmasize - inw(s->iobase+4)) % s->dma_dac.dmasize;
578 diff = (s->dma_dac.dmasize + hwptr - s->dma_dac.hwptr) % s->dma_dac.dmasize;
579 s->dma_dac.hwptr = hwptr;
580 s->dma_dac.total_bytes += diff;
581 #if 0
582 printk(KERN_DEBUG "solo1: wr: hwptr %u swptr %u dmasize %u count %u\n",
583 s->dma_dac.hwptr, s->dma_dac.swptr, s->dma_dac.dmasize, s->dma_dac.count);
584 #endif
585 if (s->dma_dac.mapped) {
586 s->dma_dac.count += diff;
587 if (s->dma_dac.count >= (signed)s->dma_dac.fragsize)
588 wake_up(&s->dma_dac.wait);
589 } else {
590 s->dma_dac.count -= diff;
591 if (s->dma_dac.count <= 0) {
592 s->ena &= ~FMODE_WRITE;
593 write_mixer(s, 0x78, 0x12);
594 s->dma_dac.error++;
595 } else if (s->dma_dac.count <= (signed)s->dma_dac.fragsize && !s->dma_dac.endcleared) {
596 clear_advance(s->dma_dac.rawbuf, s->dma_dac.dmasize, s->dma_dac.swptr,
597 s->dma_dac.fragsize, (s->fmt & (AFMT_U8 | AFMT_U16_LE)) ? 0 : 0x80);
598 s->dma_dac.endcleared = 1;
599 }
600 if (s->dma_dac.count < (signed)s->dma_dac.dmasize)
601 wake_up(&s->dma_dac.wait);
602 }
603 }
604 }
605
606 /* --------------------------------------------------------------------- */
607
608 static void prog_codec(struct solo1_state *s)
609 {
610 unsigned long flags;
611 int fdiv, filter;
612 unsigned char c;
613
614 reset_ctrl(s);
615 write_seq(s, 0xd3);
616 /* program sampling rates */
617 filter = s->rate * 9 / 20; /* Set filter roll-off to 90% of rate/2 */
618 fdiv = 256 - 7160000 / (filter * 82);
619 spin_lock_irqsave(&s->lock, flags);
620 write_ctrl(s, 0xa1, s->clkdiv);
621 write_ctrl(s, 0xa2, fdiv);
622 write_mixer(s, 0x70, s->clkdiv);
623 write_mixer(s, 0x72, fdiv);
624 /* program ADC parameters */
625 write_ctrl(s, 0xb8, 0xe);
626 write_ctrl(s, 0xb9, /*0x1*/0);
627 write_ctrl(s, 0xa8, (s->channels > 1) ? 0x11 : 0x12);
628 c = 0xd0;
629 if (s->fmt & (AFMT_S16_LE | AFMT_U16_LE))
630 c |= 0x04;
631 if (s->fmt & (AFMT_S16_LE | AFMT_S8))
632 c |= 0x20;
633 if (s->channels > 1)
634 c ^= 0x48;
635 write_ctrl(s, 0xb7, (c & 0x70) | 1);
636 write_ctrl(s, 0xb7, c);
637 write_ctrl(s, 0xb1, 0x50);
638 write_ctrl(s, 0xb2, 0x50);
639 /* program DAC parameters */
640 c = 0x40;
641 if (s->fmt & (AFMT_S16_LE | AFMT_U16_LE))
642 c |= 1;
643 if (s->fmt & (AFMT_S16_LE | AFMT_S8))
644 c |= 4;
645 if (s->channels > 1)
646 c |= 2;
647 write_mixer(s, 0x7a, c);
648 write_mixer(s, 0x78, 0x10);
649 s->ena = 0;
650 spin_unlock_irqrestore(&s->lock, flags);
651 }
652
653 /* --------------------------------------------------------------------- */
654
655 static const char invalid_magic[] = KERN_CRIT "solo1: invalid magic value\n";
656
657 #define VALIDATE_STATE(s) \
658 ({ \
659 if (!(s) || (s)->magic != SOLO1_MAGIC) { \
660 printk(invalid_magic); \
661 return -ENXIO; \
662 } \
663 })
664
665 /* --------------------------------------------------------------------- */
666
667 static int mixer_ioctl(struct solo1_state *s, unsigned int cmd, unsigned long arg)
668 {
669 static const unsigned int mixer_src[8] = {
670 SOUND_MASK_MIC, SOUND_MASK_MIC, SOUND_MASK_CD, SOUND_MASK_VOLUME,
671 SOUND_MASK_MIC, 0, SOUND_MASK_LINE, 0
672 };
673 static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = {
674 [SOUND_MIXER_PCM] = 1, /* voice */
675 [SOUND_MIXER_SYNTH] = 2, /* FM */
676 [SOUND_MIXER_CD] = 3, /* CD */
677 [SOUND_MIXER_LINE] = 4, /* Line */
678 [SOUND_MIXER_LINE1] = 5, /* AUX */
679 [SOUND_MIXER_MIC] = 6, /* Mic */
680 [SOUND_MIXER_LINE2] = 7, /* Mono in */
681 [SOUND_MIXER_SPEAKER] = 8, /* Speaker */
682 [SOUND_MIXER_RECLEV] = 9, /* Recording level */
683 [SOUND_MIXER_VOLUME] = 10 /* Master Volume */
684 };
685 static const unsigned char mixreg[] = {
686 0x7c, /* voice */
687 0x36, /* FM */
688 0x38, /* CD */
689 0x3e, /* Line */
690 0x3a, /* AUX */
691 0x1a, /* Mic */
692 0x6d /* Mono in */
693 };
694 unsigned char l, r, rl, rr, vidx;
695 int i, val;
696
697 VALIDATE_STATE(s);
698
699 if (cmd == SOUND_MIXER_PRIVATE1) {
700 /* enable/disable/query mixer preamp */
701 if (get_user(val, (int *)arg))
702 return -EFAULT;
703 if (val != -1) {
704 val = val ? 0xff : 0xf7;
705 write_mixer(s, 0x7d, (read_mixer(s, 0x7d) | 0x08) & val);
706 }
707 val = (read_mixer(s, 0x7d) & 0x08) ? 1 : 0;
708 return put_user(val, (int *)arg);
709 }
710 if (cmd == SOUND_MIXER_PRIVATE2) {
711 /* enable/disable/query spatializer */
712 if (get_user(val, (int *)arg))
713 return -EFAULT;
714 if (val != -1) {
715 val &= 0x3f;
716 write_mixer(s, 0x52, val);
717 write_mixer(s, 0x50, val ? 0x08 : 0);
718 }
719 return put_user(read_mixer(s, 0x52), (int *)arg);
720 }
721 if (cmd == SOUND_MIXER_INFO) {
722 mixer_info info;
723 strncpy(info.id, "Solo1", sizeof(info.id));
724 strncpy(info.name, "ESS Solo1", sizeof(info.name));
725 info.modify_counter = s->mix.modcnt;
726 if (copy_to_user((void *)arg, &info, sizeof(info)))
727 return -EFAULT;
728 return 0;
729 }
730 if (cmd == SOUND_OLD_MIXER_INFO) {
731 _old_mixer_info info;
732 strncpy(info.id, "Solo1", sizeof(info.id));
733 strncpy(info.name, "ESS Solo1", sizeof(info.name));
734 if (copy_to_user((void *)arg, &info, sizeof(info)))
735 return -EFAULT;
736 return 0;
737 }
738 if (cmd == OSS_GETVERSION)
739 return put_user(SOUND_VERSION, (int *)arg);
740 if (_IOC_TYPE(cmd) != 'M' || _SIOC_SIZE(cmd) != sizeof(int))
741 return -EINVAL;
742 if (_SIOC_DIR(cmd) == _SIOC_READ) {
743 switch (_IOC_NR(cmd)) {
744 case SOUND_MIXER_RECSRC: /* Arg contains a bit for each recording source */
745 return put_user(mixer_src[read_mixer(s, 0x1c) & 7], (int *)arg);
746
747 case SOUND_MIXER_DEVMASK: /* Arg contains a bit for each supported device */
748 return put_user(SOUND_MASK_PCM | SOUND_MASK_SYNTH | SOUND_MASK_CD |
749 SOUND_MASK_LINE | SOUND_MASK_LINE1 | SOUND_MASK_MIC |
750 SOUND_MASK_VOLUME | SOUND_MASK_LINE2 | SOUND_MASK_RECLEV |
751 SOUND_MASK_SPEAKER, (int *)arg);
752
753 case SOUND_MIXER_RECMASK: /* Arg contains a bit for each supported recording source */
754 return put_user(SOUND_MASK_LINE | SOUND_MASK_MIC | SOUND_MASK_CD | SOUND_MASK_VOLUME, (int *)arg);
755
756 case SOUND_MIXER_STEREODEVS: /* Mixer channels supporting stereo */
757 return put_user(SOUND_MASK_PCM | SOUND_MASK_SYNTH | SOUND_MASK_CD |
758 SOUND_MASK_LINE | SOUND_MASK_LINE1 | SOUND_MASK_MIC |
759 SOUND_MASK_VOLUME | SOUND_MASK_LINE2 | SOUND_MASK_RECLEV, (int *)arg);
760
761 case SOUND_MIXER_CAPS:
762 return put_user(SOUND_CAP_EXCL_INPUT, (int *)arg);
763
764 default:
765 i = _IOC_NR(cmd);
766 if (i >= SOUND_MIXER_NRDEVICES || !(vidx = mixtable1[i]))
767 return -EINVAL;
768 return put_user(s->mix.vol[vidx-1], (int *)arg);
769 }
770 }
771 if (_SIOC_DIR(cmd) != (_SIOC_READ|_SIOC_WRITE))
772 return -EINVAL;
773 s->mix.modcnt++;
774 switch (_IOC_NR(cmd)) {
775 case SOUND_MIXER_RECSRC: /* Arg contains a bit for each recording source */
776 #if 0
777 {
778 static const unsigned char regs[] = {
779 0x1c, 0x1a, 0x36, 0x38, 0x3a, 0x3c, 0x3e, 0x60, 0x62, 0x6d, 0x7c
780 };
781 int i;
782
783 for (i = 0; i < sizeof(regs); i++)
784 printk(KERN_DEBUG "solo1: mixer reg 0x%02x: 0x%02x\n",
785 regs[i], read_mixer(s, regs[i]));
786 printk(KERN_DEBUG "solo1: ctrl reg 0x%02x: 0x%02x\n",
787 0xb4, read_ctrl(s, 0xb4));
788 }
789 #endif
790 if (get_user(val, (int *)arg))
791 return -EFAULT;
792 i = hweight32(val);
793 if (i == 0)
794 return 0;
795 else if (i > 1)
796 val &= ~mixer_src[read_mixer(s, 0x1c) & 7];
797 for (i = 0; i < 8; i++) {
798 if (mixer_src[i] & val)
799 break;
800 }
801 if (i > 7)
802 return 0;
803 write_mixer(s, 0x1c, i);
804 return 0;
805
806 case SOUND_MIXER_VOLUME:
807 if (get_user(val, (int *)arg))
808 return -EFAULT;
809 l = val & 0xff;
810 if (l > 100)
811 l = 100;
812 r = (val >> 8) & 0xff;
813 if (r > 100)
814 r = 100;
815 if (l < 6) {
816 rl = 0x40;
817 l = 0;
818 } else {
819 rl = (l * 2 - 11) / 3;
820 l = (rl * 3 + 11) / 2;
821 }
822 if (r < 6) {
823 rr = 0x40;
824 r = 0;
825 } else {
826 rr = (r * 2 - 11) / 3;
827 r = (rr * 3 + 11) / 2;
828 }
829 write_mixer(s, 0x60, rl);
830 write_mixer(s, 0x62, rr);
831 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
832 s->mix.vol[9] = ((unsigned int)r << 8) | l;
833 #else
834 s->mix.vol[9] = val;
835 #endif
836 return put_user(s->mix.vol[9], (int *)arg);
837
838 case SOUND_MIXER_SPEAKER:
839 if (get_user(val, (int *)arg))
840 return -EFAULT;
841 l = val & 0xff;
842 if (l > 100)
843 l = 100;
844 else if (l < 2)
845 l = 2;
846 rl = (l - 2) / 14;
847 l = rl * 14 + 2;
848 write_mixer(s, 0x3c, rl);
849 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
850 s->mix.vol[7] = l * 0x101;
851 #else
852 s->mix.vol[7] = val;
853 #endif
854 return put_user(s->mix.vol[7], (int *)arg);
855
856 case SOUND_MIXER_RECLEV:
857 if (get_user(val, (int *)arg))
858 return -EFAULT;
859 l = (val << 1) & 0x1fe;
860 if (l > 200)
861 l = 200;
862 else if (l < 5)
863 l = 5;
864 r = (val >> 7) & 0x1fe;
865 if (r > 200)
866 r = 200;
867 else if (r < 5)
868 r = 5;
869 rl = (l - 5) / 13;
870 rr = (r - 5) / 13;
871 r = (rl * 13 + 5) / 2;
872 l = (rr * 13 + 5) / 2;
873 write_ctrl(s, 0xb4, (rl << 4) | rr);
874 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
875 s->mix.vol[8] = ((unsigned int)r << 8) | l;
876 #else
877 s->mix.vol[8] = val;
878 #endif
879 return put_user(s->mix.vol[8], (int *)arg);
880
881 default:
882 i = _IOC_NR(cmd);
883 if (i >= SOUND_MIXER_NRDEVICES || !(vidx = mixtable1[i]))
884 return -EINVAL;
885 if (get_user(val, (int *)arg))
886 return -EFAULT;
887 l = (val << 1) & 0x1fe;
888 if (l > 200)
889 l = 200;
890 else if (l < 5)
891 l = 5;
892 r = (val >> 7) & 0x1fe;
893 if (r > 200)
894 r = 200;
895 else if (r < 5)
896 r = 5;
897 rl = (l - 5) / 13;
898 rr = (r - 5) / 13;
899 r = (rl * 13 + 5) / 2;
900 l = (rr * 13 + 5) / 2;
901 write_mixer(s, mixreg[vidx-1], (rl << 4) | rr);
902 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
903 s->mix.vol[vidx-1] = ((unsigned int)r << 8) | l;
904 #else
905 s->mix.vol[vidx-1] = val;
906 #endif
907 return put_user(s->mix.vol[vidx-1], (int *)arg);
908 }
909 }
910
911 /* --------------------------------------------------------------------- */
912
913 static int solo1_open_mixdev(struct inode *inode, struct file *file)
914 {
915 unsigned int minor = minor(inode->i_rdev);
916 struct solo1_state *s = NULL;
917 struct pci_dev *pci_dev;
918
919 pci_for_each_dev(pci_dev) {
920 struct pci_driver *drvr;
921 drvr = pci_dev_driver (pci_dev);
922 if (drvr != &solo1_driver)
923 continue;
924 s = (struct solo1_state*)pci_get_drvdata(pci_dev);
925 if (!s)
926 continue;
927 if (s->dev_mixer == minor)
928 break;
929 }
930 if (!s)
931 return -ENODEV;
932 VALIDATE_STATE(s);
933 file->private_data = s;
934 return 0;
935 }
936
937 static int solo1_release_mixdev(struct inode *inode, struct file *file)
938 {
939 struct solo1_state *s = (struct solo1_state *)file->private_data;
940
941 VALIDATE_STATE(s);
942 return 0;
943 }
944
945 static int solo1_ioctl_mixdev(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
946 {
947 return mixer_ioctl((struct solo1_state *)file->private_data, cmd, arg);
948 }
949
950 static /*const*/ struct file_operations solo1_mixer_fops = {
951 owner: THIS_MODULE,
952 llseek: no_llseek,
953 ioctl: solo1_ioctl_mixdev,
954 open: solo1_open_mixdev,
955 release: solo1_release_mixdev,
956 };
957
958 /* --------------------------------------------------------------------- */
959
960 static int drain_dac(struct solo1_state *s, int nonblock)
961 {
962 DECLARE_WAITQUEUE(wait, current);
963 unsigned long flags;
964 int count;
965 unsigned tmo;
966
967 if (s->dma_dac.mapped)
968 return 0;
969 add_wait_queue(&s->dma_dac.wait, &wait);
970 for (;;) {
971 set_current_state(TASK_INTERRUPTIBLE);
972 spin_lock_irqsave(&s->lock, flags);
973 count = s->dma_dac.count;
974 spin_unlock_irqrestore(&s->lock, flags);
975 if (count <= 0)
976 break;
977 if (signal_pending(current))
978 break;
979 if (nonblock) {
980 remove_wait_queue(&s->dma_dac.wait, &wait);
981 set_current_state(TASK_RUNNING);
982 return -EBUSY;
983 }
984 tmo = 3 * HZ * (count + s->dma_dac.fragsize) / 2 / s->rate;
985 if (s->fmt & (AFMT_S16_LE | AFMT_U16_LE))
986 tmo >>= 1;
987 if (s->channels > 1)
988 tmo >>= 1;
989 if (!schedule_timeout(tmo + 1))
990 printk(KERN_DEBUG "solo1: dma timed out??\n");
991 }
992 remove_wait_queue(&s->dma_dac.wait, &wait);
993 set_current_state(TASK_RUNNING);
994 if (signal_pending(current))
995 return -ERESTARTSYS;
996 return 0;
997 }
998
999 /* --------------------------------------------------------------------- */
1000
1001 static ssize_t solo1_read(struct file *file, char *buffer, size_t count, loff_t *ppos)
1002 {
1003 struct solo1_state *s = (struct solo1_state *)file->private_data;
1004 DECLARE_WAITQUEUE(wait, current);
1005 ssize_t ret;
1006 unsigned long flags;
1007 unsigned swptr;
1008 int cnt;
1009
1010 VALIDATE_STATE(s);
1011 if (ppos != &file->f_pos)
1012 return -ESPIPE;
1013 if (s->dma_adc.mapped)
1014 return -ENXIO;
1015 if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
1016 return ret;
1017 if (!access_ok(VERIFY_WRITE, buffer, count))
1018 return -EFAULT;
1019 ret = 0;
1020 add_wait_queue(&s->dma_adc.wait, &wait);
1021 while (count > 0) {
1022 spin_lock_irqsave(&s->lock, flags);
1023 swptr = s->dma_adc.swptr;
1024 cnt = s->dma_adc.dmasize-swptr;
1025 if (s->dma_adc.count < cnt)
1026 cnt = s->dma_adc.count;
1027 if (cnt <= 0)
1028 __set_current_state(TASK_INTERRUPTIBLE);
1029 spin_unlock_irqrestore(&s->lock, flags);
1030 if (cnt > count)
1031 cnt = count;
1032 #ifdef DEBUGREC
1033 printk(KERN_DEBUG "solo1_read: reg B8: 0x%02x DMAstat: 0x%02x DMAcnt: 0x%04x SBstat: 0x%02x cnt: %u\n",
1034 read_ctrl(s, 0xb8), inb(s->ddmabase+8), inw(s->ddmabase+4), inb(s->sbbase+0xc), cnt);
1035 #endif
1036 if (cnt <= 0) {
1037 if (s->dma_adc.enabled)
1038 start_adc(s);
1039 #ifdef DEBUGREC
1040 printk(KERN_DEBUG "solo1_read: regs: A1: 0x%02x A2: 0x%02x A4: 0x%02x A5: 0x%02x A8: 0x%02x\n"
1041 KERN_DEBUG "solo1_read: regs: B1: 0x%02x B2: 0x%02x B7: 0x%02x B8: 0x%02x B9: 0x%02x\n"
1042 KERN_DEBUG "solo1_read: DMA: addr: 0x%08x cnt: 0x%04x stat: 0x%02x mask: 0x%02x\n"
1043 KERN_DEBUG "solo1_read: SBstat: 0x%02x cnt: %u\n",
1044 read_ctrl(s, 0xa1), read_ctrl(s, 0xa2), read_ctrl(s, 0xa4), read_ctrl(s, 0xa5), read_ctrl(s, 0xa8),
1045 read_ctrl(s, 0xb1), read_ctrl(s, 0xb2), read_ctrl(s, 0xb7), read_ctrl(s, 0xb8), read_ctrl(s, 0xb9),
1046 inl(s->ddmabase), inw(s->ddmabase+4), inb(s->ddmabase+8), inb(s->ddmabase+15), inb(s->sbbase+0xc), cnt);
1047 #endif
1048 if (inb(s->ddmabase+15) & 1)
1049 printk(KERN_ERR "solo1: cannot start recording, DDMA mask bit stuck at 1\n");
1050 if (file->f_flags & O_NONBLOCK) {
1051 if (!ret)
1052 ret = -EAGAIN;
1053 break;
1054 }
1055 schedule();
1056 #ifdef DEBUGREC
1057 printk(KERN_DEBUG "solo1_read: regs: A1: 0x%02x A2: 0x%02x A4: 0x%02x A5: 0x%02x A8: 0x%02x\n"
1058 KERN_DEBUG "solo1_read: regs: B1: 0x%02x B2: 0x%02x B7: 0x%02x B8: 0x%02x B9: 0x%02x\n"
1059 KERN_DEBUG "solo1_read: DMA: addr: 0x%08x cnt: 0x%04x stat: 0x%02x mask: 0x%02x\n"
1060 KERN_DEBUG "solo1_read: SBstat: 0x%02x cnt: %u\n",
1061 read_ctrl(s, 0xa1), read_ctrl(s, 0xa2), read_ctrl(s, 0xa4), read_ctrl(s, 0xa5), read_ctrl(s, 0xa8),
1062 read_ctrl(s, 0xb1), read_ctrl(s, 0xb2), read_ctrl(s, 0xb7), read_ctrl(s, 0xb8), read_ctrl(s, 0xb9),
1063 inl(s->ddmabase), inw(s->ddmabase+4), inb(s->ddmabase+8), inb(s->ddmabase+15), inb(s->sbbase+0xc), cnt);
1064 #endif
1065 if (signal_pending(current)) {
1066 if (!ret)
1067 ret = -ERESTARTSYS;
1068 break;
1069 }
1070 continue;
1071 }
1072 if (copy_to_user(buffer, s->dma_adc.rawbuf + swptr, cnt)) {
1073 if (!ret)
1074 ret = -EFAULT;
1075 break;
1076 }
1077 swptr = (swptr + cnt) % s->dma_adc.dmasize;
1078 spin_lock_irqsave(&s->lock, flags);
1079 s->dma_adc.swptr = swptr;
1080 s->dma_adc.count -= cnt;
1081 spin_unlock_irqrestore(&s->lock, flags);
1082 count -= cnt;
1083 buffer += cnt;
1084 ret += cnt;
1085 if (s->dma_adc.enabled)
1086 start_adc(s);
1087 #ifdef DEBUGREC
1088 printk(KERN_DEBUG "solo1_read: reg B8: 0x%02x DMAstat: 0x%02x DMAcnt: 0x%04x SBstat: 0x%02x\n",
1089 read_ctrl(s, 0xb8), inb(s->ddmabase+8), inw(s->ddmabase+4), inb(s->sbbase+0xc));
1090 #endif
1091 }
1092 remove_wait_queue(&s->dma_adc.wait, &wait);
1093 set_current_state(TASK_RUNNING);
1094 return ret;
1095 }
1096
1097 static ssize_t solo1_write(struct file *file, const char *buffer, size_t count, loff_t *ppos)
1098 {
1099 struct solo1_state *s = (struct solo1_state *)file->private_data;
1100 DECLARE_WAITQUEUE(wait, current);
1101 ssize_t ret;
1102 unsigned long flags;
1103 unsigned swptr;
1104 int cnt;
1105
1106 VALIDATE_STATE(s);
1107 if (ppos != &file->f_pos)
1108 return -ESPIPE;
1109 if (s->dma_dac.mapped)
1110 return -ENXIO;
1111 if (!s->dma_dac.ready && (ret = prog_dmabuf_dac(s)))
1112 return ret;
1113 if (!access_ok(VERIFY_READ, buffer, count))
1114 return -EFAULT;
1115 #if 0
1116 printk(KERN_DEBUG "solo1_write: reg 70: 0x%02x 71: 0x%02x 72: 0x%02x 74: 0x%02x 76: 0x%02x 78: 0x%02x 7A: 0x%02x\n"
1117 KERN_DEBUG "solo1_write: DMA: addr: 0x%08x cnt: 0x%04x stat: 0x%02x SBstat: 0x%02x\n",
1118 read_mixer(s, 0x70), read_mixer(s, 0x71), read_mixer(s, 0x72), read_mixer(s, 0x74), read_mixer(s, 0x76),
1119 read_mixer(s, 0x78), read_mixer(s, 0x7a), inl(s->iobase), inw(s->iobase+4), inb(s->iobase+6), inb(s->sbbase+0xc));
1120 printk(KERN_DEBUG "solo1_write: reg 78: 0x%02x reg 7A: 0x%02x DMAcnt: 0x%04x DMAstat: 0x%02x SBstat: 0x%02x\n",
1121 read_mixer(s, 0x78), read_mixer(s, 0x7a), inw(s->iobase+4), inb(s->iobase+6), inb(s->sbbase+0xc));
1122 #endif
1123 ret = 0;
1124 add_wait_queue(&s->dma_dac.wait, &wait);
1125 while (count > 0) {
1126 spin_lock_irqsave(&s->lock, flags);
1127 if (s->dma_dac.count < 0) {
1128 s->dma_dac.count = 0;
1129 s->dma_dac.swptr = s->dma_dac.hwptr;
1130 }
1131 swptr = s->dma_dac.swptr;
1132 cnt = s->dma_dac.dmasize-swptr;
1133 if (s->dma_dac.count + cnt > s->dma_dac.dmasize)
1134 cnt = s->dma_dac.dmasize - s->dma_dac.count;
1135 if (cnt <= 0)
1136 __set_current_state(TASK_INTERRUPTIBLE);
1137 spin_unlock_irqrestore(&s->lock, flags);
1138 if (cnt > count)
1139 cnt = count;
1140 if (cnt <= 0) {
1141 if (s->dma_dac.enabled)
1142 start_dac(s);
1143 if (file->f_flags & O_NONBLOCK) {
1144 if (!ret)
1145 ret = -EAGAIN;
1146 break;
1147 }
1148 schedule();
1149 if (signal_pending(current)) {
1150 if (!ret)
1151 ret = -ERESTARTSYS;
1152 break;
1153 }
1154 continue;
1155 }
1156 if (copy_from_user(s->dma_dac.rawbuf + swptr, buffer, cnt)) {
1157 if (!ret)
1158 ret = -EFAULT;
1159 break;
1160 }
1161 swptr = (swptr + cnt) % s->dma_dac.dmasize;
1162 spin_lock_irqsave(&s->lock, flags);
1163 s->dma_dac.swptr = swptr;
1164 s->dma_dac.count += cnt;
1165 s->dma_dac.endcleared = 0;
1166 spin_unlock_irqrestore(&s->lock, flags);
1167 count -= cnt;
1168 buffer += cnt;
1169 ret += cnt;
1170 if (s->dma_dac.enabled)
1171 start_dac(s);
1172 }
1173 remove_wait_queue(&s->dma_dac.wait, &wait);
1174 set_current_state(TASK_RUNNING);
1175 return ret;
1176 }
1177
1178 /* No kernel lock - we have our own spinlock */
1179 static unsigned int solo1_poll(struct file *file, struct poll_table_struct *wait)
1180 {
1181 struct solo1_state *s = (struct solo1_state *)file->private_data;
1182 unsigned long flags;
1183 unsigned int mask = 0;
1184
1185 VALIDATE_STATE(s);
1186 if (file->f_mode & FMODE_WRITE) {
1187 if (!s->dma_dac.ready && prog_dmabuf_dac(s))
1188 return 0;
1189 poll_wait(file, &s->dma_dac.wait, wait);
1190 }
1191 if (file->f_mode & FMODE_READ) {
1192 if (!s->dma_adc.ready && prog_dmabuf_adc(s))
1193 return 0;
1194 poll_wait(file, &s->dma_adc.wait, wait);
1195 }
1196 spin_lock_irqsave(&s->lock, flags);
1197 solo1_update_ptr(s);
1198 if (file->f_mode & FMODE_READ) {
1199 if (s->dma_adc.mapped) {
1200 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
1201 mask |= POLLIN | POLLRDNORM;
1202 } else {
1203 if (s->dma_adc.count > 0)
1204 mask |= POLLIN | POLLRDNORM;
1205 }
1206 }
1207 if (file->f_mode & FMODE_WRITE) {
1208 if (s->dma_dac.mapped) {
1209 if (s->dma_dac.count >= (signed)s->dma_dac.fragsize)
1210 mask |= POLLOUT | POLLWRNORM;
1211 } else {
1212 if ((signed)s->dma_dac.dmasize > s->dma_dac.count)
1213 mask |= POLLOUT | POLLWRNORM;
1214 }
1215 }
1216 spin_unlock_irqrestore(&s->lock, flags);
1217 return mask;
1218 }
1219
1220
1221 static int solo1_mmap(struct file *file, struct vm_area_struct *vma)
1222 {
1223 struct solo1_state *s = (struct solo1_state *)file->private_data;
1224 struct dmabuf *db;
1225 int ret = -EINVAL;
1226 unsigned long size;
1227
1228 VALIDATE_STATE(s);
1229 lock_kernel();
1230 if (vma->vm_flags & VM_WRITE) {
1231 if ((ret = prog_dmabuf_dac(s)) != 0)
1232 goto out;
1233 db = &s->dma_dac;
1234 } else if (vma->vm_flags & VM_READ) {
1235 if ((ret = prog_dmabuf_adc(s)) != 0)
1236 goto out;
1237 db = &s->dma_adc;
1238 } else
1239 goto out;
1240 ret = -EINVAL;
1241 if (vma->vm_pgoff != 0)
1242 goto out;
1243 size = vma->vm_end - vma->vm_start;
1244 if (size > (PAGE_SIZE << db->buforder))
1245 goto out;
1246 ret = -EAGAIN;
1247 if (remap_page_range(vma, vma->vm_start, virt_to_phys(db->rawbuf), size, vma->vm_page_prot))
1248 goto out;
1249 db->mapped = 1;
1250 ret = 0;
1251 out:
1252 unlock_kernel();
1253 return ret;
1254 }
1255
1256 static int solo1_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
1257 {
1258 struct solo1_state *s = (struct solo1_state *)file->private_data;
1259 unsigned long flags;
1260 audio_buf_info abinfo;
1261 count_info cinfo;
1262 int val, mapped, ret, count;
1263 int div1, div2;
1264 unsigned rate1, rate2;
1265
1266 VALIDATE_STATE(s);
1267 mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
1268 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1269 switch (cmd) {
1270 case OSS_GETVERSION:
1271 return put_user(SOUND_VERSION, (int *)arg);
1272
1273 case SNDCTL_DSP_SYNC:
1274 if (file->f_mode & FMODE_WRITE)
1275 return drain_dac(s, 0/*file->f_flags & O_NONBLOCK*/);
1276 return 0;
1277
1278 case SNDCTL_DSP_SETDUPLEX:
1279 return 0;
1280
1281 case SNDCTL_DSP_GETCAPS:
1282 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME | DSP_CAP_TRIGGER | DSP_CAP_MMAP, (int *)arg);
1283
1284 case SNDCTL_DSP_RESET:
1285 if (file->f_mode & FMODE_WRITE) {
1286 stop_dac(s);
1287 synchronize_irq(s->irq);
1288 s->dma_dac.swptr = s->dma_dac.hwptr = s->dma_dac.count = s->dma_dac.total_bytes = 0;
1289 }
1290 if (file->f_mode & FMODE_READ) {
1291 stop_adc(s);
1292 synchronize_irq(s->irq);
1293 s->dma_adc.swptr = s->dma_adc.hwptr = s->dma_adc.count = s->dma_adc.total_bytes = 0;
1294 }
1295 prog_codec(s);
1296 return 0;
1297
1298 case SNDCTL_DSP_SPEED:
1299 if (get_user(val, (int *)arg))
1300 return -EFAULT;
1301 if (val >= 0) {
1302 stop_adc(s);
1303 stop_dac(s);
1304 s->dma_adc.ready = s->dma_dac.ready = 0;
1305 /* program sampling rates */
1306 if (val > 48000)
1307 val = 48000;
1308 if (val < 6300)
1309 val = 6300;
1310 div1 = (768000 + val / 2) / val;
1311 rate1 = (768000 + div1 / 2) / div1;
1312 div1 = -div1;
1313 div2 = (793800 + val / 2) / val;
1314 rate2 = (793800 + div2 / 2) / div2;
1315 div2 = (-div2) & 0x7f;
1316 if (abs(val - rate2) < abs(val - rate1)) {
1317 rate1 = rate2;
1318 div1 = div2;
1319 }
1320 s->rate = rate1;
1321 s->clkdiv = div1;
1322 prog_codec(s);
1323 }
1324 return put_user(s->rate, (int *)arg);
1325
1326 case SNDCTL_DSP_STEREO:
1327 if (get_user(val, (int *)arg))
1328 return -EFAULT;
1329 stop_adc(s);
1330 stop_dac(s);
1331 s->dma_adc.ready = s->dma_dac.ready = 0;
1332 /* program channels */
1333 s->channels = val ? 2 : 1;
1334 prog_codec(s);
1335 return 0;
1336
1337 case SNDCTL_DSP_CHANNELS:
1338 if (get_user(val, (int *)arg))
1339 return -EFAULT;
1340 if (val != 0) {
1341 stop_adc(s);
1342 stop_dac(s);
1343 s->dma_adc.ready = s->dma_dac.ready = 0;
1344 /* program channels */
1345 s->channels = (val >= 2) ? 2 : 1;
1346 prog_codec(s);
1347 }
1348 return put_user(s->channels, (int *)arg);
1349
1350 case SNDCTL_DSP_GETFMTS: /* Returns a mask */
1351 return put_user(AFMT_S16_LE|AFMT_U16_LE|AFMT_S8|AFMT_U8, (int *)arg);
1352
1353 case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
1354 if (get_user(val, (int *)arg))
1355 return -EFAULT;
1356 if (val != AFMT_QUERY) {
1357 stop_adc(s);
1358 stop_dac(s);
1359 s->dma_adc.ready = s->dma_dac.ready = 0;
1360 /* program format */
1361 if (val != AFMT_S16_LE && val != AFMT_U16_LE &&
1362 val != AFMT_S8 && val != AFMT_U8)
1363 val = AFMT_U8;
1364 s->fmt = val;
1365 prog_codec(s);
1366 }
1367 return put_user(s->fmt, (int *)arg);
1368
1369 case SNDCTL_DSP_POST:
1370 return 0;
1371
1372 case SNDCTL_DSP_GETTRIGGER:
1373 val = 0;
1374 if (file->f_mode & s->ena & FMODE_READ)
1375 val |= PCM_ENABLE_INPUT;
1376 if (file->f_mode & s->ena & FMODE_WRITE)
1377 val |= PCM_ENABLE_OUTPUT;
1378 return put_user(val, (int *)arg);
1379
1380 case SNDCTL_DSP_SETTRIGGER:
1381 if (get_user(val, (int *)arg))
1382 return -EFAULT;
1383 if (file->f_mode & FMODE_READ) {
1384 if (val & PCM_ENABLE_INPUT) {
1385 if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
1386 return ret;
1387 s->dma_dac.enabled = 1;
1388 start_adc(s);
1389 if (inb(s->ddmabase+15) & 1)
1390 printk(KERN_ERR "solo1: cannot start recording, DDMA mask bit stuck at 1\n");
1391 } else {
1392 s->dma_dac.enabled = 0;
1393 stop_adc(s);
1394 }
1395 }
1396 if (file->f_mode & FMODE_WRITE) {
1397 if (val & PCM_ENABLE_OUTPUT) {
1398 if (!s->dma_dac.ready && (ret = prog_dmabuf_dac(s)))
1399 return ret;
1400 s->dma_dac.enabled = 1;
1401 start_dac(s);
1402 } else {
1403 s->dma_dac.enabled = 0;
1404 stop_dac(s);
1405 }
1406 }
1407 return 0;
1408
1409 case SNDCTL_DSP_GETOSPACE:
1410 if (!(file->f_mode & FMODE_WRITE))
1411 return -EINVAL;
1412 if (!s->dma_dac.ready && (val = prog_dmabuf_dac(s)) != 0)
1413 return val;
1414 spin_lock_irqsave(&s->lock, flags);
1415 solo1_update_ptr(s);
1416 abinfo.fragsize = s->dma_dac.fragsize;
1417 count = s->dma_dac.count;
1418 if (count < 0)
1419 count = 0;
1420 abinfo.bytes = s->dma_dac.dmasize - count;
1421 abinfo.fragstotal = s->dma_dac.numfrag;
1422 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
1423 spin_unlock_irqrestore(&s->lock, flags);
1424 return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
1425
1426 case SNDCTL_DSP_GETISPACE:
1427 if (!(file->f_mode & FMODE_READ))
1428 return -EINVAL;
1429 if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s)) != 0)
1430 return val;
1431 spin_lock_irqsave(&s->lock, flags);
1432 solo1_update_ptr(s);
1433 abinfo.fragsize = s->dma_adc.fragsize;
1434 abinfo.bytes = s->dma_adc.count;
1435 abinfo.fragstotal = s->dma_adc.numfrag;
1436 abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
1437 spin_unlock_irqrestore(&s->lock, flags);
1438 return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
1439
1440 case SNDCTL_DSP_NONBLOCK:
1441 file->f_flags |= O_NONBLOCK;
1442 return 0;
1443
1444 case SNDCTL_DSP_GETODELAY:
1445 if (!(file->f_mode & FMODE_WRITE))
1446 return -EINVAL;
1447 if (!s->dma_dac.ready && (val = prog_dmabuf_dac(s)) != 0)
1448 return val;
1449 spin_lock_irqsave(&s->lock, flags);
1450 solo1_update_ptr(s);
1451 count = s->dma_dac.count;
1452 spin_unlock_irqrestore(&s->lock, flags);
1453 if (count < 0)
1454 count = 0;
1455 return put_user(count, (int *)arg);
1456
1457 case SNDCTL_DSP_GETIPTR:
1458 if (!(file->f_mode & FMODE_READ))
1459 return -EINVAL;
1460 if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s)) != 0)
1461 return val;
1462 spin_lock_irqsave(&s->lock, flags);
1463 solo1_update_ptr(s);
1464 cinfo.bytes = s->dma_adc.total_bytes;
1465 cinfo.blocks = s->dma_adc.count >> s->dma_adc.fragshift;
1466 cinfo.ptr = s->dma_adc.hwptr;
1467 if (s->dma_adc.mapped)
1468 s->dma_adc.count &= s->dma_adc.fragsize-1;
1469 spin_unlock_irqrestore(&s->lock, flags);
1470 if (copy_to_user((void *)arg, &cinfo, sizeof(cinfo)))
1471 return -EFAULT;
1472 return 0;
1473
1474 case SNDCTL_DSP_GETOPTR:
1475 if (!(file->f_mode & FMODE_WRITE))
1476 return -EINVAL;
1477 if (!s->dma_dac.ready && (val = prog_dmabuf_dac(s)) != 0)
1478 return val;
1479 spin_lock_irqsave(&s->lock, flags);
1480 solo1_update_ptr(s);
1481 cinfo.bytes = s->dma_dac.total_bytes;
1482 count = s->dma_dac.count;
1483 if (count < 0)
1484 count = 0;
1485 cinfo.blocks = count >> s->dma_dac.fragshift;
1486 cinfo.ptr = s->dma_dac.hwptr;
1487 if (s->dma_dac.mapped)
1488 s->dma_dac.count &= s->dma_dac.fragsize-1;
1489 spin_unlock_irqrestore(&s->lock, flags);
1490 #if 0
1491 printk(KERN_DEBUG "esssolo1: GETOPTR: bytes %u blocks %u ptr %u, buforder %u numfrag %u fragshift %u\n"
1492 KERN_DEBUG "esssolo1: swptr %u count %u fragsize %u dmasize %u fragsamples %u\n",
1493 cinfo.bytes, cinfo.blocks, cinfo.ptr, s->dma_dac.buforder, s->dma_dac.numfrag, s->dma_dac.fragshift,
1494 s->dma_dac.swptr, s->dma_dac.count, s->dma_dac.fragsize, s->dma_dac.dmasize, s->dma_dac.fragsamples);
1495 #endif
1496 if (copy_to_user((void *)arg, &cinfo, sizeof(cinfo)))
1497 return -EFAULT;
1498 return 0;
1499
1500 case SNDCTL_DSP_GETBLKSIZE:
1501 if (file->f_mode & FMODE_WRITE) {
1502 if ((val = prog_dmabuf_dac(s)))
1503 return val;
1504 return put_user(s->dma_dac.fragsize, (int *)arg);
1505 }
1506 if ((val = prog_dmabuf_adc(s)))
1507 return val;
1508 return put_user(s->dma_adc.fragsize, (int *)arg);
1509
1510 case SNDCTL_DSP_SETFRAGMENT:
1511 if (get_user(val, (int *)arg))
1512 return -EFAULT;
1513 if (file->f_mode & FMODE_READ) {
1514 s->dma_adc.ossfragshift = val & 0xffff;
1515 s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
1516 if (s->dma_adc.ossfragshift < 4)
1517 s->dma_adc.ossfragshift = 4;
1518 if (s->dma_adc.ossfragshift > 15)
1519 s->dma_adc.ossfragshift = 15;
1520 if (s->dma_adc.ossmaxfrags < 4)
1521 s->dma_adc.ossmaxfrags = 4;
1522 }
1523 if (file->f_mode & FMODE_WRITE) {
1524 s->dma_dac.ossfragshift = val & 0xffff;
1525 s->dma_dac.ossmaxfrags = (val >> 16) & 0xffff;
1526 if (s->dma_dac.ossfragshift < 4)
1527 s->dma_dac.ossfragshift = 4;
1528 if (s->dma_dac.ossfragshift > 15)
1529 s->dma_dac.ossfragshift = 15;
1530 if (s->dma_dac.ossmaxfrags < 4)
1531 s->dma_dac.ossmaxfrags = 4;
1532 }
1533 return 0;
1534
1535 case SNDCTL_DSP_SUBDIVIDE:
1536 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
1537 (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision))
1538 return -EINVAL;
1539 if (get_user(val, (int *)arg))
1540 return -EFAULT;
1541 if (val != 1 && val != 2 && val != 4)
1542 return -EINVAL;
1543 if (file->f_mode & FMODE_READ)
1544 s->dma_adc.subdivision = val;
1545 if (file->f_mode & FMODE_WRITE)
1546 s->dma_dac.subdivision = val;
1547 return 0;
1548
1549 case SOUND_PCM_READ_RATE:
1550 return put_user(s->rate, (int *)arg);
1551
1552 case SOUND_PCM_READ_CHANNELS:
1553 return put_user(s->channels, (int *)arg);
1554
1555 case SOUND_PCM_READ_BITS:
1556 return put_user((s->fmt & (AFMT_S8|AFMT_U8)) ? 8 : 16, (int *)arg);
1557
1558 case SOUND_PCM_WRITE_FILTER:
1559 case SNDCTL_DSP_SETSYNCRO:
1560 case SOUND_PCM_READ_FILTER:
1561 return -EINVAL;
1562
1563 }
1564 return mixer_ioctl(s, cmd, arg);
1565 }
1566
1567 static int solo1_release(struct inode *inode, struct file *file)
1568 {
1569 struct solo1_state *s = (struct solo1_state *)file->private_data;
1570
1571 VALIDATE_STATE(s);
1572 lock_kernel();
1573 if (file->f_mode & FMODE_WRITE)
1574 drain_dac(s, file->f_flags & O_NONBLOCK);
1575 down(&s->open_sem);
1576 if (file->f_mode & FMODE_WRITE) {
1577 stop_dac(s);
1578 outb(0, s->iobase+6); /* disable DMA */
1579 dealloc_dmabuf(s, &s->dma_dac);
1580 }
1581 if (file->f_mode & FMODE_READ) {
1582 stop_adc(s);
1583 outb(1, s->ddmabase+0xf); /* mask DMA channel */
1584 outb(0, s->ddmabase+0xd); /* DMA master clear */
1585 dealloc_dmabuf(s, &s->dma_adc);
1586 }
1587 s->open_mode &= ~(FMODE_READ | FMODE_WRITE);
1588 wake_up(&s->open_wait);
1589 up(&s->open_sem);
1590 unlock_kernel();
1591 return 0;
1592 }
1593
1594 static int solo1_open(struct inode *inode, struct file *file)
1595 {
1596 unsigned int minor = minor(inode->i_rdev);
1597 DECLARE_WAITQUEUE(wait, current);
1598 struct solo1_state *s = NULL;
1599 struct pci_dev *pci_dev;
1600
1601 pci_for_each_dev(pci_dev) {
1602 struct pci_driver *drvr;
1603
1604 drvr = pci_dev_driver(pci_dev);
1605 if (drvr != &solo1_driver)
1606 continue;
1607 s = (struct solo1_state*)pci_get_drvdata(pci_dev);
1608 if (!s)
1609 continue;
1610 if (!((s->dev_audio ^ minor) & ~0xf))
1611 break;
1612 }
1613 if (!s)
1614 return -ENODEV;
1615 VALIDATE_STATE(s);
1616 file->private_data = s;
1617 /* wait for device to become free */
1618 down(&s->open_sem);
1619 while (s->open_mode & (FMODE_READ | FMODE_WRITE)) {
1620 if (file->f_flags & O_NONBLOCK) {
1621 up(&s->open_sem);
1622 return -EBUSY;
1623 }
1624 add_wait_queue(&s->open_wait, &wait);
1625 __set_current_state(TASK_INTERRUPTIBLE);
1626 up(&s->open_sem);
1627 schedule();
1628 remove_wait_queue(&s->open_wait, &wait);
1629 set_current_state(TASK_RUNNING);
1630 if (signal_pending(current))
1631 return -ERESTARTSYS;
1632 down(&s->open_sem);
1633 }
1634 s->fmt = AFMT_U8;
1635 s->channels = 1;
1636 s->rate = 8000;
1637 s->clkdiv = 96 | 0x80;
1638 s->ena = 0;
1639 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags = s->dma_adc.subdivision = 0;
1640 s->dma_adc.enabled = 1;
1641 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags = s->dma_dac.subdivision = 0;
1642 s->dma_dac.enabled = 1;
1643 s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
1644 up(&s->open_sem);
1645 prog_codec(s);
1646 return 0;
1647 }
1648
1649 static /*const*/ struct file_operations solo1_audio_fops = {
1650 owner: THIS_MODULE,
1651 llseek: no_llseek,
1652 read: solo1_read,
1653 write: solo1_write,
1654 poll: solo1_poll,
1655 ioctl: solo1_ioctl,
1656 mmap: solo1_mmap,
1657 open: solo1_open,
1658 release: solo1_release,
1659 };
1660
1661 /* --------------------------------------------------------------------- */
1662
1663 /* hold spinlock for the following! */
1664 static void solo1_handle_midi(struct solo1_state *s)
1665 {
1666 unsigned char ch;
1667 int wake;
1668
1669 if (!(s->mpubase))
1670 return;
1671 wake = 0;
1672 while (!(inb(s->mpubase+1) & 0x80)) {
1673 ch = inb(s->mpubase);
1674 if (s->midi.icnt < MIDIINBUF) {
1675 s->midi.ibuf[s->midi.iwr] = ch;
1676 s->midi.iwr = (s->midi.iwr + 1) % MIDIINBUF;
1677 s->midi.icnt++;
1678 }
1679 wake = 1;
1680 }
1681 if (wake)
1682 wake_up(&s->midi.iwait);
1683 wake = 0;
1684 while (!(inb(s->mpubase+1) & 0x40) && s->midi.ocnt > 0) {
1685 outb(s->midi.obuf[s->midi.ord], s->mpubase);
1686 s->midi.ord = (s->midi.ord + 1) % MIDIOUTBUF;
1687 s->midi.ocnt--;
1688 if (s->midi.ocnt < MIDIOUTBUF-16)
1689 wake = 1;
1690 }
1691 if (wake)
1692 wake_up(&s->midi.owait);
1693 }
1694
1695 static void solo1_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1696 {
1697 struct solo1_state *s = (struct solo1_state *)dev_id;
1698 unsigned int intsrc;
1699
1700 /* fastpath out, to ease interrupt sharing */
1701 intsrc = inb(s->iobase+7); /* get interrupt source(s) */
1702 if (!intsrc)
1703 return;
1704 (void)inb(s->sbbase+0xe); /* clear interrupt */
1705 spin_lock(&s->lock);
1706 /* clear audio interrupts first */
1707 if (intsrc & 0x20)
1708 write_mixer(s, 0x7a, read_mixer(s, 0x7a) & 0x7f);
1709 solo1_update_ptr(s);
1710 solo1_handle_midi(s);
1711 spin_unlock(&s->lock);
1712 }
1713
1714 static void solo1_midi_timer(unsigned long data)
1715 {
1716 struct solo1_state *s = (struct solo1_state *)data;
1717 unsigned long flags;
1718
1719 spin_lock_irqsave(&s->lock, flags);
1720 solo1_handle_midi(s);
1721 spin_unlock_irqrestore(&s->lock, flags);
1722 s->midi.timer.expires = jiffies+1;
1723 add_timer(&s->midi.timer);
1724 }
1725
1726 /* --------------------------------------------------------------------- */
1727
1728 static ssize_t solo1_midi_read(struct file *file, char *buffer, size_t count, loff_t *ppos)
1729 {
1730 struct solo1_state *s = (struct solo1_state *)file->private_data;
1731 DECLARE_WAITQUEUE(wait, current);
1732 ssize_t ret;
1733 unsigned long flags;
1734 unsigned ptr;
1735 int cnt;
1736
1737 VALIDATE_STATE(s);
1738 if (ppos != &file->f_pos)
1739 return -ESPIPE;
1740 if (!access_ok(VERIFY_WRITE, buffer, count))
1741 return -EFAULT;
1742 if (count == 0)
1743 return 0;
1744 ret = 0;
1745 add_wait_queue(&s->midi.iwait, &wait);
1746 while (count > 0) {
1747 spin_lock_irqsave(&s->lock, flags);
1748 ptr = s->midi.ird;
1749 cnt = MIDIINBUF - ptr;
1750 if (s->midi.icnt < cnt)
1751 cnt = s->midi.icnt;
1752 if (cnt <= 0)
1753 __set_current_state(TASK_INTERRUPTIBLE);
1754 spin_unlock_irqrestore(&s->lock, flags);
1755 if (cnt > count)
1756 cnt = count;
1757 if (cnt <= 0) {
1758 if (file->f_flags & O_NONBLOCK) {
1759 if (!ret)
1760 ret = -EAGAIN;
1761 break;
1762 }
1763 schedule();
1764 if (signal_pending(current)) {
1765 if (!ret)
1766 ret = -ERESTARTSYS;
1767 break;
1768 }
1769 continue;
1770 }
1771 if (copy_to_user(buffer, s->midi.ibuf + ptr, cnt)) {
1772 if (!ret)
1773 ret = -EFAULT;
1774 break;
1775 }
1776 ptr = (ptr + cnt) % MIDIINBUF;
1777 spin_lock_irqsave(&s->lock, flags);
1778 s->midi.ird = ptr;
1779 s->midi.icnt -= cnt;
1780 spin_unlock_irqrestore(&s->lock, flags);
1781 count -= cnt;
1782 buffer += cnt;
1783 ret += cnt;
1784 break;
1785 }
1786 __set_current_state(TASK_RUNNING);
1787 remove_wait_queue(&s->midi.iwait, &wait);
1788 return ret;
1789 }
1790
1791 static ssize_t solo1_midi_write(struct file *file, const char *buffer, size_t count, loff_t *ppos)
1792 {
1793 struct solo1_state *s = (struct solo1_state *)file->private_data;
1794 DECLARE_WAITQUEUE(wait, current);
1795 ssize_t ret;
1796 unsigned long flags;
1797 unsigned ptr;
1798 int cnt;
1799
1800 VALIDATE_STATE(s);
1801 if (ppos != &file->f_pos)
1802 return -ESPIPE;
1803 if (!access_ok(VERIFY_READ, buffer, count))
1804 return -EFAULT;
1805 if (count == 0)
1806 return 0;
1807 ret = 0;
1808 add_wait_queue(&s->midi.owait, &wait);
1809 while (count > 0) {
1810 spin_lock_irqsave(&s->lock, flags);
1811 ptr = s->midi.owr;
1812 cnt = MIDIOUTBUF - ptr;
1813 if (s->midi.ocnt + cnt > MIDIOUTBUF)
1814 cnt = MIDIOUTBUF - s->midi.ocnt;
1815 if (cnt <= 0) {
1816 __set_current_state(TASK_INTERRUPTIBLE);
1817 solo1_handle_midi(s);
1818 }
1819 spin_unlock_irqrestore(&s->lock, flags);
1820 if (cnt > count)
1821 cnt = count;
1822 if (cnt <= 0) {
1823 if (file->f_flags & O_NONBLOCK) {
1824 if (!ret)
1825 ret = -EAGAIN;
1826 break;
1827 }
1828 schedule();
1829 if (signal_pending(current)) {
1830 if (!ret)
1831 ret = -ERESTARTSYS;
1832 break;
1833 }
1834 continue;
1835 }
1836 if (copy_from_user(s->midi.obuf + ptr, buffer, cnt)) {
1837 if (!ret)
1838 ret = -EFAULT;
1839 break;
1840 }
1841 ptr = (ptr + cnt) % MIDIOUTBUF;
1842 spin_lock_irqsave(&s->lock, flags);
1843 s->midi.owr = ptr;
1844 s->midi.ocnt += cnt;
1845 spin_unlock_irqrestore(&s->lock, flags);
1846 count -= cnt;
1847 buffer += cnt;
1848 ret += cnt;
1849 spin_lock_irqsave(&s->lock, flags);
1850 solo1_handle_midi(s);
1851 spin_unlock_irqrestore(&s->lock, flags);
1852 }
1853 __set_current_state(TASK_RUNNING);
1854 remove_wait_queue(&s->midi.owait, &wait);
1855 return ret;
1856 }
1857
1858 /* No kernel lock - we have our own spinlock */
1859 static unsigned int solo1_midi_poll(struct file *file, struct poll_table_struct *wait)
1860 {
1861 struct solo1_state *s = (struct solo1_state *)file->private_data;
1862 unsigned long flags;
1863 unsigned int mask = 0;
1864
1865 VALIDATE_STATE(s);
1866 if (file->f_flags & FMODE_WRITE)
1867 poll_wait(file, &s->midi.owait, wait);
1868 if (file->f_flags & FMODE_READ)
1869 poll_wait(file, &s->midi.iwait, wait);
1870 spin_lock_irqsave(&s->lock, flags);
1871 if (file->f_flags & FMODE_READ) {
1872 if (s->midi.icnt > 0)
1873 mask |= POLLIN | POLLRDNORM;
1874 }
1875 if (file->f_flags & FMODE_WRITE) {
1876 if (s->midi.ocnt < MIDIOUTBUF)
1877 mask |= POLLOUT | POLLWRNORM;
1878 }
1879 spin_unlock_irqrestore(&s->lock, flags);
1880 return mask;
1881 }
1882
1883 static int solo1_midi_open(struct inode *inode, struct file *file)
1884 {
1885 unsigned int minor = minor(inode->i_rdev);
1886 DECLARE_WAITQUEUE(wait, current);
1887 unsigned long flags;
1888 struct solo1_state *s = NULL;
1889 struct pci_dev *pci_dev;
1890
1891 pci_for_each_dev(pci_dev) {
1892 struct pci_driver *drvr;
1893
1894 drvr = pci_dev_driver(pci_dev);
1895 if (drvr != &solo1_driver)
1896 continue;
1897 s = (struct solo1_state*)pci_get_drvdata(pci_dev);
1898 if (!s)
1899 continue;
1900 if (s->dev_midi == minor)
1901 break;
1902 }
1903 if (!s)
1904 return -ENODEV;
1905 VALIDATE_STATE(s);
1906 file->private_data = s;
1907 /* wait for device to become free */
1908 down(&s->open_sem);
1909 while (s->open_mode & (file->f_mode << FMODE_MIDI_SHIFT)) {
1910 if (file->f_flags & O_NONBLOCK) {
1911 up(&s->open_sem);
1912 return -EBUSY;
1913 }
1914 add_wait_queue(&s->open_wait, &wait);
1915 __set_current_state(TASK_INTERRUPTIBLE);
1916 up(&s->open_sem);
1917 schedule();
1918 remove_wait_queue(&s->open_wait, &wait);
1919 set_current_state(TASK_RUNNING);
1920 if (signal_pending(current))
1921 return -ERESTARTSYS;
1922 down(&s->open_sem);
1923 }
1924 spin_lock_irqsave(&s->lock, flags);
1925 if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
1926 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
1927 s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
1928 outb(0xff, s->mpubase+1); /* reset command */
1929 outb(0x3f, s->mpubase+1); /* uart command */
1930 if (!(inb(s->mpubase+1) & 0x80))
1931 inb(s->mpubase);
1932 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
1933 outb(0xb0, s->iobase + 7); /* enable A1, A2, MPU irq's */
1934 init_timer(&s->midi.timer);
1935 s->midi.timer.expires = jiffies+1;
1936 s->midi.timer.data = (unsigned long)s;
1937 s->midi.timer.function = solo1_midi_timer;
1938 add_timer(&s->midi.timer);
1939 }
1940 if (file->f_mode & FMODE_READ) {
1941 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
1942 }
1943 if (file->f_mode & FMODE_WRITE) {
1944 s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
1945 }
1946 spin_unlock_irqrestore(&s->lock, flags);
1947 s->open_mode |= (file->f_mode << FMODE_MIDI_SHIFT) & (FMODE_MIDI_READ | FMODE_MIDI_WRITE);
1948 up(&s->open_sem);
1949 return 0;
1950 }
1951
1952 static int solo1_midi_release(struct inode *inode, struct file *file)
1953 {
1954 struct solo1_state *s = (struct solo1_state *)file->private_data;
1955 DECLARE_WAITQUEUE(wait, current);
1956 unsigned long flags;
1957 unsigned count, tmo;
1958
1959 VALIDATE_STATE(s);
1960
1961 lock_kernel();
1962 if (file->f_mode & FMODE_WRITE) {
1963 add_wait_queue(&s->midi.owait, &wait);
1964 for (;;) {
1965 __set_current_state(TASK_INTERRUPTIBLE);
1966 spin_lock_irqsave(&s->lock, flags);
1967 count = s->midi.ocnt;
1968 spin_unlock_irqrestore(&s->lock, flags);
1969 if (count <= 0)
1970 break;
1971 if (signal_pending(current))
1972 break;
1973 if (file->f_flags & O_NONBLOCK) {
1974 remove_wait_queue(&s->midi.owait, &wait);
1975 set_current_state(TASK_RUNNING);
1976 unlock_kernel();
1977 return -EBUSY;
1978 }
1979 tmo = (count * HZ) / 3100;
1980 if (!schedule_timeout(tmo ? : 1) && tmo)
1981 printk(KERN_DEBUG "solo1: midi timed out??\n");
1982 }
1983 remove_wait_queue(&s->midi.owait, &wait);
1984 set_current_state(TASK_RUNNING);
1985 }
1986 down(&s->open_sem);
1987 s->open_mode &= (~(file->f_mode << FMODE_MIDI_SHIFT)) & (FMODE_MIDI_READ|FMODE_MIDI_WRITE);
1988 spin_lock_irqsave(&s->lock, flags);
1989 if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
1990 outb(0x30, s->iobase + 7); /* enable A1, A2 irq's */
1991 del_timer(&s->midi.timer);
1992 }
1993 spin_unlock_irqrestore(&s->lock, flags);
1994 wake_up(&s->open_wait);
1995 up(&s->open_sem);
1996 unlock_kernel();
1997 return 0;
1998 }
1999
2000 static /*const*/ struct file_operations solo1_midi_fops = {
2001 owner: THIS_MODULE,
2002 llseek: no_llseek,
2003 read: solo1_midi_read,
2004 write: solo1_midi_write,
2005 poll: solo1_midi_poll,
2006 open: solo1_midi_open,
2007 release: solo1_midi_release,
2008 };
2009
2010 /* --------------------------------------------------------------------- */
2011
2012 static int solo1_dmfm_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
2013 {
2014 static const unsigned char op_offset[18] = {
2015 0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
2016 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D,
2017 0x10, 0x11, 0x12, 0x13, 0x14, 0x15
2018 };
2019 struct solo1_state *s = (struct solo1_state *)file->private_data;
2020 struct dm_fm_voice v;
2021 struct dm_fm_note n;
2022 struct dm_fm_params p;
2023 unsigned int io;
2024 unsigned int regb;
2025
2026 switch (cmd) {
2027 case FM_IOCTL_RESET:
2028 for (regb = 0xb0; regb < 0xb9; regb++) {
2029 outb(regb, s->sbbase);
2030 outb(0, s->sbbase+1);
2031 outb(regb, s->sbbase+2);
2032 outb(0, s->sbbase+3);
2033 }
2034 return 0;
2035
2036 case FM_IOCTL_PLAY_NOTE:
2037 if (copy_from_user(&n, (void *)arg, sizeof(n)))
2038 return -EFAULT;
2039 if (n.voice >= 18)
2040 return -EINVAL;
2041 if (n.voice >= 9) {
2042 regb = n.voice - 9;
2043 io = s->sbbase+2;
2044 } else {
2045 regb = n.voice;
2046 io = s->sbbase;
2047 }
2048 outb(0xa0 + regb, io);
2049 outb(n.fnum & 0xff, io+1);
2050 outb(0xb0 + regb, io);
2051 outb(((n.fnum >> 8) & 3) | ((n.octave & 7) << 2) | ((n.key_on & 1) << 5), io+1);
2052 return 0;
2053
2054 case FM_IOCTL_SET_VOICE:
2055 if (copy_from_user(&v, (void *)arg, sizeof(v)))
2056 return -EFAULT;
2057 if (v.voice >= 18)
2058 return -EINVAL;
2059 regb = op_offset[v.voice];
2060 io = s->sbbase + ((v.op & 1) << 1);
2061 outb(0x20 + regb, io);
2062 outb(((v.am & 1) << 7) | ((v.vibrato & 1) << 6) | ((v.do_sustain & 1) << 5) |
2063 ((v.kbd_scale & 1) << 4) | (v.harmonic & 0xf), io+1);
2064 outb(0x40 + regb, io);
2065 outb(((v.scale_level & 0x3) << 6) | (v.volume & 0x3f), io+1);
2066 outb(0x60 + regb, io);
2067 outb(((v.attack & 0xf) << 4) | (v.decay & 0xf), io+1);
2068 outb(0x80 + regb, io);
2069 outb(((v.sustain & 0xf) << 4) | (v.release & 0xf), io+1);
2070 outb(0xe0 + regb, io);
2071 outb(v.waveform & 0x7, io+1);
2072 if (n.voice >= 9) {
2073 regb = n.voice - 9;
2074 io = s->sbbase+2;
2075 } else {
2076 regb = n.voice;
2077 io = s->sbbase;
2078 }
2079 outb(0xc0 + regb, io);
2080 outb(((v.right & 1) << 5) | ((v.left & 1) << 4) | ((v.feedback & 7) << 1) |
2081 (v.connection & 1), io+1);
2082 return 0;
2083
2084 case FM_IOCTL_SET_PARAMS:
2085 if (copy_from_user(&p, (void *)arg, sizeof(p)))
2086 return -EFAULT;
2087 outb(0x08, s->sbbase);
2088 outb((p.kbd_split & 1) << 6, s->sbbase+1);
2089 outb(0xbd, s->sbbase);
2090 outb(((p.am_depth & 1) << 7) | ((p.vib_depth & 1) << 6) | ((p.rhythm & 1) << 5) | ((p.bass & 1) << 4) |
2091 ((p.snare & 1) << 3) | ((p.tomtom & 1) << 2) | ((p.cymbal & 1) << 1) | (p.hihat & 1), s->sbbase+1);
2092 return 0;
2093
2094 case FM_IOCTL_SET_OPL:
2095 outb(4, s->sbbase+2);
2096 outb(arg, s->sbbase+3);
2097 return 0;
2098
2099 case FM_IOCTL_SET_MODE:
2100 outb(5, s->sbbase+2);
2101 outb(arg & 1, s->sbbase+3);
2102 return 0;
2103
2104 default:
2105 return -EINVAL;
2106 }
2107 }
2108
2109 static int solo1_dmfm_open(struct inode *inode, struct file *file)
2110 {
2111 unsigned int minor = minor(inode->i_rdev);
2112 DECLARE_WAITQUEUE(wait, current);
2113 struct solo1_state *s = NULL;
2114 struct pci_dev *pci_dev;
2115
2116 pci_for_each_dev(pci_dev) {
2117 struct pci_driver *drvr;
2118
2119 drvr = pci_dev_driver(pci_dev);
2120 if (drvr != &solo1_driver)
2121 continue;
2122 s = (struct solo1_state*)pci_get_drvdata(pci_dev);
2123 if (!s)
2124 continue;
2125 if (s->dev_dmfm == minor)
2126 break;
2127 }
2128 if (!s)
2129 return -ENODEV;
2130 VALIDATE_STATE(s);
2131 file->private_data = s;
2132 /* wait for device to become free */
2133 down(&s->open_sem);
2134 while (s->open_mode & FMODE_DMFM) {
2135 if (file->f_flags & O_NONBLOCK) {
2136 up(&s->open_sem);
2137 return -EBUSY;
2138 }
2139 add_wait_queue(&s->open_wait, &wait);
2140 __set_current_state(TASK_INTERRUPTIBLE);
2141 up(&s->open_sem);
2142 schedule();
2143 remove_wait_queue(&s->open_wait, &wait);
2144 set_current_state(TASK_RUNNING);
2145 if (signal_pending(current))
2146 return -ERESTARTSYS;
2147 down(&s->open_sem);
2148 }
2149 if (!request_region(s->sbbase, FMSYNTH_EXTENT, "ESS Solo1")) {
2150 up(&s->open_sem);
2151 printk(KERN_ERR "solo1: FM synth io ports in use, opl3 loaded?\n");
2152 return -EBUSY;
2153 }
2154 /* init the stuff */
2155 outb(1, s->sbbase);
2156 outb(0x20, s->sbbase+1); /* enable waveforms */
2157 outb(4, s->sbbase+2);
2158 outb(0, s->sbbase+3); /* no 4op enabled */
2159 outb(5, s->sbbase+2);
2160 outb(1, s->sbbase+3); /* enable OPL3 */
2161 s->open_mode |= FMODE_DMFM;
2162 up(&s->open_sem);
2163 return 0;
2164 }
2165
2166 static int solo1_dmfm_release(struct inode *inode, struct file *file)
2167 {
2168 struct solo1_state *s = (struct solo1_state *)file->private_data;
2169 unsigned int regb;
2170
2171 VALIDATE_STATE(s);
2172 lock_kernel();
2173 down(&s->open_sem);
2174 s->open_mode &= ~FMODE_DMFM;
2175 for (regb = 0xb0; regb < 0xb9; regb++) {
2176 outb(regb, s->sbbase);
2177 outb(0, s->sbbase+1);
2178 outb(regb, s->sbbase+2);
2179 outb(0, s->sbbase+3);
2180 }
2181 release_region(s->sbbase, FMSYNTH_EXTENT);
2182 wake_up(&s->open_wait);
2183 up(&s->open_sem);
2184 unlock_kernel();
2185 return 0;
2186 }
2187
2188 static /*const*/ struct file_operations solo1_dmfm_fops = {
2189 owner: THIS_MODULE,
2190 llseek: no_llseek,
2191 ioctl: solo1_dmfm_ioctl,
2192 open: solo1_dmfm_open,
2193 release: solo1_dmfm_release,
2194 };
2195
2196 /* --------------------------------------------------------------------- */
2197
2198 static struct initvol {
2199 int mixch;
2200 int vol;
2201 } initvol[] __initdata = {
2202 { SOUND_MIXER_WRITE_VOLUME, 0x4040 },
2203 { SOUND_MIXER_WRITE_PCM, 0x4040 },
2204 { SOUND_MIXER_WRITE_SYNTH, 0x4040 },
2205 { SOUND_MIXER_WRITE_CD, 0x4040 },
2206 { SOUND_MIXER_WRITE_LINE, 0x4040 },
2207 { SOUND_MIXER_WRITE_LINE1, 0x4040 },
2208 { SOUND_MIXER_WRITE_LINE2, 0x4040 },
2209 { SOUND_MIXER_WRITE_RECLEV, 0x4040 },
2210 { SOUND_MIXER_WRITE_SPEAKER, 0x4040 },
2211 { SOUND_MIXER_WRITE_MIC, 0x4040 }
2212 };
2213
2214 static int setup_solo1(struct solo1_state *s)
2215 {
2216 struct pci_dev *pcidev = s->dev;
2217 mm_segment_t fs;
2218 int i, val;
2219
2220 /* initialize DDMA base address */
2221 printk(KERN_DEBUG "solo1: ddma base address: 0x%lx\n", s->ddmabase);
2222 pci_write_config_word(pcidev, 0x60, (s->ddmabase & (~0xf)) | 1);
2223 /* set DMA policy to DDMA, IRQ emulation off (CLKRUN disabled for now) */
2224 pci_write_config_dword(pcidev, 0x50, 0);
2225 /* disable legacy audio address decode */
2226 pci_write_config_word(pcidev, 0x40, 0x907f);
2227
2228 /* initialize the chips */
2229 if (!reset_ctrl(s)) {
2230 printk(KERN_ERR "esssolo1: cannot reset controller\n");
2231 return -1;
2232 }
2233 outb(0xb0, s->iobase+7); /* enable A1, A2, MPU irq's */
2234
2235 /* initialize mixer regs */
2236 write_mixer(s, 0x7f, 0); /* disable music digital recording */
2237 write_mixer(s, 0x7d, 0x0c); /* enable mic preamp, MONO_OUT is 2nd DAC right channel */
2238 write_mixer(s, 0x64, 0x45); /* volume control */
2239 write_mixer(s, 0x48, 0x10); /* enable music DAC/ES6xx interface */
2240 write_mixer(s, 0x50, 0); /* disable spatializer */
2241 write_mixer(s, 0x52, 0);
2242 write_mixer(s, 0x14, 0); /* DAC1 minimum volume */
2243 write_mixer(s, 0x71, 0x20); /* enable new 0xA1 reg format */
2244 outb(0, s->ddmabase+0xd); /* DMA master clear */
2245 outb(1, s->ddmabase+0xf); /* mask channel */
2246 /*outb(0, s->ddmabase+0x8);*/ /* enable controller (enable is low active!!) */
2247
2248 pci_set_master(pcidev); /* enable bus mastering */
2249
2250 fs = get_fs();
2251 set_fs(KERNEL_DS);
2252 val = SOUND_MASK_LINE;
2253 mixer_ioctl(s, SOUND_MIXER_WRITE_RECSRC, (unsigned long)&val);
2254 for (i = 0; i < sizeof(initvol)/sizeof(initvol[0]); i++) {
2255 val = initvol[i].vol;
2256 mixer_ioctl(s, initvol[i].mixch, (unsigned long)&val);
2257 }
2258 val = 1; /* enable mic preamp */
2259 mixer_ioctl(s, SOUND_MIXER_PRIVATE1, (unsigned long)&val);
2260 set_fs(fs);
2261 return 0;
2262 }
2263
2264 static int
2265 solo1_suspend(struct pci_dev *pci_dev, u32 state) {
2266 struct solo1_state *s = (struct solo1_state*)pci_get_drvdata(pci_dev);
2267 if (!s)
2268 return 1;
2269 outb(0, s->iobase+6);
2270 /* DMA master clear */
2271 outb(0, s->ddmabase+0xd);
2272 /* reset sequencer and FIFO */
2273 outb(3, s->sbbase+6);
2274 /* turn off DDMA controller address space */
2275 pci_write_config_word(s->dev, 0x60, 0);
2276 return 0;
2277 }
2278
2279 static int
2280 solo1_resume(struct pci_dev *pci_dev) {
2281 struct solo1_state *s = (struct solo1_state*)pci_get_drvdata(pci_dev);
2282 if (!s)
2283 return 1;
2284 setup_solo1(s);
2285 return 0;
2286 }
2287
2288 static int __devinit solo1_probe(struct pci_dev *pcidev, const struct pci_device_id *pciid)
2289 {
2290 struct solo1_state *s;
2291 int ret;
2292
2293 if ((ret=pci_enable_device(pcidev)))
2294 return ret;
2295 if (!(pci_resource_flags(pcidev, 0) & IORESOURCE_IO) ||
2296 !(pci_resource_flags(pcidev, 1) & IORESOURCE_IO) ||
2297 !(pci_resource_flags(pcidev, 2) & IORESOURCE_IO) ||
2298 !(pci_resource_flags(pcidev, 3) & IORESOURCE_IO))
2299 return -ENODEV;
2300 if (pcidev->irq == 0)
2301 return -ENODEV;
2302
2303 /* Recording requires 24-bit DMA, so attempt to set dma mask
2304 * to 24 bits first, then 32 bits (playback only) if that fails.
2305 */
2306 if (pci_set_dma_mask(pcidev, 0x00ffffff) &&
2307 pci_set_dma_mask(pcidev, 0xffffffff)) {
2308 printk(KERN_WARNING "solo1: architecture does not support 24bit or 32bit PCI busmaster DMA\n");
2309 return -ENODEV;
2310 }
2311
2312 if (!(s = kmalloc(sizeof(struct solo1_state), GFP_KERNEL))) {
2313 printk(KERN_WARNING "solo1: out of memory\n");
2314 return -ENOMEM;
2315 }
2316 memset(s, 0, sizeof(struct solo1_state));
2317 init_waitqueue_head(&s->dma_adc.wait);
2318 init_waitqueue_head(&s->dma_dac.wait);
2319 init_waitqueue_head(&s->open_wait);
2320 init_waitqueue_head(&s->midi.iwait);
2321 init_waitqueue_head(&s->midi.owait);
2322 init_MUTEX(&s->open_sem);
2323 spin_lock_init(&s->lock);
2324 s->magic = SOLO1_MAGIC;
2325 s->dev = pcidev;
2326 s->iobase = pci_resource_start(pcidev, 0);
2327 s->sbbase = pci_resource_start(pcidev, 1);
2328 s->vcbase = pci_resource_start(pcidev, 2);
2329 s->ddmabase = s->vcbase + DDMABASE_OFFSET;
2330 s->mpubase = pci_resource_start(pcidev, 3);
2331 s->gameport.io = pci_resource_start(pcidev, 4);
2332 s->irq = pcidev->irq;
2333 ret = -EBUSY;
2334 if (!request_region(s->iobase, IOBASE_EXTENT, "ESS Solo1")) {
2335 printk(KERN_ERR "solo1: io ports in use\n");
2336 goto err_region1;
2337 }
2338 if (!request_region(s->sbbase+FMSYNTH_EXTENT, SBBASE_EXTENT-FMSYNTH_EXTENT, "ESS Solo1")) {
2339 printk(KERN_ERR "solo1: io ports in use\n");
2340 goto err_region2;
2341 }
2342 if (!request_region(s->ddmabase, DDMABASE_EXTENT, "ESS Solo1")) {
2343 printk(KERN_ERR "solo1: io ports in use\n");
2344 goto err_region3;
2345 }
2346 if (!request_region(s->mpubase, MPUBASE_EXTENT, "ESS Solo1")) {
2347 printk(KERN_ERR "solo1: io ports in use\n");
2348 goto err_region4;
2349 }
2350 if (s->gameport.io && !request_region(s->gameport.io, GAMEPORT_EXTENT, "ESS Solo1")) {
2351 printk(KERN_ERR "solo1: gameport io ports in use\n");
2352 s->gameport.io = 0;
2353 }
2354 if ((ret=request_irq(s->irq,solo1_interrupt,SA_SHIRQ,"ESS Solo1",s))) {
2355 printk(KERN_ERR "solo1: irq %u in use\n", s->irq);
2356 goto err_irq;
2357 }
2358 printk(KERN_INFO "solo1: joystick port at %#x\n", s->gameport.io+1);
2359 /* register devices */
2360 if ((s->dev_audio = register_sound_dsp(&solo1_audio_fops, -1)) < 0) {
2361 ret = s->dev_audio;
2362 goto err_dev1;
2363 }
2364 if ((s->dev_mixer = register_sound_mixer(&solo1_mixer_fops, -1)) < 0) {
2365 ret = s->dev_mixer;
2366 goto err_dev2;
2367 }
2368 if ((s->dev_midi = register_sound_midi(&solo1_midi_fops, -1)) < 0) {
2369 ret = s->dev_midi;
2370 goto err_dev3;
2371 }
2372 if ((s->dev_dmfm = register_sound_special(&solo1_dmfm_fops, 15 /* ?? */)) < 0) {
2373 ret = s->dev_dmfm;
2374 goto err_dev4;
2375 }
2376 if (setup_solo1(s)) {
2377 ret = -EIO;
2378 goto err;
2379 }
2380 /* register gameport */
2381 gameport_register_port(&s->gameport);
2382 /* store it in the driver field */
2383 pci_set_drvdata(pcidev, s);
2384 return 0;
2385
2386 err:
2387 unregister_sound_special(s->dev_dmfm);
2388 err_dev4:
2389 unregister_sound_midi(s->dev_midi);
2390 err_dev3:
2391 unregister_sound_mixer(s->dev_mixer);
2392 err_dev2:
2393 unregister_sound_dsp(s->dev_audio);
2394 err_dev1:
2395 printk(KERN_ERR "solo1: initialisation error\n");
2396 free_irq(s->irq, s);
2397 err_irq:
2398 if (s->gameport.io)
2399 release_region(s->gameport.io, GAMEPORT_EXTENT);
2400 release_region(s->mpubase, MPUBASE_EXTENT);
2401 err_region4:
2402 release_region(s->ddmabase, DDMABASE_EXTENT);
2403 err_region3:
2404 release_region(s->sbbase+FMSYNTH_EXTENT, SBBASE_EXTENT-FMSYNTH_EXTENT);
2405 err_region2:
2406 release_region(s->iobase, IOBASE_EXTENT);
2407 err_region1:
2408 kfree(s);
2409 return ret;
2410 }
2411
2412 static void __devinit solo1_remove(struct pci_dev *dev)
2413 {
2414 struct solo1_state *s = pci_get_drvdata(dev);
2415
2416 if (!s)
2417 return;
2418 /* stop DMA controller */
2419 outb(0, s->iobase+6);
2420 outb(0, s->ddmabase+0xd); /* DMA master clear */
2421 outb(3, s->sbbase+6); /* reset sequencer and FIFO */
2422 synchronize_irq(s->irq);
2423 pci_write_config_word(s->dev, 0x60, 0); /* turn off DDMA controller address space */
2424 free_irq(s->irq, s);
2425 if (s->gameport.io) {
2426 gameport_unregister_port(&s->gameport);
2427 release_region(s->gameport.io, GAMEPORT_EXTENT);
2428 }
2429 release_region(s->iobase, IOBASE_EXTENT);
2430 release_region(s->sbbase+FMSYNTH_EXTENT, SBBASE_EXTENT-FMSYNTH_EXTENT);
2431 release_region(s->ddmabase, DDMABASE_EXTENT);
2432 release_region(s->mpubase, MPUBASE_EXTENT);
2433 unregister_sound_dsp(s->dev_audio);
2434 unregister_sound_mixer(s->dev_mixer);
2435 unregister_sound_midi(s->dev_midi);
2436 unregister_sound_special(s->dev_dmfm);
2437 kfree(s);
2438 pci_set_drvdata(dev, NULL);
2439 }
2440
2441 static struct pci_device_id id_table[] __devinitdata = {
2442 { PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_SOLO1, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
2443 { 0, }
2444 };
2445
2446 MODULE_DEVICE_TABLE(pci, id_table);
2447
2448 static struct pci_driver solo1_driver = {
2449 name: "ESS Solo1",
2450 id_table: id_table,
2451 probe: solo1_probe,
2452 remove: solo1_remove,
2453 suspend: solo1_suspend,
2454 resume: solo1_resume
2455 };
2456
2457
2458 static int __init init_solo1(void)
2459 {
2460 if (!pci_present()) /* No PCI bus in this machine! */
2461 return -ENODEV;
2462 printk(KERN_INFO "solo1: version v0.19 time " __TIME__ " " __DATE__ "\n");
2463 if (!pci_register_driver(&solo1_driver)) {
2464 pci_unregister_driver(&solo1_driver);
2465 return -ENODEV;
2466 }
2467 return 0;
2468 }
2469
2470 /* --------------------------------------------------------------------- */
2471
2472 MODULE_AUTHOR("Thomas M. Sailer, sailer@ife.ee.ethz.ch, hb9jnx@hb9w.che.eu");
2473 MODULE_DESCRIPTION("ESS Solo1 Driver");
2474 MODULE_LICENSE("GPL");
2475
2476
2477 static void __exit cleanup_solo1(void)
2478 {
2479 printk(KERN_INFO "solo1: unloading\n");
2480 pci_unregister_driver(&solo1_driver);
2481 }
2482
2483 /* --------------------------------------------------------------------- */
2484
2485 module_init(init_solo1);
2486 module_exit(cleanup_solo1);
2487
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