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Pull one more egcs 1.1.2 workaround.
[linux-2.6/linux-mips.git] / sound / oss / ad1848.c
blobb0b848f220b5c0b356683081b27ed453fbc2a807
1 /*
2 * sound/ad1848.c
3 *
4 * The low level driver for the AD1848/CS4248 codec chip which
5 * is used for example in the MS Sound System.
6 *
7 * The CS4231 which is used in the GUS MAX and some other cards is
8 * upwards compatible with AD1848 and this driver is able to drive it.
9 *
10 * CS4231A and AD1845 are upward compatible with CS4231. However
11 * the new features of these chips are different.
12 *
13 * CS4232 is a PnP audio chip which contains a CS4231A (and SB, MPU).
14 * CS4232A is an improved version of CS4232.
15 *
16 *
17 *
18 * Copyright (C) by Hannu Savolainen 1993-1997
19 *
20 * OSS/Free for Linux is distributed under the GNU GENERAL PUBLIC LICENSE (GPL)
21 * Version 2 (June 1991). See the "COPYING" file distributed with this software
22 * for more info.
23 *
24 *
25 * Thomas Sailer : ioctl code reworked (vmalloc/vfree removed)
26 * general sleep/wakeup clean up.
27 * Alan Cox : reformatted. Fixed SMP bugs. Moved to kernel alloc/free
28 * of irqs. Use dev_id.
29 * Christoph Hellwig : adapted to module_init/module_exit
30 * Aki Laukkanen : added power management support
31 * Arnaldo C. de Melo : added missing restore_flags in ad1848_resume
32 * Miguel Freitas : added ISA PnP support
33 * Alan Cox : Added CS4236->4239 identification
34 * Daniel T. Cobra : Alernate config/mixer for later chips
35 * Alan Cox : Merged chip idents and config code
36 *
37 * TODO
38 * APM save restore assist code on IBM thinkpad
39 *
40 * Status:
41 * Tested. Believed fully functional.
42 */
43
44 #include <linux/config.h>
45 #include <linux/init.h>
46 #include <linux/module.h>
47 #include <linux/stddef.h>
48 #include <linux/pm.h>
49 #include <linux/isapnp.h>
50 #include <linux/pnp.h>
51 #include <linux/spinlock.h>
52
53 #define DEB(x)
54 #define DEB1(x)
55 #include "sound_config.h"
56
57 #include "ad1848.h"
58 #include "ad1848_mixer.h"
59
60 typedef struct
61 {
62 spinlock_t lock;
63 int base;
64 int irq;
65 int dma1, dma2;
66 int dual_dma; /* 1, when two DMA channels allocated */
67 int subtype;
68 unsigned char MCE_bit;
69 unsigned char saved_regs[64]; /* Includes extended register space */
70 int debug_flag;
71
72 int audio_flags;
73 int record_dev, playback_dev;
74
75 int xfer_count;
76 int audio_mode;
77 int open_mode;
78 int intr_active;
79 char *chip_name, *name;
80 int model;
81 #define MD_1848 1
82 #define MD_4231 2
83 #define MD_4231A 3
84 #define MD_1845 4
85 #define MD_4232 5
86 #define MD_C930 6
87 #define MD_IWAVE 7
88 #define MD_4235 8 /* Crystal Audio CS4235 */
89 #define MD_1845_SSCAPE 9 /* Ensoniq Soundscape PNP*/
90 #define MD_4236 10 /* 4236 and higher */
91 #define MD_42xB 11 /* CS 42xB */
92 #define MD_4239 12 /* CS4239 */
93
94 /* Mixer parameters */
95 int recmask;
96 int supported_devices, orig_devices;
97 int supported_rec_devices, orig_rec_devices;
98 int *levels;
99 short mixer_reroute[32];
100 int dev_no;
101 volatile unsigned long timer_ticks;
102 int timer_running;
103 int irq_ok;
104 mixer_ents *mix_devices;
105 int mixer_output_port;
106
107 /* Power management */
108 struct pm_dev *pmdev;
109 } ad1848_info;
110
111 typedef struct ad1848_port_info
112 {
113 int open_mode;
114 int speed;
115 unsigned char speed_bits;
116 int channels;
117 int audio_format;
118 unsigned char format_bits;
119 }
120 ad1848_port_info;
121
122 static struct address_info cfg;
123 static int nr_ad1848_devs;
124
125 int deskpro_xl;
126 int deskpro_m;
127 int soundpro;
128
129 static volatile signed char irq2dev[17] = {
130 -1, -1, -1, -1, -1, -1, -1, -1,
131 -1, -1, -1, -1, -1, -1, -1, -1, -1
132 };
133
134 #ifndef EXCLUDE_TIMERS
135 static int timer_installed = -1;
136 #endif
137
138 static int loaded;
139
140 static int ad_format_mask[13 /*devc->model */ ] =
141 {
142 0,
143 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW,
144 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
145 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
146 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW, /* AD1845 */
147 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
148 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
149 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
150 AFMT_U8 | AFMT_S16_LE /* CS4235 */,
151 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW /* Ensoniq Soundscape*/,
152 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
153 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
154 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM
155 };
156
157 static ad1848_info adev_info[MAX_AUDIO_DEV];
158
159 #define io_Index_Addr(d) ((d)->base)
160 #define io_Indexed_Data(d) ((d)->base+1)
161 #define io_Status(d) ((d)->base+2)
162 #define io_Polled_IO(d) ((d)->base+3)
163
164 static struct {
165 unsigned char flags;
166 #define CAP_F_TIMER 0x01
167 } capabilities [10 /*devc->model */ ] = {
168 {0}
169 ,{0} /* MD_1848 */
170 ,{CAP_F_TIMER} /* MD_4231 */
171 ,{CAP_F_TIMER} /* MD_4231A */
172 ,{CAP_F_TIMER} /* MD_1845 */
173 ,{CAP_F_TIMER} /* MD_4232 */
174 ,{0} /* MD_C930 */
175 ,{CAP_F_TIMER} /* MD_IWAVE */
176 ,{0} /* MD_4235 */
177 ,{CAP_F_TIMER} /* MD_1845_SSCAPE */
178 };
179
180 #ifdef CONFIG_PNP
181 static int isapnp = 1;
182 static int isapnpjump = 0;
183 static int reverse = 0;
184
185 static int audio_activated = 0;
186 #else
187 static int isapnp = 0;
188 #endif
189
190
191
192 static int ad1848_open(int dev, int mode);
193 static void ad1848_close(int dev);
194 static void ad1848_output_block(int dev, unsigned long buf, int count, int intrflag);
195 static void ad1848_start_input(int dev, unsigned long buf, int count, int intrflag);
196 static int ad1848_prepare_for_output(int dev, int bsize, int bcount);
197 static int ad1848_prepare_for_input(int dev, int bsize, int bcount);
198 static void ad1848_halt(int dev);
199 static void ad1848_halt_input(int dev);
200 static void ad1848_halt_output(int dev);
201 static void ad1848_trigger(int dev, int bits);
202 static int ad1848_pm_callback(struct pm_dev *dev, pm_request_t rqst, void *data);
203
204 #ifndef EXCLUDE_TIMERS
205 static int ad1848_tmr_install(int dev);
206 static void ad1848_tmr_reprogram(int dev);
207 #endif
208
209 static int ad_read(ad1848_info * devc, int reg)
210 {
211 unsigned long flags;
212 int x;
213 int timeout = 900000;
214
215 while (timeout > 0 && inb(devc->base) == 0x80) /*Are we initializing */
216 timeout--;
217
218 spin_lock_irqsave(&devc->lock,flags);
219
220 if(reg < 32)
221 {
222 outb(((unsigned char) (reg & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
223 x = inb(io_Indexed_Data(devc));
224 }
225 else
226 {
227 int xreg, xra;
228
229 xreg = (reg & 0xff) - 32;
230 xra = (((xreg & 0x0f) << 4) & 0xf0) | 0x08 | ((xreg & 0x10) >> 2);
231 outb(((unsigned char) (23 & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
232 outb(((unsigned char) (xra & 0xff)), io_Indexed_Data(devc));
233 x = inb(io_Indexed_Data(devc));
234 }
235 spin_unlock_irqrestore(&devc->lock,flags);
236
237 return x;
238 }
239
240 static void ad_write(ad1848_info * devc, int reg, int data)
241 {
242 unsigned long flags;
243 int timeout = 900000;
244
245 while (timeout > 0 && inb(devc->base) == 0x80) /* Are we initializing */
246 timeout--;
247
248 spin_lock_irqsave(&devc->lock,flags);
249
250 if(reg < 32)
251 {
252 outb(((unsigned char) (reg & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
253 outb(((unsigned char) (data & 0xff)), io_Indexed_Data(devc));
254 }
255 else
256 {
257 int xreg, xra;
258
259 xreg = (reg & 0xff) - 32;
260 xra = (((xreg & 0x0f) << 4) & 0xf0) | 0x08 | ((xreg & 0x10) >> 2);
261 outb(((unsigned char) (23 & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
262 outb(((unsigned char) (xra & 0xff)), io_Indexed_Data(devc));
263 outb((unsigned char) (data & 0xff), io_Indexed_Data(devc));
264 }
265 spin_unlock_irqrestore(&devc->lock,flags);
266 }
267
268 static void wait_for_calibration(ad1848_info * devc)
269 {
270 int timeout = 0;
271
272 /*
273 * Wait until the auto calibration process has finished.
274 *
275 * 1) Wait until the chip becomes ready (reads don't return 0x80).
276 * 2) Wait until the ACI bit of I11 gets on and then off.
277 */
278
279 timeout = 100000;
280 while (timeout > 0 && inb(devc->base) == 0x80)
281 timeout--;
282 if (inb(devc->base) & 0x80)
283 printk(KERN_WARNING "ad1848: Auto calibration timed out(1).\n");
284
285 timeout = 100;
286 while (timeout > 0 && !(ad_read(devc, 11) & 0x20))
287 timeout--;
288 if (!(ad_read(devc, 11) & 0x20))
289 return;
290
291 timeout = 80000;
292 while (timeout > 0 && (ad_read(devc, 11) & 0x20))
293 timeout--;
294 if (ad_read(devc, 11) & 0x20)
295 if ( (devc->model != MD_1845) || (devc->model != MD_1845_SSCAPE))
296 printk(KERN_WARNING "ad1848: Auto calibration timed out(3).\n");
297 }
298
299 static void ad_mute(ad1848_info * devc)
300 {
301 int i;
302 unsigned char prev;
303
304 /*
305 * Save old register settings and mute output channels
306 */
307
308 for (i = 6; i < 8; i++)
309 {
310 prev = devc->saved_regs[i] = ad_read(devc, i);
311 }
312
313 }
314
315 static void ad_unmute(ad1848_info * devc)
316 {
317 }
318
319 static void ad_enter_MCE(ad1848_info * devc)
320 {
321 unsigned long flags;
322 int timeout = 1000;
323 unsigned short prev;
324
325 while (timeout > 0 && inb(devc->base) == 0x80) /*Are we initializing */
326 timeout--;
327
328 spin_lock_irqsave(&devc->lock,flags);
329
330 devc->MCE_bit = 0x40;
331 prev = inb(io_Index_Addr(devc));
332 if (prev & 0x40)
333 {
334 spin_unlock_irqrestore(&devc->lock,flags);
335 return;
336 }
337 outb((devc->MCE_bit), io_Index_Addr(devc));
338 spin_unlock_irqrestore(&devc->lock,flags);
339 }
340
341 static void ad_leave_MCE(ad1848_info * devc)
342 {
343 unsigned long flags;
344 unsigned char prev, acal;
345 int timeout = 1000;
346
347 while (timeout > 0 && inb(devc->base) == 0x80) /*Are we initializing */
348 timeout--;
349
350 spin_lock_irqsave(&devc->lock,flags);
351
352 acal = ad_read(devc, 9);
353
354 devc->MCE_bit = 0x00;
355 prev = inb(io_Index_Addr(devc));
356 outb((0x00), io_Index_Addr(devc)); /* Clear the MCE bit */
357
358 if ((prev & 0x40) == 0) /* Not in MCE mode */
359 {
360 spin_unlock_irqrestore(&devc->lock,flags);
361 return;
362 }
363 outb((0x00), io_Index_Addr(devc)); /* Clear the MCE bit */
364 if (acal & 0x08) /* Auto calibration is enabled */
365 wait_for_calibration(devc);
366 spin_unlock_irqrestore(&devc->lock,flags);
367 }
368
369 static int ad1848_set_recmask(ad1848_info * devc, int mask)
370 {
371 unsigned char recdev;
372 int i, n;
373
374 mask &= devc->supported_rec_devices;
375
376 /* Rename the mixer bits if necessary */
377 for (i = 0; i < 32; i++)
378 {
379 if (devc->mixer_reroute[i] != i)
380 {
381 if (mask & (1 << i))
382 {
383 mask &= ~(1 << i);
384 mask |= (1 << devc->mixer_reroute[i]);
385 }
386 }
387 }
388
389 n = 0;
390 for (i = 0; i < 32; i++) /* Count selected device bits */
391 if (mask & (1 << i))
392 n++;
393
394 if (!soundpro) {
395 if (n == 0)
396 mask = SOUND_MASK_MIC;
397 else if (n != 1) { /* Too many devices selected */
398 mask &= ~devc->recmask; /* Filter out active settings */
399
400 n = 0;
401 for (i = 0; i < 32; i++) /* Count selected device bits */
402 if (mask & (1 << i))
403 n++;
404
405 if (n != 1)
406 mask = SOUND_MASK_MIC;
407 }
408 switch (mask) {
409 case SOUND_MASK_MIC:
410 recdev = 2;
411 break;
412
413 case SOUND_MASK_LINE:
414 case SOUND_MASK_LINE3:
415 recdev = 0;
416 break;
417
418 case SOUND_MASK_CD:
419 case SOUND_MASK_LINE1:
420 recdev = 1;
421 break;
422
423 case SOUND_MASK_IMIX:
424 recdev = 3;
425 break;
426
427 default:
428 mask = SOUND_MASK_MIC;
429 recdev = 2;
430 }
431
432 recdev <<= 6;
433 ad_write(devc, 0, (ad_read(devc, 0) & 0x3f) | recdev);
434 ad_write(devc, 1, (ad_read(devc, 1) & 0x3f) | recdev);
435 } else { /* soundpro */
436 unsigned char val;
437 int set_rec_bit;
438 int j;
439
440 for (i = 0; i < 32; i++) { /* For each bit */
441 if ((devc->supported_rec_devices & (1 << i)) == 0)
442 continue; /* Device not supported */
443
444 for (j = LEFT_CHN; j <= RIGHT_CHN; j++) {
445 if (devc->mix_devices[i][j].nbits == 0) /* Inexistent channel */
446 continue;
447
448 /*
449 * This is tricky:
450 * set_rec_bit becomes 1 if the corresponding bit in mask is set
451 * then it gets flipped if the polarity is inverse
452 */
453 set_rec_bit = ((mask & (1 << i)) != 0) ^ devc->mix_devices[i][j].recpol;
454
455 val = ad_read(devc, devc->mix_devices[i][j].recreg);
456 val &= ~(1 << devc->mix_devices[i][j].recpos);
457 val |= (set_rec_bit << devc->mix_devices[i][j].recpos);
458 ad_write(devc, devc->mix_devices[i][j].recreg, val);
459 }
460 }
461 }
462
463 /* Rename the mixer bits back if necessary */
464 for (i = 0; i < 32; i++)
465 {
466 if (devc->mixer_reroute[i] != i)
467 {
468 if (mask & (1 << devc->mixer_reroute[i]))
469 {
470 mask &= ~(1 << devc->mixer_reroute[i]);
471 mask |= (1 << i);
472 }
473 }
474 }
475 devc->recmask = mask;
476 return mask;
477 }
478
479 static void change_bits(ad1848_info * devc, unsigned char *regval,
480 unsigned char *muteval, int dev, int chn, int newval)
481 {
482 unsigned char mask;
483 int shift;
484 int mute;
485 int mutemask;
486 int set_mute_bit;
487
488 set_mute_bit = (newval == 0) ^ devc->mix_devices[dev][chn].mutepol;
489
490 if (devc->mix_devices[dev][chn].polarity == 1) /* Reverse */
491 newval = 100 - newval;
492
493 mask = (1 << devc->mix_devices[dev][chn].nbits) - 1;
494 shift = devc->mix_devices[dev][chn].bitpos;
495
496 if (devc->mix_devices[dev][chn].mutepos == 8)
497 { /* if there is no mute bit */
498 mute = 0; /* No mute bit; do nothing special */
499 mutemask = ~0; /* No mute bit; do nothing special */
500 }
501 else
502 {
503 mute = (set_mute_bit << devc->mix_devices[dev][chn].mutepos);
504 mutemask = ~(1 << devc->mix_devices[dev][chn].mutepos);
505 }
506
507 newval = (int) ((newval * mask) + 50) / 100; /* Scale it */
508 *regval &= ~(mask << shift); /* Clear bits */
509 *regval |= (newval & mask) << shift; /* Set new value */
510
511 *muteval &= mutemask;
512 *muteval |= mute;
513 }
514
515 static int ad1848_mixer_get(ad1848_info * devc, int dev)
516 {
517 if (!((1 << dev) & devc->supported_devices))
518 return -EINVAL;
519
520 dev = devc->mixer_reroute[dev];
521
522 return devc->levels[dev];
523 }
524
525 static void ad1848_mixer_set_channel(ad1848_info *devc, int dev, int value, int channel)
526 {
527 int regoffs, muteregoffs;
528 unsigned char val, muteval;
529
530 regoffs = devc->mix_devices[dev][channel].regno;
531 muteregoffs = devc->mix_devices[dev][channel].mutereg;
532 val = ad_read(devc, regoffs);
533
534 if (muteregoffs != regoffs) {
535 muteval = ad_read(devc, muteregoffs);
536 change_bits(devc, &val, &muteval, dev, channel, value);
537 }
538 else
539 change_bits(devc, &val, &val, dev, channel, value);
540
541 ad_write(devc, regoffs, val);
542 devc->saved_regs[regoffs] = val;
543 if (muteregoffs != regoffs) {
544 ad_write(devc, muteregoffs, muteval);
545 devc->saved_regs[muteregoffs] = muteval;
546 }
547 }
548
549 static int ad1848_mixer_set(ad1848_info * devc, int dev, int value)
550 {
551 int left = value & 0x000000ff;
552 int right = (value & 0x0000ff00) >> 8;
553 int retvol;
554
555 if (dev > 31)
556 return -EINVAL;
557
558 if (!(devc->supported_devices & (1 << dev)))
559 return -EINVAL;
560
561 dev = devc->mixer_reroute[dev];
562
563 if (devc->mix_devices[dev][LEFT_CHN].nbits == 0)
564 return -EINVAL;
565
566 if (left > 100)
567 left = 100;
568 if (right > 100)
569 right = 100;
570
571 if (devc->mix_devices[dev][RIGHT_CHN].nbits == 0) /* Mono control */
572 right = left;
573
574 retvol = left | (right << 8);
575
576 /* Scale volumes */
577 left = mix_cvt[left];
578 right = mix_cvt[right];
579
580 devc->levels[dev] = retvol;
581
582 /*
583 * Set the left channel
584 */
585 ad1848_mixer_set_channel(devc, dev, left, LEFT_CHN);
586
587 /*
588 * Set the right channel
589 */
590 if (devc->mix_devices[dev][RIGHT_CHN].nbits == 0)
591 goto out;
592 ad1848_mixer_set_channel(devc, dev, right, RIGHT_CHN);
593
594 out:
595 return retvol;
596 }
597
598 static void ad1848_mixer_reset(ad1848_info * devc)
599 {
600 int i;
601 char name[32];
602
603 devc->mix_devices = &(ad1848_mix_devices[0]);
604
605 sprintf(name, "%s_%d", devc->chip_name, nr_ad1848_devs);
606
607 for (i = 0; i < 32; i++)
608 devc->mixer_reroute[i] = i;
609
610 devc->supported_rec_devices = MODE1_REC_DEVICES;
611
612 switch (devc->model)
613 {
614 case MD_4231:
615 case MD_4231A:
616 case MD_1845:
617 case MD_1845_SSCAPE:
618 devc->supported_devices = MODE2_MIXER_DEVICES;
619 break;
620
621 case MD_C930:
622 devc->supported_devices = C930_MIXER_DEVICES;
623 devc->mix_devices = &(c930_mix_devices[0]);
624 break;
625
626 case MD_IWAVE:
627 devc->supported_devices = MODE3_MIXER_DEVICES;
628 devc->mix_devices = &(iwave_mix_devices[0]);
629 break;
630
631 case MD_42xB:
632 case MD_4239:
633 devc->mix_devices = &(cs42xb_mix_devices[0]);
634 devc->supported_devices = MODE3_MIXER_DEVICES;
635 break;
636 case MD_4232:
637 case MD_4236:
638 devc->supported_devices = MODE3_MIXER_DEVICES;
639 break;
640
641 case MD_1848:
642 if (soundpro) {
643 devc->supported_devices = SPRO_MIXER_DEVICES;
644 devc->supported_rec_devices = SPRO_REC_DEVICES;
645 devc->mix_devices = &(spro_mix_devices[0]);
646 break;
647 }
648
649 default:
650 devc->supported_devices = MODE1_MIXER_DEVICES;
651 }
652
653 devc->orig_devices = devc->supported_devices;
654 devc->orig_rec_devices = devc->supported_rec_devices;
655
656 devc->levels = load_mixer_volumes(name, default_mixer_levels, 1);
657
658 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++)
659 {
660 if (devc->supported_devices & (1 << i))
661 ad1848_mixer_set(devc, i, devc->levels[i]);
662 }
663
664 ad1848_set_recmask(devc, SOUND_MASK_MIC);
665
666 devc->mixer_output_port = devc->levels[31] | AUDIO_HEADPHONE | AUDIO_LINE_OUT;
667
668 if (!soundpro) {
669 if (devc->mixer_output_port & AUDIO_SPEAKER)
670 ad_write(devc, 26, ad_read(devc, 26) & ~0x40); /* Unmute mono out */
671 else
672 ad_write(devc, 26, ad_read(devc, 26) | 0x40); /* Mute mono out */
673 } else {
674 /*
675 * From the "wouldn't it be nice if the mixer API had (better)
676 * support for custom stuff" category
677 */
678 /* Enable surround mode and SB16 mixer */
679 ad_write(devc, 16, 0x60);
680 }
681 }
682
683 static int ad1848_mixer_ioctl(int dev, unsigned int cmd, caddr_t arg)
684 {
685 ad1848_info *devc = mixer_devs[dev]->devc;
686 int val;
687
688 if (cmd == SOUND_MIXER_PRIVATE1)
689 {
690 if (get_user(val, (int *)arg))
691 return -EFAULT;
692
693 if (val != 0xffff)
694 {
695 val &= (AUDIO_SPEAKER | AUDIO_HEADPHONE | AUDIO_LINE_OUT);
696 devc->mixer_output_port = val;
697 val |= AUDIO_HEADPHONE | AUDIO_LINE_OUT; /* Always on */
698 devc->mixer_output_port = val;
699 if (val & AUDIO_SPEAKER)
700 ad_write(devc, 26, ad_read(devc, 26) & ~0x40); /* Unmute mono out */
701 else
702 ad_write(devc, 26, ad_read(devc, 26) | 0x40); /* Mute mono out */
703 }
704 val = devc->mixer_output_port;
705 return put_user(val, (int *)arg);
706 }
707 if (cmd == SOUND_MIXER_PRIVATE2)
708 {
709 if (get_user(val, (int *)arg))
710 return -EFAULT;
711 return(ad1848_control(AD1848_MIXER_REROUTE, val));
712 }
713 if (((cmd >> 8) & 0xff) == 'M')
714 {
715 if (_SIOC_DIR(cmd) & _SIOC_WRITE)
716 {
717 switch (cmd & 0xff)
718 {
719 case SOUND_MIXER_RECSRC:
720 if (get_user(val, (int *)arg))
721 return -EFAULT;
722 val = ad1848_set_recmask(devc, val);
723 break;
724
725 default:
726 if (get_user(val, (int *)arg))
727 return -EFAULT;
728 val = ad1848_mixer_set(devc, cmd & 0xff, val);
729 break;
730 }
731 return put_user(val, (int *)arg);
732 }
733 else
734 {
735 switch (cmd & 0xff)
736 {
737 /*
738 * Return parameters
739 */
740
741 case SOUND_MIXER_RECSRC:
742 val = devc->recmask;
743 break;
744
745 case SOUND_MIXER_DEVMASK:
746 val = devc->supported_devices;
747 break;
748
749 case SOUND_MIXER_STEREODEVS:
750 val = devc->supported_devices;
751 if (devc->model != MD_C930)
752 val &= ~(SOUND_MASK_SPEAKER | SOUND_MASK_IMIX);
753 break;
754
755 case SOUND_MIXER_RECMASK:
756 val = devc->supported_rec_devices;
757 break;
758
759 case SOUND_MIXER_CAPS:
760 val=SOUND_CAP_EXCL_INPUT;
761 break;
762
763 default:
764 val = ad1848_mixer_get(devc, cmd & 0xff);
765 break;
766 }
767 return put_user(val, (int *)arg);
768 }
769 }
770 else
771 return -EINVAL;
772 }
773
774 static int ad1848_set_speed(int dev, int arg)
775 {
776 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
777 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
778
779 /*
780 * The sampling speed is encoded in the least significant nibble of I8. The
781 * LSB selects the clock source (0=24.576 MHz, 1=16.9344 MHz) and other
782 * three bits select the divisor (indirectly):
783 *
784 * The available speeds are in the following table. Keep the speeds in
785 * the increasing order.
786 */
787 typedef struct
788 {
789 int speed;
790 unsigned char bits;
791 }
792 speed_struct;
793
794 static speed_struct speed_table[] =
795 {
796 {5510, (0 << 1) | 1},
797 {5510, (0 << 1) | 1},
798 {6620, (7 << 1) | 1},
799 {8000, (0 << 1) | 0},
800 {9600, (7 << 1) | 0},
801 {11025, (1 << 1) | 1},
802 {16000, (1 << 1) | 0},
803 {18900, (2 << 1) | 1},
804 {22050, (3 << 1) | 1},
805 {27420, (2 << 1) | 0},
806 {32000, (3 << 1) | 0},
807 {33075, (6 << 1) | 1},
808 {37800, (4 << 1) | 1},
809 {44100, (5 << 1) | 1},
810 {48000, (6 << 1) | 0}
811 };
812
813 int i, n, selected = -1;
814
815 n = sizeof(speed_table) / sizeof(speed_struct);
816
817 if (arg <= 0)
818 return portc->speed;
819
820 if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE) /* AD1845 has different timer than others */
821 {
822 if (arg < 4000)
823 arg = 4000;
824 if (arg > 50000)
825 arg = 50000;
826
827 portc->speed = arg;
828 portc->speed_bits = speed_table[3].bits;
829 return portc->speed;
830 }
831 if (arg < speed_table[0].speed)
832 selected = 0;
833 if (arg > speed_table[n - 1].speed)
834 selected = n - 1;
835
836 for (i = 1 /*really */ ; selected == -1 && i < n; i++)
837 {
838 if (speed_table[i].speed == arg)
839 selected = i;
840 else if (speed_table[i].speed > arg)
841 {
842 int diff1, diff2;
843
844 diff1 = arg - speed_table[i - 1].speed;
845 diff2 = speed_table[i].speed - arg;
846
847 if (diff1 < diff2)
848 selected = i - 1;
849 else
850 selected = i;
851 }
852 }
853 if (selected == -1)
854 {
855 printk(KERN_WARNING "ad1848: Can't find speed???\n");
856 selected = 3;
857 }
858 portc->speed = speed_table[selected].speed;
859 portc->speed_bits = speed_table[selected].bits;
860 return portc->speed;
861 }
862
863 static short ad1848_set_channels(int dev, short arg)
864 {
865 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
866
867 if (arg != 1 && arg != 2)
868 return portc->channels;
869
870 portc->channels = arg;
871 return arg;
872 }
873
874 static unsigned int ad1848_set_bits(int dev, unsigned int arg)
875 {
876 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
877 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
878
879 static struct format_tbl
880 {
881 int format;
882 unsigned char bits;
883 }
884 format2bits[] =
885 {
886 {
887 0, 0
888 }
889 ,
890 {
891 AFMT_MU_LAW, 1
892 }
893 ,
894 {
895 AFMT_A_LAW, 3
896 }
897 ,
898 {
899 AFMT_IMA_ADPCM, 5
900 }
901 ,
902 {
903 AFMT_U8, 0
904 }
905 ,
906 {
907 AFMT_S16_LE, 2
908 }
909 ,
910 {
911 AFMT_S16_BE, 6
912 }
913 ,
914 {
915 AFMT_S8, 0
916 }
917 ,
918 {
919 AFMT_U16_LE, 0
920 }
921 ,
922 {
923 AFMT_U16_BE, 0
924 }
925 };
926 int i, n = sizeof(format2bits) / sizeof(struct format_tbl);
927
928 if (arg == 0)
929 return portc->audio_format;
930
931 if (!(arg & ad_format_mask[devc->model]))
932 arg = AFMT_U8;
933
934 portc->audio_format = arg;
935
936 for (i = 0; i < n; i++)
937 if (format2bits[i].format == arg)
938 {
939 if ((portc->format_bits = format2bits[i].bits) == 0)
940 return portc->audio_format = AFMT_U8; /* Was not supported */
941
942 return arg;
943 }
944 /* Still hanging here. Something must be terribly wrong */
945 portc->format_bits = 0;
946 return portc->audio_format = AFMT_U8;
947 }
948
949 static struct audio_driver ad1848_audio_driver =
950 {
951 owner: THIS_MODULE,
952 open: ad1848_open,
953 close: ad1848_close,
954 output_block: ad1848_output_block,
955 start_input: ad1848_start_input,
956 prepare_for_input: ad1848_prepare_for_input,
957 prepare_for_output: ad1848_prepare_for_output,
958 halt_io: ad1848_halt,
959 halt_input: ad1848_halt_input,
960 halt_output: ad1848_halt_output,
961 trigger: ad1848_trigger,
962 set_speed: ad1848_set_speed,
963 set_bits: ad1848_set_bits,
964 set_channels: ad1848_set_channels
965 };
966
967 static struct mixer_operations ad1848_mixer_operations =
968 {
969 owner: THIS_MODULE,
970 id: "SOUNDPORT",
971 name: "AD1848/CS4248/CS4231",
972 ioctl: ad1848_mixer_ioctl
973 };
974
975 static int ad1848_open(int dev, int mode)
976 {
977 ad1848_info *devc;
978 ad1848_port_info *portc;
979 unsigned long flags;
980
981 if (dev < 0 || dev >= num_audiodevs)
982 return -ENXIO;
983
984 devc = (ad1848_info *) audio_devs[dev]->devc;
985 portc = (ad1848_port_info *) audio_devs[dev]->portc;
986
987 spin_lock_irqsave(&devc->lock,flags);
988 if (portc->open_mode || (devc->open_mode & mode))
989 {
990 spin_unlock_irqrestore(&devc->lock,flags);
991 return -EBUSY;
992 }
993 devc->dual_dma = 0;
994
995 if (audio_devs[dev]->flags & DMA_DUPLEX)
996 {
997 devc->dual_dma = 1;
998 }
999 devc->intr_active = 0;
1000 devc->audio_mode = 0;
1001 devc->open_mode |= mode;
1002 portc->open_mode = mode;
1003 ad1848_trigger(dev, 0);
1004
1005 if (mode & OPEN_READ)
1006 devc->record_dev = dev;
1007 if (mode & OPEN_WRITE)
1008 devc->playback_dev = dev;
1009 spin_unlock_irqrestore(&devc->lock,flags);
1010 /*
1011 * Mute output until the playback really starts. This decreases clicking (hope so).
1012 */
1013 ad_mute(devc);
1014
1015 return 0;
1016 }
1017
1018 static void ad1848_close(int dev)
1019 {
1020 unsigned long flags;
1021 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1022 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1023
1024 DEB(printk("ad1848_close(void)\n"));
1025
1026 spin_lock_irqsave(&devc->lock,flags);
1027
1028 devc->intr_active = 0;
1029 ad1848_halt(dev);
1030
1031 devc->audio_mode = 0;
1032 devc->open_mode &= ~portc->open_mode;
1033 portc->open_mode = 0;
1034
1035 ad_unmute(devc);
1036 spin_unlock_irqrestore(&devc->lock,flags);
1037 }
1038
1039 static void ad1848_output_block(int dev, unsigned long buf, int count, int intrflag)
1040 {
1041 unsigned long flags, cnt;
1042 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1043 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1044
1045 cnt = count;
1046
1047 if (portc->audio_format == AFMT_IMA_ADPCM)
1048 {
1049 cnt /= 4;
1050 }
1051 else
1052 {
1053 if (portc->audio_format & (AFMT_S16_LE | AFMT_S16_BE)) /* 16 bit data */
1054 cnt >>= 1;
1055 }
1056 if (portc->channels > 1)
1057 cnt >>= 1;
1058 cnt--;
1059
1060 if ((devc->audio_mode & PCM_ENABLE_OUTPUT) && (audio_devs[dev]->flags & DMA_AUTOMODE) &&
1061 intrflag &&
1062 cnt == devc->xfer_count)
1063 {
1064 devc->audio_mode |= PCM_ENABLE_OUTPUT;
1065 devc->intr_active = 1;
1066 return; /*
1067 * Auto DMA mode on. No need to react
1068 */
1069 }
1070 spin_lock_irqsave(&devc->lock,flags);
1071
1072 ad_write(devc, 15, (unsigned char) (cnt & 0xff));
1073 ad_write(devc, 14, (unsigned char) ((cnt >> 8) & 0xff));
1074
1075 devc->xfer_count = cnt;
1076 devc->audio_mode |= PCM_ENABLE_OUTPUT;
1077 devc->intr_active = 1;
1078 spin_unlock_irqrestore(&devc->lock,flags);
1079 }
1080
1081 static void ad1848_start_input(int dev, unsigned long buf, int count, int intrflag)
1082 {
1083 unsigned long flags, cnt;
1084 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1085 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1086
1087 cnt = count;
1088 if (portc->audio_format == AFMT_IMA_ADPCM)
1089 {
1090 cnt /= 4;
1091 }
1092 else
1093 {
1094 if (portc->audio_format & (AFMT_S16_LE | AFMT_S16_BE)) /* 16 bit data */
1095 cnt >>= 1;
1096 }
1097 if (portc->channels > 1)
1098 cnt >>= 1;
1099 cnt--;
1100
1101 if ((devc->audio_mode & PCM_ENABLE_INPUT) && (audio_devs[dev]->flags & DMA_AUTOMODE) &&
1102 intrflag &&
1103 cnt == devc->xfer_count)
1104 {
1105 devc->audio_mode |= PCM_ENABLE_INPUT;
1106 devc->intr_active = 1;
1107 return; /*
1108 * Auto DMA mode on. No need to react
1109 */
1110 }
1111 spin_lock_irqsave(&devc->lock,flags);
1112
1113 if (devc->model == MD_1848)
1114 {
1115 ad_write(devc, 15, (unsigned char) (cnt & 0xff));
1116 ad_write(devc, 14, (unsigned char) ((cnt >> 8) & 0xff));
1117 }
1118 else
1119 {
1120 ad_write(devc, 31, (unsigned char) (cnt & 0xff));
1121 ad_write(devc, 30, (unsigned char) ((cnt >> 8) & 0xff));
1122 }
1123
1124 ad_unmute(devc);
1125
1126 devc->xfer_count = cnt;
1127 devc->audio_mode |= PCM_ENABLE_INPUT;
1128 devc->intr_active = 1;
1129 spin_unlock_irqrestore(&devc->lock,flags);
1130 }
1131
1132 static int ad1848_prepare_for_output(int dev, int bsize, int bcount)
1133 {
1134 int timeout;
1135 unsigned char fs, old_fs, tmp = 0;
1136 unsigned long flags;
1137 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1138 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1139
1140 ad_mute(devc);
1141
1142 spin_lock_irqsave(&devc->lock,flags);
1143 fs = portc->speed_bits | (portc->format_bits << 5);
1144
1145 if (portc->channels > 1)
1146 fs |= 0x10;
1147
1148 ad_enter_MCE(devc); /* Enables changes to the format select reg */
1149
1150 if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE) /* Use alternate speed select registers */
1151 {
1152 fs &= 0xf0; /* Mask off the rate select bits */
1153
1154 ad_write(devc, 22, (portc->speed >> 8) & 0xff); /* Speed MSB */
1155 ad_write(devc, 23, portc->speed & 0xff); /* Speed LSB */
1156 }
1157 old_fs = ad_read(devc, 8);
1158
1159 if (devc->model == MD_4232 || devc->model >= MD_4236)
1160 {
1161 tmp = ad_read(devc, 16);
1162 ad_write(devc, 16, tmp | 0x30);
1163 }
1164 if (devc->model == MD_IWAVE)
1165 ad_write(devc, 17, 0xc2); /* Disable variable frequency select */
1166
1167 ad_write(devc, 8, fs);
1168
1169 /*
1170 * Write to I8 starts resynchronization. Wait until it completes.
1171 */
1172
1173 timeout = 0;
1174 while (timeout < 100 && inb(devc->base) != 0x80)
1175 timeout++;
1176 timeout = 0;
1177 while (timeout < 10000 && inb(devc->base) == 0x80)
1178 timeout++;
1179
1180 if (devc->model >= MD_4232)
1181 ad_write(devc, 16, tmp & ~0x30);
1182
1183 ad_leave_MCE(devc); /*
1184 * Starts the calibration process.
1185 */
1186 spin_unlock_irqrestore(&devc->lock,flags);
1187 devc->xfer_count = 0;
1188
1189 #ifndef EXCLUDE_TIMERS
1190 if (dev == timer_installed && devc->timer_running)
1191 if ((fs & 0x01) != (old_fs & 0x01))
1192 {
1193 ad1848_tmr_reprogram(dev);
1194 }
1195 #endif
1196 ad1848_halt_output(dev);
1197 return 0;
1198 }
1199
1200 static int ad1848_prepare_for_input(int dev, int bsize, int bcount)
1201 {
1202 int timeout;
1203 unsigned char fs, old_fs, tmp = 0;
1204 unsigned long flags;
1205 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1206 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1207
1208 if (devc->audio_mode)
1209 return 0;
1210
1211 spin_lock_irqsave(&devc->lock,flags);
1212 fs = portc->speed_bits | (portc->format_bits << 5);
1213
1214 if (portc->channels > 1)
1215 fs |= 0x10;
1216
1217 ad_enter_MCE(devc); /* Enables changes to the format select reg */
1218
1219 if ((devc->model == MD_1845) || (devc->model == MD_1845_SSCAPE)) /* Use alternate speed select registers */
1220 {
1221 fs &= 0xf0; /* Mask off the rate select bits */
1222
1223 ad_write(devc, 22, (portc->speed >> 8) & 0xff); /* Speed MSB */
1224 ad_write(devc, 23, portc->speed & 0xff); /* Speed LSB */
1225 }
1226 if (devc->model == MD_4232)
1227 {
1228 tmp = ad_read(devc, 16);
1229 ad_write(devc, 16, tmp | 0x30);
1230 }
1231 if (devc->model == MD_IWAVE)
1232 ad_write(devc, 17, 0xc2); /* Disable variable frequency select */
1233
1234 /*
1235 * If mode >= 2 (CS4231), set I28. It's the capture format register.
1236 */
1237
1238 if (devc->model != MD_1848)
1239 {
1240 old_fs = ad_read(devc, 28);
1241 ad_write(devc, 28, fs);
1242
1243 /*
1244 * Write to I28 starts resynchronization. Wait until it completes.
1245 */
1246
1247 timeout = 0;
1248 while (timeout < 100 && inb(devc->base) != 0x80)
1249 timeout++;
1250
1251 timeout = 0;
1252 while (timeout < 10000 && inb(devc->base) == 0x80)
1253 timeout++;
1254
1255 if (devc->model != MD_1848 && devc->model != MD_1845 && devc->model != MD_1845_SSCAPE)
1256 {
1257 /*
1258 * CS4231 compatible devices don't have separate sampling rate selection
1259 * register for recording an playback. The I8 register is shared so we have to
1260 * set the speed encoding bits of it too.
1261 */
1262 unsigned char tmp = portc->speed_bits | (ad_read(devc, 8) & 0xf0);
1263
1264 ad_write(devc, 8, tmp);
1265 /*
1266 * Write to I8 starts resynchronization. Wait until it completes.
1267 */
1268 timeout = 0;
1269 while (timeout < 100 && inb(devc->base) != 0x80)
1270 timeout++;
1271
1272 timeout = 0;
1273 while (timeout < 10000 && inb(devc->base) == 0x80)
1274 timeout++;
1275 }
1276 }
1277 else
1278 { /* For AD1848 set I8. */
1279
1280 old_fs = ad_read(devc, 8);
1281 ad_write(devc, 8, fs);
1282 /*
1283 * Write to I8 starts resynchronization. Wait until it completes.
1284 */
1285 timeout = 0;
1286 while (timeout < 100 && inb(devc->base) != 0x80)
1287 timeout++;
1288 timeout = 0;
1289 while (timeout < 10000 && inb(devc->base) == 0x80)
1290 timeout++;
1291 }
1292
1293 if (devc->model == MD_4232)
1294 ad_write(devc, 16, tmp & ~0x30);
1295
1296 ad_leave_MCE(devc); /*
1297 * Starts the calibration process.
1298 */
1299 spin_unlock_irqrestore(&devc->lock,flags);
1300 devc->xfer_count = 0;
1301
1302 #ifndef EXCLUDE_TIMERS
1303 if (dev == timer_installed && devc->timer_running)
1304 {
1305 if ((fs & 0x01) != (old_fs & 0x01))
1306 {
1307 ad1848_tmr_reprogram(dev);
1308 }
1309 }
1310 #endif
1311 ad1848_halt_input(dev);
1312 return 0;
1313 }
1314
1315 static void ad1848_halt(int dev)
1316 {
1317 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1318 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1319
1320 unsigned char bits = ad_read(devc, 9);
1321
1322 if (bits & 0x01 && (portc->open_mode & OPEN_WRITE))
1323 ad1848_halt_output(dev);
1324
1325 if (bits & 0x02 && (portc->open_mode & OPEN_READ))
1326 ad1848_halt_input(dev);
1327 devc->audio_mode = 0;
1328 }
1329
1330 static void ad1848_halt_input(int dev)
1331 {
1332 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1333 unsigned long flags;
1334
1335 if (!(ad_read(devc, 9) & 0x02))
1336 return; /* Capture not enabled */
1337
1338 spin_lock_irqsave(&devc->lock,flags);
1339
1340 ad_mute(devc);
1341
1342 {
1343 int tmout;
1344
1345 if(!isa_dma_bridge_buggy)
1346 disable_dma(audio_devs[dev]->dmap_in->dma);
1347
1348 for (tmout = 0; tmout < 100000; tmout++)
1349 if (ad_read(devc, 11) & 0x10)
1350 break;
1351 ad_write(devc, 9, ad_read(devc, 9) & ~0x02); /* Stop capture */
1352
1353 if(!isa_dma_bridge_buggy)
1354 enable_dma(audio_devs[dev]->dmap_in->dma);
1355 devc->audio_mode &= ~PCM_ENABLE_INPUT;
1356 }
1357
1358 outb(0, io_Status(devc)); /* Clear interrupt status */
1359 outb(0, io_Status(devc)); /* Clear interrupt status */
1360
1361 devc->audio_mode &= ~PCM_ENABLE_INPUT;
1362
1363 spin_unlock_irqrestore(&devc->lock,flags);
1364 }
1365
1366 static void ad1848_halt_output(int dev)
1367 {
1368 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1369 unsigned long flags;
1370
1371 if (!(ad_read(devc, 9) & 0x01))
1372 return; /* Playback not enabled */
1373
1374 spin_lock_irqsave(&devc->lock,flags);
1375
1376 ad_mute(devc);
1377 {
1378 int tmout;
1379
1380 if(!isa_dma_bridge_buggy)
1381 disable_dma(audio_devs[dev]->dmap_out->dma);
1382
1383 for (tmout = 0; tmout < 100000; tmout++)
1384 if (ad_read(devc, 11) & 0x10)
1385 break;
1386 ad_write(devc, 9, ad_read(devc, 9) & ~0x01); /* Stop playback */
1387
1388 if(!isa_dma_bridge_buggy)
1389 enable_dma(audio_devs[dev]->dmap_out->dma);
1390
1391 devc->audio_mode &= ~PCM_ENABLE_OUTPUT;
1392 }
1393
1394 outb((0), io_Status(devc)); /* Clear interrupt status */
1395 outb((0), io_Status(devc)); /* Clear interrupt status */
1396
1397 devc->audio_mode &= ~PCM_ENABLE_OUTPUT;
1398
1399 spin_unlock_irqrestore(&devc->lock,flags);
1400 }
1401
1402 static void ad1848_trigger(int dev, int state)
1403 {
1404 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1405 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1406 unsigned long flags;
1407 unsigned char tmp, old;
1408
1409 spin_lock_irqsave(&devc->lock,flags);
1410 state &= devc->audio_mode;
1411
1412 tmp = old = ad_read(devc, 9);
1413
1414 if (portc->open_mode & OPEN_READ)
1415 {
1416 if (state & PCM_ENABLE_INPUT)
1417 tmp |= 0x02;
1418 else
1419 tmp &= ~0x02;
1420 }
1421 if (portc->open_mode & OPEN_WRITE)
1422 {
1423 if (state & PCM_ENABLE_OUTPUT)
1424 tmp |= 0x01;
1425 else
1426 tmp &= ~0x01;
1427 }
1428 /* ad_mute(devc); */
1429 if (tmp != old)
1430 {
1431 ad_write(devc, 9, tmp);
1432 ad_unmute(devc);
1433 }
1434 spin_unlock_irqrestore(&devc->lock,flags);
1435 }
1436
1437 static void ad1848_init_hw(ad1848_info * devc)
1438 {
1439 int i;
1440 int *init_values;
1441
1442 /*
1443 * Initial values for the indirect registers of CS4248/AD1848.
1444 */
1445 static int init_values_a[] =
1446 {
1447 0xa8, 0xa8, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00,
1448 0x00, 0x0c, 0x02, 0x00, 0x8a, 0x01, 0x00, 0x00,
1449
1450 /* Positions 16 to 31 just for CS4231/2 and ad1845 */
1451 0x80, 0x00, 0x10, 0x10, 0x00, 0x00, 0x1f, 0x40,
1452 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
1453 };
1454
1455 static int init_values_b[] =
1456 {
1457 /*
1458 Values for the newer chips
1459 Some of the register initialization values were changed. In
1460 order to get rid of the click that preceded PCM playback,
1461 calibration was disabled on the 10th byte. On that same byte,
1462 dual DMA was enabled; on the 11th byte, ADC dithering was
1463 enabled, since that is theoretically desirable; on the 13th
1464 byte, Mode 3 was selected, to enable access to extended
1465 registers.
1466 */
1467 0xa8, 0xa8, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00,
1468 0x00, 0x00, 0x06, 0x00, 0xe0, 0x01, 0x00, 0x00,
1469 0x80, 0x00, 0x10, 0x10, 0x00, 0x00, 0x1f, 0x40,
1470 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
1471 };
1472
1473 /*
1474 * Select initialisation data
1475 */
1476
1477 init_values = init_values_a;
1478 if(devc->model >= MD_4236)
1479 init_values = init_values_b;
1480
1481 for (i = 0; i < 16; i++)
1482 ad_write(devc, i, init_values[i]);
1483
1484
1485 ad_mute(devc); /* Initialize some variables */
1486 ad_unmute(devc); /* Leave it unmuted now */
1487
1488 if (devc->model > MD_1848)
1489 {
1490 if (devc->model == MD_1845_SSCAPE)
1491 ad_write(devc, 12, ad_read(devc, 12) | 0x50);
1492 else
1493 ad_write(devc, 12, ad_read(devc, 12) | 0x40); /* Mode2 = enabled */
1494
1495 if (devc->model == MD_IWAVE)
1496 ad_write(devc, 12, 0x6c); /* Select codec mode 3 */
1497
1498 if (devc->model != MD_1845_SSCAPE)
1499 for (i = 16; i < 32; i++)
1500 ad_write(devc, i, init_values[i]);
1501
1502 if (devc->model == MD_IWAVE)
1503 ad_write(devc, 16, 0x30); /* Playback and capture counters enabled */
1504 }
1505 if (devc->model > MD_1848)
1506 {
1507 if (devc->audio_flags & DMA_DUPLEX)
1508 ad_write(devc, 9, ad_read(devc, 9) & ~0x04); /* Dual DMA mode */
1509 else
1510 ad_write(devc, 9, ad_read(devc, 9) | 0x04); /* Single DMA mode */
1511
1512 if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE)
1513 ad_write(devc, 27, ad_read(devc, 27) | 0x08); /* Alternate freq select enabled */
1514
1515 if (devc->model == MD_IWAVE)
1516 { /* Some magic Interwave specific initialization */
1517 ad_write(devc, 12, 0x6c); /* Select codec mode 3 */
1518 ad_write(devc, 16, 0x30); /* Playback and capture counters enabled */
1519 ad_write(devc, 17, 0xc2); /* Alternate feature enable */
1520 }
1521 }
1522 else
1523 {
1524 devc->audio_flags &= ~DMA_DUPLEX;
1525 ad_write(devc, 9, ad_read(devc, 9) | 0x04); /* Single DMA mode */
1526 if (soundpro)
1527 ad_write(devc, 12, ad_read(devc, 12) | 0x40); /* Mode2 = enabled */
1528 }
1529
1530 outb((0), io_Status(devc)); /* Clear pending interrupts */
1531
1532 /*
1533 * Toggle the MCE bit. It completes the initialization phase.
1534 */
1535
1536 ad_enter_MCE(devc); /* In case the bit was off */
1537 ad_leave_MCE(devc);
1538
1539 ad1848_mixer_reset(devc);
1540 }
1541
1542 int ad1848_detect(int io_base, int *ad_flags, int *osp)
1543 {
1544 unsigned char tmp;
1545 ad1848_info *devc = &adev_info[nr_ad1848_devs];
1546 unsigned char tmp1 = 0xff, tmp2 = 0xff;
1547 int optiC930 = 0; /* OPTi 82C930 flag */
1548 int interwave = 0;
1549 int ad1847_flag = 0;
1550 int cs4248_flag = 0;
1551 int sscape_flag = 0;
1552
1553 int i;
1554
1555 DDB(printk("ad1848_detect(%x)\n", io_base));
1556
1557 if (ad_flags)
1558 {
1559 if (*ad_flags == 0x12345678)
1560 {
1561 interwave = 1;
1562 *ad_flags = 0;
1563 }
1564
1565 if (*ad_flags == 0x87654321)
1566 {
1567 sscape_flag = 1;
1568 *ad_flags = 0;
1569 }
1570
1571 if (*ad_flags == 0x12345677)
1572 {
1573 cs4248_flag = 1;
1574 *ad_flags = 0;
1575 }
1576 }
1577 if (nr_ad1848_devs >= MAX_AUDIO_DEV)
1578 {
1579 printk(KERN_ERR "ad1848 - Too many audio devices\n");
1580 return 0;
1581 }
1582 if (check_region(io_base, 4))
1583 {
1584 printk(KERN_ERR "ad1848.c: Port %x not free.\n", io_base);
1585 return 0;
1586 }
1587 devc->base = io_base;
1588 devc->irq_ok = 0;
1589 devc->timer_running = 0;
1590 devc->MCE_bit = 0x40;
1591 devc->irq = 0;
1592 devc->open_mode = 0;
1593 devc->chip_name = devc->name = "AD1848";
1594 devc->model = MD_1848; /* AD1848 or CS4248 */
1595 devc->levels = NULL;
1596 devc->debug_flag = 0;
1597
1598 /*
1599 * Check that the I/O address is in use.
1600 *
1601 * The bit 0x80 of the base I/O port is known to be 0 after the
1602 * chip has performed its power on initialization. Just assume
1603 * this has happened before the OS is starting.
1604 *
1605 * If the I/O address is unused, it typically returns 0xff.
1606 */
1607
1608 if (inb(devc->base) == 0xff)
1609 {
1610 DDB(printk("ad1848_detect: The base I/O address appears to be dead\n"));
1611 }
1612
1613 /*
1614 * Wait for the device to stop initialization
1615 */
1616
1617 DDB(printk("ad1848_detect() - step 0\n"));
1618
1619 for (i = 0; i < 10000000; i++)
1620 {
1621 unsigned char x = inb(devc->base);
1622
1623 if (x == 0xff || !(x & 0x80))
1624 break;
1625 }
1626
1627 DDB(printk("ad1848_detect() - step A\n"));
1628
1629 if (inb(devc->base) == 0x80) /* Not ready. Let's wait */
1630 ad_leave_MCE(devc);
1631
1632 if ((inb(devc->base) & 0x80) != 0x00) /* Not a AD1848 */
1633 {
1634 DDB(printk("ad1848 detect error - step A (%02x)\n", (int) inb(devc->base)));
1635 return 0;
1636 }
1637
1638 /*
1639 * Test if it's possible to change contents of the indirect registers.
1640 * Registers 0 and 1 are ADC volume registers. The bit 0x10 is read only
1641 * so try to avoid using it.
1642 */
1643
1644 DDB(printk("ad1848_detect() - step B\n"));
1645 ad_write(devc, 0, 0xaa);
1646 ad_write(devc, 1, 0x45); /* 0x55 with bit 0x10 clear */
1647
1648 if ((tmp1 = ad_read(devc, 0)) != 0xaa || (tmp2 = ad_read(devc, 1)) != 0x45)
1649 {
1650 if (tmp2 == 0x65) /* AD1847 has couple of bits hardcoded to 1 */
1651 ad1847_flag = 1;
1652 else
1653 {
1654 DDB(printk("ad1848 detect error - step B (%x/%x)\n", tmp1, tmp2));
1655 return 0;
1656 }
1657 }
1658 DDB(printk("ad1848_detect() - step C\n"));
1659 ad_write(devc, 0, 0x45);
1660 ad_write(devc, 1, 0xaa);
1661
1662 if ((tmp1 = ad_read(devc, 0)) != 0x45 || (tmp2 = ad_read(devc, 1)) != 0xaa)
1663 {
1664 if (tmp2 == 0x8a) /* AD1847 has few bits hardcoded to 1 */
1665 ad1847_flag = 1;
1666 else
1667 {
1668 DDB(printk("ad1848 detect error - step C (%x/%x)\n", tmp1, tmp2));
1669 return 0;
1670 }
1671 }
1672
1673 /*
1674 * The indirect register I12 has some read only bits. Let's
1675 * try to change them.
1676 */
1677
1678 DDB(printk("ad1848_detect() - step D\n"));
1679 tmp = ad_read(devc, 12);
1680 ad_write(devc, 12, (~tmp) & 0x0f);
1681
1682 if ((tmp & 0x0f) != ((tmp1 = ad_read(devc, 12)) & 0x0f))
1683 {
1684 DDB(printk("ad1848 detect error - step D (%x)\n", tmp1));
1685 return 0;
1686 }
1687
1688 /*
1689 * NOTE! Last 4 bits of the reg I12 tell the chip revision.
1690 * 0x01=RevB and 0x0A=RevC.
1691 */
1692
1693 /*
1694 * The original AD1848/CS4248 has just 15 indirect registers. This means
1695 * that I0 and I16 should return the same value (etc.).
1696 * However this doesn't work with CS4248. Actually it seems to be impossible
1697 * to detect if the chip is a CS4231 or CS4248.
1698 * Ensure that the Mode2 enable bit of I12 is 0. Otherwise this test fails
1699 * with CS4231.
1700 */
1701
1702 /*
1703 * OPTi 82C930 has mode2 control bit in another place. This test will fail
1704 * with it. Accept this situation as a possible indication of this chip.
1705 */
1706
1707 DDB(printk("ad1848_detect() - step F\n"));
1708 ad_write(devc, 12, 0); /* Mode2=disabled */
1709
1710 for (i = 0; i < 16; i++)
1711 {
1712 if ((tmp1 = ad_read(devc, i)) != (tmp2 = ad_read(devc, i + 16)))
1713 {
1714 DDB(printk("ad1848 detect step F(%d/%x/%x) - OPTi chip???\n", i, tmp1, tmp2));
1715 if (!ad1847_flag)
1716 optiC930 = 1;
1717 break;
1718 }
1719 }
1720
1721 /*
1722 * Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit (0x40).
1723 * The bit 0x80 is always 1 in CS4248 and CS4231.
1724 */
1725
1726 DDB(printk("ad1848_detect() - step G\n"));
1727
1728 if (ad_flags && *ad_flags == 400)
1729 *ad_flags = 0;
1730 else
1731 ad_write(devc, 12, 0x40); /* Set mode2, clear 0x80 */
1732
1733
1734 if (ad_flags)
1735 *ad_flags = 0;
1736
1737 tmp1 = ad_read(devc, 12);
1738 if (tmp1 & 0x80)
1739 {
1740 if (ad_flags)
1741 *ad_flags |= AD_F_CS4248;
1742
1743 devc->chip_name = "CS4248"; /* Our best knowledge just now */
1744 }
1745 if (optiC930 || (tmp1 & 0xc0) == (0x80 | 0x40))
1746 {
1747 /*
1748 * CS4231 detected - is it?
1749 *
1750 * Verify that setting I0 doesn't change I16.
1751 */
1752
1753 DDB(printk("ad1848_detect() - step H\n"));
1754 ad_write(devc, 16, 0); /* Set I16 to known value */
1755
1756 ad_write(devc, 0, 0x45);
1757 if ((tmp1 = ad_read(devc, 16)) != 0x45) /* No change -> CS4231? */
1758 {
1759 ad_write(devc, 0, 0xaa);
1760 if ((tmp1 = ad_read(devc, 16)) == 0xaa) /* Rotten bits? */
1761 {
1762 DDB(printk("ad1848 detect error - step H(%x)\n", tmp1));
1763 return 0;
1764 }
1765
1766 /*
1767 * Verify that some bits of I25 are read only.
1768 */
1769
1770 DDB(printk("ad1848_detect() - step I\n"));
1771 tmp1 = ad_read(devc, 25); /* Original bits */
1772 ad_write(devc, 25, ~tmp1); /* Invert all bits */
1773 if ((ad_read(devc, 25) & 0xe7) == (tmp1 & 0xe7))
1774 {
1775 int id;
1776
1777 /*
1778 * It's at least CS4231
1779 */
1780
1781 devc->chip_name = "CS4231";
1782 devc->model = MD_4231;
1783
1784 /*
1785 * It could be an AD1845 or CS4231A as well.
1786 * CS4231 and AD1845 report the same revision info in I25
1787 * while the CS4231A reports different.
1788 */
1789
1790 id = ad_read(devc, 25);
1791 if ((id & 0xe7) == 0x80) /* Device busy??? */
1792 id = ad_read(devc, 25);
1793 if ((id & 0xe7) == 0x80) /* Device still busy??? */
1794 id = ad_read(devc, 25);
1795 DDB(printk("ad1848_detect() - step J (%02x/%02x)\n", id, ad_read(devc, 25)));
1796
1797 if ((id & 0xe7) == 0x80) {
1798 /*
1799 * It must be a CS4231 or AD1845. The register I23 of
1800 * CS4231 is undefined and it appears to be read only.
1801 * AD1845 uses I23 for setting sample rate. Assume
1802 * the chip is AD1845 if I23 is changeable.
1803 */
1804
1805 unsigned char tmp = ad_read(devc, 23);
1806 ad_write(devc, 23, ~tmp);
1807
1808 if (interwave)
1809 {
1810 devc->model = MD_IWAVE;
1811 devc->chip_name = "IWave";
1812 }
1813 else if (ad_read(devc, 23) != tmp) /* AD1845 ? */
1814 {
1815 devc->chip_name = "AD1845";
1816 devc->model = MD_1845;
1817 }
1818 else if (cs4248_flag)
1819 {
1820 if (ad_flags)
1821 *ad_flags |= AD_F_CS4248;
1822 devc->chip_name = "CS4248";
1823 devc->model = MD_1848;
1824 ad_write(devc, 12, ad_read(devc, 12) & ~0x40); /* Mode2 off */
1825 }
1826 ad_write(devc, 23, tmp); /* Restore */
1827 }
1828 else
1829 {
1830 switch (id & 0x1f) {
1831 case 3: /* CS4236/CS4235/CS42xB/CS4239 */
1832 {
1833 int xid;
1834 ad_write(devc, 12, ad_read(devc, 12) | 0x60); /* switch to mode 3 */
1835 ad_write(devc, 23, 0x9c); /* select extended register 25 */
1836 xid = inb(io_Indexed_Data(devc));
1837 ad_write(devc, 12, ad_read(devc, 12) & ~0x60); /* back to mode 0 */
1838 switch (xid & 0x1f)
1839 {
1840 case 0x00:
1841 devc->chip_name = "CS4237B(B)";
1842 devc->model = MD_42xB;
1843 break;
1844 case 0x08:
1845 /* Seems to be a 4238 ?? */
1846 devc->chip_name = "CS4238";
1847 devc->model = MD_42xB;
1848 break;
1849 case 0x09:
1850 devc->chip_name = "CS4238B";
1851 devc->model = MD_42xB;
1852 break;
1853 case 0x0b:
1854 devc->chip_name = "CS4236B";
1855 devc->model = MD_4236;
1856 break;
1857 case 0x10:
1858 devc->chip_name = "CS4237B";
1859 devc->model = MD_42xB;
1860 break;
1861 case 0x1d:
1862 devc->chip_name = "CS4235";
1863 devc->model = MD_4235;
1864 break;
1865 case 0x1e:
1866 devc->chip_name = "CS4239";
1867 devc->model = MD_4239;
1868 break;
1869 default:
1870 printk("Chip ident is %X.\n", xid&0x1F);
1871 devc->chip_name = "CS42xx";
1872 devc->model = MD_4232;
1873 break;
1874 }
1875 }
1876 break;
1877
1878 case 2: /* CS4232/CS4232A */
1879 devc->chip_name = "CS4232";
1880 devc->model = MD_4232;
1881 break;
1882
1883 case 0:
1884 if ((id & 0xe0) == 0xa0)
1885 {
1886 devc->chip_name = "CS4231A";
1887 devc->model = MD_4231A;
1888 }
1889 else
1890 {
1891 devc->chip_name = "CS4321";
1892 devc->model = MD_4231;
1893 }
1894 break;
1895
1896 default: /* maybe */
1897 DDB(printk("ad1848: I25 = %02x/%02x\n", ad_read(devc, 25), ad_read(devc, 25) & 0xe7));
1898 if (optiC930)
1899 {
1900 devc->chip_name = "82C930";
1901 devc->model = MD_C930;
1902 }
1903 else
1904 {
1905 devc->chip_name = "CS4231";
1906 devc->model = MD_4231;
1907 }
1908 }
1909 }
1910 }
1911 ad_write(devc, 25, tmp1); /* Restore bits */
1912
1913 DDB(printk("ad1848_detect() - step K\n"));
1914 }
1915 } else if (tmp1 == 0x0a) {
1916 /*
1917 * Is it perhaps a SoundPro CMI8330?
1918 * If so, then we should be able to change indirect registers
1919 * greater than I15 after activating MODE2, even though reading
1920 * back I12 does not show it.
1921 */
1922
1923 /*
1924 * Let's try comparing register values
1925 */
1926 for (i = 0; i < 16; i++) {
1927 if ((tmp1 = ad_read(devc, i)) != (tmp2 = ad_read(devc, i + 16))) {
1928 DDB(printk("ad1848 detect step H(%d/%x/%x) - SoundPro chip?\n", i, tmp1, tmp2));
1929 soundpro = 1;
1930 devc->chip_name = "SoundPro CMI 8330";
1931 break;
1932 }
1933 }
1934 }
1935
1936 DDB(printk("ad1848_detect() - step L\n"));
1937 if (ad_flags)
1938 {
1939 if (devc->model != MD_1848)
1940 *ad_flags |= AD_F_CS4231;
1941 }
1942 DDB(printk("ad1848_detect() - Detected OK\n"));
1943
1944 if (devc->model == MD_1848 && ad1847_flag)
1945 devc->chip_name = "AD1847";
1946
1947
1948 if (sscape_flag == 1)
1949 devc->model = MD_1845_SSCAPE;
1950
1951 return 1;
1952 }
1953
1954 int ad1848_init (char *name, int io_base, int irq, int dma_playback,
1955 int dma_capture, int share_dma, int *osp, struct module *owner)
1956 {
1957 /*
1958 * NOTE! If irq < 0, there is another driver which has allocated the IRQ
1959 * so that this driver doesn't need to allocate/deallocate it.
1960 * The actually used IRQ is ABS(irq).
1961 */
1962
1963 int my_dev;
1964 char dev_name[100];
1965 int e;
1966
1967 ad1848_info *devc = &adev_info[nr_ad1848_devs];
1968
1969 ad1848_port_info *portc = NULL;
1970
1971 spin_lock_init(&devc->lock);
1972 devc->irq = (irq > 0) ? irq : 0;
1973 devc->open_mode = 0;
1974 devc->timer_ticks = 0;
1975 devc->dma1 = dma_playback;
1976 devc->dma2 = dma_capture;
1977 devc->subtype = cfg.card_subtype;
1978 devc->audio_flags = DMA_AUTOMODE;
1979 devc->playback_dev = devc->record_dev = 0;
1980 if (name != NULL)
1981 devc->name = name;
1982
1983 if (name != NULL && name[0] != 0)
1984 sprintf(dev_name,
1985 "%s (%s)", name, devc->chip_name);
1986 else
1987 sprintf(dev_name,
1988 "Generic audio codec (%s)", devc->chip_name);
1989
1990 if (!request_region(devc->base, 4, devc->name))
1991 return -1;
1992
1993 conf_printf2(dev_name, devc->base, devc->irq, dma_playback, dma_capture);
1994
1995 if (devc->model == MD_1848 || devc->model == MD_C930)
1996 devc->audio_flags |= DMA_HARDSTOP;
1997
1998 if (devc->model > MD_1848)
1999 {
2000 if (devc->dma1 == devc->dma2 || devc->dma2 == -1 || devc->dma1 == -1)
2001 devc->audio_flags &= ~DMA_DUPLEX;
2002 else
2003 devc->audio_flags |= DMA_DUPLEX;
2004 }
2005
2006 portc = (ad1848_port_info *) kmalloc(sizeof(ad1848_port_info), GFP_KERNEL);
2007 if(portc==NULL) {
2008 release_region(devc->base, 4);
2009 return -1;
2010 }
2011
2012 if ((my_dev = sound_install_audiodrv(AUDIO_DRIVER_VERSION,
2013 dev_name,
2014 &ad1848_audio_driver,
2015 sizeof(struct audio_driver),
2016 devc->audio_flags,
2017 ad_format_mask[devc->model],
2018 devc,
2019 dma_playback,
2020 dma_capture)) < 0)
2021 {
2022 release_region(devc->base, 4);
2023 kfree(portc);
2024 return -1;
2025 }
2026
2027 audio_devs[my_dev]->portc = portc;
2028 audio_devs[my_dev]->mixer_dev = -1;
2029 if (owner)
2030 audio_devs[my_dev]->d->owner = owner;
2031 memset((char *) portc, 0, sizeof(*portc));
2032
2033 nr_ad1848_devs++;
2034
2035 devc->pmdev = pm_register(PM_ISA_DEV, my_dev, ad1848_pm_callback);
2036 if (devc->pmdev)
2037 devc->pmdev->data = devc;
2038
2039 ad1848_init_hw(devc);
2040
2041 if (irq > 0)
2042 {
2043 devc->dev_no = my_dev;
2044 if (request_irq(devc->irq, adintr, 0, devc->name, (void *)my_dev) < 0)
2045 {
2046 printk(KERN_WARNING "ad1848: Unable to allocate IRQ\n");
2047 /* Don't free it either then.. */
2048 devc->irq = 0;
2049 }
2050 if (capabilities[devc->model].flags & CAP_F_TIMER)
2051 {
2052 #ifndef CONFIG_SMP
2053 int x;
2054 unsigned char tmp = ad_read(devc, 16);
2055 #endif
2056
2057 devc->timer_ticks = 0;
2058
2059 ad_write(devc, 21, 0x00); /* Timer MSB */
2060 ad_write(devc, 20, 0x10); /* Timer LSB */
2061 #ifndef CONFIG_SMP
2062 ad_write(devc, 16, tmp | 0x40); /* Enable timer */
2063 for (x = 0; x < 100000 && devc->timer_ticks == 0; x++);
2064 ad_write(devc, 16, tmp & ~0x40); /* Disable timer */
2065
2066 if (devc->timer_ticks == 0)
2067 printk(KERN_WARNING "ad1848: Interrupt test failed (IRQ%d)\n", irq);
2068 else
2069 {
2070 DDB(printk("Interrupt test OK\n"));
2071 devc->irq_ok = 1;
2072 }
2073 #else
2074 devc->irq_ok = 1;
2075 #endif
2076 }
2077 else
2078 devc->irq_ok = 1; /* Couldn't test. assume it's OK */
2079 } else if (irq < 0)
2080 irq2dev[-irq] = devc->dev_no = my_dev;
2081
2082 #ifndef EXCLUDE_TIMERS
2083 if ((capabilities[devc->model].flags & CAP_F_TIMER) &&
2084 devc->irq_ok)
2085 ad1848_tmr_install(my_dev);
2086 #endif
2087
2088 if (!share_dma)
2089 {
2090 if (sound_alloc_dma(dma_playback, devc->name))
2091 printk(KERN_WARNING "ad1848.c: Can't allocate DMA%d\n", dma_playback);
2092
2093 if (dma_capture != dma_playback)
2094 if (sound_alloc_dma(dma_capture, devc->name))
2095 printk(KERN_WARNING "ad1848.c: Can't allocate DMA%d\n", dma_capture);
2096 }
2097
2098 if ((e = sound_install_mixer(MIXER_DRIVER_VERSION,
2099 dev_name,
2100 &ad1848_mixer_operations,
2101 sizeof(struct mixer_operations),
2102 devc)) >= 0)
2103 {
2104 audio_devs[my_dev]->mixer_dev = e;
2105 if (owner)
2106 mixer_devs[e]->owner = owner;
2107 }
2108 return my_dev;
2109 }
2110
2111 int ad1848_control(int cmd, int arg)
2112 {
2113 ad1848_info *devc;
2114
2115 if (nr_ad1848_devs < 1)
2116 return -ENODEV;
2117
2118 devc = &adev_info[nr_ad1848_devs - 1];
2119
2120 switch (cmd)
2121 {
2122 case AD1848_SET_XTAL: /* Change clock frequency of AD1845 (only ) */
2123 if (devc->model != MD_1845 || devc->model != MD_1845_SSCAPE)
2124 return -EINVAL;
2125 ad_enter_MCE(devc);
2126 ad_write(devc, 29, (ad_read(devc, 29) & 0x1f) | (arg << 5));
2127 ad_leave_MCE(devc);
2128 break;
2129
2130 case AD1848_MIXER_REROUTE:
2131 {
2132 int o = (arg >> 8) & 0xff;
2133 int n = arg & 0xff;
2134
2135 if (o < 0 || o >= SOUND_MIXER_NRDEVICES)
2136 return -EINVAL;
2137
2138 if (!(devc->supported_devices & (1 << o)) &&
2139 !(devc->supported_rec_devices & (1 << o)))
2140 return -EINVAL;
2141
2142 if (n == SOUND_MIXER_NONE)
2143 { /* Just hide this control */
2144 ad1848_mixer_set(devc, o, 0); /* Shut up it */
2145 devc->supported_devices &= ~(1 << o);
2146 devc->supported_rec_devices &= ~(1 << o);
2147 break;
2148 }
2149
2150 /* Make the mixer control identified by o to appear as n */
2151 if (n < 0 || n >= SOUND_MIXER_NRDEVICES)
2152 return -EINVAL;
2153
2154 devc->mixer_reroute[n] = o; /* Rename the control */
2155 if (devc->supported_devices & (1 << o))
2156 devc->supported_devices |= (1 << n);
2157 if (devc->supported_rec_devices & (1 << o))
2158 devc->supported_rec_devices |= (1 << n);
2159
2160 devc->supported_devices &= ~(1 << o);
2161 devc->supported_rec_devices &= ~(1 << o);
2162 }
2163 break;
2164 }
2165 return 0;
2166 }
2167
2168 void ad1848_unload(int io_base, int irq, int dma_playback, int dma_capture, int share_dma)
2169 {
2170 int i, mixer, dev = 0;
2171 ad1848_info *devc = NULL;
2172
2173 for (i = 0; devc == NULL && i < nr_ad1848_devs; i++)
2174 {
2175 if (adev_info[i].base == io_base)
2176 {
2177 devc = &adev_info[i];
2178 dev = devc->dev_no;
2179 }
2180 }
2181
2182 if (devc != NULL)
2183 {
2184 if(audio_devs[dev]->portc!=NULL)
2185 kfree(audio_devs[dev]->portc);
2186 release_region(devc->base, 4);
2187
2188 if (!share_dma)
2189 {
2190 if (devc->irq > 0) /* There is no point in freeing irq, if it wasn't allocated */
2191 free_irq(devc->irq, (void *)devc->dev_no);
2192
2193 sound_free_dma(dma_playback);
2194
2195 if (dma_playback != dma_capture)
2196 sound_free_dma(dma_capture);
2197
2198 }
2199 mixer = audio_devs[devc->dev_no]->mixer_dev;
2200 if(mixer>=0)
2201 sound_unload_mixerdev(mixer);
2202
2203 if (devc->pmdev)
2204 pm_unregister(devc->pmdev);
2205
2206 nr_ad1848_devs--;
2207 for ( ; i < nr_ad1848_devs ; i++)
2208 adev_info[i] = adev_info[i+1];
2209 }
2210 else
2211 printk(KERN_ERR "ad1848: Can't find device to be unloaded. Base=%x\n", io_base);
2212 }
2213
2214 void adintr(int irq, void *dev_id, struct pt_regs *dummy)
2215 {
2216 unsigned char status;
2217 ad1848_info *devc;
2218 int dev;
2219 int alt_stat = 0xff;
2220 unsigned char c930_stat = 0;
2221 int cnt = 0;
2222
2223 dev = (int)dev_id;
2224 devc = (ad1848_info *) audio_devs[dev]->devc;
2225
2226 interrupt_again: /* Jump back here if int status doesn't reset */
2227
2228 status = inb(io_Status(devc));
2229
2230 if (status == 0x80)
2231 printk(KERN_DEBUG "adintr: Why?\n");
2232 if (devc->model == MD_1848)
2233 outb((0), io_Status(devc)); /* Clear interrupt status */
2234
2235 if (status & 0x01)
2236 {
2237 if (devc->model == MD_C930)
2238 { /* 82C930 has interrupt status register in MAD16 register MC11 */
2239
2240 spin_lock(&devc->lock);
2241
2242 /* 0xe0e is C930 address port
2243 * 0xe0f is C930 data port
2244 */
2245 outb(11, 0xe0e);
2246 c930_stat = inb(0xe0f);
2247 outb((~c930_stat), 0xe0f);
2248
2249 spin_unlock(&devc->lock);
2250
2251 alt_stat = (c930_stat << 2) & 0x30;
2252 }
2253 else if (devc->model != MD_1848)
2254 {
2255 alt_stat = ad_read(devc, 24);
2256 ad_write(devc, 24, ad_read(devc, 24) & ~alt_stat); /* Selective ack */
2257 }
2258
2259 if ((devc->open_mode & OPEN_READ) && (devc->audio_mode & PCM_ENABLE_INPUT) && (alt_stat & 0x20))
2260 {
2261 DMAbuf_inputintr(devc->record_dev);
2262 }
2263 if ((devc->open_mode & OPEN_WRITE) && (devc->audio_mode & PCM_ENABLE_OUTPUT) &&
2264 (alt_stat & 0x10))
2265 {
2266 DMAbuf_outputintr(devc->playback_dev, 1);
2267 }
2268 if (devc->model != MD_1848 && (alt_stat & 0x40)) /* Timer interrupt */
2269 {
2270 devc->timer_ticks++;
2271 #ifndef EXCLUDE_TIMERS
2272 if (timer_installed == dev && devc->timer_running)
2273 sound_timer_interrupt();
2274 #endif
2275 }
2276 }
2277 /*
2278 * Sometimes playback or capture interrupts occur while a timer interrupt
2279 * is being handled. The interrupt will not be retriggered if we don't
2280 * handle it now. Check if an interrupt is still pending and restart
2281 * the handler in this case.
2282 */
2283 if (inb(io_Status(devc)) & 0x01 && cnt++ < 4)
2284 {
2285 goto interrupt_again;
2286 }
2287 }
2288
2289 /*
2290 * Experimental initialization sequence for the integrated sound system
2291 * of the Compaq Deskpro M.
2292 */
2293
2294 static int init_deskpro_m(struct address_info *hw_config)
2295 {
2296 unsigned char tmp;
2297
2298 if ((tmp = inb(0xc44)) == 0xff)
2299 {
2300 DDB(printk("init_deskpro_m: Dead port 0xc44\n"));
2301 return 0;
2302 }
2303
2304 outb(0x10, 0xc44);
2305 outb(0x40, 0xc45);
2306 outb(0x00, 0xc46);
2307 outb(0xe8, 0xc47);
2308 outb(0x14, 0xc44);
2309 outb(0x40, 0xc45);
2310 outb(0x00, 0xc46);
2311 outb(0xe8, 0xc47);
2312 outb(0x10, 0xc44);
2313
2314 return 1;
2315 }
2316
2317 /*
2318 * Experimental initialization sequence for the integrated sound system
2319 * of Compaq Deskpro XL.
2320 */
2321
2322 static int init_deskpro(struct address_info *hw_config)
2323 {
2324 unsigned char tmp;
2325
2326 if ((tmp = inb(0xc44)) == 0xff)
2327 {
2328 DDB(printk("init_deskpro: Dead port 0xc44\n"));
2329 return 0;
2330 }
2331 outb((tmp | 0x04), 0xc44); /* Select bank 1 */
2332 if (inb(0xc44) != 0x04)
2333 {
2334 DDB(printk("init_deskpro: Invalid bank1 signature in port 0xc44\n"));
2335 return 0;
2336 }
2337 /*
2338 * OK. It looks like a Deskpro so let's proceed.
2339 */
2340
2341 /*
2342 * I/O port 0xc44 Audio configuration register.
2343 *
2344 * bits 0xc0: Audio revision bits
2345 * 0x00 = Compaq Business Audio
2346 * 0x40 = MS Sound System Compatible (reset default)
2347 * 0x80 = Reserved
2348 * 0xc0 = Reserved
2349 * bit 0x20: No Wait State Enable
2350 * 0x00 = Disabled (reset default, DMA mode)
2351 * 0x20 = Enabled (programmed I/O mode)
2352 * bit 0x10: MS Sound System Decode Enable
2353 * 0x00 = Decoding disabled (reset default)
2354 * 0x10 = Decoding enabled
2355 * bit 0x08: FM Synthesis Decode Enable
2356 * 0x00 = Decoding Disabled (reset default)
2357 * 0x08 = Decoding enabled
2358 * bit 0x04 Bank select
2359 * 0x00 = Bank 0
2360 * 0x04 = Bank 1
2361 * bits 0x03 MSS Base address
2362 * 0x00 = 0x530 (reset default)
2363 * 0x01 = 0x604
2364 * 0x02 = 0xf40
2365 * 0x03 = 0xe80
2366 */
2367
2368 #ifdef DEBUGXL
2369 /* Debug printing */
2370 printk("Port 0xc44 (before): ");
2371 outb((tmp & ~0x04), 0xc44);
2372 printk("%02x ", inb(0xc44));
2373 outb((tmp | 0x04), 0xc44);
2374 printk("%02x\n", inb(0xc44));
2375 #endif
2376
2377 /* Set bank 1 of the register */
2378 tmp = 0x58; /* MSS Mode, MSS&FM decode enabled */
2379
2380 switch (hw_config->io_base)
2381 {
2382 case 0x530:
2383 tmp |= 0x00;
2384 break;
2385 case 0x604:
2386 tmp |= 0x01;
2387 break;
2388 case 0xf40:
2389 tmp |= 0x02;
2390 break;
2391 case 0xe80:
2392 tmp |= 0x03;
2393 break;
2394 default:
2395 DDB(printk("init_deskpro: Invalid MSS port %x\n", hw_config->io_base));
2396 return 0;
2397 }
2398 outb((tmp & ~0x04), 0xc44); /* Write to bank=0 */
2399
2400 #ifdef DEBUGXL
2401 /* Debug printing */
2402 printk("Port 0xc44 (after): ");
2403 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2404 printk("%02x ", inb(0xc44));
2405 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2406 printk("%02x\n", inb(0xc44));
2407 #endif
2408
2409 /*
2410 * I/O port 0xc45 FM Address Decode/MSS ID Register.
2411 *
2412 * bank=0, bits 0xfe: FM synthesis Decode Compare bits 7:1 (default=0x88)
2413 * bank=0, bit 0x01: SBIC Power Control Bit
2414 * 0x00 = Powered up
2415 * 0x01 = Powered down
2416 * bank=1, bits 0xfc: MSS ID (default=0x40)
2417 */
2418
2419 #ifdef DEBUGXL
2420 /* Debug printing */
2421 printk("Port 0xc45 (before): ");
2422 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2423 printk("%02x ", inb(0xc45));
2424 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2425 printk("%02x\n", inb(0xc45));
2426 #endif
2427
2428 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2429 outb((0x88), 0xc45); /* FM base 7:0 = 0x88 */
2430 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2431 outb((0x10), 0xc45); /* MSS ID = 0x10 (MSS port returns 0x04) */
2432
2433 #ifdef DEBUGXL
2434 /* Debug printing */
2435 printk("Port 0xc45 (after): ");
2436 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2437 printk("%02x ", inb(0xc45));
2438 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2439 printk("%02x\n", inb(0xc45));
2440 #endif
2441
2442
2443 /*
2444 * I/O port 0xc46 FM Address Decode/Address ASIC Revision Register.
2445 *
2446 * bank=0, bits 0xff: FM synthesis Decode Compare bits 15:8 (default=0x03)
2447 * bank=1, bits 0xff: Audio addressing ASIC id
2448 */
2449
2450 #ifdef DEBUGXL
2451 /* Debug printing */
2452 printk("Port 0xc46 (before): ");
2453 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2454 printk("%02x ", inb(0xc46));
2455 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2456 printk("%02x\n", inb(0xc46));
2457 #endif
2458
2459 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2460 outb((0x03), 0xc46); /* FM base 15:8 = 0x03 */
2461 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2462 outb((0x11), 0xc46); /* ASIC ID = 0x11 */
2463
2464 #ifdef DEBUGXL
2465 /* Debug printing */
2466 printk("Port 0xc46 (after): ");
2467 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2468 printk("%02x ", inb(0xc46));
2469 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2470 printk("%02x\n", inb(0xc46));
2471 #endif
2472
2473 /*
2474 * I/O port 0xc47 FM Address Decode Register.
2475 *
2476 * bank=0, bits 0xff: Decode enable selection for various FM address bits
2477 * bank=1, bits 0xff: Reserved
2478 */
2479
2480 #ifdef DEBUGXL
2481 /* Debug printing */
2482 printk("Port 0xc47 (before): ");
2483 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2484 printk("%02x ", inb(0xc47));
2485 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2486 printk("%02x\n", inb(0xc47));
2487 #endif
2488
2489 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2490 outb((0x7c), 0xc47); /* FM decode enable bits = 0x7c */
2491 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2492 outb((0x00), 0xc47); /* Reserved bank1 = 0x00 */
2493
2494 #ifdef DEBUGXL
2495 /* Debug printing */
2496 printk("Port 0xc47 (after): ");
2497 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2498 printk("%02x ", inb(0xc47));
2499 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2500 printk("%02x\n", inb(0xc47));
2501 #endif
2502
2503 /*
2504 * I/O port 0xc6f = Audio Disable Function Register
2505 */
2506
2507 #ifdef DEBUGXL
2508 printk("Port 0xc6f (before) = %02x\n", inb(0xc6f));
2509 #endif
2510
2511 outb((0x80), 0xc6f);
2512
2513 #ifdef DEBUGXL
2514 printk("Port 0xc6f (after) = %02x\n", inb(0xc6f));
2515 #endif
2516
2517 return 1;
2518 }
2519
2520 int probe_ms_sound(struct address_info *hw_config)
2521 {
2522 unsigned char tmp;
2523
2524 DDB(printk("Entered probe_ms_sound(%x, %d)\n", hw_config->io_base, hw_config->card_subtype));
2525
2526 if (check_region(hw_config->io_base, 8))
2527 {
2528 printk(KERN_ERR "MSS: I/O port conflict\n");
2529 return 0;
2530 }
2531 if (hw_config->card_subtype == 1) /* Has no IRQ/DMA registers */
2532 {
2533 /* check_opl3(0x388, hw_config); */
2534 return ad1848_detect(hw_config->io_base + 4, NULL, hw_config->osp);
2535 }
2536
2537 if (deskpro_xl && hw_config->card_subtype == 2) /* Compaq Deskpro XL */
2538 {
2539 if (!init_deskpro(hw_config))
2540 return 0;
2541 }
2542
2543 if (deskpro_m) /* Compaq Deskpro M */
2544 {
2545 if (!init_deskpro_m(hw_config))
2546 return 0;
2547 }
2548
2549 /*
2550 * Check if the IO port returns valid signature. The original MS Sound
2551 * system returns 0x04 while some cards (AudioTrix Pro for example)
2552 * return 0x00 or 0x0f.
2553 */
2554
2555 if ((tmp = inb(hw_config->io_base + 3)) == 0xff) /* Bus float */
2556 {
2557 int ret;
2558
2559 DDB(printk("I/O address is inactive (%x)\n", tmp));
2560 if (!(ret = ad1848_detect(hw_config->io_base + 4, NULL, hw_config->osp)))
2561 return 0;
2562 return 1;
2563 }
2564 DDB(printk("MSS signature = %x\n", tmp & 0x3f));
2565 if ((tmp & 0x3f) != 0x04 &&
2566 (tmp & 0x3f) != 0x0f &&
2567 (tmp & 0x3f) != 0x00)
2568 {
2569 int ret;
2570
2571 MDB(printk(KERN_ERR "No MSS signature detected on port 0x%x (0x%x)\n", hw_config->io_base, (int) inb(hw_config->io_base + 3)));
2572 DDB(printk("Trying to detect codec anyway but IRQ/DMA may not work\n"));
2573 if (!(ret = ad1848_detect(hw_config->io_base + 4, NULL, hw_config->osp)))
2574 return 0;
2575
2576 hw_config->card_subtype = 1;
2577 return 1;
2578 }
2579 if ((hw_config->irq != 5) &&
2580 (hw_config->irq != 7) &&
2581 (hw_config->irq != 9) &&
2582 (hw_config->irq != 10) &&
2583 (hw_config->irq != 11) &&
2584 (hw_config->irq != 12))
2585 {
2586 printk(KERN_ERR "MSS: Bad IRQ %d\n", hw_config->irq);
2587 return 0;
2588 }
2589 if (hw_config->dma != 0 && hw_config->dma != 1 && hw_config->dma != 3)
2590 {
2591 printk(KERN_ERR "MSS: Bad DMA %d\n", hw_config->dma);
2592 return 0;
2593 }
2594 /*
2595 * Check that DMA0 is not in use with a 8 bit board.
2596 */
2597
2598 if (hw_config->dma == 0 && inb(hw_config->io_base + 3) & 0x80)
2599 {
2600 printk(KERN_ERR "MSS: Can't use DMA0 with a 8 bit card/slot\n");
2601 return 0;
2602 }
2603 if (hw_config->irq > 7 && hw_config->irq != 9 && inb(hw_config->io_base + 3) & 0x80)
2604 {
2605 printk(KERN_ERR "MSS: Can't use IRQ%d with a 8 bit card/slot\n", hw_config->irq);
2606 return 0;
2607 }
2608 return ad1848_detect(hw_config->io_base + 4, NULL, hw_config->osp);
2609 }
2610
2611 void attach_ms_sound(struct address_info *hw_config, struct module *owner)
2612 {
2613 static signed char interrupt_bits[12] =
2614 {
2615 -1, -1, -1, -1, -1, 0x00, -1, 0x08, -1, 0x10, 0x18, 0x20
2616 };
2617 signed char bits;
2618 char dma2_bit = 0;
2619
2620 static char dma_bits[4] =
2621 {
2622 1, 2, 0, 3
2623 };
2624
2625 int config_port = hw_config->io_base + 0;
2626 int version_port = hw_config->io_base + 3;
2627 int dma = hw_config->dma;
2628 int dma2 = hw_config->dma2;
2629
2630 if (hw_config->card_subtype == 1) /* Has no IRQ/DMA registers */
2631 {
2632 hw_config->slots[0] = ad1848_init("MS Sound System", hw_config->io_base + 4,
2633 hw_config->irq,
2634 hw_config->dma,
2635 hw_config->dma2, 0,
2636 hw_config->osp,
2637 owner);
2638 request_region(hw_config->io_base, 4, "WSS config");
2639 return;
2640 }
2641 /*
2642 * Set the IRQ and DMA addresses.
2643 */
2644
2645 bits = interrupt_bits[hw_config->irq];
2646 if (bits == -1)
2647 {
2648 printk(KERN_ERR "MSS: Bad IRQ %d\n", hw_config->irq);
2649 return;
2650 }
2651 outb((bits | 0x40), config_port);
2652 if ((inb(version_port) & 0x40) == 0)
2653 printk(KERN_ERR "[MSS: IRQ Conflict?]\n");
2654
2655 /*
2656 * Handle the capture DMA channel
2657 */
2658
2659 if (dma2 != -1 && dma2 != dma)
2660 {
2661 if (!((dma == 0 && dma2 == 1) ||
2662 (dma == 1 && dma2 == 0) ||
2663 (dma == 3 && dma2 == 0)))
2664 { /* Unsupported combination. Try to swap channels */
2665 int tmp = dma;
2666
2667 dma = dma2;
2668 dma2 = tmp;
2669 }
2670 if ((dma == 0 && dma2 == 1) ||
2671 (dma == 1 && dma2 == 0) ||
2672 (dma == 3 && dma2 == 0))
2673 {
2674 dma2_bit = 0x04; /* Enable capture DMA */
2675 }
2676 else
2677 {
2678 printk(KERN_WARNING "MSS: Invalid capture DMA\n");
2679 dma2 = dma;
2680 }
2681 }
2682 else
2683 {
2684 dma2 = dma;
2685 }
2686
2687 hw_config->dma = dma;
2688 hw_config->dma2 = dma2;
2689
2690 outb((bits | dma_bits[dma] | dma2_bit), config_port); /* Write IRQ+DMA setup */
2691
2692 hw_config->slots[0] = ad1848_init("MS Sound System", hw_config->io_base + 4,
2693 hw_config->irq,
2694 dma, dma2, 0,
2695 hw_config->osp,
2696 THIS_MODULE);
2697 request_region(hw_config->io_base, 4, "WSS config");
2698 }
2699
2700 void unload_ms_sound(struct address_info *hw_config)
2701 {
2702 ad1848_unload(hw_config->io_base + 4,
2703 hw_config->irq,
2704 hw_config->dma,
2705 hw_config->dma2, 0);
2706 sound_unload_audiodev(hw_config->slots[0]);
2707 release_region(hw_config->io_base, 4);
2708 }
2709
2710 #ifndef EXCLUDE_TIMERS
2711
2712 /*
2713 * Timer stuff (for /dev/music).
2714 */
2715
2716 static unsigned int current_interval = 0;
2717
2718 static unsigned int ad1848_tmr_start(int dev, unsigned int usecs)
2719 {
2720 unsigned long flags;
2721 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
2722 unsigned long xtal_nsecs; /* nanoseconds per xtal oscillator tick */
2723 unsigned long divider;
2724
2725 spin_lock_irqsave(&devc->lock,flags);
2726
2727 /*
2728 * Length of the timer interval (in nanoseconds) depends on the
2729 * selected crystal oscillator. Check this from bit 0x01 of I8.
2730 *
2731 * AD1845 has just one oscillator which has cycle time of 10.050 us
2732 * (when a 24.576 MHz xtal oscillator is used).
2733 *
2734 * Convert requested interval to nanoseconds before computing
2735 * the timer divider.
2736 */
2737
2738 if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE)
2739 xtal_nsecs = 10050;
2740 else if (ad_read(devc, 8) & 0x01)
2741 xtal_nsecs = 9920;
2742 else
2743 xtal_nsecs = 9969;
2744
2745 divider = (usecs * 1000 + xtal_nsecs / 2) / xtal_nsecs;
2746
2747 if (divider < 100) /* Don't allow shorter intervals than about 1ms */
2748 divider = 100;
2749
2750 if (divider > 65535) /* Overflow check */
2751 divider = 65535;
2752
2753 ad_write(devc, 21, (divider >> 8) & 0xff); /* Set upper bits */
2754 ad_write(devc, 20, divider & 0xff); /* Set lower bits */
2755 ad_write(devc, 16, ad_read(devc, 16) | 0x40); /* Start the timer */
2756 devc->timer_running = 1;
2757 spin_unlock_irqrestore(&devc->lock,flags);
2758
2759 return current_interval = (divider * xtal_nsecs + 500) / 1000;
2760 }
2761
2762 static void ad1848_tmr_reprogram(int dev)
2763 {
2764 /*
2765 * Audio driver has changed sampling rate so that a different xtal
2766 * oscillator was selected. We have to reprogram the timer rate.
2767 */
2768
2769 ad1848_tmr_start(dev, current_interval);
2770 sound_timer_syncinterval(current_interval);
2771 }
2772
2773 static void ad1848_tmr_disable(int dev)
2774 {
2775 unsigned long flags;
2776 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
2777
2778 spin_lock_irqsave(&devc->lock,flags);
2779 ad_write(devc, 16, ad_read(devc, 16) & ~0x40);
2780 devc->timer_running = 0;
2781 spin_unlock_irqrestore(&devc->lock,flags);
2782 }
2783
2784 static void ad1848_tmr_restart(int dev)
2785 {
2786 unsigned long flags;
2787 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
2788
2789 if (current_interval == 0)
2790 return;
2791
2792 spin_lock_irqsave(&devc->lock,flags);
2793 ad_write(devc, 16, ad_read(devc, 16) | 0x40);
2794 devc->timer_running = 1;
2795 spin_unlock_irqrestore(&devc->lock,flags);
2796 }
2797
2798 static struct sound_lowlev_timer ad1848_tmr =
2799 {
2800 0,
2801 2,
2802 ad1848_tmr_start,
2803 ad1848_tmr_disable,
2804 ad1848_tmr_restart
2805 };
2806
2807 static int ad1848_tmr_install(int dev)
2808 {
2809 if (timer_installed != -1)
2810 return 0; /* Don't install another timer */
2811
2812 timer_installed = ad1848_tmr.dev = dev;
2813 sound_timer_init(&ad1848_tmr, audio_devs[dev]->name);
2814
2815 return 1;
2816 }
2817 #endif /* EXCLUDE_TIMERS */
2818
2819 static int ad1848_suspend(ad1848_info *devc)
2820 {
2821 unsigned long flags;
2822
2823 spin_lock_irqsave(&devc->lock,flags);
2824
2825 ad_mute(devc);
2826
2827 spin_unlock_irqrestore(&devc->lock,flags);
2828 return 0;
2829 }
2830
2831 static int ad1848_resume(ad1848_info *devc)
2832 {
2833 unsigned long flags;
2834 int mixer_levels[32], i;
2835
2836 spin_lock_irqsave(&devc->lock,flags);
2837
2838 /* Thinkpad is a bit more of PITA than normal. The BIOS tends to
2839 restore it in a different config to the one we use. Need to
2840 fix this somehow */
2841
2842 /* store old mixer levels */
2843 memcpy(mixer_levels, devc->levels, sizeof (mixer_levels));
2844 ad1848_init_hw(devc);
2845
2846 /* restore mixer levels */
2847 for (i = 0; i < 32; i++)
2848 ad1848_mixer_set(devc, devc->dev_no, mixer_levels[i]);
2849
2850 if (!devc->subtype) {
2851 static signed char interrupt_bits[12] = { -1, -1, -1, -1, -1, 0x00, -1, 0x08, -1, 0x10, 0x18, 0x20 };
2852 static char dma_bits[4] = { 1, 2, 0, 3 };
2853
2854 signed char bits;
2855 char dma2_bit = 0;
2856
2857 int config_port = devc->base + 0;
2858
2859 bits = interrupt_bits[devc->irq];
2860 if (bits == -1) {
2861 printk(KERN_ERR "MSS: Bad IRQ %d\n", devc->irq);
2862 spin_unlock_irqrestore(&devc->lock,flags);
2863 return -1;
2864 }
2865
2866 outb((bits | 0x40), config_port);
2867
2868 if (devc->dma2 != -1 && devc->dma2 != devc->dma1)
2869 if ( (devc->dma1 == 0 && devc->dma2 == 1) ||
2870 (devc->dma1 == 1 && devc->dma2 == 0) ||
2871 (devc->dma1 == 3 && devc->dma2 == 0))
2872 dma2_bit = 0x04;
2873
2874 outb((bits | dma_bits[devc->dma1] | dma2_bit), config_port);
2875 }
2876
2877 spin_unlock_irqrestore(&devc->lock,flags);
2878 return 0;
2879 }
2880
2881 static int ad1848_pm_callback(struct pm_dev *dev, pm_request_t rqst, void *data)
2882 {
2883 ad1848_info *devc = dev->data;
2884 if (devc) {
2885 DEB(printk("ad1848: pm event received: 0x%x\n", rqst));
2886
2887 switch (rqst) {
2888 case PM_SUSPEND:
2889 ad1848_suspend(devc);
2890 break;
2891 case PM_RESUME:
2892 ad1848_resume(devc);
2893 break;
2894 }
2895 }
2896 return 0;
2897 }
2898
2899
2900 EXPORT_SYMBOL(ad1848_detect);
2901 EXPORT_SYMBOL(ad1848_init);
2902 EXPORT_SYMBOL(ad1848_unload);
2903 EXPORT_SYMBOL(ad1848_control);
2904 EXPORT_SYMBOL(adintr);
2905 EXPORT_SYMBOL(probe_ms_sound);
2906 EXPORT_SYMBOL(attach_ms_sound);
2907 EXPORT_SYMBOL(unload_ms_sound);
2908
2909 static int __initdata io = -1;
2910 static int __initdata irq = -1;
2911 static int __initdata dma = -1;
2912 static int __initdata dma2 = -1;
2913 static int __initdata type = 0;
2914
2915 MODULE_PARM(io, "i"); /* I/O for a raw AD1848 card */
2916 MODULE_PARM(irq, "i"); /* IRQ to use */
2917 MODULE_PARM(dma, "i"); /* First DMA channel */
2918 MODULE_PARM(dma2, "i"); /* Second DMA channel */
2919 MODULE_PARM(type, "i"); /* Card type */
2920 MODULE_PARM(deskpro_xl, "i"); /* Special magic for Deskpro XL boxen */
2921 MODULE_PARM(deskpro_m, "i"); /* Special magic for Deskpro M box */
2922 MODULE_PARM(soundpro, "i"); /* More special magic for SoundPro chips */
2923
2924 #ifdef CONFIG_PNP
2925 MODULE_PARM(isapnp, "i");
2926 MODULE_PARM(isapnpjump, "i");
2927 MODULE_PARM(reverse, "i");
2928 MODULE_PARM_DESC(isapnp, "When set to 0, Plug & Play support will be disabled");
2929 MODULE_PARM_DESC(isapnpjump, "Jumps to a specific slot in the driver's PnP table. Use the source, Luke.");
2930 MODULE_PARM_DESC(reverse, "When set to 1, will reverse ISAPnP search order");
2931
2932 struct pnp_dev *ad1848_dev = NULL;
2933
2934 /* Please add new entries at the end of the table */
2935 static struct {
2936 char *name;
2937 unsigned short card_vendor, card_device,
2938 vendor, function;
2939 short mss_io, irq, dma, dma2; /* index into isapnp table */
2940 int type;
2941 } ad1848_isapnp_list[] __initdata = {
2942 {"CMI 8330 SoundPRO",
2943 ISAPNP_VENDOR('C','M','I'), ISAPNP_DEVICE(0x0001),
2944 ISAPNP_VENDOR('@','@','@'), ISAPNP_FUNCTION(0x0001),
2945 0, 0, 0,-1, 0},
2946 {"CS4232 based card",
2947 ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2948 ISAPNP_VENDOR('C','S','C'), ISAPNP_FUNCTION(0x0000),
2949 0, 0, 0, 1, 0},
2950 {"CS4232 based card",
2951 ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2952 ISAPNP_VENDOR('C','S','C'), ISAPNP_FUNCTION(0x0100),
2953 0, 0, 0, 1, 0},
2954 {"OPL3-SA2 WSS mode",
2955 ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2956 ISAPNP_VENDOR('Y','M','H'), ISAPNP_FUNCTION(0x0021),
2957 1, 0, 0, 1, 1},
2958 {"Advanced Gravis InterWave Audio",
2959 ISAPNP_VENDOR('G','R','V'), ISAPNP_DEVICE(0x0001),
2960 ISAPNP_VENDOR('G','R','V'), ISAPNP_FUNCTION(0x0000),
2961 0, 0, 0, 1, 0},
2962 {0}
2963 };
2964
2965 static struct isapnp_device_id id_table[] __devinitdata = {
2966 { ISAPNP_VENDOR('C','M','I'), ISAPNP_DEVICE(0x0001),
2967 ISAPNP_VENDOR('@','@','@'), ISAPNP_FUNCTION(0x0001), 0 },
2968 { ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2969 ISAPNP_VENDOR('C','S','C'), ISAPNP_FUNCTION(0x0000), 0 },
2970 { ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2971 ISAPNP_VENDOR('C','S','C'), ISAPNP_FUNCTION(0x0100), 0 },
2972 { ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2973 ISAPNP_VENDOR('Y','M','H'), ISAPNP_FUNCTION(0x0021), 0 },
2974 { ISAPNP_VENDOR('G','R','V'), ISAPNP_DEVICE(0x0001),
2975 ISAPNP_VENDOR('G','R','V'), ISAPNP_FUNCTION(0x0000), 0 },
2976 {0}
2977 };
2978
2979 MODULE_DEVICE_TABLE(isapnp, id_table);
2980
2981 static struct pnp_dev *activate_dev(char *devname, char *resname, struct pnp_dev *dev)
2982 {
2983 int err;
2984
2985 /* Device already active? Let's use it */
2986 if(dev->active)
2987 return(dev);
2988
2989 if((err = pnp_activate_dev(dev)) < 0) {
2990 printk(KERN_ERR "ad1848: %s %s config failed (out of resources?)[%d]\n", devname, resname, err);
2991
2992 pnp_disable_dev(dev);
2993
2994 return(NULL);
2995 }
2996 audio_activated = 1;
2997 return(dev);
2998 }
2999
3000 static struct pnp_dev *ad1848_init_generic(struct pnp_card *bus, struct address_info *hw_config, int slot)
3001 {
3002
3003 /* Configure Audio device */
3004 if((ad1848_dev = pnp_find_dev(bus, ad1848_isapnp_list[slot].vendor, ad1848_isapnp_list[slot].function, NULL)))
3005 {
3006 if((ad1848_dev = activate_dev(ad1848_isapnp_list[slot].name, "ad1848", ad1848_dev)))
3007 {
3008 get_device(&ad1848_dev->dev);
3009 hw_config->io_base = ad1848_dev->resource[ad1848_isapnp_list[slot].mss_io].start;
3010 hw_config->irq = ad1848_dev->irq_resource[ad1848_isapnp_list[slot].irq].start;
3011 hw_config->dma = ad1848_dev->dma_resource[ad1848_isapnp_list[slot].dma].start;
3012 if(ad1848_isapnp_list[slot].dma2 != -1)
3013 hw_config->dma2 = ad1848_dev->dma_resource[ad1848_isapnp_list[slot].dma2].start;
3014 else
3015 hw_config->dma2 = -1;
3016 hw_config->card_subtype = ad1848_isapnp_list[slot].type;
3017 } else
3018 return(NULL);
3019 } else
3020 return(NULL);
3021
3022 return(ad1848_dev);
3023 }
3024
3025 static int __init ad1848_isapnp_init(struct address_info *hw_config, struct pnp_card *bus, int slot)
3026 {
3027 char *busname = bus->name[0] ? bus->name : ad1848_isapnp_list[slot].name;
3028
3029 /* Initialize this baby. */
3030
3031 if(ad1848_init_generic(bus, hw_config, slot)) {
3032 /* We got it. */
3033
3034 printk(KERN_NOTICE "ad1848: ISAPnP reports '%s' at i/o %#x, irq %d, dma %d, %d\n",
3035 busname,
3036 hw_config->io_base, hw_config->irq, hw_config->dma,
3037 hw_config->dma2);
3038 return 1;
3039 }
3040 return 0;
3041 }
3042
3043 static int __init ad1848_isapnp_probe(struct address_info *hw_config)
3044 {
3045 static int first = 1;
3046 int i;
3047
3048 /* Count entries in sb_isapnp_list */
3049 for (i = 0; ad1848_isapnp_list[i].card_vendor != 0; i++);
3050 i--;
3051
3052 /* Check and adjust isapnpjump */
3053 if( isapnpjump < 0 || isapnpjump > i) {
3054 isapnpjump = reverse ? i : 0;
3055 printk(KERN_ERR "ad1848: Valid range for isapnpjump is 0-%d. Adjusted to %d.\n", i, isapnpjump);
3056 }
3057
3058 if(!first || !reverse)
3059 i = isapnpjump;
3060 first = 0;
3061 while(ad1848_isapnp_list[i].card_vendor != 0) {
3062 static struct pnp_card *bus = NULL;
3063
3064 while ((bus = pnp_find_card(
3065 ad1848_isapnp_list[i].card_vendor,
3066 ad1848_isapnp_list[i].card_device,
3067 bus))) {
3068
3069 if(ad1848_isapnp_init(hw_config, bus, i)) {
3070 isapnpjump = i; /* start next search from here */
3071 return 0;
3072 }
3073 }
3074 i += reverse ? -1 : 1;
3075 }
3076
3077 return -ENODEV;
3078 }
3079 #endif
3080
3081
3082 static int __init init_ad1848(void)
3083 {
3084 printk(KERN_INFO "ad1848/cs4248 codec driver Copyright (C) by Hannu Savolainen 1993-1996\n");
3085
3086 #ifdef CONFIG_PNP
3087 if(isapnp && (ad1848_isapnp_probe(&cfg) < 0) ) {
3088 printk(KERN_NOTICE "ad1848: No ISAPnP cards found, trying standard ones...\n");
3089 isapnp = 0;
3090 }
3091 #endif
3092
3093 if(io != -1) {
3094 if( isapnp == 0 )
3095 {
3096 if(irq == -1 || dma == -1) {
3097 printk(KERN_WARNING "ad1848: must give I/O , IRQ and DMA.\n");
3098 return -EINVAL;
3099 }
3100
3101 cfg.irq = irq;
3102 cfg.io_base = io;
3103 cfg.dma = dma;
3104 cfg.dma2 = dma2;
3105 cfg.card_subtype = type;
3106 }
3107
3108 if(!probe_ms_sound(&cfg))
3109 return -ENODEV;
3110 attach_ms_sound(&cfg, THIS_MODULE);
3111 loaded = 1;
3112 }
3113 return 0;
3114 }
3115
3116 static void __exit cleanup_ad1848(void)
3117 {
3118 if(loaded)
3119 unload_ms_sound(&cfg);
3120
3121 #ifdef CONFIG_PNP
3122 if(ad1848_dev){
3123 if(audio_activated)
3124 pnp_disable_dev(ad1848_dev);
3125 put_device(&ad1848_dev->dev);
3126 }
3127 #endif
3128 }
3129
3130 module_init(init_ad1848);
3131 module_exit(cleanup_ad1848);
3132
3133 #ifndef MODULE
3134 static int __init setup_ad1848(char *str)
3135 {
3136 /* io, irq, dma, dma2, type */
3137 int ints[6];
3138
3139 str = get_options(str, ARRAY_SIZE(ints), ints);
3140
3141 io = ints[1];
3142 irq = ints[2];
3143 dma = ints[3];
3144 dma2 = ints[4];
3145 type = ints[5];
3146
3147 return 1;
3148 }
3149
3150 __setup("ad1848=", setup_ad1848);
3151 #endif
3152 MODULE_LICENSE("GPL");
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