drivers/sound/nm256.h

   1 #ifndef _NM256_H_
   2 #define _NM256_H_
   3
   4 #include "ac97.h"
   5
   6 /* The revisions that we currently handle.  */
   7 enum nm256rev {
   8     REV_NM256AV, REV_NM256ZX
   9 };
  10
  11 /* Per-card structure. */
  12 struct nm256_info
  13 {
  14     /* Magic number used to verify that this struct is valid. */
  15 #define NM_MAGIC_SIG 0x55aa00ff
  16     int magsig;
  17
  18     /* Revision number */
  19     enum nm256rev rev;
  20
  21     struct ac97_hwint mdev;
  22
  23     /* Our audio device numbers. */
  24     int dev[2];
  25
  26     /* The # of times each device has been opened. (Should only be
  27        0 or 1). */
  28     int opencnt[2];
  29
  30     /* We use two devices, because we can do simultaneous play and record.
  31        This keeps track of which device is being used for what purpose;
  32        these are the actual device numbers. */
  33     int dev_for_play;
  34     int dev_for_record;
  35
  36     /* The mixer device. */
  37     int mixer_oss_dev;
  38
  39     /*
  40      * Can only be opened once for each operation.  These aren't set
  41      * until an actual I/O operation is performed; this allows one
  42      * device to be open for read/write without inhibiting I/O to
  43      * the other device.
  44      */
  45     int is_open_play;
  46     int is_open_record;
  47
  48     /* Non-zero if we're currently playing a sample. */
  49     int playing;
  50     /* Ditto for recording a sample. */
  51     int recording;
  52
  53     /* The two memory ports.  */
  54     struct nm256_ports {
  55         /* Physical address of the port. */
  56         u32 physaddr;
  57         /* Our mapped-in pointer. */
  58         char *ptr;
  59         /* PTR's offset within the physical port.  */
  60         u32 start_offset;
  61         /* And the offset of the end of the buffer.  */
  62         u32 end_offset;
  63     } port[2];
  64
  65     /* The following are offsets within memory port 1. */
  66     u32 coeffBuf;
  67     u32 allCoeffBuf;
  68
  69     /* Record and playback buffers. */
  70     u32 abuf1, abuf2;
  71
  72     /* Offset of the AC97 mixer in memory port 2. */
  73     u32 mixer;
  74
  75     /* Offset of the mixer status register in memory port 2.  */
  76     u32 mixer_status_offset;
  77
  78     /* Non-zero if we have written initial values to the mixer. */
  79     u8 mixer_values_init;
  80
  81     /*
  82      * Status mask bit; (*mixer_status_loc & mixer_status_mask) == 0 means
  83      * it's ready.
  84      */
  85     u16 mixer_status_mask;
  86
  87     /* The sizes of the playback and record ring buffers. */
  88     u32 playbackBufferSize;
  89     u32 recordBufferSize;
  90
  91     /* Are the coefficient values in the memory cache current? */
  92     u8 coeffsCurrent;
  93
  94     /* For writes, the amount we last wrote. */
  95     u32 requested_amt;
  96     /* The start of the block currently playing. */
  97     u32 curPlayPos;
  98
  99     /* The amount of data we were requested to record. */
 100     u32 requestedRecAmt;
 101     /* The offset of the currently-recording block. */
 102     u32 curRecPos;
 103     /* The destination buffer. */
 104     char *recBuf;
 105
 106     /* Our IRQ number. */
 107     int irq;
 108
 109     /* A flag indicating how many times we've grabbed the IRQ. */
 110     int has_irq;
 111
 112     /* The card interrupt service routine. */
 113     void (*introutine) (int, void *, struct pt_regs *);
 114
 115     /* Current audio config, cached. */
 116     struct sinfo {
 117         u32 samplerate;
 118         u8 bits;
 119         u8 stereo;
 120     } sinfo[2]; /* goes with each device */
 121
 122     /* The cards are stored in a chain;  this is the next card. */
 123     struct nm256_info *next_card;
 124 };
 125
 126 /* Debug flag--bigger numbers mean more output. */
 127 extern int nm256_debug;
 128
 129 /* The BIOS signature. */
 130 #define NM_SIGNATURE 0x4e4d0000
 131 /* Signature mask. */
 132 #define NM_SIG_MASK 0xffff0000
 133
 134 /* Size of the second memory area. */
 135 #define NM_PORT2_SIZE 4096
 136
 137 /* The base offset of the mixer in the second memory area. */
 138 #define NM_MIXER_OFFSET 0x600
 139
 140 /* The maximum size of a coefficient entry. */
 141 #define NM_MAX_COEFFICIENT 0x5000
 142
 143 /* The interrupt register. */
 144 #define NM_INT_REG 0xa04
 145 /* And its bits. */
 146 #define NM_PLAYBACK_INT 0x40
 147 #define NM_RECORD_INT 0x100
 148 #define NM_MISC_INT_1 0x4000
 149 #define NM_MISC_INT_2 0x1
 150 #define NM_ACK_INT(CARD, X) nm256_writePort16((CARD), 2, NM_INT_REG, (X) << 1)
 151
 152 /* The AV's "mixer ready" status bit and location. */
 153 #define NM_MIXER_STATUS_OFFSET 0xa04
 154 #define NM_MIXER_READY_MASK 0x0800
 155 #define NM_MIXER_PRESENCE 0xa06
 156 #define NM_PRESENCE_MASK 0x0050
 157 #define NM_PRESENCE_VALUE 0x0040
 158
 159 /*
 160  * For the ZX.  It uses the same interrupt register, but it holds 32
 161  * bits instead of 16.
 162  */
 163 #define NM2_PLAYBACK_INT 0x10000
 164 #define NM2_RECORD_INT 0x80000
 165 #define NM2_MISC_INT_1 0x8
 166 #define NM2_MISC_INT_2 0x2
 167 #define NM2_ACK_INT(CARD, X) nm256_writePort32((CARD), 2, NM_INT_REG, (X))
 168
 169 /* The ZX's "mixer ready" status bit and location. */
 170 #define NM2_MIXER_STATUS_OFFSET 0xa06
 171 #define NM2_MIXER_READY_MASK 0x0800
 172
 173 /* The playback registers start from here. */
 174 #define NM_PLAYBACK_REG_OFFSET 0x0
 175 /* The record registers start from here. */
 176 #define NM_RECORD_REG_OFFSET 0x200
 177
 178 /* The rate register is located 2 bytes from the start of the register area. */
 179 #define NM_RATE_REG_OFFSET 2
 180
 181 /* Mono/stereo flag, number of bits on playback, and rate mask. */
 182 #define NM_RATE_STEREO 1
 183 #define NM_RATE_BITS_16 2
 184 #define NM_RATE_MASK 0xf0
 185
 186 /* Playback enable register. */
 187 #define NM_PLAYBACK_ENABLE_REG (NM_PLAYBACK_REG_OFFSET + 0x1)
 188 #define NM_PLAYBACK_ENABLE_FLAG 1
 189 #define NM_PLAYBACK_ONESHOT 2
 190 #define NM_PLAYBACK_FREERUN 4
 191
 192 /* Mutes the audio output. */
 193 #define NM_AUDIO_MUTE_REG (NM_PLAYBACK_REG_OFFSET + 0x18)
 194 #define NM_AUDIO_MUTE_LEFT 0x8000
 195 #define NM_AUDIO_MUTE_RIGHT 0x0080
 196
 197 /* Recording enable register. */
 198 #define NM_RECORD_ENABLE_REG (NM_RECORD_REG_OFFSET + 0)
 199 #define NM_RECORD_ENABLE_FLAG 1
 200 #define NM_RECORD_FREERUN 2
 201
 202 #define NM_RBUFFER_START (NM_RECORD_REG_OFFSET + 0x4)
 203 #define NM_RBUFFER_END   (NM_RECORD_REG_OFFSET + 0x10)
 204 #define NM_RBUFFER_WMARK (NM_RECORD_REG_OFFSET + 0xc)
 205 #define NM_RBUFFER_CURRP (NM_RECORD_REG_OFFSET + 0x8)
 206
 207 #define NM_PBUFFER_START (NM_PLAYBACK_REG_OFFSET + 0x4)
 208 #define NM_PBUFFER_END   (NM_PLAYBACK_REG_OFFSET + 0x14)
 209 #define NM_PBUFFER_WMARK (NM_PLAYBACK_REG_OFFSET + 0xc)
 210 #define NM_PBUFFER_CURRP (NM_PLAYBACK_REG_OFFSET + 0x8)
 211
 212 /* A few trivial routines to make it easier to work with the registers
 213    on the chip. */
 214
 215 /* This is a common code portion used to fix up the port offsets. */
 216 #define NM_FIX_PORT \
 217   if (port < 1 || port > 2 || card == NULL) \
 218       return -1; \
 219 \
 220     if (offset < card->port[port - 1].start_offset \
 221         || offset >= card->port[port - 1].end_offset) { \
 222         printk (KERN_ERR "Bad access: port %d, offset 0x%x\n", port, offset); \
 223         return -1; \
 224     } \
 225     offset -= card->port[port - 1].start_offset;
 226
 227 #define DEFwritePortX(X, func) \
 228 static inline int nm256_writePort##X (struct nm256_info *card,\
 229                                       int port, int offset, int value)\
 230 {\
 231     u##X *addr;\
 232 \
 233     if (nm256_debug > 1)\
 234         printk (KERN_DEBUG "Writing 0x%x to %d:0x%x\n", value, port, offset);\
 235 \
 236     NM_FIX_PORT;\
 237 \
 238     addr = (u##X *)(card->port[port - 1].ptr + offset);\
 239     func (value, addr);\
 240     return 0;\
 241 }
 242
 243 DEFwritePortX (8, writeb)
 244 DEFwritePortX (16, writew)
 245 DEFwritePortX (32, writel)
 246
 247 #define DEFreadPortX(X, func) \
 248 static inline u##X nm256_readPort##X (struct nm256_info *card,\
 249                                         int port, int offset)\
 250 {\
 251     u##X *addr;\
 252 \
 253     NM_FIX_PORT\
 254 \
 255     addr = (u##X *)(card->port[port - 1].ptr + offset);\
 256     return func(addr);\
 257 }
 258
 259 DEFreadPortX (8, readb)
 260 DEFreadPortX (16, readw)
 261 DEFreadPortX (32, readl)
 262
 263 static inline int
 264 nm256_writeBuffer8 (struct nm256_info *card, u8 *src, int port, int offset,
 265                       int amt)
 266 {
 267     NM_FIX_PORT;
 268     memcpy_toio (card->port[port - 1].ptr + offset, src, amt);
 269     return 0;
 270 }
 271
 272 static inline int
 273 nm256_readBuffer8 (struct nm256_info *card, u8 *dst, int port, int offset,
 274                      int amt)
 275 {
 276     NM_FIX_PORT;
 277     memcpy_fromio (dst, card->port[port - 1].ptr + offset, amt);
 278     return 0;
 279 }
 280
 281 /* Returns a non-zero value if we should use the coefficient cache. */
 282 extern int nm256_cachedCoefficients (struct nm256_info *card);
 283
 284 #endif
 285 \f
 286 /*
 287  * Local variables:
 288  * c-basic-offset: 4
 289  * End:
 290  */