include/asm-mips64/processor.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994 Waldorf GMBH
   7  * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
   8  * Copyright (C) 1996 Paul M. Antoine
   9  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
  10  */
  11 #ifndef _ASM_PROCESSOR_H
  12 #define _ASM_PROCESSOR_H
  13
  14 #include <linux/config.h>
  15
  16 /*
  17  * Return current * instruction pointer ("program counter").
  18  */
  19 #define current_text_addr()                                             \
  20 ({                                                                      \
  21         void *_a;                                                       \
  22                                                                         \
  23         __asm__ ("bal\t1f\t\t\t# current_text_addr\n"                   \
  24                 "1:\tmove\t%0, $31"                                     \
  25                 : "=r" (_a)                                             \
  26                 :                                                       \
  27                 : "$31");                                               \
  28                                                                         \
  29         _a;                                                             \
  30 })
  31
  32 #ifndef __ASSEMBLY__
  33 #include <linux/cache.h>
  34 #include <linux/threads.h>
  35
  36 #include <asm/cachectl.h>
  37 #include <asm/mipsregs.h>
  38 #include <asm/reg.h>
  39 #include <asm/system.h>
  40
  41 #if defined(CONFIG_SGI_IP27)
  42 #include <asm/sn/types.h>
  43 #include <asm/sn/intr_public.h>
  44 #endif
  45
  46 /*
  47  * Descriptor for a cache
  48  */
  49 struct cache_desc {
  50         unsigned short linesz;  /* Size of line in bytes */
  51         unsigned short ways;    /* Number of ways */
  52         unsigned int sets;      /* Number of lines per set */
  53         unsigned int waysize;   /* Bytes per way */
  54         unsigned int waybit;    /* Bits to select in a cache set */
  55         unsigned int flags;     /* Flags describing cache properties */
  56 };
  57
  58 /*
  59  * Flag definitions
  60  */
  61 #define MIPS_CACHE_NOT_PRESENT  0x00000001
  62 #define MIPS_CACHE_VTAG         0x00000002      /* Virtually tagged cache */
  63 #define MIPS_CACHE_ALIASES      0x00000004      /* Cache could have aliases */
  64 #define MIPS_CACHE_IC_F_DC      0x00000008      /* Ic can refill from D-cache */
  65
  66 struct cpuinfo_mips {
  67         unsigned long   udelay_val;
  68         unsigned long   asid_cache;
  69 #if defined(CONFIG_SGI_IP27)
  70         cpuid_t         p_cpuid;        /* PROM assigned cpuid */
  71         cnodeid_t       p_nodeid;       /* my node ID in compact-id-space */
  72         nasid_t         p_nasid;        /* my node ID in numa-as-id-space */
  73         unsigned char   p_slice;        /* Physical position on node board */
  74         hub_intmasks_t  p_intmasks;     /* SN0 per-CPU interrupt masks */
  75 #endif
  76 #if 0
  77         unsigned long loops_per_sec;
  78         unsigned long ipi_count;
  79         unsigned long irq_attempt[NR_IRQS];
  80         unsigned long smp_local_irq_count;
  81         unsigned long prof_multiplier;
  82         unsigned long prof_counter;
  83 #endif
  84
  85         /*
  86          * Capability and feature descriptor structure for MIPS CPU
  87          */
  88         unsigned long options;
  89         unsigned int processor_id;
  90         unsigned int fpu_id;
  91         unsigned int cputype;
  92         int isa_level;
  93         int tlbsize;
  94         struct cache_desc icache;       /* Primary I-cache */
  95         struct cache_desc dcache;       /* Primary D or combined I/D cache */
  96         struct cache_desc scache;       /* Secondary cache */
  97         struct cache_desc tcache;       /* Tertiary/split secondary cache */
  98 } __attribute__((aligned(SMP_CACHE_BYTES)));
  99
 100 /*
 101  * Assumption: Options of CPU 0 are a superset of all processors.
 102  * This is true for all known MIPS systems.
 103  */
 104 #define cpu_has_tlb             (cpu_data[0].options & MIPS_CPU_TLB)
 105 #define cpu_has_4kex            (cpu_data[0].options & MIPS_CPU_4KEX)
 106 #define cpu_has_4ktlb           (cpu_data[0].options & MIPS_CPU_4KTLB)
 107 #define cpu_has_fpu             (cpu_data[0].options & MIPS_CPU_FPU)
 108 #define cpu_has_32fpr           (cpu_data[0].options & MIPS_CPU_32FPR)
 109 #define cpu_has_counter         (cpu_data[0].options & MIPS_CPU_COUNTER)
 110 #define cpu_has_watch           (cpu_data[0].options & MIPS_CPU_WATCH)
 111 #define cpu_has_mips16          (cpu_data[0].options & MIPS_CPU_MIPS16)
 112 #define cpu_has_divec           (cpu_data[0].options & MIPS_CPU_DIVEC)
 113 #define cpu_has_vce             (cpu_data[0].options & MIPS_CPU_VCE)
 114 #define cpu_has_cache_cdex      (cpu_data[0].options & MIPS_CPU_CACHE_CDEX)
 115 #define cpu_has_mcheck          (cpu_data[0].options & MIPS_CPU_MCHECK)
 116 #define cpu_has_ejtag           (cpu_data[0].options & MIPS_CPU_EJTAG)
 117 #define cpu_has_nofpuex         (cpu_data[0].options & MIPS_CPU_NOFPUEX)
 118 #define cpu_has_llsc            (cpu_data[0].options & MIPS_CPU_LLSC)
 119 #define cpu_has_vtag_icache     (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
 120 #define cpu_has_dc_aliases      (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
 121 #define cpu_has_ic_fills_f_dc   (cpu_data[0].dcache.flags & MIPS_CACHE_IC_F_DC)
 122 #define cpu_has_64bits          1
 123 #define cpu_has_subset_pcaches  (cpu_data[0].options & MIPS_CPU_SUBSET_CACHES)
 124
 125 extern struct cpuinfo_mips cpu_data[];
 126 #define current_cpu_data cpu_data[smp_processor_id()]
 127
 128 extern void cpu_probe(void);
 129 extern void cpu_report(void);
 130
 131 /*
 132  * System setup and hardware flags..
 133  */
 134 extern void (*cpu_wait)(void);
 135
 136 extern unsigned int vced_count, vcei_count;
 137
 138 /*
 139  * Bus types (default is ISA, but people can check others with these..)
 140  */
 141 #ifdef CONFIG_EISA
 142 extern int EISA_bus;
 143 #else
 144 #define EISA_bus (0)
 145 #endif
 146
 147 #define MCA_bus 0
 148 #define MCA_bus__is_a_macro /* for versions in ksyms.c */
 149
 150 /*
 151  * User space process size: 1TB. This is hardcoded into a few places,
 152  * so don't change it unless you know what you are doing.  TASK_SIZE
 153  * is limited to 1TB by the R4000 architecture; R10000 and better can
 154  * support 16TB.
 155  */
 156 #define TASK_SIZE32        0x7fff8000UL
 157 #define TASK_SIZE       0x10000000000UL
 158
 159 /* This decides where the kernel will search for a free chunk of vm
 160  * space during mmap's.
 161  */
 162 #define TASK_UNMAPPED_BASE      ((current->thread.mflags & MF_32BIT_ADDR) ? \
 163         PAGE_ALIGN(TASK_SIZE32 / 3) : PAGE_ALIGN(TASK_SIZE / 3))
 164
 165 /*
 166  * Size of io_bitmap in longwords: 32 is ports 0-0x3ff.
 167  */
 168 #define IO_BITMAP_SIZE  32
 169
 170 #define NUM_FPU_REGS    32
 171
 172 struct mips_fpu_hard_struct {
 173         unsigned long fp_regs[NUM_FPU_REGS];
 174         unsigned int control;
 175 };
 176
 177 /*
 178  * It would be nice to add some more fields for emulator statistics, but there
 179  * are a number of fixed offsets in offset.h and elsewhere that would have to
 180  * be recalculated by hand.  So the additional information will be private to
 181  * the FPU emulator for now.  See asm-mips/fpu_emulator.h.
 182  */
 183 typedef u64 fpureg_t;
 184 struct mips_fpu_soft_struct {
 185         fpureg_t        regs[NUM_FPU_REGS];
 186         unsigned int    sr;
 187 };
 188
 189 union mips_fpu_union {
 190         struct mips_fpu_hard_struct hard;
 191         struct mips_fpu_soft_struct soft;
 192 };
 193
 194 #define INIT_FPU { \
 195         {{0,},} \
 196 }
 197
 198 typedef struct {
 199         unsigned long seg;
 200 } mm_segment_t;
 201
 202 /*
 203  * If you change thread_struct remember to change the #defines below too!
 204  */
 205 struct thread_struct {
 206         /* Saved main processor registers. */
 207         unsigned long reg16;
 208         unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23;
 209         unsigned long reg29, reg30, reg31;
 210
 211         /* Saved cp0 stuff. */
 212         unsigned long cp0_status;
 213
 214         /* Saved fpu/fpu emulator stuff. */
 215         union mips_fpu_union fpu;
 216
 217         /* Other stuff associated with the thread. */
 218         unsigned long cp0_badvaddr;     /* Last user fault */
 219         unsigned long cp0_baduaddr;     /* Last kernel fault accessing USEG */
 220         unsigned long error_code;
 221         unsigned long trap_no;
 222 #define MF_FIXADE       1               /* Fix address errors in software */
 223 #define MF_LOGADE       2               /* Log address errors to syslog */
 224 #define MF_32BIT_REGS   4               /* also implies 16/32 fprs */
 225 #define MF_32BIT_ADDR   8               /* 32-bit address space (o32/n32) */
 226         unsigned long mflags;
 227         unsigned long irix_trampoline;  /* Wheee... */
 228         unsigned long irix_oldctx;
 229 };
 230
 231 #define MF_ABI_MASK     (MF_32BIT_REGS | MF_32BIT_ADDR)
 232 #define MF_O32          (MF_32BIT_REGS | MF_32BIT_ADDR)
 233 #define MF_N32          MF_32BIT_ADDR
 234 #define MF_N64          0
 235
 236 #endif /* !__ASSEMBLY__ */
 237
 238 #define INIT_THREAD  { \
 239         /* \
 240          * saved main processor registers \
 241          */ \
 242         0, 0, 0, 0, 0, 0, 0, 0, \
 243                        0, 0, 0, \
 244         /* \
 245          * saved cp0 stuff \
 246          */ \
 247         0, \
 248         /* \
 249          * saved fpu/fpu emulator stuff \
 250          */ \
 251         INIT_FPU, \
 252         /* \
 253          * Other stuff associated with the process \
 254          */ \
 255         0, 0, 0, 0, \
 256         /* \
 257          * For now the default is to fix address errors \
 258          */ \
 259         MF_FIXADE, 0, 0 \
 260 }
 261
 262 #ifdef __KERNEL__
 263
 264 #define KERNEL_STACK_SIZE       0x4000
 265
 266 #ifndef __ASSEMBLY__
 267
 268 struct task_struct;
 269
 270 /* Free all resources held by a thread. */
 271 #define release_thread(thread) do { } while(0)
 272
 273 /* Prepare to copy thread state - unlazy all lazy status */
 274 #define prepare_to_copy(tsk)    do { } while (0)
 275
 276 extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
 277
 278 extern unsigned long thread_saved_pc(struct task_struct *tsk);
 279
 280 #define user_mode(regs) (((regs)->cp0_status & ST0_KSU) == KSU_USER)
 281
 282 /*
 283  * Do necessary setup to start up a newly executed thread.
 284  */
 285 extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp);
 286
 287 unsigned long get_wchan(struct task_struct *p);
 288
 289 #define __PT_REG(reg) ((long)&((struct pt_regs *)0)->reg - sizeof(struct pt_regs))
 290 #define __KSTK_TOS(tsk) ((unsigned long)(tsk->thread_info) + KERNEL_STACK_SIZE - 32)
 291 #define KSTK_EIP(tsk) (*(unsigned long *)(__KSTK_TOS(tsk) + __PT_REG(cp0_epc)))
 292 #define KSTK_ESP(tsk) (*(unsigned long *)(__KSTK_TOS(tsk) + __PT_REG(regs[29])))
 293 #define KSTK_STATUS(tsk) (*(unsigned long *)(__KSTK_TOS(tsk) + __PT_REG(cp0_status)))
 294
 295 #define cpu_relax()     barrier()
 296
 297 #endif /* !__ASSEMBLY__ */
 298 #endif /* __KERNEL__ */
 299
 300 /*
 301  * Return_address is a replacement for __builtin_return_address(count)
 302  * which on certain architectures cannot reasonably be implemented in GCC
 303  * (MIPS, Alpha) or is unuseable with -fomit-frame-pointer (i386).
 304  * Note that __builtin_return_address(x>=1) is forbidden because GCC
 305  * aborts compilation on some CPUs.  It's simply not possible to unwind
 306  * some CPU's stackframes.
 307  *
 308  * __builtin_return_address works only for non-leaf functions.  We avoid the
 309  * overhead of a function call by forcing the compiler to save the return
 310  * address register on the stack.
 311  */
 312 #define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
 313
 314 #endif /* _ASM_PROCESSOR_H */