arch/sh/kernel/cpu/irq_ipr.c

   1 /* $Id: irq_ipr.c,v 1.1.2.1 2002/11/17 10:53:43 mrbrown Exp $
   2  *
   3  * linux/arch/sh/kernel/irq_ipr.c
   4  *
   5  * Copyright (C) 1999  Niibe Yutaka & Takeshi Yaegashi
   6  * Copyright (C) 2000  Kazumoto Kojima
   7  *
   8  * Interrupt handling for IPR-based IRQ.
   9  *
  10  * Supported system:
  11  *      On-chip supporting modules (TMU, RTC, etc.).
  12  *      On-chip supporting modules for SH7709/SH7709A/SH7729.
  13  *      Hitachi SolutionEngine external I/O:
  14  *              MS7709SE01, MS7709ASE01, and MS7750SE01
  15  *
  16  */
  17
  18 #include <linux/config.h>
  19 #include <linux/init.h>
  20 #include <linux/irq.h>
  21
  22 #include <asm/system.h>
  23 #include <asm/io.h>
  24 #include <asm/machvec.h>
  25
  26 struct ipr_data {
  27         unsigned int addr;      /* Address of Interrupt Priority Register */
  28         int shift;              /* Shifts of the 16-bit data */
  29         int priority;           /* The priority */
  30 };
  31 static struct ipr_data ipr_data[NR_IRQS];
  32
  33 static void enable_ipr_irq(unsigned int irq);
  34 static void disable_ipr_irq(unsigned int irq);
  35
  36 /* shutdown is same as "disable" */
  37 #define shutdown_ipr_irq disable_ipr_irq
  38
  39 static void mask_and_ack_ipr(unsigned int);
  40 static void end_ipr_irq(unsigned int irq);
  41
  42 static unsigned int startup_ipr_irq(unsigned int irq)
  43 {
  44         enable_ipr_irq(irq);
  45         return 0; /* never anything pending */
  46 }
  47
  48 static struct hw_interrupt_type ipr_irq_type = {
  49         "IPR-IRQ",
  50         startup_ipr_irq,
  51         shutdown_ipr_irq,
  52         enable_ipr_irq,
  53         disable_ipr_irq,
  54         mask_and_ack_ipr,
  55         end_ipr_irq
  56 };
  57
  58 static void disable_ipr_irq(unsigned int irq)
  59 {
  60         unsigned long val, flags;
  61         unsigned int addr = ipr_data[irq].addr;
  62         unsigned short mask = 0xffff ^ (0x0f << ipr_data[irq].shift);
  63
  64         /* Set the priority in IPR to 0 */
  65         local_irq_save(flags);
  66         val = ctrl_inw(addr);
  67         val &= mask;
  68         ctrl_outw(val, addr);
  69         local_irq_restore(flags);
  70 }
  71
  72 static void enable_ipr_irq(unsigned int irq)
  73 {
  74         unsigned long val, flags;
  75         unsigned int addr = ipr_data[irq].addr;
  76         int priority = ipr_data[irq].priority;
  77         unsigned short value = (priority << ipr_data[irq].shift);
  78
  79         /* Set priority in IPR back to original value */
  80         local_irq_save(flags);
  81         val = ctrl_inw(addr);
  82         val |= value;
  83         ctrl_outw(val, addr);
  84         local_irq_restore(flags);
  85 }
  86
  87 static void mask_and_ack_ipr(unsigned int irq)
  88 {
  89         disable_ipr_irq(irq);
  90
  91 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
  92         /* This is needed when we use edge triggered setting */
  93         /* XXX: Is it really needed? */
  94         if (IRQ0_IRQ <= irq && irq <= IRQ5_IRQ) {
  95                 /* Clear external interrupt request */
  96                 int a = ctrl_inb(INTC_IRR0);
  97                 a &= ~(1 << (irq - IRQ0_IRQ));
  98                 ctrl_outb(a, INTC_IRR0);
  99         }
 100 #endif
 101 }
 102
 103 static void end_ipr_irq(unsigned int irq)
 104 {
 105         if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
 106                 enable_ipr_irq(irq);
 107 }
 108
 109 void make_ipr_irq(unsigned int irq, unsigned int addr, int pos, int priority)
 110 {
 111         disable_irq_nosync(irq);
 112         ipr_data[irq].addr = addr;
 113         ipr_data[irq].shift = pos*4; /* POSition (0-3) x 4 means shift */
 114         ipr_data[irq].priority = priority;
 115
 116         irq_desc[irq].handler = &ipr_irq_type;
 117         disable_ipr_irq(irq);
 118 }
 119
 120 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
 121 static unsigned char pint_map[256];
 122 static unsigned long portcr_mask = 0;
 123
 124 static void enable_pint_irq(unsigned int irq);
 125 static void disable_pint_irq(unsigned int irq);
 126
 127 /* shutdown is same as "disable" */
 128 #define shutdown_pint_irq disable_pint_irq
 129
 130 static void mask_and_ack_pint(unsigned int);
 131 static void end_pint_irq(unsigned int irq);
 132
 133 static unsigned int startup_pint_irq(unsigned int irq)
 134 {
 135         enable_pint_irq(irq);
 136         return 0; /* never anything pending */
 137 }
 138
 139 static struct hw_interrupt_type pint_irq_type = {
 140         "PINT-IRQ",
 141         startup_pint_irq,
 142         shutdown_pint_irq,
 143         enable_pint_irq,
 144         disable_pint_irq,
 145         mask_and_ack_pint,
 146         end_pint_irq
 147 };
 148
 149 static void disable_pint_irq(unsigned int irq)
 150 {
 151         unsigned long val, flags;
 152
 153         local_irq_save(flags);
 154         val = ctrl_inw(INTC_INTER);
 155         val &= ~(1 << (irq - PINT_IRQ_BASE));
 156         ctrl_outw(val, INTC_INTER);     /* disable PINTn */
 157         portcr_mask &= ~(3 << (irq - PINT_IRQ_BASE)*2);
 158         local_irq_restore(flags);
 159 }
 160
 161 static void enable_pint_irq(unsigned int irq)
 162 {
 163         unsigned long val, flags;
 164
 165         local_irq_save(flags);
 166         val = ctrl_inw(INTC_INTER);
 167         val |= 1 << (irq - PINT_IRQ_BASE);
 168         ctrl_outw(val, INTC_INTER);     /* enable PINTn */
 169         portcr_mask |= 3 << (irq - PINT_IRQ_BASE)*2;
 170         local_irq_restore(flags);
 171 }
 172
 173 static void mask_and_ack_pint(unsigned int irq)
 174 {
 175         disable_pint_irq(irq);
 176 }
 177
 178 static void end_pint_irq(unsigned int irq)
 179 {
 180         if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
 181                 enable_pint_irq(irq);
 182 }
 183
 184 void make_pint_irq(unsigned int irq)
 185 {
 186         disable_irq_nosync(irq);
 187         irq_desc[irq].handler = &pint_irq_type;
 188         disable_pint_irq(irq);
 189 }
 190 #endif
 191
 192 void __init init_IRQ(void)
 193 {
 194 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
 195         int i;
 196 #endif
 197
 198         make_ipr_irq(TIMER_IRQ, TIMER_IPR_ADDR, TIMER_IPR_POS, TIMER_PRIORITY);
 199         make_ipr_irq(RTC_IRQ, RTC_IPR_ADDR, RTC_IPR_POS, RTC_PRIORITY);
 200
 201 #ifdef SCI_ERI_IRQ
 202         make_ipr_irq(SCI_ERI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY);
 203         make_ipr_irq(SCI_RXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY);
 204         make_ipr_irq(SCI_TXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY);
 205 #endif
 206
 207 #ifdef SCIF1_ERI_IRQ
 208         make_ipr_irq(SCIF1_ERI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);
 209         make_ipr_irq(SCIF1_RXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);
 210         make_ipr_irq(SCIF1_BRI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);
 211         make_ipr_irq(SCIF1_TXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);
 212 #endif
 213
 214 #ifdef SCIF_ERI_IRQ
 215         make_ipr_irq(SCIF_ERI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
 216         make_ipr_irq(SCIF_RXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
 217         make_ipr_irq(SCIF_BRI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
 218         make_ipr_irq(SCIF_TXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
 219 #endif
 220
 221 #ifdef IRDA_ERI_IRQ
 222         make_ipr_irq(IRDA_ERI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
 223         make_ipr_irq(IRDA_RXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
 224         make_ipr_irq(IRDA_BRI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
 225         make_ipr_irq(IRDA_TXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
 226 #endif
 227
 228 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
 229         /*
 230          * Initialize the Interrupt Controller (INTC)
 231          * registers to their power on values
 232          */
 233
 234         /*
 235          * Enable external irq (INTC IRQ mode).
 236          * You should set corresponding bits of PFC to "00"
 237          * to enable these interrupts.
 238          */
 239         make_ipr_irq(IRQ0_IRQ, IRQ0_IPR_ADDR, IRQ0_IPR_POS, IRQ0_PRIORITY);
 240         make_ipr_irq(IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, IRQ1_PRIORITY);
 241         make_ipr_irq(IRQ2_IRQ, IRQ2_IPR_ADDR, IRQ2_IPR_POS, IRQ2_PRIORITY);
 242         make_ipr_irq(IRQ3_IRQ, IRQ3_IPR_ADDR, IRQ3_IPR_POS, IRQ3_PRIORITY);
 243         make_ipr_irq(IRQ4_IRQ, IRQ4_IPR_ADDR, IRQ4_IPR_POS, IRQ4_PRIORITY);
 244         make_ipr_irq(IRQ5_IRQ, IRQ5_IPR_ADDR, IRQ5_IPR_POS, IRQ5_PRIORITY);
 245         make_ipr_irq(PINT0_IRQ, PINT0_IPR_ADDR, PINT0_IPR_POS, PINT0_PRIORITY);
 246         make_ipr_irq(PINT8_IRQ, PINT8_IPR_ADDR, PINT8_IPR_POS, PINT8_PRIORITY);
 247         enable_ipr_irq(PINT0_IRQ);
 248         enable_ipr_irq(PINT8_IRQ);
 249
 250         for(i = 0; i < 16; i++)
 251                 make_pint_irq(PINT_IRQ_BASE + i);
 252         for(i = 0; i < 256; i++)
 253         {
 254                 if(i & 1) pint_map[i] = 0;
 255                 else if(i & 2) pint_map[i] = 1;
 256                 else if(i & 4) pint_map[i] = 2;
 257                 else if(i & 8) pint_map[i] = 3;
 258                 else if(i & 0x10) pint_map[i] = 4;
 259                 else if(i & 0x20) pint_map[i] = 5;
 260                 else if(i & 0x40) pint_map[i] = 6;
 261                 else if(i & 0x80) pint_map[i] = 7;
 262         }
 263 #endif /* CONFIG_CPU_SUBTYPE_SH7707 || CONFIG_CPU_SUBTYPE_SH7709 */
 264
 265         /* Perform the machine specific initialisation */
 266         if (sh_mv.mv_init_irq != NULL) {
 267                 sh_mv.mv_init_irq();
 268         }
 269 }
 270 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
 271 int ipr_irq_demux(int irq)
 272 {
 273         unsigned long creg, dreg, d, sav;
 274
 275         if(irq == PINT0_IRQ)
 276         {
 277 #if defined(CONFIG_CPU_SUBTYPE_SH7707)
 278                 creg = PORT_PACR;
 279                 dreg = PORT_PADR;
 280 #else
 281                 creg = PORT_PCCR;
 282                 dreg = PORT_PCDR;
 283 #endif
 284                 sav = ctrl_inw(creg);
 285                 ctrl_outw(sav | portcr_mask, creg);
 286                 d = (~ctrl_inb(dreg) ^ ctrl_inw(INTC_ICR2)) & ctrl_inw(INTC_INTER) & 0xff;
 287                 ctrl_outw(sav, creg);
 288                 if(d == 0) return irq;
 289                 return PINT_IRQ_BASE + pint_map[d];
 290         }
 291         else if(irq == PINT8_IRQ)
 292         {
 293 #if defined(CONFIG_CPU_SUBTYPE_SH7707)
 294                 creg = PORT_PBCR;
 295                 dreg = PORT_PBDR;
 296 #else
 297                 creg = PORT_PFCR;
 298                 dreg = PORT_PFDR;
 299 #endif
 300                 sav = ctrl_inw(creg);
 301                 ctrl_outw(sav | (portcr_mask >> 16), creg);
 302                 d = (~ctrl_inb(dreg) ^ (ctrl_inw(INTC_ICR2) >> 8)) & (ctrl_inw(INTC_INTER) >> 8) & 0xff;
 303                 ctrl_outw(sav, creg);
 304                 if(d == 0) return irq;
 305                 return PINT_IRQ_BASE + 8 + pint_map[d];
 306         }
 307         return irq;
 308 }
 309 #endif