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[PATCH] CPU hotplug: call check_tsc_sync_source() with irqs off
[linux-2.6/linux-mips.git] / drivers / mmc / sdhci.c
blobd749f08601b8138510d0d7e0e610e47586a1b58d
1 /*
2 * linux/drivers/mmc/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2006 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
10 */
11
12 #include <linux/delay.h>
13 #include <linux/highmem.h>
14 #include <linux/pci.h>
15 #include <linux/dma-mapping.h>
16
17 #include <linux/mmc/host.h>
18 #include <linux/mmc/protocol.h>
19
20 #include <asm/scatterlist.h>
21
22 #include "sdhci.h"
23
24 #define DRIVER_NAME "sdhci"
25
26 #define DBG(f, x...) \
27 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
28
29 static unsigned int debug_nodma = 0;
30 static unsigned int debug_forcedma = 0;
31 static unsigned int debug_quirks = 0;
32
33 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
34 #define SDHCI_QUIRK_FORCE_DMA (1<<1)
35 /* Controller doesn't like some resets when there is no card inserted. */
36 #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
37 #define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3)
38
39 static const struct pci_device_id pci_ids[] __devinitdata = {
40 {
41 .vendor = PCI_VENDOR_ID_RICOH,
42 .device = PCI_DEVICE_ID_RICOH_R5C822,
43 .subvendor = PCI_VENDOR_ID_IBM,
44 .subdevice = PCI_ANY_ID,
45 .driver_data = SDHCI_QUIRK_CLOCK_BEFORE_RESET |
46 SDHCI_QUIRK_FORCE_DMA,
47 },
48
49 {
50 .vendor = PCI_VENDOR_ID_RICOH,
51 .device = PCI_DEVICE_ID_RICOH_R5C822,
52 .subvendor = PCI_ANY_ID,
53 .subdevice = PCI_ANY_ID,
54 .driver_data = SDHCI_QUIRK_FORCE_DMA |
55 SDHCI_QUIRK_NO_CARD_NO_RESET,
56 },
57
58 {
59 .vendor = PCI_VENDOR_ID_TI,
60 .device = PCI_DEVICE_ID_TI_XX21_XX11_SD,
61 .subvendor = PCI_ANY_ID,
62 .subdevice = PCI_ANY_ID,
63 .driver_data = SDHCI_QUIRK_FORCE_DMA,
64 },
65
66 {
67 .vendor = PCI_VENDOR_ID_ENE,
68 .device = PCI_DEVICE_ID_ENE_CB712_SD,
69 .subvendor = PCI_ANY_ID,
70 .subdevice = PCI_ANY_ID,
71 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE,
72 },
73
74 { /* Generic SD host controller */
75 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
76 },
77
78 { /* end: all zeroes */ },
79 };
80
81 MODULE_DEVICE_TABLE(pci, pci_ids);
82
83 static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
84 static void sdhci_finish_data(struct sdhci_host *);
85
86 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
87 static void sdhci_finish_command(struct sdhci_host *);
88
89 static void sdhci_dumpregs(struct sdhci_host *host)
90 {
91 printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
92
93 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
94 readl(host->ioaddr + SDHCI_DMA_ADDRESS),
95 readw(host->ioaddr + SDHCI_HOST_VERSION));
96 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
97 readw(host->ioaddr + SDHCI_BLOCK_SIZE),
98 readw(host->ioaddr + SDHCI_BLOCK_COUNT));
99 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
100 readl(host->ioaddr + SDHCI_ARGUMENT),
101 readw(host->ioaddr + SDHCI_TRANSFER_MODE));
102 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
103 readl(host->ioaddr + SDHCI_PRESENT_STATE),
104 readb(host->ioaddr + SDHCI_HOST_CONTROL));
105 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
106 readb(host->ioaddr + SDHCI_POWER_CONTROL),
107 readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
108 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
109 readb(host->ioaddr + SDHCI_WALK_UP_CONTROL),
110 readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
111 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
112 readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
113 readl(host->ioaddr + SDHCI_INT_STATUS));
114 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
115 readl(host->ioaddr + SDHCI_INT_ENABLE),
116 readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
117 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
118 readw(host->ioaddr + SDHCI_ACMD12_ERR),
119 readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
120 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
121 readl(host->ioaddr + SDHCI_CAPABILITIES),
122 readl(host->ioaddr + SDHCI_MAX_CURRENT));
123
124 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
125 }
126
127 /*****************************************************************************\
128 * *
129 * Low level functions *
130 * *
131 \*****************************************************************************/
132
133 static void sdhci_reset(struct sdhci_host *host, u8 mask)
134 {
135 unsigned long timeout;
136
137 if (host->chip->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
138 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
139 SDHCI_CARD_PRESENT))
140 return;
141 }
142
143 writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
144
145 if (mask & SDHCI_RESET_ALL)
146 host->clock = 0;
147
148 /* Wait max 100 ms */
149 timeout = 100;
150
151 /* hw clears the bit when it's done */
152 while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
153 if (timeout == 0) {
154 printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
155 mmc_hostname(host->mmc), (int)mask);
156 sdhci_dumpregs(host);
157 return;
158 }
159 timeout--;
160 mdelay(1);
161 }
162 }
163
164 static void sdhci_init(struct sdhci_host *host)
165 {
166 u32 intmask;
167
168 sdhci_reset(host, SDHCI_RESET_ALL);
169
170 intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
171 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
172 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
173 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
174 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
175 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE;
176
177 writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
178 writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
179 }
180
181 static void sdhci_activate_led(struct sdhci_host *host)
182 {
183 u8 ctrl;
184
185 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
186 ctrl |= SDHCI_CTRL_LED;
187 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
188 }
189
190 static void sdhci_deactivate_led(struct sdhci_host *host)
191 {
192 u8 ctrl;
193
194 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
195 ctrl &= ~SDHCI_CTRL_LED;
196 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
197 }
198
199 /*****************************************************************************\
200 * *
201 * Core functions *
202 * *
203 \*****************************************************************************/
204
205 static inline char* sdhci_sg_to_buffer(struct sdhci_host* host)
206 {
207 return page_address(host->cur_sg->page) + host->cur_sg->offset;
208 }
209
210 static inline int sdhci_next_sg(struct sdhci_host* host)
211 {
212 /*
213 * Skip to next SG entry.
214 */
215 host->cur_sg++;
216 host->num_sg--;
217
218 /*
219 * Any entries left?
220 */
221 if (host->num_sg > 0) {
222 host->offset = 0;
223 host->remain = host->cur_sg->length;
224 }
225
226 return host->num_sg;
227 }
228
229 static void sdhci_read_block_pio(struct sdhci_host *host)
230 {
231 int blksize, chunk_remain;
232 u32 data;
233 char *buffer;
234 int size;
235
236 DBG("PIO reading\n");
237
238 blksize = host->data->blksz;
239 chunk_remain = 0;
240 data = 0;
241
242 buffer = sdhci_sg_to_buffer(host) + host->offset;
243
244 while (blksize) {
245 if (chunk_remain == 0) {
246 data = readl(host->ioaddr + SDHCI_BUFFER);
247 chunk_remain = min(blksize, 4);
248 }
249
250 size = min(host->size, host->remain);
251 size = min(size, chunk_remain);
252
253 chunk_remain -= size;
254 blksize -= size;
255 host->offset += size;
256 host->remain -= size;
257 host->size -= size;
258 while (size) {
259 *buffer = data & 0xFF;
260 buffer++;
261 data >>= 8;
262 size--;
263 }
264
265 if (host->remain == 0) {
266 if (sdhci_next_sg(host) == 0) {
267 BUG_ON(blksize != 0);
268 return;
269 }
270 buffer = sdhci_sg_to_buffer(host);
271 }
272 }
273 }
274
275 static void sdhci_write_block_pio(struct sdhci_host *host)
276 {
277 int blksize, chunk_remain;
278 u32 data;
279 char *buffer;
280 int bytes, size;
281
282 DBG("PIO writing\n");
283
284 blksize = host->data->blksz;
285 chunk_remain = 4;
286 data = 0;
287
288 bytes = 0;
289 buffer = sdhci_sg_to_buffer(host) + host->offset;
290
291 while (blksize) {
292 size = min(host->size, host->remain);
293 size = min(size, chunk_remain);
294
295 chunk_remain -= size;
296 blksize -= size;
297 host->offset += size;
298 host->remain -= size;
299 host->size -= size;
300 while (size) {
301 data >>= 8;
302 data |= (u32)*buffer << 24;
303 buffer++;
304 size--;
305 }
306
307 if (chunk_remain == 0) {
308 writel(data, host->ioaddr + SDHCI_BUFFER);
309 chunk_remain = min(blksize, 4);
310 }
311
312 if (host->remain == 0) {
313 if (sdhci_next_sg(host) == 0) {
314 BUG_ON(blksize != 0);
315 return;
316 }
317 buffer = sdhci_sg_to_buffer(host);
318 }
319 }
320 }
321
322 static void sdhci_transfer_pio(struct sdhci_host *host)
323 {
324 u32 mask;
325
326 BUG_ON(!host->data);
327
328 if (host->size == 0)
329 return;
330
331 if (host->data->flags & MMC_DATA_READ)
332 mask = SDHCI_DATA_AVAILABLE;
333 else
334 mask = SDHCI_SPACE_AVAILABLE;
335
336 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
337 if (host->data->flags & MMC_DATA_READ)
338 sdhci_read_block_pio(host);
339 else
340 sdhci_write_block_pio(host);
341
342 if (host->size == 0)
343 break;
344
345 BUG_ON(host->num_sg == 0);
346 }
347
348 DBG("PIO transfer complete.\n");
349 }
350
351 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
352 {
353 u8 count;
354 unsigned target_timeout, current_timeout;
355
356 WARN_ON(host->data);
357
358 if (data == NULL)
359 return;
360
361 DBG("blksz %04x blks %04x flags %08x\n",
362 data->blksz, data->blocks, data->flags);
363 DBG("tsac %d ms nsac %d clk\n",
364 data->timeout_ns / 1000000, data->timeout_clks);
365
366 /* Sanity checks */
367 BUG_ON(data->blksz * data->blocks > 524288);
368 BUG_ON(data->blksz > host->mmc->max_blk_size);
369 BUG_ON(data->blocks > 65535);
370
371 /* timeout in us */
372 target_timeout = data->timeout_ns / 1000 +
373 data->timeout_clks / host->clock;
374
375 /*
376 * Figure out needed cycles.
377 * We do this in steps in order to fit inside a 32 bit int.
378 * The first step is the minimum timeout, which will have a
379 * minimum resolution of 6 bits:
380 * (1) 2^13*1000 > 2^22,
381 * (2) host->timeout_clk < 2^16
382 * =>
383 * (1) / (2) > 2^6
384 */
385 count = 0;
386 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
387 while (current_timeout < target_timeout) {
388 count++;
389 current_timeout <<= 1;
390 if (count >= 0xF)
391 break;
392 }
393
394 if (count >= 0xF) {
395 printk(KERN_WARNING "%s: Too large timeout requested!\n",
396 mmc_hostname(host->mmc));
397 count = 0xE;
398 }
399
400 writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
401
402 if (host->flags & SDHCI_USE_DMA) {
403 int count;
404
405 count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len,
406 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
407 BUG_ON(count != 1);
408
409 writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS);
410 } else {
411 host->size = data->blksz * data->blocks;
412
413 host->cur_sg = data->sg;
414 host->num_sg = data->sg_len;
415
416 host->offset = 0;
417 host->remain = host->cur_sg->length;
418 }
419
420 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
421 writew(SDHCI_MAKE_BLKSZ(7, data->blksz),
422 host->ioaddr + SDHCI_BLOCK_SIZE);
423 writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
424 }
425
426 static void sdhci_set_transfer_mode(struct sdhci_host *host,
427 struct mmc_data *data)
428 {
429 u16 mode;
430
431 WARN_ON(host->data);
432
433 if (data == NULL)
434 return;
435
436 mode = SDHCI_TRNS_BLK_CNT_EN;
437 if (data->blocks > 1)
438 mode |= SDHCI_TRNS_MULTI;
439 if (data->flags & MMC_DATA_READ)
440 mode |= SDHCI_TRNS_READ;
441 if (host->flags & SDHCI_USE_DMA)
442 mode |= SDHCI_TRNS_DMA;
443
444 writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
445 }
446
447 static void sdhci_finish_data(struct sdhci_host *host)
448 {
449 struct mmc_data *data;
450 u16 blocks;
451
452 BUG_ON(!host->data);
453
454 data = host->data;
455 host->data = NULL;
456
457 if (host->flags & SDHCI_USE_DMA) {
458 pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
459 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
460 }
461
462 /*
463 * Controller doesn't count down when in single block mode.
464 */
465 if ((data->blocks == 1) && (data->error == MMC_ERR_NONE))
466 blocks = 0;
467 else
468 blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT);
469 data->bytes_xfered = data->blksz * (data->blocks - blocks);
470
471 if ((data->error == MMC_ERR_NONE) && blocks) {
472 printk(KERN_ERR "%s: Controller signalled completion even "
473 "though there were blocks left.\n",
474 mmc_hostname(host->mmc));
475 data->error = MMC_ERR_FAILED;
476 } else if (host->size != 0) {
477 printk(KERN_ERR "%s: %d bytes were left untransferred.\n",
478 mmc_hostname(host->mmc), host->size);
479 data->error = MMC_ERR_FAILED;
480 }
481
482 DBG("Ending data transfer (%d bytes)\n", data->bytes_xfered);
483
484 if (data->stop) {
485 /*
486 * The controller needs a reset of internal state machines
487 * upon error conditions.
488 */
489 if (data->error != MMC_ERR_NONE) {
490 sdhci_reset(host, SDHCI_RESET_CMD);
491 sdhci_reset(host, SDHCI_RESET_DATA);
492 }
493
494 sdhci_send_command(host, data->stop);
495 } else
496 tasklet_schedule(&host->finish_tasklet);
497 }
498
499 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
500 {
501 int flags;
502 u32 mask;
503 unsigned long timeout;
504
505 WARN_ON(host->cmd);
506
507 DBG("Sending cmd (%x)\n", cmd->opcode);
508
509 /* Wait max 10 ms */
510 timeout = 10;
511
512 mask = SDHCI_CMD_INHIBIT;
513 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
514 mask |= SDHCI_DATA_INHIBIT;
515
516 /* We shouldn't wait for data inihibit for stop commands, even
517 though they might use busy signaling */
518 if (host->mrq->data && (cmd == host->mrq->data->stop))
519 mask &= ~SDHCI_DATA_INHIBIT;
520
521 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
522 if (timeout == 0) {
523 printk(KERN_ERR "%s: Controller never released "
524 "inhibit bit(s).\n", mmc_hostname(host->mmc));
525 sdhci_dumpregs(host);
526 cmd->error = MMC_ERR_FAILED;
527 tasklet_schedule(&host->finish_tasklet);
528 return;
529 }
530 timeout--;
531 mdelay(1);
532 }
533
534 mod_timer(&host->timer, jiffies + 10 * HZ);
535
536 host->cmd = cmd;
537
538 sdhci_prepare_data(host, cmd->data);
539
540 writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
541
542 sdhci_set_transfer_mode(host, cmd->data);
543
544 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
545 printk(KERN_ERR "%s: Unsupported response type!\n",
546 mmc_hostname(host->mmc));
547 cmd->error = MMC_ERR_INVALID;
548 tasklet_schedule(&host->finish_tasklet);
549 return;
550 }
551
552 if (!(cmd->flags & MMC_RSP_PRESENT))
553 flags = SDHCI_CMD_RESP_NONE;
554 else if (cmd->flags & MMC_RSP_136)
555 flags = SDHCI_CMD_RESP_LONG;
556 else if (cmd->flags & MMC_RSP_BUSY)
557 flags = SDHCI_CMD_RESP_SHORT_BUSY;
558 else
559 flags = SDHCI_CMD_RESP_SHORT;
560
561 if (cmd->flags & MMC_RSP_CRC)
562 flags |= SDHCI_CMD_CRC;
563 if (cmd->flags & MMC_RSP_OPCODE)
564 flags |= SDHCI_CMD_INDEX;
565 if (cmd->data)
566 flags |= SDHCI_CMD_DATA;
567
568 writew(SDHCI_MAKE_CMD(cmd->opcode, flags),
569 host->ioaddr + SDHCI_COMMAND);
570 }
571
572 static void sdhci_finish_command(struct sdhci_host *host)
573 {
574 int i;
575
576 BUG_ON(host->cmd == NULL);
577
578 if (host->cmd->flags & MMC_RSP_PRESENT) {
579 if (host->cmd->flags & MMC_RSP_136) {
580 /* CRC is stripped so we need to do some shifting. */
581 for (i = 0;i < 4;i++) {
582 host->cmd->resp[i] = readl(host->ioaddr +
583 SDHCI_RESPONSE + (3-i)*4) << 8;
584 if (i != 3)
585 host->cmd->resp[i] |=
586 readb(host->ioaddr +
587 SDHCI_RESPONSE + (3-i)*4-1);
588 }
589 } else {
590 host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
591 }
592 }
593
594 host->cmd->error = MMC_ERR_NONE;
595
596 DBG("Ending cmd (%x)\n", host->cmd->opcode);
597
598 if (host->cmd->data)
599 host->data = host->cmd->data;
600 else
601 tasklet_schedule(&host->finish_tasklet);
602
603 host->cmd = NULL;
604 }
605
606 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
607 {
608 int div;
609 u16 clk;
610 unsigned long timeout;
611
612 if (clock == host->clock)
613 return;
614
615 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
616
617 if (clock == 0)
618 goto out;
619
620 for (div = 1;div < 256;div *= 2) {
621 if ((host->max_clk / div) <= clock)
622 break;
623 }
624 div >>= 1;
625
626 clk = div << SDHCI_DIVIDER_SHIFT;
627 clk |= SDHCI_CLOCK_INT_EN;
628 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
629
630 /* Wait max 10 ms */
631 timeout = 10;
632 while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
633 & SDHCI_CLOCK_INT_STABLE)) {
634 if (timeout == 0) {
635 printk(KERN_ERR "%s: Internal clock never "
636 "stabilised.\n", mmc_hostname(host->mmc));
637 sdhci_dumpregs(host);
638 return;
639 }
640 timeout--;
641 mdelay(1);
642 }
643
644 clk |= SDHCI_CLOCK_CARD_EN;
645 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
646
647 out:
648 host->clock = clock;
649 }
650
651 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
652 {
653 u8 pwr;
654
655 if (host->power == power)
656 return;
657
658 if (power == (unsigned short)-1) {
659 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
660 goto out;
661 }
662
663 /*
664 * Spec says that we should clear the power reg before setting
665 * a new value. Some controllers don't seem to like this though.
666 */
667 if (!(host->chip->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
668 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
669
670 pwr = SDHCI_POWER_ON;
671
672 switch (power) {
673 case MMC_VDD_170:
674 case MMC_VDD_180:
675 case MMC_VDD_190:
676 pwr |= SDHCI_POWER_180;
677 break;
678 case MMC_VDD_290:
679 case MMC_VDD_300:
680 case MMC_VDD_310:
681 pwr |= SDHCI_POWER_300;
682 break;
683 case MMC_VDD_320:
684 case MMC_VDD_330:
685 case MMC_VDD_340:
686 pwr |= SDHCI_POWER_330;
687 break;
688 default:
689 BUG();
690 }
691
692 writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
693
694 out:
695 host->power = power;
696 }
697
698 /*****************************************************************************\
699 * *
700 * MMC callbacks *
701 * *
702 \*****************************************************************************/
703
704 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
705 {
706 struct sdhci_host *host;
707 unsigned long flags;
708
709 host = mmc_priv(mmc);
710
711 spin_lock_irqsave(&host->lock, flags);
712
713 WARN_ON(host->mrq != NULL);
714
715 sdhci_activate_led(host);
716
717 host->mrq = mrq;
718
719 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
720 host->mrq->cmd->error = MMC_ERR_TIMEOUT;
721 tasklet_schedule(&host->finish_tasklet);
722 } else
723 sdhci_send_command(host, mrq->cmd);
724
725 mmiowb();
726 spin_unlock_irqrestore(&host->lock, flags);
727 }
728
729 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
730 {
731 struct sdhci_host *host;
732 unsigned long flags;
733 u8 ctrl;
734
735 host = mmc_priv(mmc);
736
737 spin_lock_irqsave(&host->lock, flags);
738
739 /*
740 * Reset the chip on each power off.
741 * Should clear out any weird states.
742 */
743 if (ios->power_mode == MMC_POWER_OFF) {
744 writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
745 sdhci_init(host);
746 }
747
748 sdhci_set_clock(host, ios->clock);
749
750 if (ios->power_mode == MMC_POWER_OFF)
751 sdhci_set_power(host, -1);
752 else
753 sdhci_set_power(host, ios->vdd);
754
755 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
756
757 if (ios->bus_width == MMC_BUS_WIDTH_4)
758 ctrl |= SDHCI_CTRL_4BITBUS;
759 else
760 ctrl &= ~SDHCI_CTRL_4BITBUS;
761
762 if (ios->timing == MMC_TIMING_SD_HS)
763 ctrl |= SDHCI_CTRL_HISPD;
764 else
765 ctrl &= ~SDHCI_CTRL_HISPD;
766
767 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
768
769 mmiowb();
770 spin_unlock_irqrestore(&host->lock, flags);
771 }
772
773 static int sdhci_get_ro(struct mmc_host *mmc)
774 {
775 struct sdhci_host *host;
776 unsigned long flags;
777 int present;
778
779 host = mmc_priv(mmc);
780
781 spin_lock_irqsave(&host->lock, flags);
782
783 present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
784
785 spin_unlock_irqrestore(&host->lock, flags);
786
787 return !(present & SDHCI_WRITE_PROTECT);
788 }
789
790 static const struct mmc_host_ops sdhci_ops = {
791 .request = sdhci_request,
792 .set_ios = sdhci_set_ios,
793 .get_ro = sdhci_get_ro,
794 };
795
796 /*****************************************************************************\
797 * *
798 * Tasklets *
799 * *
800 \*****************************************************************************/
801
802 static void sdhci_tasklet_card(unsigned long param)
803 {
804 struct sdhci_host *host;
805 unsigned long flags;
806
807 host = (struct sdhci_host*)param;
808
809 spin_lock_irqsave(&host->lock, flags);
810
811 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
812 if (host->mrq) {
813 printk(KERN_ERR "%s: Card removed during transfer!\n",
814 mmc_hostname(host->mmc));
815 printk(KERN_ERR "%s: Resetting controller.\n",
816 mmc_hostname(host->mmc));
817
818 sdhci_reset(host, SDHCI_RESET_CMD);
819 sdhci_reset(host, SDHCI_RESET_DATA);
820
821 host->mrq->cmd->error = MMC_ERR_FAILED;
822 tasklet_schedule(&host->finish_tasklet);
823 }
824 }
825
826 spin_unlock_irqrestore(&host->lock, flags);
827
828 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
829 }
830
831 static void sdhci_tasklet_finish(unsigned long param)
832 {
833 struct sdhci_host *host;
834 unsigned long flags;
835 struct mmc_request *mrq;
836
837 host = (struct sdhci_host*)param;
838
839 spin_lock_irqsave(&host->lock, flags);
840
841 del_timer(&host->timer);
842
843 mrq = host->mrq;
844
845 DBG("Ending request, cmd (%x)\n", mrq->cmd->opcode);
846
847 /*
848 * The controller needs a reset of internal state machines
849 * upon error conditions.
850 */
851 if ((mrq->cmd->error != MMC_ERR_NONE) ||
852 (mrq->data && ((mrq->data->error != MMC_ERR_NONE) ||
853 (mrq->data->stop && (mrq->data->stop->error != MMC_ERR_NONE))))) {
854
855 /* Some controllers need this kick or reset won't work here */
856 if (host->chip->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
857 unsigned int clock;
858
859 /* This is to force an update */
860 clock = host->clock;
861 host->clock = 0;
862 sdhci_set_clock(host, clock);
863 }
864
865 /* Spec says we should do both at the same time, but Ricoh
866 controllers do not like that. */
867 sdhci_reset(host, SDHCI_RESET_CMD);
868 sdhci_reset(host, SDHCI_RESET_DATA);
869 }
870
871 host->mrq = NULL;
872 host->cmd = NULL;
873 host->data = NULL;
874
875 sdhci_deactivate_led(host);
876
877 mmiowb();
878 spin_unlock_irqrestore(&host->lock, flags);
879
880 mmc_request_done(host->mmc, mrq);
881 }
882
883 static void sdhci_timeout_timer(unsigned long data)
884 {
885 struct sdhci_host *host;
886 unsigned long flags;
887
888 host = (struct sdhci_host*)data;
889
890 spin_lock_irqsave(&host->lock, flags);
891
892 if (host->mrq) {
893 printk(KERN_ERR "%s: Timeout waiting for hardware "
894 "interrupt.\n", mmc_hostname(host->mmc));
895 sdhci_dumpregs(host);
896
897 if (host->data) {
898 host->data->error = MMC_ERR_TIMEOUT;
899 sdhci_finish_data(host);
900 } else {
901 if (host->cmd)
902 host->cmd->error = MMC_ERR_TIMEOUT;
903 else
904 host->mrq->cmd->error = MMC_ERR_TIMEOUT;
905
906 tasklet_schedule(&host->finish_tasklet);
907 }
908 }
909
910 mmiowb();
911 spin_unlock_irqrestore(&host->lock, flags);
912 }
913
914 /*****************************************************************************\
915 * *
916 * Interrupt handling *
917 * *
918 \*****************************************************************************/
919
920 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
921 {
922 BUG_ON(intmask == 0);
923
924 if (!host->cmd) {
925 printk(KERN_ERR "%s: Got command interrupt even though no "
926 "command operation was in progress.\n",
927 mmc_hostname(host->mmc));
928 sdhci_dumpregs(host);
929 return;
930 }
931
932 if (intmask & SDHCI_INT_RESPONSE)
933 sdhci_finish_command(host);
934 else {
935 if (intmask & SDHCI_INT_TIMEOUT)
936 host->cmd->error = MMC_ERR_TIMEOUT;
937 else if (intmask & SDHCI_INT_CRC)
938 host->cmd->error = MMC_ERR_BADCRC;
939 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
940 host->cmd->error = MMC_ERR_FAILED;
941 else
942 host->cmd->error = MMC_ERR_INVALID;
943
944 tasklet_schedule(&host->finish_tasklet);
945 }
946 }
947
948 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
949 {
950 BUG_ON(intmask == 0);
951
952 if (!host->data) {
953 /*
954 * A data end interrupt is sent together with the response
955 * for the stop command.
956 */
957 if (intmask & SDHCI_INT_DATA_END)
958 return;
959
960 printk(KERN_ERR "%s: Got data interrupt even though no "
961 "data operation was in progress.\n",
962 mmc_hostname(host->mmc));
963 sdhci_dumpregs(host);
964
965 return;
966 }
967
968 if (intmask & SDHCI_INT_DATA_TIMEOUT)
969 host->data->error = MMC_ERR_TIMEOUT;
970 else if (intmask & SDHCI_INT_DATA_CRC)
971 host->data->error = MMC_ERR_BADCRC;
972 else if (intmask & SDHCI_INT_DATA_END_BIT)
973 host->data->error = MMC_ERR_FAILED;
974
975 if (host->data->error != MMC_ERR_NONE)
976 sdhci_finish_data(host);
977 else {
978 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
979 sdhci_transfer_pio(host);
980
981 if (intmask & SDHCI_INT_DATA_END)
982 sdhci_finish_data(host);
983 }
984 }
985
986 static irqreturn_t sdhci_irq(int irq, void *dev_id)
987 {
988 irqreturn_t result;
989 struct sdhci_host* host = dev_id;
990 u32 intmask;
991
992 spin_lock(&host->lock);
993
994 intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
995
996 if (!intmask || intmask == 0xffffffff) {
997 result = IRQ_NONE;
998 goto out;
999 }
1000
1001 DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask);
1002
1003 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1004 writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
1005 host->ioaddr + SDHCI_INT_STATUS);
1006 tasklet_schedule(&host->card_tasklet);
1007 }
1008
1009 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1010
1011 if (intmask & SDHCI_INT_CMD_MASK) {
1012 writel(intmask & SDHCI_INT_CMD_MASK,
1013 host->ioaddr + SDHCI_INT_STATUS);
1014 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
1015 }
1016
1017 if (intmask & SDHCI_INT_DATA_MASK) {
1018 writel(intmask & SDHCI_INT_DATA_MASK,
1019 host->ioaddr + SDHCI_INT_STATUS);
1020 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
1021 }
1022
1023 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1024
1025 if (intmask & SDHCI_INT_BUS_POWER) {
1026 printk(KERN_ERR "%s: Card is consuming too much power!\n",
1027 mmc_hostname(host->mmc));
1028 writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
1029 }
1030
1031 intmask &= SDHCI_INT_BUS_POWER;
1032
1033 if (intmask) {
1034 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
1035 mmc_hostname(host->mmc), intmask);
1036 sdhci_dumpregs(host);
1037
1038 writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
1039 }
1040
1041 result = IRQ_HANDLED;
1042
1043 mmiowb();
1044 out:
1045 spin_unlock(&host->lock);
1046
1047 return result;
1048 }
1049
1050 /*****************************************************************************\
1051 * *
1052 * Suspend/resume *
1053 * *
1054 \*****************************************************************************/
1055
1056 #ifdef CONFIG_PM
1057
1058 static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state)
1059 {
1060 struct sdhci_chip *chip;
1061 int i, ret;
1062
1063 chip = pci_get_drvdata(pdev);
1064 if (!chip)
1065 return 0;
1066
1067 DBG("Suspending...\n");
1068
1069 for (i = 0;i < chip->num_slots;i++) {
1070 if (!chip->hosts[i])
1071 continue;
1072 ret = mmc_suspend_host(chip->hosts[i]->mmc, state);
1073 if (ret) {
1074 for (i--;i >= 0;i--)
1075 mmc_resume_host(chip->hosts[i]->mmc);
1076 return ret;
1077 }
1078 }
1079
1080 pci_save_state(pdev);
1081 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1082
1083 for (i = 0;i < chip->num_slots;i++) {
1084 if (!chip->hosts[i])
1085 continue;
1086 free_irq(chip->hosts[i]->irq, chip->hosts[i]);
1087 }
1088
1089 pci_disable_device(pdev);
1090 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1091
1092 return 0;
1093 }
1094
1095 static int sdhci_resume (struct pci_dev *pdev)
1096 {
1097 struct sdhci_chip *chip;
1098 int i, ret;
1099
1100 chip = pci_get_drvdata(pdev);
1101 if (!chip)
1102 return 0;
1103
1104 DBG("Resuming...\n");
1105
1106 pci_set_power_state(pdev, PCI_D0);
1107 pci_restore_state(pdev);
1108 ret = pci_enable_device(pdev);
1109 if (ret)
1110 return ret;
1111
1112 for (i = 0;i < chip->num_slots;i++) {
1113 if (!chip->hosts[i])
1114 continue;
1115 if (chip->hosts[i]->flags & SDHCI_USE_DMA)
1116 pci_set_master(pdev);
1117 ret = request_irq(chip->hosts[i]->irq, sdhci_irq,
1118 IRQF_SHARED, chip->hosts[i]->slot_descr,
1119 chip->hosts[i]);
1120 if (ret)
1121 return ret;
1122 sdhci_init(chip->hosts[i]);
1123 mmiowb();
1124 ret = mmc_resume_host(chip->hosts[i]->mmc);
1125 if (ret)
1126 return ret;
1127 }
1128
1129 return 0;
1130 }
1131
1132 #else /* CONFIG_PM */
1133
1134 #define sdhci_suspend NULL
1135 #define sdhci_resume NULL
1136
1137 #endif /* CONFIG_PM */
1138
1139 /*****************************************************************************\
1140 * *
1141 * Device probing/removal *
1142 * *
1143 \*****************************************************************************/
1144
1145 static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
1146 {
1147 int ret;
1148 unsigned int version;
1149 struct sdhci_chip *chip;
1150 struct mmc_host *mmc;
1151 struct sdhci_host *host;
1152
1153 u8 first_bar;
1154 unsigned int caps;
1155
1156 chip = pci_get_drvdata(pdev);
1157 BUG_ON(!chip);
1158
1159 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1160 if (ret)
1161 return ret;
1162
1163 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1164
1165 if (first_bar > 5) {
1166 printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n");
1167 return -ENODEV;
1168 }
1169
1170 if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) {
1171 printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n");
1172 return -ENODEV;
1173 }
1174
1175 if (pci_resource_len(pdev, first_bar + slot) != 0x100) {
1176 printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. "
1177 "You may experience problems.\n");
1178 }
1179
1180 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1181 printk(KERN_ERR DRIVER_NAME ": Vendor specific interface. Aborting.\n");
1182 return -ENODEV;
1183 }
1184
1185 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1186 printk(KERN_ERR DRIVER_NAME ": Unknown interface. Aborting.\n");
1187 return -ENODEV;
1188 }
1189
1190 mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
1191 if (!mmc)
1192 return -ENOMEM;
1193
1194 host = mmc_priv(mmc);
1195 host->mmc = mmc;
1196
1197 host->chip = chip;
1198 chip->hosts[slot] = host;
1199
1200 host->bar = first_bar + slot;
1201
1202 host->addr = pci_resource_start(pdev, host->bar);
1203 host->irq = pdev->irq;
1204
1205 DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq);
1206
1207 snprintf(host->slot_descr, 20, "sdhci:slot%d", slot);
1208
1209 ret = pci_request_region(pdev, host->bar, host->slot_descr);
1210 if (ret)
1211 goto free;
1212
1213 host->ioaddr = ioremap_nocache(host->addr,
1214 pci_resource_len(pdev, host->bar));
1215 if (!host->ioaddr) {
1216 ret = -ENOMEM;
1217 goto release;
1218 }
1219
1220 sdhci_reset(host, SDHCI_RESET_ALL);
1221
1222 version = readw(host->ioaddr + SDHCI_HOST_VERSION);
1223 version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
1224 if (version != 0) {
1225 printk(KERN_ERR "%s: Unknown controller version (%d). "
1226 "You may experience problems.\n", host->slot_descr,
1227 version);
1228 }
1229
1230 caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
1231
1232 if (debug_nodma)
1233 DBG("DMA forced off\n");
1234 else if (debug_forcedma) {
1235 DBG("DMA forced on\n");
1236 host->flags |= SDHCI_USE_DMA;
1237 } else if (chip->quirks & SDHCI_QUIRK_FORCE_DMA)
1238 host->flags |= SDHCI_USE_DMA;
1239 else if ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA)
1240 DBG("Controller doesn't have DMA interface\n");
1241 else if (!(caps & SDHCI_CAN_DO_DMA))
1242 DBG("Controller doesn't have DMA capability\n");
1243 else
1244 host->flags |= SDHCI_USE_DMA;
1245
1246 if (host->flags & SDHCI_USE_DMA) {
1247 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1248 printk(KERN_WARNING "%s: No suitable DMA available. "
1249 "Falling back to PIO.\n", host->slot_descr);
1250 host->flags &= ~SDHCI_USE_DMA;
1251 }
1252 }
1253
1254 if (host->flags & SDHCI_USE_DMA)
1255 pci_set_master(pdev);
1256 else /* XXX: Hack to get MMC layer to avoid highmem */
1257 pdev->dma_mask = 0;
1258
1259 host->max_clk =
1260 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1261 if (host->max_clk == 0) {
1262 printk(KERN_ERR "%s: Hardware doesn't specify base clock "
1263 "frequency.\n", host->slot_descr);
1264 ret = -ENODEV;
1265 goto unmap;
1266 }
1267 host->max_clk *= 1000000;
1268
1269 host->timeout_clk =
1270 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1271 if (host->timeout_clk == 0) {
1272 printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
1273 "frequency.\n", host->slot_descr);
1274 ret = -ENODEV;
1275 goto unmap;
1276 }
1277 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1278 host->timeout_clk *= 1000;
1279
1280 /*
1281 * Set host parameters.
1282 */
1283 mmc->ops = &sdhci_ops;
1284 mmc->f_min = host->max_clk / 256;
1285 mmc->f_max = host->max_clk;
1286 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | MMC_CAP_BYTEBLOCK;
1287
1288 if (caps & SDHCI_CAN_DO_HISPD)
1289 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1290
1291 mmc->ocr_avail = 0;
1292 if (caps & SDHCI_CAN_VDD_330)
1293 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
1294 if (caps & SDHCI_CAN_VDD_300)
1295 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
1296 if (caps & SDHCI_CAN_VDD_180)
1297 mmc->ocr_avail |= MMC_VDD_17_18|MMC_VDD_18_19;
1298
1299 if (mmc->ocr_avail == 0) {
1300 printk(KERN_ERR "%s: Hardware doesn't report any "
1301 "support voltages.\n", host->slot_descr);
1302 ret = -ENODEV;
1303 goto unmap;
1304 }
1305
1306 spin_lock_init(&host->lock);
1307
1308 /*
1309 * Maximum number of segments. Hardware cannot do scatter lists.
1310 */
1311 if (host->flags & SDHCI_USE_DMA)
1312 mmc->max_hw_segs = 1;
1313 else
1314 mmc->max_hw_segs = 16;
1315 mmc->max_phys_segs = 16;
1316
1317 /*
1318 * Maximum number of sectors in one transfer. Limited by DMA boundary
1319 * size (512KiB).
1320 */
1321 mmc->max_req_size = 524288;
1322
1323 /*
1324 * Maximum segment size. Could be one segment with the maximum number
1325 * of bytes.
1326 */
1327 mmc->max_seg_size = mmc->max_req_size;
1328
1329 /*
1330 * Maximum block size. This varies from controller to controller and
1331 * is specified in the capabilities register.
1332 */
1333 mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
1334 if (mmc->max_blk_size >= 3) {
1335 printk(KERN_ERR "%s: Invalid maximum block size.\n",
1336 host->slot_descr);
1337 ret = -ENODEV;
1338 goto unmap;
1339 }
1340 mmc->max_blk_size = 512 << mmc->max_blk_size;
1341
1342 /*
1343 * Maximum block count.
1344 */
1345 mmc->max_blk_count = 65535;
1346
1347 /*
1348 * Init tasklets.
1349 */
1350 tasklet_init(&host->card_tasklet,
1351 sdhci_tasklet_card, (unsigned long)host);
1352 tasklet_init(&host->finish_tasklet,
1353 sdhci_tasklet_finish, (unsigned long)host);
1354
1355 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
1356
1357 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1358 host->slot_descr, host);
1359 if (ret)
1360 goto untasklet;
1361
1362 sdhci_init(host);
1363
1364 #ifdef CONFIG_MMC_DEBUG
1365 sdhci_dumpregs(host);
1366 #endif
1367
1368 mmiowb();
1369
1370 mmc_add_host(mmc);
1371
1372 printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n", mmc_hostname(mmc),
1373 host->addr, host->irq,
1374 (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
1375
1376 return 0;
1377
1378 untasklet:
1379 tasklet_kill(&host->card_tasklet);
1380 tasklet_kill(&host->finish_tasklet);
1381 unmap:
1382 iounmap(host->ioaddr);
1383 release:
1384 pci_release_region(pdev, host->bar);
1385 free:
1386 mmc_free_host(mmc);
1387
1388 return ret;
1389 }
1390
1391 static void sdhci_remove_slot(struct pci_dev *pdev, int slot)
1392 {
1393 struct sdhci_chip *chip;
1394 struct mmc_host *mmc;
1395 struct sdhci_host *host;
1396
1397 chip = pci_get_drvdata(pdev);
1398 host = chip->hosts[slot];
1399 mmc = host->mmc;
1400
1401 chip->hosts[slot] = NULL;
1402
1403 mmc_remove_host(mmc);
1404
1405 sdhci_reset(host, SDHCI_RESET_ALL);
1406
1407 free_irq(host->irq, host);
1408
1409 del_timer_sync(&host->timer);
1410
1411 tasklet_kill(&host->card_tasklet);
1412 tasklet_kill(&host->finish_tasklet);
1413
1414 iounmap(host->ioaddr);
1415
1416 pci_release_region(pdev, host->bar);
1417
1418 mmc_free_host(mmc);
1419 }
1420
1421 static int __devinit sdhci_probe(struct pci_dev *pdev,
1422 const struct pci_device_id *ent)
1423 {
1424 int ret, i;
1425 u8 slots, rev;
1426 struct sdhci_chip *chip;
1427
1428 BUG_ON(pdev == NULL);
1429 BUG_ON(ent == NULL);
1430
1431 pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
1432
1433 printk(KERN_INFO DRIVER_NAME
1434 ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n",
1435 pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
1436 (int)rev);
1437
1438 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1439 if (ret)
1440 return ret;
1441
1442 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1443 DBG("found %d slot(s)\n", slots);
1444 if (slots == 0)
1445 return -ENODEV;
1446
1447 ret = pci_enable_device(pdev);
1448 if (ret)
1449 return ret;
1450
1451 chip = kzalloc(sizeof(struct sdhci_chip) +
1452 sizeof(struct sdhci_host*) * slots, GFP_KERNEL);
1453 if (!chip) {
1454 ret = -ENOMEM;
1455 goto err;
1456 }
1457
1458 chip->pdev = pdev;
1459 chip->quirks = ent->driver_data;
1460
1461 if (debug_quirks)
1462 chip->quirks = debug_quirks;
1463
1464 chip->num_slots = slots;
1465 pci_set_drvdata(pdev, chip);
1466
1467 for (i = 0;i < slots;i++) {
1468 ret = sdhci_probe_slot(pdev, i);
1469 if (ret) {
1470 for (i--;i >= 0;i--)
1471 sdhci_remove_slot(pdev, i);
1472 goto free;
1473 }
1474 }
1475
1476 return 0;
1477
1478 free:
1479 pci_set_drvdata(pdev, NULL);
1480 kfree(chip);
1481
1482 err:
1483 pci_disable_device(pdev);
1484 return ret;
1485 }
1486
1487 static void __devexit sdhci_remove(struct pci_dev *pdev)
1488 {
1489 int i;
1490 struct sdhci_chip *chip;
1491
1492 chip = pci_get_drvdata(pdev);
1493
1494 if (chip) {
1495 for (i = 0;i < chip->num_slots;i++)
1496 sdhci_remove_slot(pdev, i);
1497
1498 pci_set_drvdata(pdev, NULL);
1499
1500 kfree(chip);
1501 }
1502
1503 pci_disable_device(pdev);
1504 }
1505
1506 static struct pci_driver sdhci_driver = {
1507 .name = DRIVER_NAME,
1508 .id_table = pci_ids,
1509 .probe = sdhci_probe,
1510 .remove = __devexit_p(sdhci_remove),
1511 .suspend = sdhci_suspend,
1512 .resume = sdhci_resume,
1513 };
1514
1515 /*****************************************************************************\
1516 * *
1517 * Driver init/exit *
1518 * *
1519 \*****************************************************************************/
1520
1521 static int __init sdhci_drv_init(void)
1522 {
1523 printk(KERN_INFO DRIVER_NAME
1524 ": Secure Digital Host Controller Interface driver\n");
1525 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1526
1527 return pci_register_driver(&sdhci_driver);
1528 }
1529
1530 static void __exit sdhci_drv_exit(void)
1531 {
1532 DBG("Exiting\n");
1533
1534 pci_unregister_driver(&sdhci_driver);
1535 }
1536
1537 module_init(sdhci_drv_init);
1538 module_exit(sdhci_drv_exit);
1539
1540 module_param(debug_nodma, uint, 0444);
1541 module_param(debug_forcedma, uint, 0444);
1542 module_param(debug_quirks, uint, 0444);
1543
1544 MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
1545 MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver");
1546 MODULE_LICENSE("GPL");
1547
1548 MODULE_PARM_DESC(debug_nodma, "Forcefully disable DMA transfers. (default 0)");
1549 MODULE_PARM_DESC(debug_forcedma, "Forcefully enable DMA transfers. (default 0)");
1550 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
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