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Hopefully get the Kconfig PCI stuff right, finally.
[linux-2.6/linux-mips.git] / drivers / isdn / hisax / isar.c
blobc4c15b3efbc2ad4b4c74dcf1488965acab44118c
1 /* $Id: isar.c,v 1.17.6.5 2001/09/23 11:51:33 keil Exp $
2 *
3 * isar.c ISAR (Siemens PSB 7110) specific routines
4 *
5 * Author Karsten Keil (keil@isdn4linux.de)
6 *
7 * This file is (c) under GNU General Public License
8 *
9 */
10
11 #include <linux/init.h>
12 #include "hisax.h"
13 #include "isar.h"
14 #include "isdnl1.h"
15 #include <linux/interrupt.h>
16
17 #define DBG_LOADFIRM 0
18 #define DUMP_MBOXFRAME 2
19
20 #define DLE 0x10
21 #define ETX 0x03
22
23
24 const u8 faxmodulation_s[] = "3,24,48,72,73,74,96,97,98,121,122,145,146";
25 const u8 faxmodulation[] = {3,24,48,72,73,74,96,97,98,121,122,145,146};
26 #define FAXMODCNT 13
27
28 static void __isar_setup(struct IsdnCardState *cs);
29 static void isar_pump_cmd(struct BCState *bcs, u8 cmd, u8 para);
30 static inline void ll_deliver_faxstat(struct BCState *bcs, u8 status);
31 static spinlock_t isar_lock = SPIN_LOCK_UNLOCKED;
32
33 static inline u8
34 isar_read_reg(struct IsdnCardState *cs, int mode, u8 addr)
35 {
36 return cs->bc_hw_ops->read_reg(cs, mode, addr);
37 }
38
39 static inline void
40 isar_write_reg(struct IsdnCardState *cs, int mode, u8 addr, u8 val)
41 {
42 cs->bc_hw_ops->write_reg(cs, mode, addr, val);
43 }
44
45 static inline int
46 waitforHIA(struct IsdnCardState *cs, int timeout)
47 {
48
49 while ((isar_read_reg(cs, 0, ISAR_HIA) & 1) && timeout) {
50 udelay(1);
51 timeout--;
52 }
53 if (!timeout)
54 printk(KERN_WARNING "HiSax: ISAR waitforHIA timeout\n");
55 return(timeout);
56 }
57
58
59 int
60 sendmsg(struct IsdnCardState *cs, u8 his, u8 creg, u8 len,
61 u8 *msg)
62 {
63 unsigned long flags;
64 int i;
65
66 if (!waitforHIA(cs, 4000))
67 return(0);
68 #if DUMP_MBOXFRAME
69 if (cs->debug & L1_DEB_HSCX)
70 debugl1(cs, "sendmsg(%02x,%02x,%d)", his, creg, len);
71 #endif
72 spin_lock_irqsave(&isar_lock, flags);
73 isar_write_reg(cs, 0, ISAR_CTRL_H, creg);
74 isar_write_reg(cs, 0, ISAR_CTRL_L, len);
75 isar_write_reg(cs, 0, ISAR_WADR, 0);
76 if (msg && len) {
77 isar_write_reg(cs, 1, ISAR_MBOX, msg[0]);
78 for (i=1; i<len; i++)
79 isar_write_reg(cs, 2, ISAR_MBOX, msg[i]);
80 #if DUMP_MBOXFRAME>1
81 if (cs->debug & L1_DEB_HSCX_FIFO) {
82 char tmp[256], *t;
83
84 i = len;
85 while (i>0) {
86 t = tmp;
87 t += sprintf(t, "sendmbox cnt %d", len);
88 QuickHex(t, &msg[len-i], (i>64) ? 64:i);
89 debugl1(cs, tmp);
90 i -= 64;
91 }
92 }
93 #endif
94 }
95 isar_write_reg(cs, 1, ISAR_HIS, his);
96 spin_unlock_irqrestore(&isar_lock, flags);
97 waitforHIA(cs, 10000);
98 return(1);
99 }
100
101 /* Call only with IRQ disabled !!! */
102 inline void
103 rcv_mbox(struct IsdnCardState *cs, struct isar_reg *ireg, u8 *msg)
104 {
105 int i;
106
107 isar_write_reg(cs, 1, ISAR_RADR, 0);
108 if (msg && ireg->clsb) {
109 msg[0] = isar_read_reg(cs, 1, ISAR_MBOX);
110 for (i=1; i < ireg->clsb; i++)
111 msg[i] = isar_read_reg(cs, 2, ISAR_MBOX);
112 #if DUMP_MBOXFRAME>1
113 if (cs->debug & L1_DEB_HSCX_FIFO) {
114 char tmp[256], *t;
115
116 i = ireg->clsb;
117 while (i>0) {
118 t = tmp;
119 t += sprintf(t, "rcv_mbox cnt %d", ireg->clsb);
120 QuickHex(t, &msg[ireg->clsb-i], (i>64) ? 64:i);
121 debugl1(cs, tmp);
122 i -= 64;
123 }
124 }
125 #endif
126 }
127 isar_write_reg(cs, 1, ISAR_IIA, 0);
128 }
129
130 /* Call only with IRQ disabled !!! */
131 inline void
132 get_irq_infos(struct IsdnCardState *cs, struct isar_reg *ireg)
133 {
134 ireg->iis = isar_read_reg(cs, 1, ISAR_IIS);
135 ireg->cmsb = isar_read_reg(cs, 1, ISAR_CTRL_H);
136 ireg->clsb = isar_read_reg(cs, 1, ISAR_CTRL_L);
137 #if DUMP_MBOXFRAME
138 if (cs->debug & L1_DEB_HSCX)
139 debugl1(cs, "rcv_mbox(%02x,%02x,%d)", ireg->iis, ireg->cmsb,
140 ireg->clsb);
141 #endif
142 }
143
144 int
145 waitrecmsg(struct IsdnCardState *cs, u8 *len,
146 u8 *msg, int maxdelay)
147 {
148 int timeout = 0;
149 unsigned long flags;
150 struct isar_reg *ir = cs->bcs[0].hw.isar.reg;
151
152
153 while((!(isar_read_reg(cs, 0, ISAR_IRQBIT) & ISAR_IRQSTA)) &&
154 (timeout++ < maxdelay))
155 udelay(1);
156 if (timeout >= maxdelay) {
157 printk(KERN_WARNING"isar recmsg IRQSTA timeout\n");
158 return(0);
159 }
160 spin_lock_irqsave(&isar_lock, flags);
161 get_irq_infos(cs, ir);
162 rcv_mbox(cs, ir, msg);
163 *len = ir->clsb;
164 spin_unlock_irqrestore(&isar_lock, flags);
165 return(1);
166 }
167
168 static int
169 ISARVersion(struct IsdnCardState *cs, char *s)
170 {
171 int ver;
172 u8 msg[] = ISAR_MSG_HWVER;
173 u8 tmp[64];
174 u8 len;
175 int debug;
176
177 cs->card_ops->reset(cs);
178 /* disable ISAR IRQ */
179 isar_write_reg(cs, 0, ISAR_IRQBIT, 0);
180 debug = cs->debug;
181 cs->debug &= ~(L1_DEB_HSCX | L1_DEB_HSCX_FIFO);
182 if (!sendmsg(cs, ISAR_HIS_VNR, 0, 3, msg))
183 return(-1);
184 if (!waitrecmsg(cs, &len, tmp, 100000))
185 return(-2);
186 cs->debug = debug;
187 if (cs->bcs[0].hw.isar.reg->iis == ISAR_IIS_VNR) {
188 if (len == 1) {
189 ver = tmp[0] & 0xf;
190 printk(KERN_INFO "%s ISAR version %d\n", s, ver);
191 return(ver);
192 }
193 return(-3);
194 }
195 return(-4);
196 }
197
198 int
199 isar_load_firmware(struct IsdnCardState *cs, u8 *buf)
200 {
201 int ret, size, cnt, debug;
202 u8 len, nom, noc;
203 u_short sadr, left, *sp;
204 u8 *p = buf;
205 u8 *msg, *tmpmsg, *mp, tmp[64];
206 struct isar_reg *ireg = cs->bcs[0].hw.isar.reg;
207
208 struct {u_short sadr;
209 u_short len;
210 u_short d_key;
211 } blk_head;
212
213 #define BLK_HEAD_SIZE 6
214 if (1 != (ret = ISARVersion(cs, "Testing"))) {
215 printk(KERN_ERR"isar_load_firmware wrong isar version %d\n", ret);
216 return(1);
217 }
218 debug = cs->debug;
219 #if DBG_LOADFIRM<2
220 cs->debug &= ~(L1_DEB_HSCX | L1_DEB_HSCX_FIFO);
221 #endif
222 printk(KERN_DEBUG"isar_load_firmware buf %#lx\n", (u_long)buf);
223 if ((ret = verify_area(VERIFY_READ, (void *) p, sizeof(int)))) {
224 printk(KERN_ERR"isar_load_firmware verify_area ret %d\n", ret);
225 return ret;
226 }
227 if ((ret = copy_from_user(&size, p, sizeof(int)))) {
228 printk(KERN_ERR"isar_load_firmware copy_from_user ret %d\n", ret);
229 return -EFAULT;
230 }
231 p += sizeof(int);
232 printk(KERN_DEBUG"isar_load_firmware size: %d\n", size);
233 if ((ret = verify_area(VERIFY_READ, (void *) p, size))) {
234 printk(KERN_ERR"isar_load_firmware verify_area ret %d\n", ret);
235 return ret;
236 }
237 cnt = 0;
238 /* disable ISAR IRQ */
239 isar_write_reg(cs, 0, ISAR_IRQBIT, 0);
240 if (!(msg = kmalloc(256, GFP_KERNEL))) {
241 printk(KERN_ERR"isar_load_firmware no buffer\n");
242 return (1);
243 }
244 if (!(tmpmsg = kmalloc(256, GFP_KERNEL))) {
245 printk(KERN_ERR"isar_load_firmware no tmp buffer\n");
246 kfree(msg);
247 return (1);
248 }
249 while (cnt < size) {
250 if ((ret = copy_from_user(&blk_head, p, BLK_HEAD_SIZE))) {
251 printk(KERN_ERR"isar_load_firmware copy_from_user ret %d\n", ret);
252 ret = -EFAULT;
253 goto reterror;
254 }
255 #ifdef __BIG_ENDIAN
256 sadr = (blk_head.sadr & 0xff)*256 + blk_head.sadr/256;
257 blk_head.sadr = sadr;
258 sadr = (blk_head.len & 0xff)*256 + blk_head.len/256;
259 blk_head.len = sadr;
260 sadr = (blk_head.d_key & 0xff)*256 + blk_head.d_key/256;
261 blk_head.d_key = sadr;
262 #endif /* __BIG_ENDIAN */
263 cnt += BLK_HEAD_SIZE;
264 p += BLK_HEAD_SIZE;
265 printk(KERN_DEBUG"isar firmware block (%#x,%5d,%#x)\n",
266 blk_head.sadr, blk_head.len, blk_head.d_key & 0xff);
267 sadr = blk_head.sadr;
268 left = blk_head.len;
269 if (!sendmsg(cs, ISAR_HIS_DKEY, blk_head.d_key & 0xff, 0, NULL)) {
270 printk(KERN_ERR"isar sendmsg dkey failed\n");
271 ret = 1;goto reterror;
272 }
273 if (!waitrecmsg(cs, &len, tmp, 100000)) {
274 printk(KERN_ERR"isar waitrecmsg dkey failed\n");
275 ret = 1;goto reterror;
276 }
277 if ((ireg->iis != ISAR_IIS_DKEY) || ireg->cmsb || len) {
278 printk(KERN_ERR"isar wrong dkey response (%x,%x,%x)\n",
279 ireg->iis, ireg->cmsb, len);
280 ret = 1;goto reterror;
281 }
282 while (left>0) {
283 if (left > 126)
284 noc = 126;
285 else
286 noc = left;
287 nom = 2*noc;
288 mp = msg;
289 *mp++ = sadr / 256;
290 *mp++ = sadr % 256;
291 left -= noc;
292 *mp++ = noc;
293 if ((ret = copy_from_user(tmpmsg, p, nom))) {
294 printk(KERN_ERR"isar_load_firmware copy_from_user ret %d\n", ret);
295 ret = -EFAULT;
296 goto reterror;
297 }
298 p += nom;
299 cnt += nom;
300 nom += 3;
301 sp = (u_short *)tmpmsg;
302 #if DBG_LOADFIRM
303 printk(KERN_DEBUG"isar: load %3d words at %04x left %d\n",
304 noc, sadr, left);
305 #endif
306 sadr += noc;
307 while(noc) {
308 #ifdef __BIG_ENDIAN
309 *mp++ = *sp % 256;
310 *mp++ = *sp / 256;
311 #else
312 *mp++ = *sp / 256;
313 *mp++ = *sp % 256;
314 #endif /* __BIG_ENDIAN */
315 sp++;
316 noc--;
317 }
318 if (!sendmsg(cs, ISAR_HIS_FIRM, 0, nom, msg)) {
319 printk(KERN_ERR"isar sendmsg prog failed\n");
320 ret = 1;goto reterror;
321 }
322 if (!waitrecmsg(cs, &len, tmp, 100000)) {
323 printk(KERN_ERR"isar waitrecmsg prog failed\n");
324 ret = 1;goto reterror;
325 }
326 if ((ireg->iis != ISAR_IIS_FIRM) || ireg->cmsb || len) {
327 printk(KERN_ERR"isar wrong prog response (%x,%x,%x)\n",
328 ireg->iis, ireg->cmsb, len);
329 ret = 1;goto reterror;
330 }
331 }
332 printk(KERN_DEBUG"isar firmware block %5d words loaded\n",
333 blk_head.len);
334 }
335 /* 10ms delay */
336 cnt = 10;
337 while (cnt--)
338 udelay(1000);
339 msg[0] = 0xff;
340 msg[1] = 0xfe;
341 ireg->bstat = 0;
342 if (!sendmsg(cs, ISAR_HIS_STDSP, 0, 2, msg)) {
343 printk(KERN_ERR"isar sendmsg start dsp failed\n");
344 ret = 1;goto reterror;
345 }
346 if (!waitrecmsg(cs, &len, tmp, 100000)) {
347 printk(KERN_ERR"isar waitrecmsg start dsp failed\n");
348 ret = 1;goto reterror;
349 }
350 if ((ireg->iis != ISAR_IIS_STDSP) || ireg->cmsb || len) {
351 printk(KERN_ERR"isar wrong start dsp response (%x,%x,%x)\n",
352 ireg->iis, ireg->cmsb, len);
353 ret = 1;goto reterror;
354 } else
355 printk(KERN_DEBUG"isar start dsp success\n");
356 /* NORMAL mode entered */
357 /* Enable IRQs of ISAR */
358 isar_write_reg(cs, 0, ISAR_IRQBIT, ISAR_IRQSTA);
359 cnt = 1000; /* max 1s */
360 while ((!ireg->bstat) && cnt) {
361 udelay(1000);
362 cnt--;
363 }
364 if (!cnt) {
365 printk(KERN_ERR"isar no general status event received\n");
366 ret = 1;goto reterror;
367 } else {
368 printk(KERN_DEBUG"isar general status event %x\n",
369 ireg->bstat);
370 }
371 /* 10ms delay */
372 cnt = 10;
373 while (cnt--)
374 udelay(1000);
375 ireg->iis = 0;
376 if (!sendmsg(cs, ISAR_HIS_DIAG, ISAR_CTRL_STST, 0, NULL)) {
377 printk(KERN_ERR"isar sendmsg self tst failed\n");
378 ret = 1;goto reterror;
379 }
380 cnt = 10000; /* max 100 ms */
381 while ((ireg->iis != ISAR_IIS_DIAG) && cnt) {
382 udelay(10);
383 cnt--;
384 }
385 udelay(1000);
386 if (!cnt) {
387 printk(KERN_ERR"isar no self tst response\n");
388 ret = 1;goto reterror;
389 }
390 if ((ireg->cmsb == ISAR_CTRL_STST) && (ireg->clsb == 1)
391 && (ireg->par[0] == 0)) {
392 printk(KERN_DEBUG"isar selftest OK\n");
393 } else {
394 printk(KERN_DEBUG"isar selftest not OK %x/%x/%x\n",
395 ireg->cmsb, ireg->clsb, ireg->par[0]);
396 ret = 1;goto reterror;
397 }
398 ireg->iis = 0;
399 if (!sendmsg(cs, ISAR_HIS_DIAG, ISAR_CTRL_SWVER, 0, NULL)) {
400 printk(KERN_ERR"isar RQST SVN failed\n");
401 ret = 1;goto reterror;
402 }
403 cnt = 30000; /* max 300 ms */
404 while ((ireg->iis != ISAR_IIS_DIAG) && cnt) {
405 udelay(10);
406 cnt--;
407 }
408 udelay(1000);
409 if (!cnt) {
410 printk(KERN_ERR"isar no SVN response\n");
411 ret = 1;goto reterror;
412 } else {
413 if ((ireg->cmsb == ISAR_CTRL_SWVER) && (ireg->clsb == 1))
414 printk(KERN_DEBUG"isar software version %#x\n",
415 ireg->par[0]);
416 else {
417 printk(KERN_ERR"isar wrong swver response (%x,%x) cnt(%d)\n",
418 ireg->cmsb, ireg->clsb, cnt);
419 ret = 1;goto reterror;
420 }
421 }
422 cs->debug = debug;
423 __isar_setup(cs);
424 ret = 0;
425 reterror:
426 cs->debug = debug;
427 if (ret)
428 /* disable ISAR IRQ */
429 isar_write_reg(cs, 0, ISAR_IRQBIT, 0);
430 kfree(msg);
431 kfree(tmpmsg);
432 return(ret);
433 }
434
435 extern void BChannel_bh(struct BCState *);
436
437 static void
438 isar_bh(void *data)
439 {
440 struct BCState *bcs = data;
441
442 BChannel_bh(bcs);
443 if (test_and_clear_bit(B_LL_NOCARRIER, &bcs->event))
444 ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_NOCARR);
445 if (test_and_clear_bit(B_LL_CONNECT, &bcs->event))
446 ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_CONNECT);
447 if (test_and_clear_bit(B_LL_OK, &bcs->event))
448 ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_OK);
449 }
450
451 static inline void
452 send_DLE_ETX(struct BCState *bcs)
453 {
454 u8 dleetx[2] = {DLE,ETX};
455 struct sk_buff *skb;
456
457 if ((skb = dev_alloc_skb(2))) {
458 memcpy(skb_put(skb, 2), dleetx, 2);
459 skb_queue_tail(&bcs->rqueue, skb);
460 sched_b_event(bcs, B_RCVBUFREADY);
461 } else {
462 printk(KERN_WARNING "HiSax: skb out of memory\n");
463 }
464 }
465
466 static inline int
467 dle_count(unsigned char *buf, int len)
468 {
469 int count = 0;
470
471 while (len--)
472 if (*buf++ == DLE)
473 count++;
474 return count;
475 }
476
477 static inline void
478 insert_dle(unsigned char *dest, unsigned char *src, int count) {
479 /* <DLE> in input stream have to be flagged as <DLE><DLE> */
480 while (count--) {
481 *dest++ = *src;
482 if (*src++ == DLE)
483 *dest++ = DLE;
484 }
485 }
486
487 static inline void
488 isar_rcv_frame(struct IsdnCardState *cs, struct BCState *bcs)
489 {
490 u8 *ptr;
491 struct sk_buff *skb;
492 struct isar_reg *ireg = bcs->hw.isar.reg;
493
494 if (!ireg->clsb) {
495 debugl1(cs, "isar zero len frame");
496 isar_write_reg(cs, 1, ISAR_IIA, 0);
497 return;
498 }
499 switch (bcs->mode) {
500 case L1_MODE_NULL:
501 debugl1(cs, "isar mode 0 spurious IIS_RDATA %x/%x/%x",
502 ireg->iis, ireg->cmsb, ireg->clsb);
503 printk(KERN_WARNING"isar mode 0 spurious IIS_RDATA %x/%x/%x\n",
504 ireg->iis, ireg->cmsb, ireg->clsb);
505 isar_write_reg(cs, 1, ISAR_IIA, 0);
506 break;
507 case L1_MODE_TRANS:
508 case L1_MODE_V32:
509 if ((skb = dev_alloc_skb(ireg->clsb))) {
510 rcv_mbox(cs, ireg, (u8 *)skb_put(skb, ireg->clsb));
511 skb_queue_tail(&bcs->rqueue, skb);
512 sched_b_event(bcs, B_RCVBUFREADY);
513 } else {
514 printk(KERN_WARNING "HiSax: skb out of memory\n");
515 isar_write_reg(cs, 1, ISAR_IIA, 0);
516 }
517 break;
518 case L1_MODE_HDLC:
519 if ((bcs->hw.isar.rcvidx + ireg->clsb) > HSCX_BUFMAX) {
520 if (cs->debug & L1_DEB_WARN)
521 debugl1(cs, "isar_rcv_frame: incoming packet too large");
522 isar_write_reg(cs, 1, ISAR_IIA, 0);
523 bcs->hw.isar.rcvidx = 0;
524 } else if (ireg->cmsb & HDLC_ERROR) {
525 if (cs->debug & L1_DEB_WARN)
526 debugl1(cs, "isar frame error %x len %d",
527 ireg->cmsb, ireg->clsb);
528 #ifdef ERROR_STATISTIC
529 if (ireg->cmsb & HDLC_ERR_RER)
530 bcs->err_inv++;
531 if (ireg->cmsb & HDLC_ERR_CER)
532 bcs->err_crc++;
533 #endif
534 bcs->hw.isar.rcvidx = 0;
535 isar_write_reg(cs, 1, ISAR_IIA, 0);
536 } else {
537 if (ireg->cmsb & HDLC_FSD)
538 bcs->hw.isar.rcvidx = 0;
539 ptr = bcs->hw.isar.rcvbuf + bcs->hw.isar.rcvidx;
540 bcs->hw.isar.rcvidx += ireg->clsb;
541 rcv_mbox(cs, ireg, ptr);
542 if (ireg->cmsb & HDLC_FED) {
543 if (bcs->hw.isar.rcvidx < 3) { /* last 2 bytes are the FCS */
544 if (cs->debug & L1_DEB_WARN)
545 debugl1(cs, "isar frame to short %d",
546 bcs->hw.isar.rcvidx);
547 } else if (!(skb = dev_alloc_skb(bcs->hw.isar.rcvidx-2))) {
548 printk(KERN_WARNING "ISAR: receive out of memory\n");
549 } else {
550 memcpy(skb_put(skb, bcs->hw.isar.rcvidx-2),
551 bcs->hw.isar.rcvbuf, bcs->hw.isar.rcvidx-2);
552 skb_queue_tail(&bcs->rqueue, skb);
553 sched_b_event(bcs, B_RCVBUFREADY);
554 }
555 bcs->hw.isar.rcvidx = 0;
556 }
557 }
558 break;
559 case L1_MODE_FAX:
560 if (bcs->hw.isar.state != STFAX_ACTIV) {
561 if (cs->debug & L1_DEB_WARN)
562 debugl1(cs, "isar_rcv_frame: not ACTIV");
563 isar_write_reg(cs, 1, ISAR_IIA, 0);
564 bcs->hw.isar.rcvidx = 0;
565 break;
566 }
567 if (bcs->hw.isar.cmd == PCTRL_CMD_FRM) {
568 rcv_mbox(cs, ireg, bcs->hw.isar.rcvbuf);
569 bcs->hw.isar.rcvidx = ireg->clsb +
570 dle_count(bcs->hw.isar.rcvbuf, ireg->clsb);
571 if (cs->debug & L1_DEB_HSCX)
572 debugl1(cs, "isar_rcv_frame: raw(%d) dle(%d)",
573 ireg->clsb, bcs->hw.isar.rcvidx);
574 if ((skb = dev_alloc_skb(bcs->hw.isar.rcvidx))) {
575 insert_dle((u8 *)skb_put(skb, bcs->hw.isar.rcvidx),
576 bcs->hw.isar.rcvbuf, ireg->clsb);
577 skb_queue_tail(&bcs->rqueue, skb);
578 sched_b_event(bcs, B_RCVBUFREADY);
579 if (ireg->cmsb & SART_NMD) { /* ABORT */
580 if (cs->debug & L1_DEB_WARN)
581 debugl1(cs, "isar_rcv_frame: no more data");
582 isar_write_reg(cs, 1, ISAR_IIA, 0);
583 bcs->hw.isar.rcvidx = 0;
584 send_DLE_ETX(bcs);
585 sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) |
586 ISAR_HIS_PUMPCTRL, PCTRL_CMD_ESC,
587 0, NULL);
588 bcs->hw.isar.state = STFAX_ESCAPE;
589 sched_b_event(bcs, B_LL_NOCARRIER);
590 }
591 } else {
592 printk(KERN_WARNING "HiSax: skb out of memory\n");
593 isar_write_reg(cs, 1, ISAR_IIA, 0);
594 }
595 break;
596 }
597 if (bcs->hw.isar.cmd != PCTRL_CMD_FRH) {
598 if (cs->debug & L1_DEB_WARN)
599 debugl1(cs, "isar_rcv_frame: unknown fax mode %x",
600 bcs->hw.isar.cmd);
601 isar_write_reg(cs, 1, ISAR_IIA, 0);
602 bcs->hw.isar.rcvidx = 0;
603 break;
604 }
605 /* PCTRL_CMD_FRH */
606 if ((bcs->hw.isar.rcvidx + ireg->clsb) > HSCX_BUFMAX) {
607 if (cs->debug & L1_DEB_WARN)
608 debugl1(cs, "isar_rcv_frame: incoming packet too large");
609 isar_write_reg(cs, 1, ISAR_IIA, 0);
610 bcs->hw.isar.rcvidx = 0;
611 } else if (ireg->cmsb & HDLC_ERROR) {
612 if (cs->debug & L1_DEB_WARN)
613 debugl1(cs, "isar frame error %x len %d",
614 ireg->cmsb, ireg->clsb);
615 bcs->hw.isar.rcvidx = 0;
616 isar_write_reg(cs, 1, ISAR_IIA, 0);
617 } else {
618 if (ireg->cmsb & HDLC_FSD)
619 bcs->hw.isar.rcvidx = 0;
620 ptr = bcs->hw.isar.rcvbuf + bcs->hw.isar.rcvidx;
621 bcs->hw.isar.rcvidx += ireg->clsb;
622 rcv_mbox(cs, ireg, ptr);
623 if (ireg->cmsb & HDLC_FED) {
624 int len = bcs->hw.isar.rcvidx +
625 dle_count(bcs->hw.isar.rcvbuf, bcs->hw.isar.rcvidx);
626 if (bcs->hw.isar.rcvidx < 3) { /* last 2 bytes are the FCS */
627 if (cs->debug & L1_DEB_WARN)
628 debugl1(cs, "isar frame to short %d",
629 bcs->hw.isar.rcvidx);
630 } else if (!(skb = dev_alloc_skb(bcs->hw.isar.rcvidx))) {
631 printk(KERN_WARNING "ISAR: receive out of memory\n");
632 } else {
633 insert_dle((u8 *)skb_put(skb, len),
634 bcs->hw.isar.rcvbuf,
635 bcs->hw.isar.rcvidx);
636 skb_queue_tail(&bcs->rqueue, skb);
637 sched_b_event(bcs, B_RCVBUFREADY);
638 send_DLE_ETX(bcs);
639 sched_b_event(bcs, B_LL_OK);
640 }
641 bcs->hw.isar.rcvidx = 0;
642 }
643 }
644 if (ireg->cmsb & SART_NMD) { /* ABORT */
645 if (cs->debug & L1_DEB_WARN)
646 debugl1(cs, "isar_rcv_frame: no more data");
647 isar_write_reg(cs, 1, ISAR_IIA, 0);
648 bcs->hw.isar.rcvidx = 0;
649 send_DLE_ETX(bcs);
650 sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) |
651 ISAR_HIS_PUMPCTRL, PCTRL_CMD_ESC, 0, NULL);
652 bcs->hw.isar.state = STFAX_ESCAPE;
653 sched_b_event(bcs, B_LL_NOCARRIER);
654 }
655 break;
656 default:
657 printk(KERN_ERR"isar_rcv_frame mode (%x)error\n", bcs->mode);
658 isar_write_reg(cs, 1, ISAR_IIA, 0);
659 break;
660 }
661 }
662
663 void
664 isar_fill_fifo(struct BCState *bcs)
665 {
666 struct IsdnCardState *cs = bcs->cs;
667 int count;
668 u8 msb;
669 u8 *ptr;
670
671 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
672 debugl1(cs, "isar_fill_fifo");
673 if (!bcs->tx_skb)
674 return;
675 if (bcs->tx_skb->len <= 0)
676 return;
677 if (!(bcs->hw.isar.reg->bstat &
678 (bcs->hw.isar.dpath == 1 ? BSTAT_RDM1 : BSTAT_RDM2)))
679 return;
680 if (bcs->tx_skb->len > bcs->hw.isar.mml) {
681 msb = 0;
682 count = bcs->hw.isar.mml;
683 } else {
684 count = bcs->tx_skb->len;
685 msb = HDLC_FED;
686 }
687 ptr = bcs->tx_skb->data;
688 if (!bcs->count) {
689 msb |= HDLC_FST;
690 if ((bcs->mode == L1_MODE_FAX) &&
691 (bcs->hw.isar.cmd == PCTRL_CMD_FTH)) {
692 if (bcs->tx_skb->len > 1) {
693 if ((ptr[0]== 0xff) && (ptr[1] == 0x13))
694 /* last frame */
695 test_and_set_bit(BC_FLG_LASTDATA,
696 &bcs->Flag);
697 }
698 }
699 }
700 skb_pull(bcs->tx_skb, count);
701 bcs->tx_cnt -= count;
702 bcs->count += count;
703 switch (bcs->mode) {
704 case L1_MODE_NULL:
705 printk(KERN_ERR"isar_fill_fifo wrong mode 0\n");
706 break;
707 case L1_MODE_TRANS:
708 case L1_MODE_V32:
709 sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) | ISAR_HIS_SDATA,
710 0, count, ptr);
711 break;
712 case L1_MODE_HDLC:
713 sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) | ISAR_HIS_SDATA,
714 msb, count, ptr);
715 break;
716 case L1_MODE_FAX:
717 if (bcs->hw.isar.state != STFAX_ACTIV) {
718 if (cs->debug & L1_DEB_WARN)
719 debugl1(cs, "isar_fill_fifo: not ACTIV");
720 } else if (bcs->hw.isar.cmd == PCTRL_CMD_FTH) {
721 sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) | ISAR_HIS_SDATA,
722 msb, count, ptr);
723 } else if (bcs->hw.isar.cmd == PCTRL_CMD_FTM) {
724 sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) | ISAR_HIS_SDATA,
725 0, count, ptr);
726 } else {
727 if (cs->debug & L1_DEB_WARN)
728 debugl1(cs, "isar_fill_fifo: not FTH/FTM");
729 }
730 break;
731 default:
732 if (cs->debug)
733 debugl1(cs, "isar_fill_fifo mode(%x) error", bcs->mode);
734 printk(KERN_ERR"isar_fill_fifo mode(%x) error\n", bcs->mode);
735 break;
736 }
737 }
738
739 inline
740 struct BCState *sel_bcs_isar(struct IsdnCardState *cs, u8 dpath)
741 {
742 if ((!dpath) || (dpath == 3))
743 return(NULL);
744 if (cs->bcs[0].hw.isar.dpath == dpath)
745 return(&cs->bcs[0]);
746 if (cs->bcs[1].hw.isar.dpath == dpath)
747 return(&cs->bcs[1]);
748 return(NULL);
749 }
750
751 inline void
752 send_frames(struct BCState *bcs)
753 {
754 if (bcs->tx_skb) {
755 if (bcs->tx_skb->len) {
756 isar_fill_fifo(bcs);
757 return;
758 } else {
759 xmit_complete_b(bcs);
760 if (bcs->mode == L1_MODE_FAX) {
761 if (bcs->hw.isar.cmd == PCTRL_CMD_FTH) {
762 if (test_bit(BC_FLG_LASTDATA, &bcs->Flag)) {
763 test_and_set_bit(BC_FLG_NMD_DATA, &bcs->Flag);
764 }
765 } else if (bcs->hw.isar.cmd == PCTRL_CMD_FTM) {
766 if (test_bit(BC_FLG_DLEETX, &bcs->Flag)) {
767 test_and_set_bit(BC_FLG_LASTDATA, &bcs->Flag);
768 test_and_set_bit(BC_FLG_NMD_DATA, &bcs->Flag);
769 }
770 }
771 }
772 bcs->count = 0;
773 }
774 }
775 if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
776 bcs->count = 0;
777 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
778 isar_fill_fifo(bcs);
779 } else {
780 if (test_and_clear_bit(BC_FLG_DLEETX, &bcs->Flag)) {
781 if (test_and_clear_bit(BC_FLG_LASTDATA, &bcs->Flag)) {
782 if (test_and_clear_bit(BC_FLG_NMD_DATA, &bcs->Flag)) {
783 u8 dummy = 0;
784 sendmsg(bcs->cs, SET_DPS(bcs->hw.isar.dpath) |
785 ISAR_HIS_SDATA, 0x01, 1, &dummy);
786 }
787 test_and_set_bit(BC_FLG_LL_OK, &bcs->Flag);
788 } else {
789 sched_b_event(bcs, B_LL_CONNECT);
790 }
791 }
792 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
793 sched_b_event(bcs, B_XMTBUFREADY);
794 }
795 }
796
797 inline void
798 check_send(struct IsdnCardState *cs, u8 rdm)
799 {
800 struct BCState *bcs;
801
802 if (rdm & BSTAT_RDM1) {
803 if ((bcs = sel_bcs_isar(cs, 1))) {
804 if (bcs->mode) {
805 send_frames(bcs);
806 }
807 }
808 }
809 if (rdm & BSTAT_RDM2) {
810 if ((bcs = sel_bcs_isar(cs, 2))) {
811 if (bcs->mode) {
812 send_frames(bcs);
813 }
814 }
815 }
816
817 }
818
819 const char *dmril[] = {"NO SPEED", "1200/75", "NODEF2", "75/1200", "NODEF4",
820 "300", "600", "1200", "2400", "4800", "7200",
821 "9600nt", "9600t", "12000", "14400", "WRONG"};
822 const char *dmrim[] = {"NO MOD", "NO DEF", "V32/V32b", "V22", "V21",
823 "Bell103", "V23", "Bell202", "V17", "V29", "V27ter"};
824
825 static void
826 isar_pump_status_rsp(struct BCState *bcs, struct isar_reg *ireg) {
827 struct IsdnCardState *cs = bcs->cs;
828 u8 ril = ireg->par[0];
829 u8 rim;
830
831 if (!test_and_clear_bit(ISAR_RATE_REQ, &bcs->hw.isar.reg->Flags))
832 return;
833 if (ril > 14) {
834 if (cs->debug & L1_DEB_WARN)
835 debugl1(cs, "wrong pstrsp ril=%d",ril);
836 ril = 15;
837 }
838 switch(ireg->par[1]) {
839 case 0:
840 rim = 0;
841 break;
842 case 0x20:
843 rim = 2;
844 break;
845 case 0x40:
846 rim = 3;
847 break;
848 case 0x41:
849 rim = 4;
850 break;
851 case 0x51:
852 rim = 5;
853 break;
854 case 0x61:
855 rim = 6;
856 break;
857 case 0x71:
858 rim = 7;
859 break;
860 case 0x82:
861 rim = 8;
862 break;
863 case 0x92:
864 rim = 9;
865 break;
866 case 0xa2:
867 rim = 10;
868 break;
869 default:
870 rim = 1;
871 break;
872 }
873 sprintf(bcs->hw.isar.conmsg,"%s %s", dmril[ril], dmrim[rim]);
874 bcs->conmsg = bcs->hw.isar.conmsg;
875 if (cs->debug & L1_DEB_HSCX)
876 debugl1(cs, "pump strsp %s", bcs->conmsg);
877 }
878
879 static void
880 isar_pump_statev_modem(struct BCState *bcs, u8 devt) {
881 struct IsdnCardState *cs = bcs->cs;
882 u8 dps = SET_DPS(bcs->hw.isar.dpath);
883
884 switch(devt) {
885 case PSEV_10MS_TIMER:
886 if (cs->debug & L1_DEB_HSCX)
887 debugl1(cs, "pump stev TIMER");
888 break;
889 case PSEV_CON_ON:
890 if (cs->debug & L1_DEB_HSCX)
891 debugl1(cs, "pump stev CONNECT");
892 l1_msg_b(bcs->st, PH_ACTIVATE | REQUEST, NULL);
893 break;
894 case PSEV_CON_OFF:
895 if (cs->debug & L1_DEB_HSCX)
896 debugl1(cs, "pump stev NO CONNECT");
897 sendmsg(cs, dps | ISAR_HIS_PSTREQ, 0, 0, NULL);
898 l1_msg_b(bcs->st, PH_DEACTIVATE | REQUEST, NULL);
899 break;
900 case PSEV_V24_OFF:
901 if (cs->debug & L1_DEB_HSCX)
902 debugl1(cs, "pump stev V24 OFF");
903 break;
904 case PSEV_CTS_ON:
905 if (cs->debug & L1_DEB_HSCX)
906 debugl1(cs, "pump stev CTS ON");
907 break;
908 case PSEV_CTS_OFF:
909 if (cs->debug & L1_DEB_HSCX)
910 debugl1(cs, "pump stev CTS OFF");
911 break;
912 case PSEV_DCD_ON:
913 if (cs->debug & L1_DEB_HSCX)
914 debugl1(cs, "pump stev CARRIER ON");
915 test_and_set_bit(ISAR_RATE_REQ, &bcs->hw.isar.reg->Flags);
916 sendmsg(cs, dps | ISAR_HIS_PSTREQ, 0, 0, NULL);
917 break;
918 case PSEV_DCD_OFF:
919 if (cs->debug & L1_DEB_HSCX)
920 debugl1(cs, "pump stev CARRIER OFF");
921 break;
922 case PSEV_DSR_ON:
923 if (cs->debug & L1_DEB_HSCX)
924 debugl1(cs, "pump stev DSR ON");
925 break;
926 case PSEV_DSR_OFF:
927 if (cs->debug & L1_DEB_HSCX)
928 debugl1(cs, "pump stev DSR_OFF");
929 break;
930 case PSEV_REM_RET:
931 if (cs->debug & L1_DEB_HSCX)
932 debugl1(cs, "pump stev REMOTE RETRAIN");
933 break;
934 case PSEV_REM_REN:
935 if (cs->debug & L1_DEB_HSCX)
936 debugl1(cs, "pump stev REMOTE RENEGOTIATE");
937 break;
938 case PSEV_GSTN_CLR:
939 if (cs->debug & L1_DEB_HSCX)
940 debugl1(cs, "pump stev GSTN CLEAR", devt);
941 break;
942 default:
943 if (cs->debug & L1_DEB_HSCX)
944 debugl1(cs, "unknown pump stev %x", devt);
945 break;
946 }
947 }
948
949 static inline void
950 ll_deliver_faxstat(struct BCState *bcs, u8 status)
951 {
952 isdn_ctrl ic;
953 struct Channel *chanp = (struct Channel *) bcs->st->lli.userdata;
954
955 if (bcs->cs->debug & L1_DEB_HSCX)
956 debugl1(bcs->cs, "HL->LL FAXIND %x", status);
957 ic.driver = bcs->cs->myid;
958 ic.command = ISDN_STAT_FAXIND;
959 ic.arg = chanp->chan;
960 ic.parm.aux.cmd = status;
961 bcs->cs->iif.statcallb(&ic);
962 }
963
964 static void
965 isar_pump_statev_fax(struct BCState *bcs, u8 devt) {
966 struct IsdnCardState *cs = bcs->cs;
967 u8 dps = SET_DPS(bcs->hw.isar.dpath);
968 u8 p1;
969
970 switch(devt) {
971 case PSEV_10MS_TIMER:
972 if (cs->debug & L1_DEB_HSCX)
973 debugl1(cs, "pump stev TIMER");
974 break;
975 case PSEV_RSP_READY:
976 if (cs->debug & L1_DEB_HSCX)
977 debugl1(cs, "pump stev RSP_READY");
978 bcs->hw.isar.state = STFAX_READY;
979 l1_msg_b(bcs->st, PH_ACTIVATE | REQUEST, NULL);
980 if (test_bit(BC_FLG_ORIG, &bcs->Flag)) {
981 isar_pump_cmd(bcs, ISDN_FAX_CLASS1_FRH, 3);
982 } else {
983 isar_pump_cmd(bcs, ISDN_FAX_CLASS1_FTH, 3);
984 }
985 break;
986 case PSEV_LINE_TX_H:
987 if (bcs->hw.isar.state == STFAX_LINE) {
988 if (cs->debug & L1_DEB_HSCX)
989 debugl1(cs, "pump stev LINE_TX_H");
990 bcs->hw.isar.state = STFAX_CONT;
991 sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, PCTRL_CMD_CONT, 0, NULL);
992 } else {
993 if (cs->debug & L1_DEB_WARN)
994 debugl1(cs, "pump stev LINE_TX_H wrong st %x",
995 bcs->hw.isar.state);
996 }
997 break;
998 case PSEV_LINE_RX_H:
999 if (bcs->hw.isar.state == STFAX_LINE) {
1000 if (cs->debug & L1_DEB_HSCX)
1001 debugl1(cs, "pump stev LINE_RX_H");
1002 bcs->hw.isar.state = STFAX_CONT;
1003 sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, PCTRL_CMD_CONT, 0, NULL);
1004 } else {
1005 if (cs->debug & L1_DEB_WARN)
1006 debugl1(cs, "pump stev LINE_RX_H wrong st %x",
1007 bcs->hw.isar.state);
1008 }
1009 break;
1010 case PSEV_LINE_TX_B:
1011 if (bcs->hw.isar.state == STFAX_LINE) {
1012 if (cs->debug & L1_DEB_HSCX)
1013 debugl1(cs, "pump stev LINE_TX_B");
1014 bcs->hw.isar.state = STFAX_CONT;
1015 sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, PCTRL_CMD_CONT, 0, NULL);
1016 } else {
1017 if (cs->debug & L1_DEB_WARN)
1018 debugl1(cs, "pump stev LINE_TX_B wrong st %x",
1019 bcs->hw.isar.state);
1020 }
1021 break;
1022 case PSEV_LINE_RX_B:
1023 if (bcs->hw.isar.state == STFAX_LINE) {
1024 if (cs->debug & L1_DEB_HSCX)
1025 debugl1(cs, "pump stev LINE_RX_B");
1026 bcs->hw.isar.state = STFAX_CONT;
1027 sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, PCTRL_CMD_CONT, 0, NULL);
1028 } else {
1029 if (cs->debug & L1_DEB_WARN)
1030 debugl1(cs, "pump stev LINE_RX_B wrong st %x",
1031 bcs->hw.isar.state);
1032 }
1033 break;
1034 case PSEV_RSP_CONN:
1035 if (bcs->hw.isar.state == STFAX_CONT) {
1036 if (cs->debug & L1_DEB_HSCX)
1037 debugl1(cs, "pump stev RSP_CONN");
1038 bcs->hw.isar.state = STFAX_ACTIV;
1039 test_and_set_bit(ISAR_RATE_REQ, &bcs->hw.isar.reg->Flags);
1040 sendmsg(cs, dps | ISAR_HIS_PSTREQ, 0, 0, NULL);
1041 if (bcs->hw.isar.cmd == PCTRL_CMD_FTH) {
1042 /* 1s Flags before data */
1043 if (test_and_set_bit(BC_FLG_FTI_RUN, &bcs->Flag))
1044 del_timer(&bcs->hw.isar.ftimer);
1045 /* 1000 ms */
1046 bcs->hw.isar.ftimer.expires =
1047 jiffies + ((1000 * HZ)/1000);
1048 test_and_set_bit(BC_FLG_LL_CONN,
1049 &bcs->Flag);
1050 add_timer(&bcs->hw.isar.ftimer);
1051 } else {
1052 sched_b_event(bcs, B_LL_CONNECT);
1053 }
1054 } else {
1055 if (cs->debug & L1_DEB_WARN)
1056 debugl1(cs, "pump stev RSP_CONN wrong st %x",
1057 bcs->hw.isar.state);
1058 }
1059 break;
1060 case PSEV_FLAGS_DET:
1061 if (cs->debug & L1_DEB_HSCX)
1062 debugl1(cs, "pump stev FLAGS_DET");
1063 break;
1064 case PSEV_RSP_DISC:
1065 if (cs->debug & L1_DEB_HSCX)
1066 debugl1(cs, "pump stev RSP_DISC");
1067 if (bcs->hw.isar.state == STFAX_ESCAPE) {
1068 switch(bcs->hw.isar.newcmd) {
1069 case 0:
1070 bcs->hw.isar.state = STFAX_READY;
1071 break;
1072 case PCTRL_CMD_FTH:
1073 case PCTRL_CMD_FTM:
1074 p1 = 10;
1075 sendmsg(cs, dps | ISAR_HIS_PUMPCTRL,
1076 PCTRL_CMD_SILON, 1, &p1);
1077 bcs->hw.isar.state = STFAX_SILDET;
1078 break;
1079 case PCTRL_CMD_FRH:
1080 case PCTRL_CMD_FRM:
1081 p1 = bcs->hw.isar.mod = bcs->hw.isar.newmod;
1082 bcs->hw.isar.newmod = 0;
1083 bcs->hw.isar.cmd = bcs->hw.isar.newcmd;
1084 bcs->hw.isar.newcmd = 0;
1085 sendmsg(cs, dps | ISAR_HIS_PUMPCTRL,
1086 bcs->hw.isar.cmd, 1, &p1);
1087 bcs->hw.isar.state = STFAX_LINE;
1088 bcs->hw.isar.try_mod = 3;
1089 break;
1090 default:
1091 if (cs->debug & L1_DEB_HSCX)
1092 debugl1(cs, "RSP_DISC unknown newcmd %x", bcs->hw.isar.newcmd);
1093 break;
1094 }
1095 } else if (bcs->hw.isar.state == STFAX_ACTIV) {
1096 if (test_and_clear_bit(BC_FLG_LL_OK, &bcs->Flag)) {
1097 sched_b_event(bcs, B_LL_OK);
1098 } else if (bcs->hw.isar.cmd == PCTRL_CMD_FRM) {
1099 send_DLE_ETX(bcs);
1100 sched_b_event(bcs, B_LL_NOCARRIER);
1101 } else {
1102 ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_FCERROR);
1103 }
1104 bcs->hw.isar.state = STFAX_READY;
1105 } else {
1106 bcs->hw.isar.state = STFAX_READY;
1107 ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_FCERROR);
1108 }
1109 break;
1110 case PSEV_RSP_SILDET:
1111 if (cs->debug & L1_DEB_HSCX)
1112 debugl1(cs, "pump stev RSP_SILDET");
1113 if (bcs->hw.isar.state == STFAX_SILDET) {
1114 p1 = bcs->hw.isar.mod = bcs->hw.isar.newmod;
1115 bcs->hw.isar.newmod = 0;
1116 bcs->hw.isar.cmd = bcs->hw.isar.newcmd;
1117 bcs->hw.isar.newcmd = 0;
1118 sendmsg(cs, dps | ISAR_HIS_PUMPCTRL,
1119 bcs->hw.isar.cmd, 1, &p1);
1120 bcs->hw.isar.state = STFAX_LINE;
1121 bcs->hw.isar.try_mod = 3;
1122 }
1123 break;
1124 case PSEV_RSP_SILOFF:
1125 if (cs->debug & L1_DEB_HSCX)
1126 debugl1(cs, "pump stev RSP_SILOFF");
1127 break;
1128 case PSEV_RSP_FCERR:
1129 if (bcs->hw.isar.state == STFAX_LINE) {
1130 if (cs->debug & L1_DEB_HSCX)
1131 debugl1(cs, "pump stev RSP_FCERR try %d",
1132 bcs->hw.isar.try_mod);
1133 if (bcs->hw.isar.try_mod--) {
1134 sendmsg(cs, dps | ISAR_HIS_PUMPCTRL,
1135 bcs->hw.isar.cmd, 1,
1136 &bcs->hw.isar.mod);
1137 break;
1138 }
1139 }
1140 if (cs->debug & L1_DEB_HSCX)
1141 debugl1(cs, "pump stev RSP_FCERR");
1142 bcs->hw.isar.state = STFAX_ESCAPE;
1143 sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, PCTRL_CMD_ESC, 0, NULL);
1144 ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_FCERROR);
1145 break;
1146 default:
1147 break;
1148 }
1149 }
1150
1151 static char debbuf[128];
1152
1153 void
1154 isar_int_main(struct IsdnCardState *cs)
1155 {
1156 struct isar_reg *ireg = cs->bcs[0].hw.isar.reg;
1157 struct BCState *bcs;
1158
1159 get_irq_infos(cs, ireg);
1160 switch (ireg->iis & ISAR_IIS_MSCMSD) {
1161 case ISAR_IIS_RDATA:
1162 if ((bcs = sel_bcs_isar(cs, ireg->iis >> 6))) {
1163 isar_rcv_frame(cs, bcs);
1164 } else {
1165 debugl1(cs, "isar spurious IIS_RDATA %x/%x/%x",
1166 ireg->iis, ireg->cmsb, ireg->clsb);
1167 isar_write_reg(cs, 1, ISAR_IIA, 0);
1168 }
1169 break;
1170 case ISAR_IIS_GSTEV:
1171 isar_write_reg(cs, 1, ISAR_IIA, 0);
1172 ireg->bstat |= ireg->cmsb;
1173 check_send(cs, ireg->cmsb);
1174 break;
1175 case ISAR_IIS_BSTEV:
1176 #ifdef ERROR_STATISTIC
1177 if ((bcs = sel_bcs_isar(cs, ireg->iis >> 6))) {
1178 if (ireg->cmsb == BSTEV_TBO)
1179 bcs->err_tx++;
1180 if (ireg->cmsb == BSTEV_RBO)
1181 bcs->err_rdo++;
1182 }
1183 #endif
1184 if (cs->debug & L1_DEB_WARN)
1185 debugl1(cs, "Buffer STEV dpath%d msb(%x)",
1186 ireg->iis>>6, ireg->cmsb);
1187 isar_write_reg(cs, 1, ISAR_IIA, 0);
1188 break;
1189 case ISAR_IIS_PSTEV:
1190 if ((bcs = sel_bcs_isar(cs, ireg->iis >> 6))) {
1191 rcv_mbox(cs, ireg, (u8 *)ireg->par);
1192 if (bcs->mode == L1_MODE_V32) {
1193 isar_pump_statev_modem(bcs, ireg->cmsb);
1194 } else if (bcs->mode == L1_MODE_FAX) {
1195 isar_pump_statev_fax(bcs, ireg->cmsb);
1196 } else {
1197 if (cs->debug & L1_DEB_WARN)
1198 debugl1(cs, "isar IIS_PSTEV pmode %d stat %x",
1199 bcs->mode, ireg->cmsb);
1200 }
1201 } else {
1202 debugl1(cs, "isar spurious IIS_PSTEV %x/%x/%x",
1203 ireg->iis, ireg->cmsb, ireg->clsb);
1204 isar_write_reg(cs, 1, ISAR_IIA, 0);
1205 }
1206 break;
1207 case ISAR_IIS_PSTRSP:
1208 if ((bcs = sel_bcs_isar(cs, ireg->iis >> 6))) {
1209 rcv_mbox(cs, ireg, (u8 *)ireg->par);
1210 isar_pump_status_rsp(bcs, ireg);
1211 } else {
1212 debugl1(cs, "isar spurious IIS_PSTRSP %x/%x/%x",
1213 ireg->iis, ireg->cmsb, ireg->clsb);
1214 isar_write_reg(cs, 1, ISAR_IIA, 0);
1215 }
1216 break;
1217 case ISAR_IIS_DIAG:
1218 case ISAR_IIS_BSTRSP:
1219 case ISAR_IIS_IOM2RSP:
1220 rcv_mbox(cs, ireg, (u8 *)ireg->par);
1221 if ((cs->debug & (L1_DEB_HSCX | L1_DEB_HSCX_FIFO))
1222 == L1_DEB_HSCX) {
1223 u8 *tp=debbuf;
1224
1225 tp += sprintf(debbuf, "msg iis(%x) msb(%x)",
1226 ireg->iis, ireg->cmsb);
1227 QuickHex(tp, (u8 *)ireg->par, ireg->clsb);
1228 debugl1(cs, debbuf);
1229 }
1230 break;
1231 case ISAR_IIS_INVMSG:
1232 rcv_mbox(cs, ireg, debbuf);
1233 if (cs->debug & L1_DEB_WARN)
1234 debugl1(cs, "invalid msg his:%x",
1235 ireg->cmsb);
1236 break;
1237 default:
1238 rcv_mbox(cs, ireg, debbuf);
1239 if (cs->debug & L1_DEB_WARN)
1240 debugl1(cs, "unhandled msg iis(%x) ctrl(%x/%x)",
1241 ireg->iis, ireg->cmsb, ireg->clsb);
1242 break;
1243 }
1244 }
1245
1246 static void
1247 ftimer_handler(struct BCState *bcs) {
1248 if (bcs->cs->debug)
1249 debugl1(bcs->cs, "ftimer flags %04x",
1250 bcs->Flag);
1251 test_and_clear_bit(BC_FLG_FTI_RUN, &bcs->Flag);
1252 if (test_and_clear_bit(BC_FLG_LL_CONN, &bcs->Flag)) {
1253 sched_b_event(bcs, B_LL_CONNECT);
1254 }
1255 }
1256
1257 static void
1258 setup_pump(struct BCState *bcs) {
1259 struct IsdnCardState *cs = bcs->cs;
1260 u8 dps = SET_DPS(bcs->hw.isar.dpath);
1261 u8 ctrl, param[6];
1262
1263 switch (bcs->mode) {
1264 case L1_MODE_NULL:
1265 case L1_MODE_TRANS:
1266 case L1_MODE_HDLC:
1267 sendmsg(cs, dps | ISAR_HIS_PUMPCFG, PMOD_BYPASS, 0, NULL);
1268 break;
1269 case L1_MODE_V32:
1270 ctrl = PMOD_DATAMODEM;
1271 if (test_bit(BC_FLG_ORIG, &bcs->Flag)) {
1272 ctrl |= PCTRL_ORIG;
1273 param[5] = PV32P6_CTN;
1274 } else {
1275 param[5] = PV32P6_ATN;
1276 }
1277 param[0] = 6; /* 6 db */
1278 param[1] = PV32P2_V23R | PV32P2_V22A | PV32P2_V22B |
1279 PV32P2_V22C | PV32P2_V21 | PV32P2_BEL;
1280 param[2] = PV32P3_AMOD | PV32P3_V32B | PV32P3_V23B;
1281 param[3] = PV32P4_UT144;
1282 param[4] = PV32P5_UT144;
1283 sendmsg(cs, dps | ISAR_HIS_PUMPCFG, ctrl, 6, param);
1284 break;
1285 case L1_MODE_FAX:
1286 ctrl = PMOD_FAX;
1287 if (test_bit(BC_FLG_ORIG, &bcs->Flag)) {
1288 ctrl |= PCTRL_ORIG;
1289 param[1] = PFAXP2_CTN;
1290 } else {
1291 param[1] = PFAXP2_ATN;
1292 }
1293 param[0] = 6; /* 6 db */
1294 sendmsg(cs, dps | ISAR_HIS_PUMPCFG, ctrl, 2, param);
1295 bcs->hw.isar.state = STFAX_NULL;
1296 bcs->hw.isar.newcmd = 0;
1297 bcs->hw.isar.newmod = 0;
1298 test_and_set_bit(BC_FLG_FTI_RUN, &bcs->Flag);
1299 break;
1300 }
1301 udelay(1000);
1302 sendmsg(cs, dps | ISAR_HIS_PSTREQ, 0, 0, NULL);
1303 udelay(1000);
1304 }
1305
1306 static void
1307 setup_sart(struct BCState *bcs) {
1308 struct IsdnCardState *cs = bcs->cs;
1309 u8 dps = SET_DPS(bcs->hw.isar.dpath);
1310 u8 ctrl, param[2];
1311
1312 switch (bcs->mode) {
1313 case L1_MODE_NULL:
1314 sendmsg(cs, dps | ISAR_HIS_SARTCFG, SMODE_DISABLE, 0,
1315 NULL);
1316 break;
1317 case L1_MODE_TRANS:
1318 sendmsg(cs, dps | ISAR_HIS_SARTCFG, SMODE_BINARY, 2,
1319 "\0\0");
1320 break;
1321 case L1_MODE_HDLC:
1322 case L1_MODE_FAX:
1323 param[0] = 0;
1324 sendmsg(cs, dps | ISAR_HIS_SARTCFG, SMODE_HDLC, 1,
1325 param);
1326 break;
1327 case L1_MODE_V32:
1328 ctrl = SMODE_V14 | SCTRL_HDMC_BOTH;
1329 param[0] = S_P1_CHS_8;
1330 param[1] = S_P2_BFT_DEF;
1331 sendmsg(cs, dps | ISAR_HIS_SARTCFG, ctrl, 2,
1332 param);
1333 break;
1334 }
1335 udelay(1000);
1336 sendmsg(cs, dps | ISAR_HIS_BSTREQ, 0, 0, NULL);
1337 udelay(1000);
1338 }
1339
1340 static void
1341 setup_iom2(struct BCState *bcs) {
1342 struct IsdnCardState *cs = bcs->cs;
1343 u8 dps = SET_DPS(bcs->hw.isar.dpath);
1344 u8 cmsb = IOM_CTRL_ENA, msg[5] = {IOM_P1_TXD,0,0,0,0};
1345
1346 if (bcs->channel)
1347 msg[1] = msg[3] = 1;
1348 switch (bcs->mode) {
1349 case L1_MODE_NULL:
1350 cmsb = 0;
1351 /* dummy slot */
1352 msg[1] = msg[3] = bcs->hw.isar.dpath + 2;
1353 break;
1354 case L1_MODE_TRANS:
1355 case L1_MODE_HDLC:
1356 break;
1357 case L1_MODE_V32:
1358 case L1_MODE_FAX:
1359 cmsb |= IOM_CTRL_ALAW | IOM_CTRL_RCV;
1360 break;
1361 }
1362 sendmsg(cs, dps | ISAR_HIS_IOM2CFG, cmsb, 5, msg);
1363 udelay(1000);
1364 sendmsg(cs, dps | ISAR_HIS_IOM2REQ, 0, 0, NULL);
1365 udelay(1000);
1366 }
1367
1368 int
1369 modeisar(struct BCState *bcs, int mode, int bc)
1370 {
1371 struct IsdnCardState *cs = bcs->cs;
1372
1373 /* Here we are selecting the best datapath for requested mode */
1374 if(bcs->mode == L1_MODE_NULL) { /* New Setup */
1375 bcs->channel = bc;
1376 switch (mode) {
1377 case L1_MODE_NULL: /* init */
1378 if (!bcs->hw.isar.dpath)
1379 /* no init for dpath 0 */
1380 return(0);
1381 break;
1382 case L1_MODE_TRANS:
1383 case L1_MODE_HDLC:
1384 /* best is datapath 2 */
1385 if (!test_and_set_bit(ISAR_DP2_USE,
1386 &bcs->hw.isar.reg->Flags))
1387 bcs->hw.isar.dpath = 2;
1388 else if (!test_and_set_bit(ISAR_DP1_USE,
1389 &bcs->hw.isar.reg->Flags))
1390 bcs->hw.isar.dpath = 1;
1391 else {
1392 printk(KERN_WARNING"isar modeisar both pathes in use\n");
1393 return(1);
1394 }
1395 break;
1396 case L1_MODE_V32:
1397 case L1_MODE_FAX:
1398 /* only datapath 1 */
1399 if (!test_and_set_bit(ISAR_DP1_USE,
1400 &bcs->hw.isar.reg->Flags))
1401 bcs->hw.isar.dpath = 1;
1402 else {
1403 printk(KERN_WARNING"isar modeisar analog funktions only with DP1\n");
1404 debugl1(cs, "isar modeisar analog funktions only with DP1");
1405 return(1);
1406 }
1407 break;
1408 }
1409 }
1410 if (cs->debug & L1_DEB_HSCX)
1411 debugl1(cs, "isar dp%d mode %d->%d ichan %d",
1412 bcs->hw.isar.dpath, bcs->mode, mode, bc);
1413 bcs->mode = mode;
1414 setup_pump(bcs);
1415 setup_iom2(bcs);
1416 setup_sart(bcs);
1417 if (bcs->mode == L1_MODE_NULL) {
1418 /* Clear resources */
1419 if (bcs->hw.isar.dpath == 1)
1420 test_and_clear_bit(ISAR_DP1_USE, &bcs->hw.isar.reg->Flags);
1421 else if (bcs->hw.isar.dpath == 2)
1422 test_and_clear_bit(ISAR_DP2_USE, &bcs->hw.isar.reg->Flags);
1423 bcs->hw.isar.dpath = 0;
1424 }
1425 return(0);
1426 }
1427
1428 static void
1429 isar_pump_cmd(struct BCState *bcs, u8 cmd, u8 para)
1430 {
1431 struct IsdnCardState *cs = bcs->cs;
1432 u8 dps = SET_DPS(bcs->hw.isar.dpath);
1433 u8 ctrl = 0, nom = 0, p1 = 0;
1434
1435 switch(cmd) {
1436 case ISDN_FAX_CLASS1_FTM:
1437 if (bcs->hw.isar.state == STFAX_READY) {
1438 p1 = para;
1439 ctrl = PCTRL_CMD_FTM;
1440 nom = 1;
1441 bcs->hw.isar.state = STFAX_LINE;
1442 bcs->hw.isar.cmd = ctrl;
1443 bcs->hw.isar.mod = para;
1444 bcs->hw.isar.newmod = 0;
1445 bcs->hw.isar.newcmd = 0;
1446 bcs->hw.isar.try_mod = 3;
1447 } else if ((bcs->hw.isar.state == STFAX_ACTIV) &&
1448 (bcs->hw.isar.cmd == PCTRL_CMD_FTM) &&
1449 (bcs->hw.isar.mod == para)) {
1450 ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_CONNECT);
1451 } else {
1452 bcs->hw.isar.newmod = para;
1453 bcs->hw.isar.newcmd = PCTRL_CMD_FTM;
1454 nom = 0;
1455 ctrl = PCTRL_CMD_ESC;
1456 bcs->hw.isar.state = STFAX_ESCAPE;
1457 }
1458 break;
1459 case ISDN_FAX_CLASS1_FTH:
1460 if (bcs->hw.isar.state == STFAX_READY) {
1461 p1 = para;
1462 ctrl = PCTRL_CMD_FTH;
1463 nom = 1;
1464 bcs->hw.isar.state = STFAX_LINE;
1465 bcs->hw.isar.cmd = ctrl;
1466 bcs->hw.isar.mod = para;
1467 bcs->hw.isar.newmod = 0;
1468 bcs->hw.isar.newcmd = 0;
1469 bcs->hw.isar.try_mod = 3;
1470 } else if ((bcs->hw.isar.state == STFAX_ACTIV) &&
1471 (bcs->hw.isar.cmd == PCTRL_CMD_FTH) &&
1472 (bcs->hw.isar.mod == para)) {
1473 ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_CONNECT);
1474 } else {
1475 bcs->hw.isar.newmod = para;
1476 bcs->hw.isar.newcmd = PCTRL_CMD_FTH;
1477 nom = 0;
1478 ctrl = PCTRL_CMD_ESC;
1479 bcs->hw.isar.state = STFAX_ESCAPE;
1480 }
1481 break;
1482 case ISDN_FAX_CLASS1_FRM:
1483 if (bcs->hw.isar.state == STFAX_READY) {
1484 p1 = para;
1485 ctrl = PCTRL_CMD_FRM;
1486 nom = 1;
1487 bcs->hw.isar.state = STFAX_LINE;
1488 bcs->hw.isar.cmd = ctrl;
1489 bcs->hw.isar.mod = para;
1490 bcs->hw.isar.newmod = 0;
1491 bcs->hw.isar.newcmd = 0;
1492 bcs->hw.isar.try_mod = 3;
1493 } else if ((bcs->hw.isar.state == STFAX_ACTIV) &&
1494 (bcs->hw.isar.cmd == PCTRL_CMD_FRM) &&
1495 (bcs->hw.isar.mod == para)) {
1496 ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_CONNECT);
1497 } else {
1498 bcs->hw.isar.newmod = para;
1499 bcs->hw.isar.newcmd = PCTRL_CMD_FRM;
1500 nom = 0;
1501 ctrl = PCTRL_CMD_ESC;
1502 bcs->hw.isar.state = STFAX_ESCAPE;
1503 }
1504 break;
1505 case ISDN_FAX_CLASS1_FRH:
1506 if (bcs->hw.isar.state == STFAX_READY) {
1507 p1 = para;
1508 ctrl = PCTRL_CMD_FRH;
1509 nom = 1;
1510 bcs->hw.isar.state = STFAX_LINE;
1511 bcs->hw.isar.cmd = ctrl;
1512 bcs->hw.isar.mod = para;
1513 bcs->hw.isar.newmod = 0;
1514 bcs->hw.isar.newcmd = 0;
1515 bcs->hw.isar.try_mod = 3;
1516 } else if ((bcs->hw.isar.state == STFAX_ACTIV) &&
1517 (bcs->hw.isar.cmd == PCTRL_CMD_FRH) &&
1518 (bcs->hw.isar.mod == para)) {
1519 ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_CONNECT);
1520 } else {
1521 bcs->hw.isar.newmod = para;
1522 bcs->hw.isar.newcmd = PCTRL_CMD_FRH;
1523 nom = 0;
1524 ctrl = PCTRL_CMD_ESC;
1525 bcs->hw.isar.state = STFAX_ESCAPE;
1526 }
1527 break;
1528 }
1529 if (ctrl)
1530 sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, ctrl, nom, &p1);
1531 }
1532
1533 void
1534 __isar_setup(struct IsdnCardState *cs)
1535 {
1536 u8 msg;
1537 int i;
1538
1539 /* Dpath 1, 2 */
1540 msg = 61;
1541 for (i=0; i<2; i++) {
1542 /* Buffer Config */
1543 sendmsg(cs, (i ? ISAR_HIS_DPS2 : ISAR_HIS_DPS1) |
1544 ISAR_HIS_P12CFG, 4, 1, &msg);
1545 cs->bcs[i].hw.isar.mml = msg;
1546 cs->bcs[i].mode = 0;
1547 cs->bcs[i].hw.isar.dpath = i + 1;
1548 modeisar(&cs->bcs[i], 0, 0);
1549 INIT_WORK(&cs->bcs[i].work, isar_bh, &cs->bcs[i]);
1550 }
1551 }
1552
1553 void
1554 isar_l2l1(struct PStack *st, int pr, void *arg)
1555 {
1556 struct sk_buff *skb = arg;
1557
1558 switch (pr) {
1559 case (PH_DATA | REQUEST):
1560 xmit_data_req_b(st->l1.bcs, skb);
1561 break;
1562 case (PH_PULL | INDICATION):
1563 xmit_pull_ind_b(st->l1.bcs, skb);
1564 break;
1565 case (PH_PULL | REQUEST):
1566 xmit_pull_req_b(st);
1567 break;
1568 case (PH_ACTIVATE | REQUEST):
1569 test_and_set_bit(BC_FLG_ACTIV, &st->l1.bcs->Flag);
1570 st->l1.bcs->hw.isar.conmsg[0] = 0;
1571 if (test_bit(FLG_ORIG, &st->l2.flag))
1572 test_and_set_bit(BC_FLG_ORIG, &st->l1.bcs->Flag);
1573 else
1574 test_and_clear_bit(BC_FLG_ORIG, &st->l1.bcs->Flag);
1575 switch(st->l1.mode) {
1576 case L1_MODE_TRANS:
1577 case L1_MODE_HDLC:
1578 if (modeisar(st->l1.bcs, st->l1.mode, st->l1.bc))
1579 l1_msg_b(st, PH_DEACTIVATE | REQUEST, arg);
1580 else
1581 l1_msg_b(st, PH_ACTIVATE | REQUEST, arg);
1582 break;
1583 case L1_MODE_V32:
1584 case L1_MODE_FAX:
1585 if (modeisar(st->l1.bcs, st->l1.mode, st->l1.bc))
1586 l1_msg_b(st, PH_DEACTIVATE | REQUEST, arg);
1587 break;
1588 }
1589 break;
1590 case (PH_DEACTIVATE | REQUEST):
1591 l1_msg_b(st, pr, arg);
1592 break;
1593 case (PH_DEACTIVATE | CONFIRM):
1594 test_and_clear_bit(BC_FLG_ACTIV, &st->l1.bcs->Flag);
1595 test_and_clear_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
1596 if (st->l1.bcs->cs->debug & L1_DEB_HSCX)
1597 debugl1(st->l1.bcs->cs, "PDAC clear BC_FLG_BUSY");
1598 modeisar(st->l1.bcs, 0, st->l1.bc);
1599 L1L2(st, PH_DEACTIVATE | CONFIRM, NULL);
1600 break;
1601 }
1602 }
1603
1604 void
1605 close_isarstate(struct BCState *bcs)
1606 {
1607 modeisar(bcs, 0, bcs->channel);
1608 if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
1609 if (bcs->hw.isar.rcvbuf) {
1610 kfree(bcs->hw.isar.rcvbuf);
1611 bcs->hw.isar.rcvbuf = NULL;
1612 }
1613 skb_queue_purge(&bcs->rqueue);
1614 skb_queue_purge(&bcs->squeue);
1615 if (bcs->tx_skb) {
1616 dev_kfree_skb_any(bcs->tx_skb);
1617 bcs->tx_skb = NULL;
1618 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
1619 if (bcs->cs->debug & L1_DEB_HSCX)
1620 debugl1(bcs->cs, "closeisar clear BC_FLG_BUSY");
1621 }
1622 }
1623 del_timer(&bcs->hw.isar.ftimer);
1624 }
1625
1626 int
1627 open_isarstate(struct IsdnCardState *cs, struct BCState *bcs)
1628 {
1629 if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
1630 if (!(bcs->hw.isar.rcvbuf = kmalloc(HSCX_BUFMAX, GFP_ATOMIC))) {
1631 printk(KERN_WARNING
1632 "HiSax: No memory for isar.rcvbuf\n");
1633 return (1);
1634 }
1635 skb_queue_head_init(&bcs->rqueue);
1636 skb_queue_head_init(&bcs->squeue);
1637 }
1638 bcs->tx_skb = NULL;
1639 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
1640 if (cs->debug & L1_DEB_HSCX)
1641 debugl1(cs, "openisar clear BC_FLG_BUSY");
1642 bcs->event = 0;
1643 bcs->hw.isar.rcvidx = 0;
1644 bcs->tx_cnt = 0;
1645 bcs->hw.isar.ftimer.function = (void *) ftimer_handler;
1646 bcs->hw.isar.ftimer.data = (long) bcs;
1647 init_timer(&bcs->hw.isar.ftimer);
1648 return (0);
1649 }
1650
1651 int
1652 setstack_isar(struct PStack *st, struct BCState *bcs)
1653 {
1654 bcs->channel = st->l1.bc;
1655 if (open_isarstate(st->l1.hardware, bcs))
1656 return (-1);
1657 st->l1.bcs = bcs;
1658 st->l1.l2l1 = isar_l2l1;
1659 setstack_manager(st);
1660 bcs->st = st;
1661 setstack_l1_B(st);
1662 return (0);
1663 }
1664
1665 int
1666 isar_auxcmd(struct IsdnCardState *cs, isdn_ctrl *ic) {
1667 u_long adr;
1668 int features, i;
1669 struct BCState *bcs;
1670
1671 if (cs->debug & L1_DEB_HSCX)
1672 debugl1(cs, "isar_auxcmd cmd/ch %x/%d", ic->command, ic->arg);
1673 switch (ic->command) {
1674 case (ISDN_CMD_FAXCMD):
1675 bcs = cs->channel[ic->arg].bcs;
1676 if (cs->debug & L1_DEB_HSCX)
1677 debugl1(cs, "isar_auxcmd cmd/subcmd %d/%d",
1678 ic->parm.aux.cmd, ic->parm.aux.subcmd);
1679 switch(ic->parm.aux.cmd) {
1680 case ISDN_FAX_CLASS1_CTRL:
1681 if (ic->parm.aux.subcmd == ETX)
1682 test_and_set_bit(BC_FLG_DLEETX,
1683 &bcs->Flag);
1684 break;
1685 case ISDN_FAX_CLASS1_FRM:
1686 case ISDN_FAX_CLASS1_FRH:
1687 case ISDN_FAX_CLASS1_FTM:
1688 case ISDN_FAX_CLASS1_FTH:
1689 if (ic->parm.aux.subcmd == AT_QUERY) {
1690 sprintf(ic->parm.aux.para,
1691 "%d", bcs->hw.isar.mod);
1692 ic->command = ISDN_STAT_FAXIND;
1693 ic->parm.aux.cmd = ISDN_FAX_CLASS1_QUERY;
1694 cs->iif.statcallb(ic);
1695 return(0);
1696 } else if (ic->parm.aux.subcmd == AT_EQ_QUERY) {
1697 strcpy(ic->parm.aux.para, faxmodulation_s);
1698 ic->command = ISDN_STAT_FAXIND;
1699 ic->parm.aux.cmd = ISDN_FAX_CLASS1_QUERY;
1700 cs->iif.statcallb(ic);
1701 return(0);
1702 } else if (ic->parm.aux.subcmd == AT_EQ_VALUE) {
1703 for(i=0;i<FAXMODCNT;i++)
1704 if (faxmodulation[i]==ic->parm.aux.para[0])
1705 break;
1706 if ((FAXMODCNT > i) &&
1707 test_bit(BC_FLG_INIT, &bcs->Flag)) {
1708 isar_pump_cmd(bcs,
1709 ic->parm.aux.cmd,
1710 ic->parm.aux.para[0]);
1711 return(0);
1712 }
1713 }
1714 /* wrong modulation or not activ */
1715 /* fall through */
1716 default:
1717 ic->command = ISDN_STAT_FAXIND;
1718 ic->parm.aux.cmd = ISDN_FAX_CLASS1_ERROR;
1719 cs->iif.statcallb(ic);
1720 }
1721 break;
1722 case (ISDN_CMD_IOCTL):
1723 switch (ic->arg) {
1724 case (9): /* load firmware */
1725 features = ISDN_FEATURE_L2_MODEM |
1726 ISDN_FEATURE_L2_FAX |
1727 ISDN_FEATURE_L3_FCLASS1;
1728 memcpy(&adr, ic->parm.num, sizeof(ulong));
1729 if (isar_load_firmware(cs, (u8 *)adr))
1730 return(1);
1731 else
1732 ll_run(cs, features);
1733 break;
1734 default:
1735 printk(KERN_DEBUG "HiSax: invalid ioctl %d\n",
1736 (int) ic->arg);
1737 return(-EINVAL);
1738 }
1739 break;
1740 default:
1741 return(-EINVAL);
1742 }
1743 return(0);
1744 }
1745
1746 static struct bc_l1_ops isar_l1_ops = {
1747 .fill_fifo = isar_fill_fifo,
1748 .open = setstack_isar,
1749 .close = close_isarstate,
1750 };
1751
1752 void __devinit
1753 initisar(struct IsdnCardState *cs)
1754 {
1755 cs->bc_l1_ops = &isar_l1_ops;
1756 }
1757
1758 int
1759 isar_setup(struct IsdnCardState *cs, struct bc_hw_ops *isar_ops)
1760 {
1761 cs->bc_hw_ops = isar_ops;
1762 return ISARVersion(cs, "HiSax:");
1763 }
Mirror of the linux-mips.org kernel tree