1 /* gerdes_amd7930.c,v 0.99 2001/10/02
3 * gerdes_amd7930.c Amd 79C30A and 79C32A specific routines
4 * (based on HiSax driver by Karsten Keil)
6 * Author Christoph Ersfeld <info@formula-n.de>
7 * Formula-n Europe AG (www.formula-n.com)
11 * This file is (c) under GNU PUBLIC LICENSE
15 * Version 0.99 is the first release of this driver and there are
16 * certainly a few bugs.
18 * Please don't report any malfunction to me without sending
19 * (compressed) debug-logs.
20 * It would be nearly impossible to retrace it.
22 * Log D-channel-processing as follows:
24 * 1. Load hisax with card-specific parameters, this example ist for
25 * Formula-n enter:now ISDN PCI and compatible
26 * (f.e. Gerdes Power ISDN PCI)
28 * modprobe hisax type=41 protocol=2 id=gerdes
30 * if you chose an other value for id, you need to modify the
35 * hisaxctrl gerdes 1 0x3ff
36 * hisaxctrl gerdes 11 0x4f
37 * cat /dev/isdnctrl >> ~/log &
39 * Please take also a look into /var/log/messages if there is
40 * anything importand concerning HISAX.
44 * Programming the driver for Formula-n enter:now ISDN PCI and
45 * necessary this driver for the used Amd 7930 D-channel-controller
46 * was spnsored by Formula-n Europe AG.
47 * Thanks to Karsten Keil and Petr Novak, who gave me support in
48 * Hisax-specific questions.
49 * I want so say special thanks to Carl-Friedrich Braun, who had to
50 * answer a lot of questions about generally ISDN and about handling
59 #include "amd7930_fn.h"
60 #include <linux/interrupt.h>
61 #include <linux/init.h>
63 static void Amd7930_new_ph(struct IsdnCardState
*cs
);
68 return (w
>> 8) & 0xff;
78 rByteAMD(struct IsdnCardState
*cs
, u8 reg
)
80 return cs
->dc_hw_ops
->read_reg(cs
, reg
);
84 wByteAMD(struct IsdnCardState
*cs
, u8 reg
, u8 val
)
86 cs
->dc_hw_ops
->write_reg(cs
, reg
, val
);
90 wWordAMD(struct IsdnCardState
*cs
, u8 reg
, u16 val
)
92 wByteAMD(cs
, 0x00, reg
);
93 wByteAMD(cs
, 0x01, LOBYTE(val
));
94 wByteAMD(cs
, 0x01, HIBYTE(val
));
98 rWordAMD(struct IsdnCardState
*cs
, u8 reg
)
101 /* direct access register */
103 res
= rByteAMD(cs
, reg
);
104 res
+= 256*rByteAMD(cs
, reg
);
106 /* indirect access register */
108 wByteAMD(cs
, 0x00, reg
);
109 res
= rByteAMD(cs
, 0x01);
110 res
+= 256*rByteAMD(cs
, 0x01);
116 AmdIrqOff(struct IsdnCardState
*cs
)
118 cs
->dc
.amd7930
.setIrqMask(cs
, 0);
122 AmdIrqOn(struct IsdnCardState
*cs
)
124 cs
->dc
.amd7930
.setIrqMask(cs
, 1);
128 Amd7930_ph_command(struct IsdnCardState
*cs
, u8 command
, char *s
)
130 if (cs
->debug
& L1_DEB_ISAC
)
131 debugl1(cs
, "AMD7930: %s: ph_command 0x%02X", s
, command
);
133 cs
->dc
.amd7930
.lmr1
= command
;
134 wByteAMD(cs
, 0xA3, command
);
139 static u8 i430States
[] = {
140 // to reset F3 F4 F5 F6 F7 F8 AR from
141 0x01, 0x02, 0x00, 0x00, 0x00, 0x07, 0x05, 0x00, // init
142 0x01, 0x02, 0x00, 0x00, 0x00, 0x07, 0x05, 0x00, // reset
143 0x01, 0x02, 0x00, 0x00, 0x00, 0x09, 0x05, 0x04, // F3
144 0x01, 0x02, 0x00, 0x00, 0x1B, 0x00, 0x00, 0x00, // F4
145 0x01, 0x02, 0x00, 0x00, 0x1B, 0x00, 0x00, 0x00, // F5
146 0x01, 0x03, 0x00, 0x00, 0x00, 0x06, 0x05, 0x00, // F6
147 0x11, 0x13, 0x00, 0x00, 0x1B, 0x00, 0x15, 0x00, // F7
148 0x01, 0x03, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, // F8
149 0x01, 0x03, 0x00, 0x00, 0x00, 0x09, 0x00, 0x0A}; // AR
152 /* Row init - reset F3 F4 F5 F6 F7 F8 AR */
153 static u8 stateHelper
[] = { 0x00, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08 };
159 Amd7930_get_state(struct IsdnCardState
*cs
) {
160 u8 lsr
= rByteAMD(cs
, 0xA1);
161 cs
->dc
.amd7930
.ph_state
= (lsr
& 0x7) + 2;
168 Amd7930_new_ph(struct IsdnCardState
*cs
)
170 u8 index
= stateHelper
[cs
->dc
.amd7930
.old_state
]*8 + stateHelper
[cs
->dc
.amd7930
.ph_state
]-1;
171 u8 message
= i430States
[index
];
173 if (cs
->debug
& L1_DEB_ISAC
)
174 debugl1(cs
, "AMD7930: new_ph %d, old_ph %d, message %d, index %d",
175 cs
->dc
.amd7930
.ph_state
, cs
->dc
.amd7930
.old_state
, message
& 0x0f, index
);
177 cs
->dc
.amd7930
.old_state
= cs
->dc
.amd7930
.ph_state
;
179 /* abort transmit if necessary */
180 if ((message
& 0xf0) && (cs
->tx_skb
)) {
181 wByteAMD(cs
, 0x21, 0xC2);
182 wByteAMD(cs
, 0x21, 0x02);
185 switch (message
& 0x0f) {
188 l1_msg(cs
, HW_RESET
| INDICATION
, NULL
);
189 Amd7930_get_state(cs
);
191 case (2): /* init, Card starts in F3 */
192 l1_msg(cs
, HW_DEACTIVATE
| CONFIRM
, NULL
);
195 l1_msg(cs
, HW_DEACTIVATE
| INDICATION
, NULL
);
198 l1_msg(cs
, HW_POWERUP
| CONFIRM
, NULL
);
199 Amd7930_ph_command(cs
, 0x50, "HW_ENABLE REQUEST");
202 l1_msg(cs
, HW_RSYNC
| INDICATION
, NULL
);
205 l1_msg(cs
, HW_INFO4_P8
| INDICATION
, NULL
);
207 case (7): /* init, Card starts in F7 */
208 l1_msg(cs
, HW_RSYNC
| INDICATION
, NULL
);
209 l1_msg(cs
, HW_INFO4_P8
| INDICATION
, NULL
);
212 l1_msg(cs
, HW_POWERUP
| CONFIRM
, NULL
);
215 Amd7930_ph_command(cs
, 0x40, "HW_ENABLE REQ cleared if set");
216 l1_msg(cs
, HW_RSYNC
| INDICATION
, NULL
);
217 l1_msg(cs
, HW_INFO2
| INDICATION
, NULL
);
218 l1_msg(cs
, HW_INFO4_P8
| INDICATION
, NULL
);
221 Amd7930_ph_command(cs
, 0x40, "T3 expired, HW_ENABLE REQ cleared");
222 cs
->dc
.amd7930
.old_state
= 3;
225 l1_msg(cs
, HW_INFO2
| INDICATION
, NULL
);
235 Amd7930_bh(void *data
)
237 struct IsdnCardState
*cs
= data
;
238 struct PStack
*stptr
;
242 if (test_and_clear_bit(D_CLEARBUSY
, &cs
->event
)) {
244 debugl1(cs
, "Amd7930: bh, D-Channel Busy cleared");
246 while (stptr
!= NULL
) {
247 stptr
->l2
.l1l2(stptr
, PH_PAUSE
| CONFIRM
, NULL
);
251 if (test_and_clear_bit(D_L1STATECHANGE
, &cs
->event
)) {
252 if (cs
->debug
& L1_DEB_ISAC
)
253 debugl1(cs
, "AMD7930: bh, D_L1STATECHANGE");
257 if (test_and_clear_bit(D_RCVBUFREADY
, &cs
->event
)) {
258 if (cs
->debug
& L1_DEB_ISAC
)
259 debugl1(cs
, "AMD7930: bh, D_RCVBUFREADY");
260 DChannel_proc_rcv(cs
);
263 if (test_and_clear_bit(D_XMTBUFREADY
, &cs
->event
)) {
264 if (cs
->debug
& L1_DEB_ISAC
)
265 debugl1(cs
, "AMD7930: bh, D_XMTBUFREADY");
266 DChannel_proc_xmt(cs
);
272 Amd7930_empty_Dfifo(struct IsdnCardState
*cs
, int flag
)
280 if ((cs
->debug
& L1_DEB_ISAC
) && !(cs
->debug
& L1_DEB_ISAC_FIFO
))
281 debugl1(cs
, "Amd7930: empty_Dfifo");
284 ptr
= cs
->rcvbuf
+ cs
->rcvidx
;
286 /* AMD interrupts off */
289 /* read D-Channel-Fifo*/
290 stat
= rByteAMD(cs
, 0x07); // DSR2
292 /* while Data in Fifo ... */
293 while ( (stat
& 2) && ((ptr
-cs
->rcvbuf
) < MAX_DFRAME_LEN_L1
) ) {
294 *ptr
= rByteAMD(cs
, 0x04); // DCRB
296 stat
= rByteAMD(cs
, 0x07); // DSR2
297 cs
->rcvidx
= ptr
- cs
->rcvbuf
;
302 der
= rWordAMD(cs
, 0x03);
304 /* no errors, packet ok */
306 rWordAMD(cs
, 0x89); // clear DRCR
308 if ((cs
->rcvidx
) > 0) {
309 if (!(skb
= alloc_skb(cs
->rcvidx
, GFP_ATOMIC
)))
310 printk(KERN_WARNING
"HiSax: Amd7930: empty_Dfifo, D receive out of memory!\n");
313 if (cs
->debug
& L1_DEB_ISAC_FIFO
) {
316 t
+= sprintf(t
, "Amd7930: empty_Dfifo cnt: %d |", cs
->rcvidx
);
317 QuickHex(t
, cs
->rcvbuf
, cs
->rcvidx
);
318 debugl1(cs
, cs
->dlog
);
320 /* moves received data in sk-buffer */
321 memcpy(skb_put(skb
, cs
->rcvidx
), cs
->rcvbuf
, cs
->rcvidx
);
322 skb_queue_tail(&cs
->rq
, skb
);
327 /* throw damaged packets away, reset recieve-buffer, indicate RX */
330 sched_d_event(cs
, D_RCVBUFREADY
);
333 /* Packet too long, overflow */
334 if(cs
->rcvidx
>= MAX_DFRAME_LEN_L1
) {
335 if (cs
->debug
& L1_DEB_WARN
)
336 debugl1(cs
, "AMD7930: empty_Dfifo L2-Framelength overrun");
340 /* AMD interrupts on */
346 Amd7930_fill_Dfifo(struct IsdnCardState
*cs
)
349 u16 dtcrr
, dtcrw
, len
, count
;
353 if ((cs
->debug
& L1_DEB_ISAC
) && !(cs
->debug
& L1_DEB_ISAC_FIFO
))
354 debugl1(cs
, "Amd7930: fill_Dfifo");
356 if ((!cs
->tx_skb
) || (cs
->tx_skb
->len
<= 0))
360 if(!cs
->dc
.amd7930
.tx_xmtlen
)
362 len
= dtcrw
= cs
->tx_skb
->len
;
364 else len
= cs
->dc
.amd7930
.tx_xmtlen
;
367 /* AMD interrupts off */
370 deb_ptr
= ptr
= cs
->tx_skb
->data
;
372 /* while free place in tx-fifo available and data in sk-buffer */
374 while((txstat
& 0x10) && (cs
->tx_cnt
< len
)) {
375 wByteAMD(cs
, 0x04, *ptr
);
378 txstat
= rByteAMD(cs
, 0x07);
380 count
= ptr
- cs
->tx_skb
->data
;
381 skb_pull(cs
->tx_skb
, count
);
384 dtcrr
= rWordAMD(cs
, 0x85); // DTCR
385 dmr3
= rByteAMD(cs
, 0x8E);
387 if (cs
->debug
& L1_DEB_ISAC
) {
388 debugl1(cs
, "Amd7930: fill_Dfifo, DMR3: 0x%02X, DTCR read: 0x%04X write: 0x%02X 0x%02X", dmr3
, dtcrr
, LOBYTE(dtcrw
), HIBYTE(dtcrw
));
391 /* writeing of dtcrw starts transmit */
392 if(!cs
->dc
.amd7930
.tx_xmtlen
) {
393 wWordAMD(cs
, 0x85, dtcrw
);
394 cs
->dc
.amd7930
.tx_xmtlen
= dtcrw
;
397 if (test_and_set_bit(FLG_DBUSY_TIMER
, &cs
->HW_Flags
)) {
398 debugl1(cs
, "Amd7930: fill_Dfifo dbusytimer running");
399 del_timer(&cs
->dbusytimer
);
401 init_timer(&cs
->dbusytimer
);
402 cs
->dbusytimer
.expires
= jiffies
+ ((DBUSY_TIMER_VALUE
* HZ
) / 1000);
403 add_timer(&cs
->dbusytimer
);
405 if (cs
->debug
& L1_DEB_ISAC_FIFO
) {
408 t
+= sprintf(t
, "Amd7930: fill_Dfifo cnt: %d |", count
);
409 QuickHex(t
, deb_ptr
, count
);
410 debugl1(cs
, cs
->dlog
);
412 /* AMD interrupts on */
417 void Amd7930_interrupt(struct IsdnCardState
*cs
, u8 irflags
)
425 dsr1
= rByteAMD(cs
, 0x02);
426 der
= rWordAMD(cs
, 0x03);
427 dsr2
= rByteAMD(cs
, 0x07);
428 lsr
= rByteAMD(cs
, 0xA1);
430 if (cs
->debug
& L1_DEB_ISAC
)
431 debugl1(cs
, "Amd7930: interrupt: flags: 0x%02X, DSR1: 0x%02X, DSR2: 0x%02X, LSR: 0x%02X, DER=0x%04X", irflags
, dsr1
, dsr2
, lsr
, der
);
433 /* D error -> read DER and DSR2 bit 2 */
434 if (der
|| (dsr2
& 4)) {
436 if (cs
->debug
& L1_DEB_WARN
)
437 debugl1(cs
, "Amd7930: interrupt: D error DER=0x%04X", der
);
439 /* RX, TX abort if collision detected */
441 wByteAMD(cs
, 0x21, 0xC2);
442 wByteAMD(cs
, 0x21, 0x02);
443 if (test_and_clear_bit(FLG_DBUSY_TIMER
, &cs
->HW_Flags
))
444 del_timer(&cs
->dbusytimer
);
445 if (test_and_clear_bit(FLG_L1_DBUSY
, &cs
->HW_Flags
))
446 sched_d_event(cs
, D_CLEARBUSY
);
449 skb_push(cs
->tx_skb
, cs
->tx_cnt
);
451 cs
->dc
.amd7930
.tx_xmtlen
= 0;
452 Amd7930_fill_Dfifo(cs
);
454 printk(KERN_WARNING
"HiSax: Amd7930 D-Collision, no skb\n");
455 debugl1(cs
, "Amd7930: interrupt: D-Collision, no skb");
458 /* remove damaged data from fifo */
459 Amd7930_empty_Dfifo(cs
, 1);
461 if (test_and_clear_bit(FLG_DBUSY_TIMER
, &cs
->HW_Flags
))
462 del_timer(&cs
->dbusytimer
);
463 if (test_and_clear_bit(FLG_L1_DBUSY
, &cs
->HW_Flags
))
464 sched_d_event(cs
, D_CLEARBUSY
);
465 /* restart TX-Frame */
467 skb_push(cs
->tx_skb
, cs
->tx_cnt
);
469 cs
->dc
.amd7930
.tx_xmtlen
= 0;
470 Amd7930_fill_Dfifo(cs
);
474 /* D TX FIFO empty -> fill */
476 if (cs
->debug
& L1_DEB_ISAC
)
477 debugl1(cs
, "Amd7930: interrupt: clear Timer and fill D-TX-FIFO if data");
479 /* AMD interrupts off */
482 if (test_and_clear_bit(FLG_DBUSY_TIMER
, &cs
->HW_Flags
))
483 del_timer(&cs
->dbusytimer
);
484 if (test_and_clear_bit(FLG_L1_DBUSY
, &cs
->HW_Flags
))
485 sched_d_event(cs
, D_CLEARBUSY
);
488 Amd7930_fill_Dfifo(cs
);
490 /* AMD interrupts on */
495 /* D RX FIFO full or tiny packet in Fifo -> empty */
496 if ((irflags
& 2) || (dsr1
& 2)) {
497 if (cs
->debug
& L1_DEB_ISAC
)
498 debugl1(cs
, "Amd7930: interrupt: empty D-FIFO");
499 Amd7930_empty_Dfifo(cs
, 0);
503 /* D-Frame transmit complete */
505 if (cs
->debug
& L1_DEB_ISAC
) {
506 debugl1(cs
, "Amd7930: interrupt: transmit packet ready");
508 /* AMD interrupts off */
511 if (test_and_clear_bit(FLG_DBUSY_TIMER
, &cs
->HW_Flags
))
512 del_timer(&cs
->dbusytimer
);
513 if (test_and_clear_bit(FLG_L1_DBUSY
, &cs
->HW_Flags
))
514 sched_d_event(cs
, D_CLEARBUSY
);
517 if (cs
->debug
& L1_DEB_ISAC
)
518 debugl1(cs
, "Amd7930: interrupt: TX-Packet ready, freeing skb");
519 dev_kfree_skb_irq(cs
->tx_skb
);
521 cs
->dc
.amd7930
.tx_xmtlen
=0;
524 if ((cs
->tx_skb
= skb_dequeue(&cs
->sq
))) {
525 if (cs
->debug
& L1_DEB_ISAC
)
526 debugl1(cs
, "Amd7930: interrupt: TX-Packet ready, next packet dequeued");
528 cs
->dc
.amd7930
.tx_xmtlen
=0;
529 Amd7930_fill_Dfifo(cs
);
532 sched_d_event(cs
, D_XMTBUFREADY
);
533 /* AMD interrupts on */
537 /* LIU status interrupt -> read LSR, check statechanges */
539 /* AMD interrupts off */
542 if (cs
->debug
& L1_DEB_ISAC
)
543 debugl1(cs
, "Amd: interrupt: LSR=0x%02X, LIU is in state %d", lsr
, ((lsr
& 0x7) +2));
545 cs
->dc
.amd7930
.ph_state
= (lsr
& 0x7) + 2;
547 sched_d_event(cs
, D_L1STATECHANGE
);
548 /* AMD interrupts on */
552 /* reads Interrupt-Register again. If there is a new interrupt-flag: restart handler */
553 irflags
= rByteAMD(cs
, 0x00);
559 Amd7930_l1hw(struct PStack
*st
, int pr
, void *arg
)
561 struct IsdnCardState
*cs
= (struct IsdnCardState
*) st
->l1
.hardware
;
562 struct sk_buff
*skb
= arg
;
564 if (cs
->debug
& L1_DEB_ISAC
)
565 debugl1(cs
, "Amd7930: l1hw called, pr: 0x%04X", pr
);
568 case (PH_DATA
| REQUEST
):
569 if (cs
->debug
& DEB_DLOG_HEX
)
570 LogFrame(cs
, skb
->data
, skb
->len
);
571 if (cs
->debug
& DEB_DLOG_VERBOSE
)
572 dlogframe(cs
, skb
, 0);
574 skb_queue_tail(&cs
->sq
, skb
);
575 #ifdef L2FRAME_DEBUG /* psa */
576 if (cs
->debug
& L1_DEB_LAPD
)
577 Logl2Frame(cs
, skb
, "Amd7930: l1hw: PH_DATA Queued", 0);
582 cs
->dc
.amd7930
.tx_xmtlen
=0;
583 #ifdef L2FRAME_DEBUG /* psa */
584 if (cs
->debug
& L1_DEB_LAPD
)
585 Logl2Frame(cs
, skb
, "Amd7930: l1hw: PH_DATA", 0);
587 Amd7930_fill_Dfifo(cs
);
590 case (PH_PULL
| INDICATION
):
592 if (cs
->debug
& L1_DEB_WARN
)
593 debugl1(cs
, "Amd7930: l1hw: l2l1 tx_skb exist this shouldn't happen");
594 skb_queue_tail(&cs
->sq
, skb
);
597 if (cs
->debug
& DEB_DLOG_HEX
)
598 LogFrame(cs
, skb
->data
, skb
->len
);
599 if (cs
->debug
& DEB_DLOG_VERBOSE
)
600 dlogframe(cs
, skb
, 0);
603 cs
->dc
.amd7930
.tx_xmtlen
=0;
604 #ifdef L2FRAME_DEBUG /* psa */
605 if (cs
->debug
& L1_DEB_LAPD
)
606 Logl2Frame(cs
, skb
, "Amd7930: l1hw: PH_DATA_PULLED", 0);
608 Amd7930_fill_Dfifo(cs
);
610 case (PH_PULL
| REQUEST
):
611 #ifdef L2FRAME_DEBUG /* psa */
612 if (cs
->debug
& L1_DEB_LAPD
)
613 debugl1(cs
, "Amd7930: l1hw: -> PH_REQUEST_PULL, skb: %s", (cs
->tx_skb
)? "yes":"no");
616 test_and_clear_bit(FLG_L1_PULL_REQ
, &st
->l1
.Flags
);
617 st
->l2
.l1l2(st
, PH_PULL
| CONFIRM
, NULL
);
619 test_and_set_bit(FLG_L1_PULL_REQ
, &st
->l1
.Flags
);
621 case (HW_RESET
| REQUEST
):
623 if ((cs
->dc
.amd7930
.ph_state
== 8))
624 /* b-channels off, PH-AR cleared
626 Amd7930_ph_command(cs
, 0x20, "HW_RESET REQEST"); //LMR1 bit 5
628 Amd7930_ph_command(cs
, 0x40, "HW_RESET REQUEST");
629 cs
->dc
.amd7930
.ph_state
= 2;
633 case (HW_ENABLE
| REQUEST
):
634 cs
->dc
.amd7930
.ph_state
= 9;
637 case (HW_INFO3
| REQUEST
):
640 case (HW_TESTLOOP
| REQUEST
):
641 /* not implemented yet */
643 case (HW_DEACTIVATE
| RESPONSE
):
644 skb_queue_purge(&cs
->rq
);
645 skb_queue_purge(&cs
->sq
);
647 dev_kfree_skb(cs
->tx_skb
);
650 if (test_and_clear_bit(FLG_DBUSY_TIMER
, &cs
->HW_Flags
))
651 del_timer(&cs
->dbusytimer
);
652 if (test_and_clear_bit(FLG_L1_DBUSY
, &cs
->HW_Flags
))
653 sched_d_event(cs
, D_CLEARBUSY
);
656 if (cs
->debug
& L1_DEB_WARN
)
657 debugl1(cs
, "Amd7930: l1hw: unknown %04x", pr
);
663 setstack_Amd7930(struct PStack
*st
, struct IsdnCardState
*cs
)
666 if (cs
->debug
& L1_DEB_ISAC
)
667 debugl1(cs
, "Amd7930: setstack called");
669 st
->l1
.l1hw
= Amd7930_l1hw
;
674 dbusy_timer_handler(struct IsdnCardState
*cs
)
676 struct PStack
*stptr
;
681 if (cs
->debug
& L1_DEB_ISAC
)
682 debugl1(cs
, "Amd7930: dbusy_timer expired!");
684 if (test_bit(FLG_DBUSY_TIMER
, &cs
->HW_Flags
)) {
685 /* D Transmit Byte Count Register:
686 * Counts down packet's number of Bytes, 0 if packet ready */
687 dtcr
= rWordAMD(cs
, 0x85);
688 dsr1
= rByteAMD(cs
, 0x02);
689 dsr2
= rByteAMD(cs
, 0x07);
690 der
= rWordAMD(cs
, 0x03);
692 if (cs
->debug
& L1_DEB_ISAC
)
693 debugl1(cs
, "Amd7930: dbusy_timer_handler: DSR1=0x%02X, DSR2=0x%02X, DER=0x%04X, cs->tx_skb->len=%u, tx_stat=%u, dtcr=%u, cs->tx_cnt=%u", dsr1
, dsr2
, der
, cs
->tx_skb
->len
, cs
->dc
.amd7930
.tx_xmtlen
, dtcr
, cs
->tx_cnt
);
695 if ((cs
->dc
.amd7930
.tx_xmtlen
- dtcr
) < cs
->tx_cnt
) { /* D-Channel Busy */
696 test_and_set_bit(FLG_L1_DBUSY
, &cs
->HW_Flags
);
698 while (stptr
!= NULL
) {
699 stptr
->l2
.l1l2(stptr
, PH_PAUSE
| INDICATION
, NULL
);
704 /* discard frame; reset transceiver */
705 test_and_clear_bit(FLG_DBUSY_TIMER
, &cs
->HW_Flags
);
707 dev_kfree_skb_any(cs
->tx_skb
);
710 cs
->dc
.amd7930
.tx_xmtlen
= 0;
712 printk(KERN_WARNING
"HiSax: Amd7930: D-Channel Busy no skb\n");
713 debugl1(cs
, "Amd7930: D-Channel Busy no skb");
716 /* Transmitter reset, abort transmit */
717 wByteAMD(cs
, 0x21, 0x82);
718 wByteAMD(cs
, 0x21, 0x02);
719 cs
->card_ops
->irq_func(cs
->irq
, cs
, NULL
); /* FIXME? */
721 if (cs
->debug
& L1_DEB_ISAC
)
722 debugl1(cs
, "Amd7930: dbusy_timer_handler: Transmitter reset");
727 static u16 initAMD
[] = {
730 0x00A5, 3, 0x01, 0x40, 0x58, // LPR, LMR1, LMR2
731 0x0086, 1, 0x0B, // DMR1 (D-Buffer TH-Interrupts on)
732 0x0087, 1, 0xFF, // DMR2
733 0x0092, 1, 0x03, // EFCR (extended mode d-channel-fifo on)
734 0x0090, 4, 0xFE, 0xFF, 0x02, 0x0F, // FRAR4, SRAR4, DMR3, DMR4 (address recognition )
735 0x0084, 2, 0x80, 0x00, // DRLR
736 0x00C0, 1, 0x47, // PPCR1
737 0x00C8, 1, 0x01, // PPCR2
745 0x0045, 4, 0x61, 0x72, 0x00, 0x00, // MCR1, MCR2, MCR3, MCR4
746 0x0063, 2, 0x08, 0x08, // GX
747 0x0064, 2, 0x08, 0x08, // GR
748 0x0065, 2, 0x99, 0x00, // GER
749 0x0066, 2, 0x7C, 0x8B, // STG
750 0x0067, 2, 0x00, 0x00, // FTGR1, FTGR2
751 0x0068, 2, 0x20, 0x20, // ATGR1, ATGR2
752 0x0069, 1, 0x4F, // MMR1
753 0x006A, 1, 0x00, // MMR2
754 0x006C, 1, 0x40, // MMR3
755 0x0021, 1, 0x02, // INIT
756 0x00A3, 1, 0x40, // LMR1
760 static struct dc_l1_ops amd7930_l1_ops
= {
761 .open
= setstack_Amd7930
,
762 .bh_func
= Amd7930_bh
,
763 .dbusy_func
= dbusy_timer_handler
,
767 Amd7930_init(struct IsdnCardState
*cs
)
772 if (cs
->debug
& L1_DEB_ISAC
)
773 debugl1(cs
, "Amd7930: initamd called");
775 dc_l1_init(cs
, &amd7930_l1_ops
);
776 cs
->dc
.amd7930
.tx_xmtlen
= 0;
777 cs
->dc
.amd7930
.old_state
= 0;
778 cs
->dc
.amd7930
.lmr1
= 0x40;
779 cs
->dc
.amd7930
.ph_command
= Amd7930_ph_command
;
781 /* AMD Initialisation */
782 for (ptr
= initAMD
; *ptr
!= 0xFFFF; ) {
786 if (*ptr
++ >= 0x100) {
788 /* setzt Register zurück */
791 wByteAMD(cs
, 0x00, cmd
);
792 for (cnt
= *ptr
++; cnt
> 0; cnt
--)
798 wByteAMD(cs
, cmd
, LOBYTE(*ptr
++));
801 wByteAMD(cs
, 0x00, cmd
);
802 for (cnt
= *ptr
++; cnt
> 0; cnt
--)
803 wByteAMD(cs
, 0x01, LOBYTE(*ptr
++));
809 amd7930_setup(struct IsdnCardState
*cs
, struct dc_hw_ops
*amd7930_ops
,
810 void (*set_irq_mask
)(struct IsdnCardState
*, u8 val
))
812 cs
->dc_hw_ops
= amd7930_ops
;
813 cs
->dc
.amd7930
.setIrqMask
= set_irq_mask
;