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Make HZ_TO_STD macro name lowercase.
[linux-2.6/linux-mips.git] / drivers / ide / pdc202xx.c
blob66a12384133ba4b720a3f16b3ea8f77f61598c40
1 /*
2 * linux/drivers/ide/pdc202xx.c Version 0.30 Mar. 18, 2000
3 *
4 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
5 * May be copied or modified under the terms of the GNU General Public License
6 *
7 * Promise Ultra33 cards with BIOS v1.20 through 1.28 will need this
8 * compiled into the kernel if you have more than one card installed.
9 * Note that BIOS v1.29 is reported to fix the problem. Since this is
10 * safe chipset tuning, including this support is harmless
11 *
12 * Promise Ultra66 cards with BIOS v1.11 this
13 * compiled into the kernel if you have more than one card installed.
14 *
15 * Promise Ultra100 cards.
16 *
17 * The latest chipset code will support the following ::
18 * Three Ultra33 controllers and 12 drives.
19 * 8 are UDMA supported and 4 are limited to DMA mode 2 multi-word.
20 * The 8/4 ratio is a BIOS code limit by promise.
21 *
22 * UNLESS you enable "CONFIG_PDC202XX_BURST"
23 *
24 */
25
26 /*
27 * Portions Copyright (C) 1999 Promise Technology, Inc.
28 * Author: Frank Tiernan (frankt@promise.com)
29 * Released under terms of General Public License
30 */
31
32 #include <linux/config.h>
33 #include <linux/types.h>
34 #include <linux/kernel.h>
35 #include <linux/delay.h>
36 #include <linux/timer.h>
37 #include <linux/mm.h>
38 #include <linux/ioport.h>
39 #include <linux/blkdev.h>
40 #include <linux/hdreg.h>
41 #include <linux/interrupt.h>
42 #include <linux/pci.h>
43 #include <linux/init.h>
44 #include <linux/ide.h>
45
46 #include <asm/io.h>
47 #include <asm/irq.h>
48
49 #include "ide_modes.h"
50
51 #define PDC202XX_DEBUG_DRIVE_INFO 0
52 #define PDC202XX_DECODE_REGISTER_INFO 0
53
54 #define DISPLAY_PDC202XX_TIMINGS
55
56 #ifndef SPLIT_BYTE
57 #define SPLIT_BYTE(B,H,L) ((H)=(B>>4), (L)=(B-((B>>4)<<4)))
58 #endif
59
60 #if defined(DISPLAY_PDC202XX_TIMINGS) && defined(CONFIG_PROC_FS)
61 #include <linux/stat.h>
62 #include <linux/proc_fs.h>
63
64 static int pdc202xx_get_info(char *, char **, off_t, int);
65 extern int (*pdc202xx_display_info)(char *, char **, off_t, int); /* ide-proc.c */
66 extern char *ide_media_verbose(ide_drive_t *);
67 static struct pci_dev *bmide_dev;
68
69 char *pdc202xx_pio_verbose (u32 drive_pci)
70 {
71 if ((drive_pci & 0x000ff000) == 0x000ff000) return("NOTSET");
72 if ((drive_pci & 0x00000401) == 0x00000401) return("PIO 4");
73 if ((drive_pci & 0x00000602) == 0x00000602) return("PIO 3");
74 if ((drive_pci & 0x00000803) == 0x00000803) return("PIO 2");
75 if ((drive_pci & 0x00000C05) == 0x00000C05) return("PIO 1");
76 if ((drive_pci & 0x00001309) == 0x00001309) return("PIO 0");
77 return("PIO ?");
78 }
79
80 char *pdc202xx_dma_verbose (u32 drive_pci)
81 {
82 if ((drive_pci & 0x00036000) == 0x00036000) return("MWDMA 2");
83 if ((drive_pci & 0x00046000) == 0x00046000) return("MWDMA 1");
84 if ((drive_pci & 0x00056000) == 0x00056000) return("MWDMA 0");
85 if ((drive_pci & 0x00056000) == 0x00056000) return("SWDMA 2");
86 if ((drive_pci & 0x00068000) == 0x00068000) return("SWDMA 1");
87 if ((drive_pci & 0x000BC000) == 0x000BC000) return("SWDMA 0");
88 return("PIO---");
89 }
90
91 char *pdc202xx_ultra_verbose (u32 drive_pci, u16 slow_cable)
92 {
93 if ((drive_pci & 0x000ff000) == 0x000ff000)
94 return("NOTSET");
95 if ((drive_pci & 0x00012000) == 0x00012000)
96 return((slow_cable) ? "UDMA 2" : "UDMA 4");
97 if ((drive_pci & 0x00024000) == 0x00024000)
98 return((slow_cable) ? "UDMA 1" : "UDMA 3");
99 if ((drive_pci & 0x00036000) == 0x00036000)
100 return("UDMA 0");
101 return(pdc202xx_dma_verbose(drive_pci));
102 }
103
104 static int pdc202xx_get_info (char *buffer, char **addr, off_t offset, int count)
105 {
106 char *p = buffer;
107
108 u32 bibma = pci_resource_start(bmide_dev, 4);
109 u32 reg60h = 0, reg64h = 0, reg68h = 0, reg6ch = 0;
110 u16 reg50h = 0, pmask = (1<<10), smask = (1<<11);
111 u8 hi = 0, lo = 0;
112
113 /*
114 * at that point bibma+0x2 et bibma+0xa are byte registers
115 * to investigate:
116 */
117 u8 c0 = inb_p((unsigned short)bibma + 0x02);
118 u8 c1 = inb_p((unsigned short)bibma + 0x0a);
119
120 u8 sc11 = inb_p((unsigned short)bibma + 0x11);
121 u8 sc1a = inb_p((unsigned short)bibma + 0x1a);
122 u8 sc1b = inb_p((unsigned short)bibma + 0x1b);
123 u8 sc1c = inb_p((unsigned short)bibma + 0x1c);
124 u8 sc1d = inb_p((unsigned short)bibma + 0x1d);
125 u8 sc1e = inb_p((unsigned short)bibma + 0x1e);
126 u8 sc1f = inb_p((unsigned short)bibma + 0x1f);
127
128 pci_read_config_word(bmide_dev, 0x50, &reg50h);
129 pci_read_config_dword(bmide_dev, 0x60, &reg60h);
130 pci_read_config_dword(bmide_dev, 0x64, &reg64h);
131 pci_read_config_dword(bmide_dev, 0x68, &reg68h);
132 pci_read_config_dword(bmide_dev, 0x6c, &reg6ch);
133
134 switch(bmide_dev->device) {
135 case PCI_DEVICE_ID_PROMISE_20267:
136 p += sprintf(p, "\n PDC20267 Chipset.\n");
137 break;
138 case PCI_DEVICE_ID_PROMISE_20262:
139 p += sprintf(p, "\n PDC20262 Chipset.\n");
140 break;
141 case PCI_DEVICE_ID_PROMISE_20246:
142 p += sprintf(p, "\n PDC20246 Chipset.\n");
143 reg50h |= 0x0c00;
144 break;
145 default:
146 p += sprintf(p, "\n PDC202XX Chipset.\n");
147 break;
148 }
149
150 p += sprintf(p, "------------------------------- General Status ---------------------------------\n");
151 p += sprintf(p, "Burst Mode : %sabled\n", (sc1f & 0x01) ? "en" : "dis");
152 p += sprintf(p, "Host Mode : %s\n", (sc1f & 0x08) ? "Tri-Stated" : "Normal");
153 p += sprintf(p, "Bus Clocking : %s\n",
154 ((sc1f & 0xC0) == 0xC0) ? "100 External" :
155 ((sc1f & 0x80) == 0x80) ? "66 External" :
156 ((sc1f & 0x40) == 0x40) ? "33 External" : "33 PCI Internal");
157 p += sprintf(p, "IO pad select : %s mA\n",
158 ((sc1c & 0x03) == 0x03) ? "10" :
159 ((sc1c & 0x02) == 0x02) ? "8" :
160 ((sc1c & 0x01) == 0x01) ? "6" :
161 ((sc1c & 0x00) == 0x00) ? "4" : "??");
162 SPLIT_BYTE(sc1e, hi, lo);
163 p += sprintf(p, "Status Polling Period : %d\n", hi);
164 p += sprintf(p, "Interrupt Check Status Polling Delay : %d\n", lo);
165 p += sprintf(p, "--------------- Primary Channel ---------------- Secondary Channel -------------\n");
166 p += sprintf(p, " %s %s\n",
167 (c0&0x80)?"disabled":"enabled ",
168 (c1&0x80)?"disabled":"enabled ");
169 p += sprintf(p, "66 Clocking %s %s\n",
170 (sc11&0x02)?"enabled ":"disabled",
171 (sc11&0x08)?"enabled ":"disabled");
172 p += sprintf(p, " Mode %s Mode %s\n",
173 (sc1a & 0x01) ? "MASTER" : "PCI ",
174 (sc1b & 0x01) ? "MASTER" : "PCI ");
175 p += sprintf(p, " %s %s\n",
176 (sc1d & 0x08) ? "Error " :
177 (sc1d & 0x04) ? "Interrupting" :
178 (sc1d & 0x02) ? "FIFO Full " :
179 (sc1d & 0x01) ? "FIFO Empty " : "????????????",
180 (sc1d & 0x80) ? "Error " :
181 (sc1d & 0x40) ? "Interrupting" :
182 (sc1d & 0x20) ? "FIFO Full " :
183 (sc1d & 0x10) ? "FIFO Empty " : "????????????");
184 p += sprintf(p, "--------------- drive0 --------- drive1 -------- drive0 ---------- drive1 ------\n");
185 p += sprintf(p, "DMA enabled: %s %s %s %s\n",
186 (c0&0x20)?"yes":"no ",(c0&0x40)?"yes":"no ",(c1&0x20)?"yes":"no ",(c1&0x40)?"yes":"no ");
187 p += sprintf(p, "DMA Mode: %s %s %s %s\n",
188 pdc202xx_ultra_verbose(reg60h, (reg50h & pmask)),
189 pdc202xx_ultra_verbose(reg64h, (reg50h & pmask)),
190 pdc202xx_ultra_verbose(reg68h, (reg50h & smask)),
191 pdc202xx_ultra_verbose(reg6ch, (reg50h & smask)));
192 p += sprintf(p, "PIO Mode: %s %s %s %s\n",
193 pdc202xx_pio_verbose(reg60h),pdc202xx_pio_verbose(reg64h),
194 pdc202xx_pio_verbose(reg68h),pdc202xx_pio_verbose(reg6ch));
195 #if 0
196 p += sprintf(p, "--------------- Can ATAPI DMA ---------------\n");
197 #endif
198
199 return p-buffer; /* => must be less than 4k! */
200 }
201 #endif /* defined(DISPLAY_PDC202XX_TIMINGS) && defined(CONFIG_PROC_FS) */
202
203 byte pdc202xx_proc = 0;
204
205 extern char *ide_xfer_verbose (byte xfer_rate);
206
207 /* A Register */
208 #define SYNC_ERRDY_EN 0xC0
209
210 #define SYNC_IN 0x80 /* control bit, different for master vs. slave drives */
211 #define ERRDY_EN 0x40 /* control bit, different for master vs. slave drives */
212 #define IORDY_EN 0x20 /* PIO: IOREADY */
213 #define PREFETCH_EN 0x10 /* PIO: PREFETCH */
214
215 #define PA3 0x08 /* PIO"A" timing */
216 #define PA2 0x04 /* PIO"A" timing */
217 #define PA1 0x02 /* PIO"A" timing */
218 #define PA0 0x01 /* PIO"A" timing */
219
220 /* B Register */
221
222 #define MB2 0x80 /* DMA"B" timing */
223 #define MB1 0x40 /* DMA"B" timing */
224 #define MB0 0x20 /* DMA"B" timing */
225
226 #define PB4 0x10 /* PIO_FORCE 1:0 */
227
228 #define PB3 0x08 /* PIO"B" timing */ /* PIO flow Control mode */
229 #define PB2 0x04 /* PIO"B" timing */ /* PIO 4 */
230 #define PB1 0x02 /* PIO"B" timing */ /* PIO 3 half */
231 #define PB0 0x01 /* PIO"B" timing */ /* PIO 3 other half */
232
233 /* C Register */
234 #define IORDYp_NO_SPEED 0x4F
235 #define SPEED_DIS 0x0F
236
237 #define DMARQp 0x80
238 #define IORDYp 0x40
239 #define DMAR_EN 0x20
240 #define DMAW_EN 0x10
241
242 #define MC3 0x08 /* DMA"C" timing */
243 #define MC2 0x04 /* DMA"C" timing */
244 #define MC1 0x02 /* DMA"C" timing */
245 #define MC0 0x01 /* DMA"C" timing */
246
247 #if PDC202XX_DECODE_REGISTER_INFO
248
249 #define REG_A 0x01
250 #define REG_B 0x02
251 #define REG_C 0x04
252 #define REG_D 0x08
253
254 static void decode_registers (byte registers, byte value)
255 {
256 byte bit = 0, bit1 = 0, bit2 = 0;
257
258 switch(registers) {
259 case REG_A:
260 bit2 = 0;
261 printk("A Register ");
262 if (value & 0x80) printk("SYNC_IN ");
263 if (value & 0x40) printk("ERRDY_EN ");
264 if (value & 0x20) printk("IORDY_EN ");
265 if (value & 0x10) printk("PREFETCH_EN ");
266 if (value & 0x08) { printk("PA3 ");bit2 |= 0x08; }
267 if (value & 0x04) { printk("PA2 ");bit2 |= 0x04; }
268 if (value & 0x02) { printk("PA1 ");bit2 |= 0x02; }
269 if (value & 0x01) { printk("PA0 ");bit2 |= 0x01; }
270 printk("PIO(A) = %d ", bit2);
271 break;
272 case REG_B:
273 bit1 = 0;bit2 = 0;
274 printk("B Register ");
275 if (value & 0x80) { printk("MB2 ");bit1 |= 0x80; }
276 if (value & 0x40) { printk("MB1 ");bit1 |= 0x40; }
277 if (value & 0x20) { printk("MB0 ");bit1 |= 0x20; }
278 printk("DMA(B) = %d ", bit1 >> 5);
279 if (value & 0x10) printk("PIO_FORCED/PB4 ");
280 if (value & 0x08) { printk("PB3 ");bit2 |= 0x08; }
281 if (value & 0x04) { printk("PB2 ");bit2 |= 0x04; }
282 if (value & 0x02) { printk("PB1 ");bit2 |= 0x02; }
283 if (value & 0x01) { printk("PB0 ");bit2 |= 0x01; }
284 printk("PIO(B) = %d ", bit2);
285 break;
286 case REG_C:
287 bit2 = 0;
288 printk("C Register ");
289 if (value & 0x80) printk("DMARQp ");
290 if (value & 0x40) printk("IORDYp ");
291 if (value & 0x20) printk("DMAR_EN ");
292 if (value & 0x10) printk("DMAW_EN ");
293
294 if (value & 0x08) { printk("MC3 ");bit2 |= 0x08; }
295 if (value & 0x04) { printk("MC2 ");bit2 |= 0x04; }
296 if (value & 0x02) { printk("MC1 ");bit2 |= 0x02; }
297 if (value & 0x01) { printk("MC0 ");bit2 |= 0x01; }
298 printk("DMA(C) = %d ", bit2);
299 break;
300 case REG_D:
301 printk("D Register ");
302 break;
303 default:
304 return;
305 }
306 printk("\n %s ", (registers & REG_D) ? "DP" :
307 (registers & REG_C) ? "CP" :
308 (registers & REG_B) ? "BP" :
309 (registers & REG_A) ? "AP" : "ERROR");
310 for (bit=128;bit>0;bit/=2)
311 printk("%s", (value & bit) ? "1" : "0");
312 printk("\n");
313 }
314
315 #endif /* PDC202XX_DECODE_REGISTER_INFO */
316
317 static int pdc202xx_tune_chipset (ide_drive_t *drive, byte speed)
318 {
319 ide_hwif_t *hwif = HWIF(drive);
320 struct pci_dev *dev = hwif->pci_dev;
321
322 unsigned int drive_conf;
323 int err;
324 byte drive_pci, AP, BP, CP, DP;
325 byte TA = 0, TB = 0, TC = 0;
326
327 switch (drive->dn) {
328 case 0: drive_pci = 0x60; break;
329 case 1: drive_pci = 0x64; break;
330 case 2: drive_pci = 0x68; break;
331 case 3: drive_pci = 0x6c; break;
332 default: return -1;
333 }
334
335 if ((drive->media != ide_disk) && (speed < XFER_SW_DMA_0)) return -1;
336
337 pci_read_config_dword(dev, drive_pci, &drive_conf);
338 pci_read_config_byte(dev, (drive_pci), &AP);
339 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
340 pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
341 pci_read_config_byte(dev, (drive_pci)|0x03, &DP);
342
343 #ifdef CONFIG_BLK_DEV_IDEDMA
344 if (speed >= XFER_SW_DMA_0) {
345 if ((BP & 0xF0) && (CP & 0x0F)) {
346 /* clear DMA modes of upper 842 bits of B Register */
347 /* clear PIO forced mode upper 1 bit of B Register */
348 pci_write_config_byte(dev, (drive_pci)|0x01, BP & ~0xF0);
349 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
350
351 /* clear DMA modes of lower 8421 bits of C Register */
352 pci_write_config_byte(dev, (drive_pci)|0x02, CP & ~0x0F);
353 pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
354 }
355 } else {
356 #else
357 {
358 #endif /* CONFIG_BLK_DEV_IDEDMA */
359 if ((AP & 0x0F) || (BP & 0x07)) {
360 /* clear PIO modes of lower 8421 bits of A Register */
361 pci_write_config_byte(dev, (drive_pci), AP & ~0x0F);
362 pci_read_config_byte(dev, (drive_pci), &AP);
363
364 /* clear PIO modes of lower 421 bits of B Register */
365 pci_write_config_byte(dev, (drive_pci)|0x01, BP & ~0x07);
366 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
367
368 pci_read_config_byte(dev, (drive_pci), &AP);
369 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
370 }
371 }
372
373 pci_read_config_byte(dev, (drive_pci), &AP);
374 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
375 pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
376
377 switch(speed) {
378 #ifdef CONFIG_BLK_DEV_IDEDMA
379 case XFER_UDMA_5:
380 case XFER_UDMA_4: TB = 0x20; TC = 0x01; break; /* speed 8 == UDMA mode 4 */
381 case XFER_UDMA_3: TB = 0x40; TC = 0x02; break; /* speed 7 == UDMA mode 3 */
382 case XFER_UDMA_2: TB = 0x20; TC = 0x01; break; /* speed 6 == UDMA mode 2 */
383 case XFER_UDMA_1: TB = 0x40; TC = 0x02; break; /* speed 5 == UDMA mode 1 */
384 case XFER_UDMA_0: TB = 0x60; TC = 0x03; break; /* speed 4 == UDMA mode 0 */
385 case XFER_MW_DMA_2: TB = 0x60; TC = 0x03; break; /* speed 4 == MDMA mode 2 */
386 case XFER_MW_DMA_1: TB = 0x60; TC = 0x04; break; /* speed 3 == MDMA mode 1 */
387 case XFER_MW_DMA_0: TB = 0x60; TC = 0x05; break; /* speed 2 == MDMA mode 0 */
388 case XFER_SW_DMA_2: TB = 0x60; TC = 0x05; break; /* speed 0 == SDMA mode 2 */
389 case XFER_SW_DMA_1: TB = 0x80; TC = 0x06; break; /* speed 1 == SDMA mode 1 */
390 case XFER_SW_DMA_0: TB = 0xC0; TC = 0x0B; break; /* speed 0 == SDMA mode 0 */
391 #endif /* CONFIG_BLK_DEV_IDEDMA */
392 case XFER_PIO_4: TA = 0x01; TB = 0x04; break;
393 case XFER_PIO_3: TA = 0x02; TB = 0x06; break;
394 case XFER_PIO_2: TA = 0x03; TB = 0x08; break;
395 case XFER_PIO_1: TA = 0x05; TB = 0x0C; break;
396 case XFER_PIO_0:
397 default: TA = 0x09; TB = 0x13; break;
398 }
399
400 #ifdef CONFIG_BLK_DEV_IDEDMA
401 if (speed >= XFER_SW_DMA_0) {
402 pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
403 pci_write_config_byte(dev, (drive_pci)|0x02, CP|TC);
404 } else {
405 #else
406 {
407 #endif /* CONFIG_BLK_DEV_IDEDMA */
408 pci_write_config_byte(dev, (drive_pci), AP|TA);
409 pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
410 }
411
412 #if PDC202XX_DECODE_REGISTER_INFO
413 pci_read_config_byte(dev, (drive_pci), &AP);
414 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
415 pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
416 pci_read_config_byte(dev, (drive_pci)|0x03, &DP);
417
418 decode_registers(REG_A, AP);
419 decode_registers(REG_B, BP);
420 decode_registers(REG_C, CP);
421 decode_registers(REG_D, DP);
422 #endif /* PDC202XX_DECODE_REGISTER_INFO */
423
424 err = ide_config_drive_speed(drive, speed);
425
426 #if PDC202XX_DEBUG_DRIVE_INFO
427 printk("%s: %s drive%d 0x%08x ",
428 drive->name, ide_xfer_verbose(speed),
429 drive->dn, drive_conf);
430 pci_read_config_dword(dev, drive_pci, &drive_conf);
431 printk("0x%08x\n", drive_conf);
432 #endif /* PDC202XX_DEBUG_DRIVE_INFO */
433 return err;
434 }
435
436 /* 0 1 2 3 4 5 6 7 8
437 * 960, 480, 390, 300, 240, 180, 120, 90, 60
438 * 180, 150, 120, 90, 60
439 * DMA_Speed
440 * 180, 120, 90, 90, 90, 60, 30
441 * 11, 5, 4, 3, 2, 1, 0
442 */
443 static int config_chipset_for_pio (ide_drive_t *drive, byte pio)
444 {
445 byte speed = 0x00;
446
447 pio = (pio == 5) ? 4 : pio;
448 speed = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, pio, NULL);
449
450 return ((int) pdc202xx_tune_chipset(drive, speed));
451 }
452
453 static void pdc202xx_tune_drive (ide_drive_t *drive, byte pio)
454 {
455 (void) config_chipset_for_pio(drive, pio);
456 }
457
458 #ifdef CONFIG_BLK_DEV_IDEDMA
459 static int config_chipset_for_dma (ide_drive_t *drive, byte ultra)
460 {
461 struct hd_driveid *id = drive->id;
462 ide_hwif_t *hwif = HWIF(drive);
463 struct pci_dev *dev = hwif->pci_dev;
464 unsigned long high_16 = pci_resource_start(dev, 4);
465 unsigned long dma_base = hwif->dma_base;
466 byte unit = (drive->select.b.unit & 0x01);
467
468 unsigned int drive_conf;
469 byte drive_pci;
470 byte test1, test2, speed = -1;
471 byte AP;
472 unsigned short EP;
473 byte CLKSPD = IN_BYTE(high_16 + 0x11);
474 byte udma_33 = ultra ? (inb(high_16 + 0x001f) & 1) : 0;
475 byte udma_66 = ((eighty_ninty_three(drive)) && udma_33) ? 1 : 0;
476 byte udma_100 = ((dev->device == PCI_DEVICE_ID_PROMISE_20267) && udma_66) ? 1 : 0;
477
478 /*
479 * Set the control register to use the 66Mhz system
480 * clock for UDMA 3/4 mode operation. If one drive on
481 * a channel is U66 capable but the other isn't we
482 * fall back to U33 mode. The BIOS INT 13 hooks turn
483 * the clock on then off for each read/write issued. I don't
484 * do that here because it would require modifying the
485 * kernel, seperating the fop routines from the kernel or
486 * somehow hooking the fops calls. It may also be possible to
487 * leave the 66Mhz clock on and readjust the timing
488 * parameters.
489 */
490
491 byte mask = hwif->channel ? 0x08 : 0x02;
492 unsigned short c_mask = hwif->channel ? (1<<11) : (1<<10);
493 byte ultra_66 = ((id->dma_ultra & 0x0010) ||
494 (id->dma_ultra & 0x0008)) ? 1 : 0;
495 byte ultra_100 = ((id->dma_ultra & 0x0020) ||
496 (id->dma_ultra & 0x0010) ||
497 (id->dma_ultra & 0x0008)) ? 1 : 0;
498
499 pci_read_config_word(dev, 0x50, &EP);
500
501 if (((ultra_66) || (ultra_100)) && (EP & c_mask)) {
502 #ifdef DEBUG
503 printk("ULTRA66: %s channel of Ultra 66 requires an 80-pin cable for Ultra66 operation.\n", hwif->channel ? "Secondary", "Primary");
504 printk(" Switching to Ultra33 mode.\n");
505 #endif /* DEBUG */
506 /* Primary : zero out second bit */
507 /* Secondary : zero out fourth bit */
508 OUT_BYTE(CLKSPD & ~mask, (high_16 + 0x11));
509 } else {
510 if ((ultra_66) || (ultra_100)) {
511 /*
512 * check to make sure drive on same channel
513 * is u66 capable
514 */
515 if (hwif->drives[!(drive->dn%2)].id) {
516 if ((hwif->drives[!(drive->dn%2)].id->dma_ultra & 0x0020) ||
517 (hwif->drives[!(drive->dn%2)].id->dma_ultra & 0x0010) ||
518 (hwif->drives[!(drive->dn%2)].id->dma_ultra & 0x0008)) {
519 OUT_BYTE(CLKSPD | mask, (high_16 + 0x11));
520 } else {
521 OUT_BYTE(CLKSPD & ~mask, (high_16 + 0x11));
522 }
523 } else { /* udma4 drive by itself */
524 OUT_BYTE(CLKSPD | mask, (high_16 + 0x11));
525 }
526 }
527 }
528
529 switch(drive->dn) {
530 case 0: drive_pci = 0x60;
531 pci_read_config_dword(dev, drive_pci, &drive_conf);
532 if ((drive_conf != 0x004ff304) && (drive_conf != 0x004ff3c4))
533 goto chipset_is_set;
534 pci_read_config_byte(dev, (drive_pci), &test1);
535 if (!(test1 & SYNC_ERRDY_EN))
536 pci_write_config_byte(dev, (drive_pci), test1|SYNC_ERRDY_EN);
537 break;
538 case 1: drive_pci = 0x64;
539 pci_read_config_dword(dev, drive_pci, &drive_conf);
540 if ((drive_conf != 0x004ff304) && (drive_conf != 0x004ff3c4))
541 goto chipset_is_set;
542 pci_read_config_byte(dev, 0x60, &test1);
543 pci_read_config_byte(dev, (drive_pci), &test2);
544 if ((test1 & SYNC_ERRDY_EN) && !(test2 & SYNC_ERRDY_EN))
545 pci_write_config_byte(dev, (drive_pci), test2|SYNC_ERRDY_EN);
546 break;
547 case 2: drive_pci = 0x68;
548 pci_read_config_dword(dev, drive_pci, &drive_conf);
549 if ((drive_conf != 0x004ff304) && (drive_conf != 0x004ff3c4))
550 goto chipset_is_set;
551 pci_read_config_byte(dev, (drive_pci), &test1);
552 if (!(test1 & SYNC_ERRDY_EN))
553 pci_write_config_byte(dev, (drive_pci), test1|SYNC_ERRDY_EN);
554 break;
555 case 3: drive_pci = 0x6c;
556 pci_read_config_dword(dev, drive_pci, &drive_conf);
557 if ((drive_conf != 0x004ff304) && (drive_conf != 0x004ff3c4))
558 goto chipset_is_set;
559 pci_read_config_byte(dev, 0x68, &test1);
560 pci_read_config_byte(dev, (drive_pci), &test2);
561 if ((test1 & SYNC_ERRDY_EN) && !(test2 & SYNC_ERRDY_EN))
562 pci_write_config_byte(dev, (drive_pci), test2|SYNC_ERRDY_EN);
563 break;
564 default:
565 return ide_dma_off;
566 }
567
568 chipset_is_set:
569
570 if (drive->media != ide_disk) return ide_dma_off_quietly;
571
572 pci_read_config_byte(dev, (drive_pci), &AP);
573 if (id->capability & 4) /* IORDY_EN */
574 pci_write_config_byte(dev, (drive_pci), AP|IORDY_EN);
575 pci_read_config_byte(dev, (drive_pci), &AP);
576 if (drive->media == ide_disk) /* PREFETCH_EN */
577 pci_write_config_byte(dev, (drive_pci), AP|PREFETCH_EN);
578
579 if ((id->dma_ultra & 0x0020) && (udma_100)) speed = XFER_UDMA_5;
580 else if ((id->dma_ultra & 0x0010) && (udma_66)) speed = XFER_UDMA_4;
581 else if ((id->dma_ultra & 0x0008) && (udma_66)) speed = XFER_UDMA_3;
582 else if ((id->dma_ultra & 0x0004) && (udma_33)) speed = XFER_UDMA_2;
583 else if ((id->dma_ultra & 0x0002) && (udma_33)) speed = XFER_UDMA_1;
584 else if ((id->dma_ultra & 0x0001) && (udma_33)) speed = XFER_UDMA_0;
585 else if (id->dma_mword & 0x0004) speed = XFER_MW_DMA_2;
586 else if (id->dma_mword & 0x0002) speed = XFER_MW_DMA_1;
587 else if (id->dma_mword & 0x0001) speed = XFER_MW_DMA_0;
588 else if (id->dma_1word & 0x0004) speed = XFER_SW_DMA_2;
589 else if (id->dma_1word & 0x0002) speed = XFER_SW_DMA_1;
590 else if (id->dma_1word & 0x0001) speed = XFER_SW_DMA_0;
591 else {
592 /* restore original pci-config space */
593 pci_write_config_dword(dev, drive_pci, drive_conf);
594 return ide_dma_off_quietly;
595 }
596
597 outb(inb(dma_base+2) & ~(1<<(5+unit)), dma_base+2);
598 (void) pdc202xx_tune_chipset(drive, speed);
599
600 return ((int) ((id->dma_ultra >> 11) & 7) ? ide_dma_on :
601 ((id->dma_ultra >> 8) & 7) ? ide_dma_on :
602 ((id->dma_mword >> 8) & 7) ? ide_dma_on :
603 ((id->dma_1word >> 8) & 7) ? ide_dma_on :
604 ide_dma_off_quietly);
605 }
606
607 static int config_drive_xfer_rate (ide_drive_t *drive)
608 {
609 struct hd_driveid *id = drive->id;
610 ide_hwif_t *hwif = HWIF(drive);
611 ide_dma_action_t dma_func = ide_dma_off_quietly;
612
613 if (id && (id->capability & 1) && hwif->autodma) {
614 /* Consult the list of known "bad" drives */
615 if (ide_dmaproc(ide_dma_bad_drive, drive)) {
616 dma_func = ide_dma_off;
617 goto fast_ata_pio;
618 }
619 dma_func = ide_dma_off_quietly;
620 if (id->field_valid & 4) {
621 if (id->dma_ultra & 0x002F) {
622 /* Force if Capable UltraDMA */
623 dma_func = config_chipset_for_dma(drive, 1);
624 if ((id->field_valid & 2) &&
625 (dma_func != ide_dma_on))
626 goto try_dma_modes;
627 }
628 } else if (id->field_valid & 2) {
629 try_dma_modes:
630 if ((id->dma_mword & 0x0007) ||
631 (id->dma_1word & 0x0007)) {
632 /* Force if Capable regular DMA modes */
633 dma_func = config_chipset_for_dma(drive, 0);
634 if (dma_func != ide_dma_on)
635 goto no_dma_set;
636 }
637 } else if (ide_dmaproc(ide_dma_good_drive, drive)) {
638 if (id->eide_dma_time > 150) {
639 goto no_dma_set;
640 }
641 /* Consult the list of known "good" drives */
642 dma_func = config_chipset_for_dma(drive, 0);
643 if (dma_func != ide_dma_on)
644 goto no_dma_set;
645 } else {
646 goto fast_ata_pio;
647 }
648 } else if ((id->capability & 8) || (id->field_valid & 2)) {
649 fast_ata_pio:
650 dma_func = ide_dma_off_quietly;
651 no_dma_set:
652 (void) config_chipset_for_pio(drive, 5);
653 }
654
655 return HWIF(drive)->dmaproc(dma_func, drive);
656 }
657
658 /*
659 * pdc202xx_dmaproc() initiates/aborts (U)DMA read/write operations on a drive.
660 */
661 int pdc202xx_dmaproc (ide_dma_action_t func, ide_drive_t *drive)
662 {
663 switch (func) {
664 case ide_dma_check:
665 return config_drive_xfer_rate(drive);
666 case ide_dma_lostirq:
667 case ide_dma_timeout:
668 if (HWIF(drive)->resetproc != NULL)
669 HWIF(drive)->resetproc(drive);
670 default:
671 break;
672 }
673 return ide_dmaproc(func, drive); /* use standard DMA stuff */
674 }
675 #endif /* CONFIG_BLK_DEV_IDEDMA */
676
677 void pdc202xx_reset (ide_drive_t *drive)
678 {
679 unsigned long high_16 = pci_resource_start(HWIF(drive)->pci_dev, 4);
680 byte udma_speed_flag = inb(high_16 + 0x001f);
681 int i = 0;
682
683 OUT_BYTE(udma_speed_flag | 0x10, high_16 + 0x001f);
684 ide_delay_50ms();
685 ide_delay_50ms();
686 OUT_BYTE(udma_speed_flag & ~0x10, high_16 + 0x001f);
687 for (i = 0; i < 40; i++)
688 ide_delay_50ms();
689 }
690
691 unsigned int __init pci_init_pdc202xx (struct pci_dev *dev, const char *name)
692 {
693 unsigned long high_16 = pci_resource_start(dev, 4);
694 byte udma_speed_flag = inb(high_16 + 0x001f);
695 byte primary_mode = inb(high_16 + 0x001a);
696 byte secondary_mode = inb(high_16 + 0x001b);
697
698 if ((dev->device == PCI_DEVICE_ID_PROMISE_20262) ||
699 (dev->device == PCI_DEVICE_ID_PROMISE_20267)) {
700 int i = 0;
701 /*
702 * software reset - this is required because the bios
703 * will set UDMA timing on if the hdd supports it. The
704 * user may want to turn udma off. A bug in the pdc20262
705 * is that it cannot handle a downgrade in timing from UDMA
706 * to DMA. Disk accesses after issuing a set feature command
707 * will result in errors. A software reset leaves the timing
708 * registers intact, but resets the drives.
709 */
710
711 OUT_BYTE(udma_speed_flag | 0x10, high_16 + 0x001f);
712 ide_delay_50ms();
713 ide_delay_50ms();
714 OUT_BYTE(udma_speed_flag & ~0x10, high_16 + 0x001f);
715 for (i=0; i<40; i++)
716 ide_delay_50ms();
717 }
718
719 if (dev->resource[PCI_ROM_RESOURCE].start) {
720 pci_write_config_dword(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
721 printk("%s: ROM enabled at 0x%08lx\n", name, dev->resource[PCI_ROM_RESOURCE].start);
722 }
723
724 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
725 byte irq = 0, irq2 = 0;
726 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
727 pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2); /* 0xbc */
728 if ((irq != irq2) && (dev->device != PCI_DEVICE_ID_PROMISE_20267)) {
729 pci_write_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, irq); /* 0xbc */
730 printk("%s: pci-config space interrupt mirror fixed.\n", name);
731 }
732 }
733
734 printk("%s: (U)DMA Burst Bit %sABLED " \
735 "Primary %s Mode " \
736 "Secondary %s Mode.\n",
737 name,
738 (udma_speed_flag & 1) ? "EN" : "DIS",
739 (primary_mode & 1) ? "MASTER" : "PCI",
740 (secondary_mode & 1) ? "MASTER" : "PCI" );
741
742 #ifdef CONFIG_PDC202XX_BURST
743 if (!(udma_speed_flag & 1)) {
744 printk("%s: FORCING BURST BIT 0x%02x -> 0x%02x ", name, udma_speed_flag, (udma_speed_flag|1));
745 outb(udma_speed_flag|1, high_16 + 0x001f);
746 printk("%sCTIVE\n", (inb(high_16 + 0x001f) & 1) ? "A" : "INA");
747 }
748 #endif /* CONFIG_PDC202XX_BURST */
749
750 #ifdef CONFIG_PDC202XX_MASTER
751 if (!(primary_mode & 1)) {
752 printk("%s: FORCING PRIMARY MODE BIT 0x%02x -> 0x%02x ",
753 name, primary_mode, (primary_mode|1));
754 outb(primary_mode|1, high_16 + 0x001a);
755 printk("%s\n", (inb(high_16 + 0x001a) & 1) ? "MASTER" : "PCI");
756 }
757
758 if (!(secondary_mode & 1)) {
759 printk("%s: FORCING SECONDARY MODE BIT 0x%02x -> 0x%02x ",
760 name, secondary_mode, (secondary_mode|1));
761 outb(secondary_mode|1, high_16 + 0x001b);
762 printk("%s\n", (inb(high_16 + 0x001b) & 1) ? "MASTER" : "PCI");
763 }
764 #endif /* CONFIG_PDC202XX_MASTER */
765
766 #if defined(DISPLAY_PDC202XX_TIMINGS) && defined(CONFIG_PROC_FS)
767 if (!pdc202xx_proc) {
768 pdc202xx_proc = 1;
769 bmide_dev = dev;
770 pdc202xx_display_info = &pdc202xx_get_info;
771 }
772 #endif /* DISPLAY_PDC202XX_TIMINGS && CONFIG_PROC_FS */
773 return dev->irq;
774 }
775
776 unsigned int __init ata66_pdc202xx (ide_hwif_t *hwif)
777 {
778 unsigned short mask = (hwif->channel) ? (1<<11) : (1<<10);
779 unsigned short CIS;
780
781 pci_read_config_word(hwif->pci_dev, 0x50, &CIS);
782 return ((CIS & mask) ? 0 : 1);
783 }
784
785 void __init ide_init_pdc202xx (ide_hwif_t *hwif)
786 {
787 hwif->tuneproc = &pdc202xx_tune_drive;
788 hwif->speedproc = &pdc202xx_tune_chipset;
789
790 if ((hwif->pci_dev->device == PCI_DEVICE_ID_PROMISE_20262) ||
791 (hwif->pci_dev->device == PCI_DEVICE_ID_PROMISE_20267))
792 hwif->resetproc = &pdc202xx_reset;
793
794 #ifdef CONFIG_BLK_DEV_IDEDMA
795 if (hwif->dma_base) {
796 hwif->dmaproc = &pdc202xx_dmaproc;
797 hwif->autodma = 1;
798 } else {
799 hwif->drives[0].autotune = 1;
800 hwif->drives[1].autotune = 1;
801 hwif->autodma = 0;
802 }
803 #else /* !CONFIG_BLK_DEV_IDEDMA */
804 hwif->drives[0].autotune = 1;
805 hwif->drives[1].autotune = 1;
806 hwif->autodma = 0;
807 #endif /* CONFIG_BLK_DEV_IDEDMA */
808 }
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