Fix PCI config space access for MIPS boards.
[linux-2.6/linux-mips.git] / include / asm-ppc / hardirq.h
blob81b9bbf98622c1ceec5087a698160dbb2e43336c
1 #ifdef __KERNEL__
2 #ifndef __ASM_HARDIRQ_H
3 #define __ASM_HARDIRQ_H
5 #include <linux/config.h>
6 #include <linux/cache.h>
7 #include <linux/smp_lock.h>
8 #include <asm/irq.h>
10 /* The __last_jiffy_stamp field is needed to ensure that no decrementer
11 * interrupt is lost on SMP machines. Since on most CPUs it is in the same
12 * cache line as local_irq_count, it is cheap to access and is also used on UP
13 * for uniformity.
15 typedef struct {
16 unsigned long __softirq_pending; /* set_bit is used on this */
17 unsigned int __syscall_count;
18 struct task_struct * __ksoftirqd_task;
19 unsigned int __last_jiffy_stamp;
20 } ____cacheline_aligned irq_cpustat_t;
22 #include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */
24 #define last_jiffy_stamp(cpu) __IRQ_STAT((cpu), __last_jiffy_stamp)
27 * We put the hardirq and softirq counter into the preemption
28 * counter. The bitmask has the following meaning:
30 * - bits 0-7 are the preemption count (max preemption depth: 256)
31 * - bits 8-15 are the softirq count (max # of softirqs: 256)
32 * - bits 16-23 are the hardirq count (max # of hardirqs: 256)
34 * - ( bit 26 is the PREEMPT_ACTIVE flag. )
36 * PREEMPT_MASK: 0x000000ff
37 * SOFTIRQ_MASK: 0x0000ff00
38 * HARDIRQ_MASK: 0x00ff0000
41 #define PREEMPT_BITS 8
42 #define SOFTIRQ_BITS 8
43 #define HARDIRQ_BITS 8
45 #define PREEMPT_SHIFT 0
46 #define SOFTIRQ_SHIFT (PREEMPT_SHIFT + PREEMPT_BITS)
47 #define HARDIRQ_SHIFT (SOFTIRQ_SHIFT + SOFTIRQ_BITS)
49 #define __MASK(x) ((1UL << (x))-1)
51 #define PREEMPT_MASK (__MASK(PREEMPT_BITS) << PREEMPT_SHIFT)
52 #define HARDIRQ_MASK (__MASK(HARDIRQ_BITS) << HARDIRQ_SHIFT)
53 #define SOFTIRQ_MASK (__MASK(SOFTIRQ_BITS) << SOFTIRQ_SHIFT)
55 #define hardirq_count() (preempt_count() & HARDIRQ_MASK)
56 #define softirq_count() (preempt_count() & SOFTIRQ_MASK)
57 #define irq_count() (preempt_count() & (HARDIRQ_MASK | SOFTIRQ_MASK))
59 #define PREEMPT_OFFSET (1UL << PREEMPT_SHIFT)
60 #define SOFTIRQ_OFFSET (1UL << SOFTIRQ_SHIFT)
61 #define HARDIRQ_OFFSET (1UL << HARDIRQ_SHIFT)
64 * The hardirq mask has to be large enough to have
65 * space for potentially all IRQ sources in the system
66 * nesting on a single CPU:
68 #if (1 << HARDIRQ_BITS) < NR_IRQS
69 # error HARDIRQ_BITS is too low!
70 #endif
73 * Are we doing bottom half or hardware interrupt processing?
74 * Are we in a softirq context? Interrupt context?
76 #define in_irq() (hardirq_count())
77 #define in_softirq() (softirq_count())
78 #define in_interrupt() (irq_count())
81 #define hardirq_trylock() (!in_interrupt())
82 #define hardirq_endlock() do { } while (0)
84 #define irq_enter() (preempt_count() += HARDIRQ_OFFSET)
86 #ifdef CONFIG_PREEMPT
87 # define in_atomic() ((preempt_count() & ~PREEMPT_ACTIVE) != kernel_locked())
88 # define IRQ_EXIT_OFFSET (HARDIRQ_OFFSET-1)
89 #else
90 # define in_atomic() (preempt_count() != 0)
91 # define IRQ_EXIT_OFFSET HARDIRQ_OFFSET
92 #endif
93 #define irq_exit() \
94 do { \
95 preempt_count() -= IRQ_EXIT_OFFSET; \
96 if (!in_interrupt() && softirq_pending(smp_processor_id())) \
97 do_softirq(); \
98 preempt_enable_no_resched(); \
99 } while (0)
101 #ifndef CONFIG_SMP
102 # define synchronize_irq(irq) barrier()
103 #else
104 extern void synchronize_irq(unsigned int irq);
105 #endif /* CONFIG_SMP */
107 extern void show_stack(unsigned long *sp);
109 #endif /* __ASM_HARDIRQ_H */
110 #endif /* __KERNEL__ */