include/asm-ppc/processor.h

   1 #ifdef __KERNEL__
   2 #ifndef __ASM_PPC_PROCESSOR_H
   3 #define __ASM_PPC_PROCESSOR_H
   4
   5 /*
   6  * Default implementation of macro that returns current
   7  * instruction pointer ("program counter").
   8  */
   9 #define current_text_addr() ({ __label__ _l; _l: &&_l;})
  10
  11 #include <linux/config.h>
  12 #include <linux/stringify.h>
  13
  14 #include <asm/ptrace.h>
  15 #include <asm/types.h>
  16 #include <asm/mpc8xx.h>
  17
  18 /* Machine State Register (MSR) Fields */
  19
  20 #ifdef CONFIG_PPC64BRIDGE
  21 #define MSR_SF          (1<<63)
  22 #define MSR_ISF         (1<<61)
  23 #endif /* CONFIG_PPC64BRIDGE */
  24 #define MSR_VEC         (1<<25)         /* Enable AltiVec */
  25 #define MSR_POW         (1<<18)         /* Enable Power Management */
  26 #define MSR_WE          (1<<18)         /* Wait State Enable */
  27 #define MSR_TGPR        (1<<17)         /* TLB Update registers in use */
  28 #define MSR_CE          (1<<17)         /* Critical Interrupt Enable */
  29 #define MSR_ILE         (1<<16)         /* Interrupt Little Endian */
  30 #define MSR_EE          (1<<15)         /* External Interrupt Enable */
  31 #define MSR_PR          (1<<14)         /* Problem State / Privilege Level */
  32 #define MSR_FP          (1<<13)         /* Floating Point enable */
  33 #define MSR_ME          (1<<12)         /* Machine Check Enable */
  34 #define MSR_FE0         (1<<11)         /* Floating Exception mode 0 */
  35 #define MSR_SE          (1<<10)         /* Single Step */
  36 #define MSR_DWE         (1<<10)         /* Debug Wait Enable (4xx) */
  37 #define MSR_BE          (1<<9)          /* Branch Trace */
  38 #define MSR_DE          (1<<9)          /* Debug Exception Enable */
  39 #define MSR_FE1         (1<<8)          /* Floating Exception mode 1 */
  40 #define MSR_IP          (1<<6)          /* Exception prefix 0x000/0xFFF */
  41 #define MSR_IR          (1<<5)          /* Instruction Relocate */
  42 #define MSR_DR          (1<<4)          /* Data Relocate */
  43 #define MSR_PE          (1<<3)          /* Protection Enable */
  44 #define MSR_PX          (1<<2)          /* Protection Exclusive Mode */
  45 #define MSR_RI          (1<<1)          /* Recoverable Exception */
  46 #define MSR_LE          (1<<0)          /* Little Endian */
  47
  48 #ifdef CONFIG_APUS_FAST_EXCEPT
  49 #define MSR_            (MSR_ME|MSR_IP|MSR_RI)
  50 #else
  51 #define MSR_            (MSR_ME|MSR_RI)
  52 #endif
  53 #ifdef CONFIG_4xx
  54 #define MSR_KERNEL      (MSR_|MSR_IR|MSR_DR|MSR_CE|MSR_DE)
  55 #else
  56 #define MSR_KERNEL      (MSR_|MSR_IR|MSR_DR)
  57 #endif
  58 #define MSR_USER        (MSR_KERNEL|MSR_PR|MSR_EE)
  59
  60 /* Floating Point Status and Control Register (FPSCR) Fields */
  61
  62 #define FPSCR_FX        0x80000000      /* FPU exception summary */
  63 #define FPSCR_FEX       0x40000000      /* FPU enabled exception summary */
  64 #define FPSCR_VX        0x20000000      /* Invalid operation summary */
  65 #define FPSCR_OX        0x10000000      /* Overflow exception summary */
  66 #define FPSCR_UX        0x08000000      /* Underflow exception summary */
  67 #define FPSCR_ZX        0x04000000      /* Zero-devide exception summary */
  68 #define FPSCR_XX        0x02000000      /* Inexact exception summary */
  69 #define FPSCR_VXSNAN    0x01000000      /* Invalid op for SNaN */
  70 #define FPSCR_VXISI     0x00800000      /* Invalid op for Inv - Inv */
  71 #define FPSCR_VXIDI     0x00400000      /* Invalid op for Inv / Inv */
  72 #define FPSCR_VXZDZ     0x00200000      /* Invalid op for Zero / Zero */
  73 #define FPSCR_VXIMZ     0x00100000      /* Invalid op for Inv * Zero */
  74 #define FPSCR_VXVC      0x00080000      /* Invalid op for Compare */
  75 #define FPSCR_FR        0x00040000      /* Fraction rounded */
  76 #define FPSCR_FI        0x00020000      /* Fraction inexact */
  77 #define FPSCR_FPRF      0x0001f000      /* FPU Result Flags */
  78 #define FPSCR_FPCC      0x0000f000      /* FPU Condition Codes */
  79 #define FPSCR_VXSOFT    0x00000400      /* Invalid op for software request */
  80 #define FPSCR_VXSQRT    0x00000200      /* Invalid op for square root */
  81 #define FPSCR_VXCVI     0x00000100      /* Invalid op for integer convert */
  82 #define FPSCR_VE        0x00000080      /* Invalid op exception enable */
  83 #define FPSCR_OE        0x00000040      /* IEEE overflow exception enable */
  84 #define FPSCR_UE        0x00000020      /* IEEE underflow exception enable */
  85 #define FPSCR_ZE        0x00000010      /* IEEE zero divide exception enable */
  86 #define FPSCR_XE        0x00000008      /* FP inexact exception enable */
  87 #define FPSCR_NI        0x00000004      /* FPU non IEEE-Mode */
  88 #define FPSCR_RN        0x00000003      /* FPU rounding control */
  89
  90 /* Special Purpose Registers (SPRNs)*/
  91
  92 #define SPRN_CCR0       0x3B3   /* Core Configuration Register (4xx) */
  93 #define SPRN_CDBCR      0x3D7   /* Cache Debug Control Register */
  94 #define SPRN_CTR        0x009   /* Count Register */
  95 #define SPRN_DABR       0x3F5   /* Data Address Breakpoint Register */
  96 #define SPRN_DAC1       0x3F6   /* Data Address Compare 1 */
  97 #define SPRN_DAC2       0x3F7   /* Data Address Compare 2 */
  98 #define SPRN_DAR        0x013   /* Data Address Register */
  99 #define SPRN_DBAT0L     0x219   /* Data BAT 0 Lower Register */
 100 #define SPRN_DBAT0U     0x218   /* Data BAT 0 Upper Register */
 101 #define SPRN_DBAT1L     0x21B   /* Data BAT 1 Lower Register */
 102 #define SPRN_DBAT1U     0x21A   /* Data BAT 1 Upper Register */
 103 #define SPRN_DBAT2L     0x21D   /* Data BAT 2 Lower Register */
 104 #define SPRN_DBAT2U     0x21C   /* Data BAT 2 Upper Register */
 105 #define SPRN_DBAT3L     0x21F   /* Data BAT 3 Lower Register */
 106 #define SPRN_DBAT3U     0x21E   /* Data BAT 3 Upper Register */
 107 #define SPRN_DBCR       0x3F2   /* Debug Control Regsiter */
 108 #define   DBCR_EDM      0x80000000
 109 #define   DBCR_IDM      0x40000000
 110 #define   DBCR_RST(x)   (((x) & 0x3) << 28)
 111 #define     DBCR_RST_NONE               0
 112 #define     DBCR_RST_CORE               1
 113 #define     DBCR_RST_CHIP               2
 114 #define     DBCR_RST_SYSTEM             3
 115 #define   DBCR_IC       0x08000000      /* Instruction Completion Debug Evnt */
 116 #define   DBCR_BT       0x04000000      /* Branch Taken Debug Event */
 117 #define   DBCR_EDE      0x02000000      /* Exception Debug Event */
 118 #define   DBCR_TDE      0x01000000      /* TRAP Debug Event */
 119 #define   DBCR_FER      0x00F80000      /* First Events Remaining Mask */
 120 #define   DBCR_FT       0x00040000      /* Freeze Timers on Debug Event */
 121 #define   DBCR_IA1      0x00020000      /* Instr. Addr. Compare 1 Enable */
 122 #define   DBCR_IA2      0x00010000      /* Instr. Addr. Compare 2 Enable */
 123 #define   DBCR_D1R      0x00008000      /* Data Addr. Compare 1 Read Enable */
 124 #define   DBCR_D1W      0x00004000      /* Data Addr. Compare 1 Write Enable */
 125 #define   DBCR_D1S(x)   (((x) & 0x3) << 12)     /* Data Adrr. Compare 1 Size */
 126 #define     DAC_BYTE    0
 127 #define     DAC_HALF    1
 128 #define     DAC_WORD    2
 129 #define     DAC_QUAD    3
 130 #define   DBCR_D2R      0x00000800      /* Data Addr. Compare 2 Read Enable */
 131 #define   DBCR_D2W      0x00000400      /* Data Addr. Compare 2 Write Enable */
 132 #define   DBCR_D2S(x)   (((x) & 0x3) << 8)      /* Data Addr. Compare 2 Size */
 133 #define   DBCR_SBT      0x00000040      /* Second Branch Taken Debug Event */
 134 #define   DBCR_SED      0x00000020      /* Second Exception Debug Event */
 135 #define   DBCR_STD      0x00000010      /* Second Trap Debug Event */
 136 #define   DBCR_SIA      0x00000008      /* Second IAC Enable */
 137 #define   DBCR_SDA      0x00000004      /* Second DAC Enable */
 138 #define   DBCR_JOI      0x00000002      /* JTAG Serial Outbound Int. Enable */
 139 #define   DBCR_JII      0x00000001      /* JTAG Serial Inbound Int. Enable */
 140 #define SPRN_DBCR0      0x3F2   /* Debug Control Register 0 */
 141 #define   DBCR0_EDM         0x80000000  /* External Debug Mode             */
 142 #define   DBCR0_IDM         0x40000000  /* Internal Debug Mode             */
 143 #define   DBCR0_RST         0x30000000  /* all the bits in the RST field   */
 144 #define   DBCR0_RST_SYSTEM  0x30000000  /* System Reset                    */
 145 #define   DBCR0_RST_CHIP    0x20000000  /* Chip   Reset                    */
 146 #define   DBCR0_RST_CORE    0x10000000  /* Core   Reset                    */
 147 #define   DBCR0_RST_NONE    0x00000000  /* No     Reset                    */
 148 #define   DBCR0_IC          0x08000000  /* Instruction Completion          */
 149 #define   DBCR0_BT          0x04000000  /* Branch Taken                    */
 150 #define   DBCR0_EDE         0x02000000  /* Exception Debug Event           */
 151 #define   DBCR0_TDE         0x01000000  /* TRAP Debug Event                */
 152 #define   DBCR0_IA1         0x00800000  /* Instr Addr compare 1 enable     */
 153 #define   DBCR0_IA2         0x00400000  /* Instr Addr compare 2 enable     */
 154 #define   DBCR0_IA12        0x00200000  /* Instr Addr 1-2 range enable     */
 155 #define   DBCR0_IA12X       0x00100000  /* Instr Addr 1-2 range eXclusive  */
 156 #define   DBCR0_IA3         0x00080000  /* Instr Addr compare 3 enable     */
 157 #define   DBCR0_IA4         0x00040000  /* Instr Addr compare 4 enable     */
 158 #define   DBCR0_IA34        0x00020000  /* Instr Addr 3-4 range Enable     */
 159 #define   DBCR0_IA34X       0x00010000  /* Instr Addr 3-4 range eXclusive  */
 160 #define   DBCR0_IA12T       0x00008000  /* Instr Addr 1-2 range Toggle     */
 161 #define   DBCR0_IA34T       0x00004000  /* Instr Addr 3-4 range Toggle     */
 162 #define   DBCR0_FT          0x00000001  /* Freeze Timers on debug event    */
 163 #define SPRN_DBCR1      0x3BD   /* Debug Control Register 1 */
 164 #define SPRN_DBSR       0x3F0   /* Debug Status Register */
 165 #define   DBSR_IC           0x80000000  /* Instruction Completion          */
 166 #define   DBSR_BT           0x40000000  /* Branch taken */
 167 #define   DBSR_TIE          0x10000000  /* Trap Instruction debug Event    */
 168 #define SPRN_DCCR       0x3FA   /* Data Cache Cacheability Register */
 169 #define   DCCR_NOCACHE          0       /* Noncacheable */
 170 #define   DCCR_CACHE            1       /* Cacheable */
 171 #define SPRN_DCMP       0x3D1   /* Data TLB Compare Register */
 172 #define SPRN_DCWR       0x3BA   /* Data Cache Write-thru Register */
 173 #define   DCWR_COPY             0       /* Copy-back */
 174 #define   DCWR_WRITE            1       /* Write-through */
 175 #define SPRN_DEAR       0x3D5   /* Data Error Address Register */
 176 #define SPRN_DEC        0x016   /* Decrement Register */
 177 #define SPRN_DER        0x095   /* Debug Enable Regsiter */
 178 #define   DER_RSTE      0x40000000      /* Reset Interrupt */
 179 #define   DER_CHSTPE    0x20000000      /* Check Stop */
 180 #define   DER_MCIE      0x10000000      /* Machine Check Interrupt */
 181 #define   DER_EXTIE     0x02000000      /* External Interrupt */
 182 #define   DER_ALIE      0x01000000      /* Alignment Interrupt */
 183 #define   DER_PRIE      0x00800000      /* Program Interrupt */
 184 #define   DER_FPUVIE    0x00400000      /* FP Unavailable Interrupt */
 185 #define   DER_DECIE     0x00200000      /* Decrementer Interrupt */
 186 #define   DER_SYSIE     0x00040000      /* System Call Interrupt */
 187 #define   DER_TRE       0x00020000      /* Trace Interrupt */
 188 #define   DER_SEIE      0x00004000      /* FP SW Emulation Interrupt */
 189 #define   DER_ITLBMSE   0x00002000      /* Imp. Spec. Instruction TLB Miss */
 190 #define   DER_ITLBERE   0x00001000      /* Imp. Spec. Instruction TLB Error */
 191 #define   DER_DTLBMSE   0x00000800      /* Imp. Spec. Data TLB Miss */
 192 #define   DER_DTLBERE   0x00000400      /* Imp. Spec. Data TLB Error */
 193 #define   DER_LBRKE     0x00000008      /* Load/Store Breakpoint Interrupt */
 194 #define   DER_IBRKE     0x00000004      /* Instruction Breakpoint Interrupt */
 195 #define   DER_EBRKE     0x00000002      /* External Breakpoint Interrupt */
 196 #define   DER_DPIE      0x00000001      /* Dev. Port Nonmaskable Request */
 197 #define SPRN_DMISS      0x3D0   /* Data TLB Miss Register */
 198 #define SPRN_DSISR      0x012   /* Data Storage Interrupt Status Register */
 199 #define SPRN_EAR        0x11A   /* External Address Register */
 200 #define SPRN_ESR        0x3D4   /* Exception Syndrome Register */
 201 #define   ESR_MCI       0x80000000      /* 405 Machine Check - Instruction */
 202 #define   ESR_IMCP      0x80000000      /* 403 Inst. Mach. Check - Protection */
 203 #define   ESR_IMCN      0x40000000      /* 403 Inst. Mach. Check - Non-config */
 204 #define   ESR_IMCB      0x20000000      /* 403 Inst. Mach. Check - Bus error */
 205 #define   ESR_IMCT      0x10000000      /* 403 Inst. Mach. Check - Timeout */
 206 #define   ESR_PIL       0x08000000      /* Program Exception - Illegal */
 207 #define   ESR_PPR       0x04000000      /* Program Exception - Priveleged */
 208 #define   ESR_PTR       0x02000000      /* Program Exception - Trap */
 209 #define   ESR_DST       0x00800000      /* Storage Exception - Data miss */
 210 #define   ESR_DIZ       0x00400000      /* Storage Exception - Zone fault */
 211 #define SPRN_EVPR       0x3D6   /* Exception Vector Prefix Register */
 212 #define SPRN_HASH1      0x3D2   /* Primary Hash Address Register */
 213 #define SPRN_HASH2      0x3D3   /* Secondary Hash Address Resgister */
 214 #define SPRN_HID0       0x3F0   /* Hardware Implementation Register 0 */
 215 #define   HID0_EMCP     (1<<31)         /* Enable Machine Check pin */
 216 #define   HID0_EBA      (1<<29)         /* Enable Bus Address Parity */
 217 #define   HID0_EBD      (1<<28)         /* Enable Bus Data Parity */
 218 #define   HID0_SBCLK    (1<<27)
 219 #define   HID0_EICE     (1<<26)
 220 #define   HID0_TBEN     (1<<26)         /* Timebase enable - 745x */
 221 #define   HID0_ECLK     (1<<25)
 222 #define   HID0_PAR      (1<<24)
 223 #define   HID0_STEN     (1<<24)         /* Software table search enable - 745x */
 224 #define   HID0_HIGH_BAT (1<<23)         /* Enable high BATs - 7455 */
 225 #define   HID0_DOZE     (1<<23)
 226 #define   HID0_NAP      (1<<22)
 227 #define   HID0_SLEEP    (1<<21)
 228 #define   HID0_DPM      (1<<20)
 229 #define   HID0_BHTCLR   (1<<18)         /* Clear branch history table - 7450 */
 230 #define   HID0_XAEN     (1<<17)         /* Extended addressing enable - 7450 */
 231 #define   HID0_NHR      (1<<16)         /* Not hard reset (software bit-7450)*/
 232 #define   HID0_ICE      (1<<15)         /* Instruction Cache Enable */
 233 #define   HID0_DCE      (1<<14)         /* Data Cache Enable */
 234 #define   HID0_ILOCK    (1<<13)         /* Instruction Cache Lock */
 235 #define   HID0_DLOCK    (1<<12)         /* Data Cache Lock */
 236 #define   HID0_ICFI     (1<<11)         /* Instr. Cache Flash Invalidate */
 237 #define   HID0_DCI      (1<<10)         /* Data Cache Invalidate */
 238 #define   HID0_SPD      (1<<9)          /* Speculative disable */
 239 #define   HID0_SGE      (1<<7)          /* Store Gathering Enable */
 240 #define   HID0_SIED     (1<<7)          /* Serial Instr. Execution [Disable] */
 241 #define   HID0_DFCA     (1<<6)          /* Data Cache Flush Assist */
 242 #define   HID0_LRSTK    (1<<4)          /* Link register stack - 745x */
 243 #define   HID0_BTIC     (1<<5)          /* Branch Target Instr Cache Enable */
 244 #define   HID0_ABE      (1<<3)          /* Address Broadcast Enable */
 245 #define   HID0_FOLD     (1<<3)          /* Branch Folding enable - 745x */
 246 #define   HID0_BHTE     (1<<2)          /* Branch History Table Enable */
 247 #define   HID0_BTCD     (1<<1)          /* Branch target cache disable */
 248 #define   HID0_NOPDST   (1<<1)          /* No-op dst, dstt, etc. instr. */
 249 #define   HID0_NOPTI    (1<<0)          /* No-op dcbt and dcbst instr. */
 250
 251 #define SPRN_HID1       0x3F1   /* Hardware Implementation Register 1 */
 252 #define   HID1_EMCP     (1<<31)         /* 7450 Machine Check Pin Enable */
 253 #define   HID1_PC0      (1<<16)         /* 7450 PLL_CFG[0] */
 254 #define   HID1_PC1      (1<<15)         /* 7450 PLL_CFG[1] */
 255 #define   HID1_PC2      (1<<14)         /* 7450 PLL_CFG[2] */
 256 #define   HID1_PC3      (1<<13)         /* 7450 PLL_CFG[3] */
 257 #define   HID1_SYNCBE   (1<<11)         /* 7450 ABE for sync, eieio */
 258 #define   HID1_ABE      (1<<10)         /* 7450 Address Broadcast Enable */
 259 #define SPRN_IABR       0x3F2   /* Instruction Address Breakpoint Register */
 260 #define SPRN_IAC1       0x3F4   /* Instruction Address Compare 1 */
 261 #define SPRN_IAC2       0x3F5   /* Instruction Address Compare 2 */
 262 #define SPRN_IBAT0L     0x211   /* Instruction BAT 0 Lower Register */
 263 #define SPRN_IBAT0U     0x210   /* Instruction BAT 0 Upper Register */
 264 #define SPRN_IBAT1L     0x213   /* Instruction BAT 1 Lower Register */
 265 #define SPRN_IBAT1U     0x212   /* Instruction BAT 1 Upper Register */
 266 #define SPRN_IBAT2L     0x215   /* Instruction BAT 2 Lower Register */
 267 #define SPRN_IBAT2U     0x214   /* Instruction BAT 2 Upper Register */
 268 #define SPRN_IBAT3L     0x217   /* Instruction BAT 3 Lower Register */
 269 #define SPRN_IBAT3U     0x216   /* Instruction BAT 3 Upper Register */
 270 #define SPRN_ICCR       0x3FB   /* Instruction Cache Cacheability Register */
 271 #define   ICCR_NOCACHE          0       /* Noncacheable */
 272 #define   ICCR_CACHE            1       /* Cacheable */
 273 #define SPRN_ICDBDR     0x3D3   /* Instruction Cache Debug Data Register */
 274 #define SPRN_ICMP       0x3D5   /* Instruction TLB Compare Register */
 275 #define SPRN_ICTC       0x3FB   /* Instruction Cache Throttling Control Reg */
 276 #define SPRN_ICTRL      0x3F3   /* 1011 7450 icache and interrupt ctrl */
 277 #define   ICTRL_EICE            0x08000000      /* enable icache parity errs */
 278 #define   ICTRL_EDCE            0x04000000      /* enable dcache parity errs */
 279 #define   ICTRL_EICP            0x00000100      /* enable icache par. check */
 280 #define SPRN_IMISS      0x3D4   /* Instruction TLB Miss Register */
 281 #define SPRN_IMMR       0x27E   /* Internal Memory Map Register */
 282 #define SPRN_L2CR       0x3F9   /* Level 2 Cache Control Regsiter */
 283 #define L2CR_L2E                0x80000000      /* L2 enable */
 284 #define L2CR_L2PE               0x40000000      /* L2 parity enable */
 285 #define L2CR_L2SIZ_MASK         0x30000000      /* L2 size mask */
 286 #define L2CR_L2SIZ_256KB        0x10000000      /* L2 size 256KB */
 287 #define L2CR_L2SIZ_512KB        0x20000000      /* L2 size 512KB */
 288 #define L2CR_L2SIZ_1MB          0x30000000      /* L2 size 1MB */
 289 #define L2CR_L2CLK_MASK         0x0e000000      /* L2 clock mask */
 290 #define L2CR_L2CLK_DISABLED     0x00000000      /* L2 clock disabled */
 291 #define L2CR_L2CLK_DIV1         0x02000000      /* L2 clock / 1 */
 292 #define L2CR_L2CLK_DIV1_5       0x04000000      /* L2 clock / 1.5 */
 293 #define L2CR_L2CLK_DIV2         0x08000000      /* L2 clock / 2 */
 294 #define L2CR_L2CLK_DIV2_5       0x0a000000      /* L2 clock / 2.5 */
 295 #define L2CR_L2CLK_DIV3         0x0c000000      /* L2 clock / 3 */
 296 #define L2CR_L2RAM_MASK         0x01800000      /* L2 RAM type mask */
 297 #define L2CR_L2RAM_FLOW         0x00000000      /* L2 RAM flow through */
 298 #define L2CR_L2RAM_PIPE         0x01000000      /* L2 RAM pipelined */
 299 #define L2CR_L2RAM_PIPE_LW      0x01800000      /* L2 RAM pipelined latewr */
 300 #define L2CR_L2DO               0x00400000      /* L2 data only */
 301 #define L2CR_L2I                0x00200000      /* L2 global invalidate */
 302 #define L2CR_L2CTL              0x00100000      /* L2 RAM control */
 303 #define L2CR_L2WT               0x00080000      /* L2 write-through */
 304 #define L2CR_L2TS               0x00040000      /* L2 test support */
 305 #define L2CR_L2OH_MASK          0x00030000      /* L2 output hold mask */
 306 #define L2CR_L2OH_0_5           0x00000000      /* L2 output hold 0.5 ns */
 307 #define L2CR_L2OH_1_0           0x00010000      /* L2 output hold 1.0 ns */
 308 #define L2CR_L2SL               0x00008000      /* L2 DLL slow */
 309 #define L2CR_L2DF               0x00004000      /* L2 differential clock */
 310 #define L2CR_L2BYP              0x00002000      /* L2 DLL bypass */
 311 #define L2CR_L2IP               0x00000001      /* L2 GI in progress */
 312 #define SPRN_L2CR2      0x3f8
 313 #define SPRN_L3CR       0x3FA   /* Level 3 Cache Control Regsiter (7450) */
 314 #define L3CR_L3E                0x80000000      /* L3 enable */
 315 #define L3CR_L3PE               0x40000000      /* L3 data parity enable */
 316 #define L3CR_L3APE              0x20000000      /* L3 addr parity enable */
 317 #define L3CR_L3SIZ              0x10000000      /* L3 size */
 318 #define L3CR_L3CLKEN            0x08000000      /* L3 clock enable */
 319 #define L3CR_L3RES              0x04000000      /* L3 special reserved bit */
 320 #define L3CR_L3CLKDIV           0x03800000      /* L3 clock divisor */
 321 #define L3CR_L3IO               0x00400000      /* L3 instruction only */
 322 #define L3CR_L3SPO              0x00040000      /* L3 sample point override */
 323 #define L3CR_L3CKSP             0x00030000      /* L3 clock sample point */
 324 #define L3CR_L3PSP              0x0000e000      /* L3 P-clock sample point */
 325 #define L3CR_L3REP              0x00001000      /* L3 replacement algorithm */
 326 #define L3CR_L3HWF              0x00000800      /* L3 hardware flush */
 327 #define L3CR_L3I                0x00000400      /* L3 global invalidate */
 328 #define L3CR_L3RT               0x00000300      /* L3 SRAM type */
 329 #define L3CR_L3NIRCA            0x00000080      /* L3 non-integer ratio clock adj. */
 330 #define L3CR_L3DO               0x00000040      /* L3 data only mode */
 331 #define L3CR_PMEN               0x00000004      /* L3 private memory enable */
 332 #define L3CR_PMSIZ              0x00000001      /* L3 private memory size */
 333 #define SPRN_MSSCR0     0x3f6   /* Memory Subsystem Control Register 0 */
 334 #define SPRN_MSSSR0     0x3f7   /* Memory Subsystem Status Register 1 */
 335 #define SPRN_LDSTCR     0x3f8   /* Load/Store control register */
 336 #define SPRN_LDSTDB     0x3f4   /* */
 337 #define SPRN_LR         0x008   /* Link Register */
 338 #define SPRN_MMCR0      0x3B8   /* Monitor Mode Control Register 0 */
 339 #define SPRN_MMCR1      0x3BC   /* Monitor Mode Control Register 1 */
 340 #define SPRN_PBL1       0x3FC   /* Protection Bound Lower 1 */
 341 #define SPRN_PBL2       0x3FE   /* Protection Bound Lower 2 */
 342 #define SPRN_PBU1       0x3FD   /* Protection Bound Upper 1 */
 343 #define SPRN_PBU2       0x3FF   /* Protection Bound Upper 2 */
 344 #define SPRN_PID        0x3B1   /* Process ID */
 345 #define SPRN_PIR        0x3FF   /* Processor Identification Register */
 346 #define SPRN_PIT        0x3DB   /* Programmable Interval Timer */
 347 #define SPRN_PMC1       0x3B9   /* Performance Counter Register 1 */
 348 #define SPRN_PMC2       0x3BA   /* Performance Counter Register 2 */
 349 #define SPRN_PMC3       0x3BD   /* Performance Counter Register 3 */
 350 #define SPRN_PMC4       0x3BE   /* Performance Counter Register 4 */
 351 #define SPRN_PTEHI      0x3D5   /* 981 7450 PTE HI word (S/W TLB load) */
 352 #define SPRN_PTELO      0x3D6   /* 982 7450 PTE LO word (S/W TLB load)  */
 353 #define SPRN_PVR        0x11F   /* Processor Version Register */
 354 #define SPRN_RPA        0x3D6   /* Required Physical Address Register */
 355 #define SPRN_SDA        0x3BF   /* Sampled Data Address Register */
 356 #define SPRN_SDR1       0x019   /* MMU Hash Base Register */
 357 #define SPRN_SGR        0x3B9   /* Storage Guarded Register */
 358 #define   SGR_NORMAL            0
 359 #define   SGR_GUARDED           1
 360 #define SPRN_SIA        0x3BB   /* Sampled Instruction Address Register */
 361 #define SPRN_SPRG0      0x110   /* Special Purpose Register General 0 */
 362 #define SPRN_SPRG1      0x111   /* Special Purpose Register General 1 */
 363 #define SPRN_SPRG2      0x112   /* Special Purpose Register General 2 */
 364 #define SPRN_SPRG3      0x113   /* Special Purpose Register General 3 */
 365 #define SPRN_SPRG4      0x114   /* Special Purpose Register General 4 (4xx) */
 366 #define SPRN_SPRG5      0x115   /* Special Purpose Register General 5 (4xx) */
 367 #define SPRN_SPRG6      0x116   /* Special Purpose Register General 6 (4xx) */
 368 #define SPRN_SPRG7      0x117   /* Special Purpose Register General 7 (4xx) */
 369 #define SPRN_SRR0       0x01A   /* Save/Restore Register 0 */
 370 #define SPRN_SRR1       0x01B   /* Save/Restore Register 1 */
 371 #define SPRN_SRR2       0x3DE   /* Save/Restore Register 2 */
 372 #define SPRN_SRR3       0x3DF   /* Save/Restore Register 3 */
 373 #define SPRN_TBHI       0x3DC   /* Time Base High (4xx) */
 374 #define SPRN_TBHU       0x3CC   /* Time Base High User-mode (4xx) */
 375 #define SPRN_TBLO       0x3DD   /* Time Base Low (4xx) */
 376 #define SPRN_TBLU       0x3CD   /* Time Base Low User-mode (4xx) */
 377 #define SPRN_TBRL       0x10C   /* Time Base Read Lower Register (user, R/O) */
 378 #define SPRN_TBRU       0x10D   /* Time Base Read Upper Register (user, R/O) */
 379 #define SPRN_TBWL       0x11C   /* Time Base Lower Register (super, R/W) */
 380 #define SPRN_TBWU       0x11D   /* Time Base Upper Register (super, R/W) */
 381 #define SPRN_TCR        0x3DA   /* Timer Control Register */
 382 #define   TCR_WP(x)             (((x)&0x3)<<30) /* WDT Period */
 383 #define     TCR_WP_MASK         TCR_WP(3)
 384 #define     WP_2_17             0               /* 2^17 clocks */
 385 #define     WP_2_21             1               /* 2^21 clocks */
 386 #define     WP_2_25             2               /* 2^25 clocks */
 387 #define     WP_2_29             3               /* 2^29 clocks */
 388 #define   TCR_WRC(x)            (((x)&0x3)<<28) /* WDT Reset Control */
 389 #define     TCR_WRC_MASK        TCR_WRC(3)
 390 #define     WRC_NONE            0               /* No reset will occur */
 391 #define     WRC_CORE            1               /* Core reset will occur */
 392 #define     WRC_CHIP            2               /* Chip reset will occur */
 393 #define     WRC_SYSTEM          3               /* System reset will occur */
 394 #define   TCR_WIE               0x08000000      /* WDT Interrupt Enable */
 395 #define   TCR_PIE               0x04000000      /* PIT Interrupt Enable */
 396 #define   TCR_FP(x)             (((x)&0x3)<<24) /* FIT Period */
 397 #define     TCR_FP_MASK         TCR_FP(3)
 398 #define     FP_2_9              0               /* 2^9 clocks */
 399 #define     FP_2_13             1               /* 2^13 clocks */
 400 #define     FP_2_17             2               /* 2^17 clocks */
 401 #define     FP_2_21             3               /* 2^21 clocks */
 402 #define   TCR_FIE               0x00800000      /* FIT Interrupt Enable */
 403 #define   TCR_ARE               0x00400000      /* Auto Reload Enable */
 404 #define SPRN_THRM1      0x3FC   /* Thermal Management Register 1 */
 405 /* these bits were defined in inverted endian sense originally, ugh, confusing */
 406 #define   THRM1_TIN             (1 << 31)
 407 #define   THRM1_TIV             (1 << 30)
 408 #define   THRM1_THRES(x)        ((x&0x7f)<<23)
 409 #define   THRM3_SITV(x)         ((x&0x3fff)<<1)
 410 #define   THRM1_TID             (1<<2)
 411 #define   THRM1_TIE             (1<<1)
 412 #define   THRM1_V               (1<<0)
 413 #define SPRN_THRM2      0x3FD   /* Thermal Management Register 2 */
 414 #define SPRN_THRM3      0x3FE   /* Thermal Management Register 3 */
 415 #define   THRM3_E               (1<<0)
 416 #define SPRN_TLBMISS    0x3D4   /* 980 7450 TLB Miss Register */
 417 #define SPRN_TSR        0x3D8   /* Timer Status Register */
 418 #define   TSR_ENW               0x80000000      /* Enable Next Watchdog */
 419 #define   TSR_WIS               0x40000000      /* WDT Interrupt Status */
 420 #define   TSR_WRS(x)            (((x)&0x3)<<28) /* WDT Reset Status */
 421 #define     WRS_NONE            0               /* No WDT reset occurred */
 422 #define     WRS_CORE            1               /* WDT forced core reset */
 423 #define     WRS_CHIP            2               /* WDT forced chip reset */
 424 #define     WRS_SYSTEM          3               /* WDT forced system reset */
 425 #define   TSR_PIS               0x08000000      /* PIT Interrupt Status */
 426 #define   TSR_FIS               0x04000000      /* FIT Interrupt Status */
 427 #define SPRN_UMMCR0     0x3A8   /* User Monitor Mode Control Register 0 */
 428 #define SPRN_UMMCR1     0x3AC   /* User Monitor Mode Control Register 0 */
 429 #define SPRN_UPMC1      0x3A9   /* User Performance Counter Register 1 */
 430 #define SPRN_UPMC2      0x3AA   /* User Performance Counter Register 2 */
 431 #define SPRN_UPMC3      0x3AD   /* User Performance Counter Register 3 */
 432 #define SPRN_UPMC4      0x3AE   /* User Performance Counter Register 4 */
 433 #define SPRN_USIA       0x3AB   /* User Sampled Instruction Address Register */
 434 #define SPRN_VRSAVE     0x100   /* Vector Register Save Register */
 435 #define SPRN_XER        0x001   /* Fixed Point Exception Register */
 436 #define SPRN_ZPR        0x3B0   /* Zone Protection Register */
 437
 438 /* Short-hand versions for a number of the above SPRNs */
 439
 440 #define CTR     SPRN_CTR        /* Counter Register */
 441 #define DAR     SPRN_DAR        /* Data Address Register */
 442 #define DABR    SPRN_DABR       /* Data Address Breakpoint Register */
 443 #define DBAT0L  SPRN_DBAT0L     /* Data BAT 0 Lower Register */
 444 #define DBAT0U  SPRN_DBAT0U     /* Data BAT 0 Upper Register */
 445 #define DBAT1L  SPRN_DBAT1L     /* Data BAT 1 Lower Register */
 446 #define DBAT1U  SPRN_DBAT1U     /* Data BAT 1 Upper Register */
 447 #define DBAT2L  SPRN_DBAT2L     /* Data BAT 2 Lower Register */
 448 #define DBAT2U  SPRN_DBAT2U     /* Data BAT 2 Upper Register */
 449 #define DBAT3L  SPRN_DBAT3L     /* Data BAT 3 Lower Register */
 450 #define DBAT3U  SPRN_DBAT3U     /* Data BAT 3 Upper Register */
 451 #define DCMP    SPRN_DCMP       /* Data TLB Compare Register */
 452 #define DEC     SPRN_DEC        /* Decrement Register */
 453 #define DMISS   SPRN_DMISS      /* Data TLB Miss Register */
 454 #define DSISR   SPRN_DSISR      /* Data Storage Interrupt Status Register */
 455 #define EAR     SPRN_EAR        /* External Address Register */
 456 #define HASH1   SPRN_HASH1      /* Primary Hash Address Register */
 457 #define HASH2   SPRN_HASH2      /* Secondary Hash Address Register */
 458 #define HID0    SPRN_HID0       /* Hardware Implementation Register 0 */
 459 #define HID1    SPRN_HID1       /* Hardware Implementation Register 1 */
 460 #define IABR    SPRN_IABR       /* Instruction Address Breakpoint Register */
 461 #define IBAT0L  SPRN_IBAT0L     /* Instruction BAT 0 Lower Register */
 462 #define IBAT0U  SPRN_IBAT0U     /* Instruction BAT 0 Upper Register */
 463 #define IBAT1L  SPRN_IBAT1L     /* Instruction BAT 1 Lower Register */
 464 #define IBAT1U  SPRN_IBAT1U     /* Instruction BAT 1 Upper Register */
 465 #define IBAT2L  SPRN_IBAT2L     /* Instruction BAT 2 Lower Register */
 466 #define IBAT2U  SPRN_IBAT2U     /* Instruction BAT 2 Upper Register */
 467 #define IBAT3L  SPRN_IBAT3L     /* Instruction BAT 3 Lower Register */
 468 #define IBAT3U  SPRN_IBAT3U     /* Instruction BAT 3 Upper Register */
 469 #define ICMP    SPRN_ICMP       /* Instruction TLB Compare Register */
 470 #define IMISS   SPRN_IMISS      /* Instruction TLB Miss Register */
 471 #define IMMR    SPRN_IMMR       /* PPC 860/821 Internal Memory Map Register */
 472 #define L2CR    SPRN_L2CR       /* PPC 750 L2 control register */
 473 #define L3CR    SPRN_L3CR       /* PPC 7450 L3 Cache control register */
 474 #define LR      SPRN_LR
 475 #define PVR     SPRN_PVR        /* Processor Version */
 476 #define RPA     SPRN_RPA        /* Required Physical Address Register */
 477 #define SDR1    SPRN_SDR1       /* MMU hash base register */
 478 #define SPR0    SPRN_SPRG0      /* Supervisor Private Registers */
 479 #define SPR1    SPRN_SPRG1
 480 #define SPR2    SPRN_SPRG2
 481 #define SPR3    SPRN_SPRG3
 482 #define SPR4    SPRN_SPRG4      /* Supervisor Private Registers (4xx) */
 483 #define SPR5    SPRN_SPRG5
 484 #define SPR6    SPRN_SPRG6
 485 #define SPR7    SPRN_SPRG7
 486 #define SPRG0   SPRN_SPRG0
 487 #define SPRG1   SPRN_SPRG1
 488 #define SPRG2   SPRN_SPRG2
 489 #define SPRG3   SPRN_SPRG3
 490 #define SPRG4   SPRN_SPRG4
 491 #define SPRG5   SPRN_SPRG5
 492 #define SPRG6   SPRN_SPRG6
 493 #define SPRG7   SPRN_SPRG7
 494 #define SRR0    SPRN_SRR0       /* Save and Restore Register 0 */
 495 #define SRR1    SPRN_SRR1       /* Save and Restore Register 1 */
 496 #define SRR2    SPRN_SRR2       /* Save and Restore Register 2 */
 497 #define SRR3    SPRN_SRR3       /* Save and Restore Register 3 */
 498 #define TBRL    SPRN_TBRL       /* Time Base Read Lower Register */
 499 #define TBRU    SPRN_TBRU       /* Time Base Read Upper Register */
 500 #define TBWL    SPRN_TBWL       /* Time Base Write Lower Register */
 501 #define TBWU    SPRN_TBWU       /* Time Base Write Upper Register */
 502 #define ICTC    1019
 503 #define THRM1   SPRN_THRM1      /* Thermal Management Register 1 */
 504 #define THRM2   SPRN_THRM2      /* Thermal Management Register 2 */
 505 #define THRM3   SPRN_THRM3      /* Thermal Management Register 3 */
 506 #define XER     SPRN_XER
 507
 508 /* Processor Version Register */
 509
 510 /* Processor Version Register (PVR) field extraction */
 511
 512 #define PVR_VER(pvr)  (((pvr) >>  16) & 0xFFFF) /* Version field */
 513 #define PVR_REV(pvr)  (((pvr) >>   0) & 0xFFFF) /* Revison field */
 514
 515 /*
 516  * IBM has further subdivided the standard PowerPC 16-bit version and
 517  * revision subfields of the PVR for the PowerPC 403s into the following:
 518  */
 519
 520 #define PVR_FAM(pvr)    (((pvr) >> 20) & 0xFFF) /* Family field */
 521 #define PVR_MEM(pvr)    (((pvr) >> 16) & 0xF)   /* Member field */
 522 #define PVR_CORE(pvr)   (((pvr) >> 12) & 0xF)   /* Core field */
 523 #define PVR_CFG(pvr)    (((pvr) >>  8) & 0xF)   /* Configuration field */
 524 #define PVR_MAJ(pvr)    (((pvr) >>  4) & 0xF)   /* Major revision field */
 525 #define PVR_MIN(pvr)    (((pvr) >>  0) & 0xF)   /* Minor revision field */
 526
 527 /* We only need to define a new _MACH_xxx for machines which are part of
 528  * a configuration which supports more than one type of different machine.
 529  * This is currently limited to CONFIG_ALL_PPC and CHRP/PReP/PMac. -- Tom
 530  */
 531 #define _MACH_prep      0x00000001
 532 #define _MACH_Pmac      0x00000002      /* pmac or pmac clone (non-chrp) */
 533 #define _MACH_chrp      0x00000004      /* chrp machine */
 534
 535 /* see residual.h for these */
 536 #define _PREP_Motorola 0x01  /* motorola prep */
 537 #define _PREP_Firm     0x02  /* firmworks prep */
 538 #define _PREP_IBM      0x00  /* ibm prep */
 539 #define _PREP_Bull     0x03  /* bull prep */
 540
 541 /* these are arbitrary */
 542 #define _CHRP_Motorola 0x04  /* motorola chrp, the cobra */
 543 #define _CHRP_IBM      0x05  /* IBM chrp, the longtrail and longtrail 2 */
 544
 545 #define _GLOBAL(n)\
 546         .stabs __stringify(n:F-1),N_FUN,0,0,n;\
 547         .globl n;\
 548 n:
 549
 550 /* Macros for setting and retrieving special purpose registers */
 551
 552 #define stringify(s)    tostring(s)
 553 #define tostring(s)     #s
 554
 555 #define mfmsr()         ({unsigned int rval; \
 556                         asm volatile("mfmsr %0" : "=r" (rval)); rval;})
 557 #define mtmsr(v)        asm volatile("mtmsr %0" : : "r" (v))
 558
 559 #define mfspr(rn)       ({unsigned int rval; \
 560                         asm volatile("mfspr %0," stringify(rn) \
 561                                      : "=r" (rval)); rval;})
 562 #define mtspr(rn, v)    asm volatile("mtspr " stringify(rn) ",%0" : : "r" (v))
 563
 564 #define mfsrin(v)       ({unsigned int rval; \
 565                         asm volatile("mfsrin %0,%1" : "=r" (rval) : "r" (v)); \
 566                                         rval;})
 567
 568 #define proc_trap()     asm volatile("trap")
 569
 570 /* Segment Registers */
 571
 572 #define SR0     0
 573 #define SR1     1
 574 #define SR2     2
 575 #define SR3     3
 576 #define SR4     4
 577 #define SR5     5
 578 #define SR6     6
 579 #define SR7     7
 580 #define SR8     8
 581 #define SR9     9
 582 #define SR10    10
 583 #define SR11    11
 584 #define SR12    12
 585 #define SR13    13
 586 #define SR14    14
 587 #define SR15    15
 588
 589 #ifndef __ASSEMBLY__
 590 #if defined(CONFIG_ALL_PPC)
 591 extern int _machine;
 592
 593 /* what kind of prep workstation we are */
 594 extern int _prep_type;
 595
 596 /*
 597  * This is used to identify the board type from a given PReP board
 598  * vendor. Board revision is also made available.
 599  */
 600 extern unsigned char ucSystemType;
 601 extern unsigned char ucBoardRev;
 602 extern unsigned char ucBoardRevMaj, ucBoardRevMin;
 603 #else
 604 #define _machine 0
 605 #endif /* CONFIG_ALL_PPC */
 606
 607 struct task_struct;
 608 void start_thread(struct pt_regs *regs, unsigned long nip, unsigned long sp);
 609 void release_thread(struct task_struct *);
 610
 611 /*
 612  * Create a new kernel thread.
 613  */
 614 extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
 615
 616 /*
 617  * Bus types
 618  */
 619 #define EISA_bus 0
 620 #define MCA_bus 0
 621
 622 /* Lazy FPU handling on uni-processor */
 623 extern struct task_struct *last_task_used_math;
 624 extern struct task_struct *last_task_used_altivec;
 625
 626 /*
 627  * this is the minimum allowable io space due to the location
 628  * of the io areas on prep (first one at 0x80000000) but
 629  * as soon as I get around to remapping the io areas with the BATs
 630  * to match the mac we can raise this. -- Cort
 631  */
 632 #define TASK_SIZE       (CONFIG_TASK_SIZE)
 633
 634 /* This decides where the kernel will search for a free chunk of vm
 635  * space during mmap's.
 636  */
 637 #define TASK_UNMAPPED_BASE      (TASK_SIZE / 8 * 3)
 638
 639 typedef struct {
 640         unsigned long seg;
 641 } mm_segment_t;
 642
 643 struct thread_struct {
 644         unsigned long   ksp;            /* Kernel stack pointer */
 645         struct pt_regs  *regs;          /* Pointer to saved register state */
 646         mm_segment_t    fs;             /* for get_fs() validation */
 647         void            *pgdir;         /* root of page-table tree */
 648         int             fpexc_mode;     /* floating-point exception mode */
 649         signed long     last_syscall;
 650 #ifdef CONFIG_4xx
 651         unsigned long   dbcr0;          /* debug control register values */
 652         unsigned long   dbcr1;
 653 #endif
 654         double          fpr[32];        /* Complete floating point set */
 655         unsigned long   fpscr_pad;      /* fpr ... fpscr must be contiguous */
 656         unsigned long   fpscr;          /* Floating point status */
 657 #ifdef CONFIG_ALTIVEC
 658         vector128       vr[32];         /* Complete AltiVec set */
 659         vector128       vscr;           /* AltiVec status */
 660         unsigned long   vrsave;
 661 #endif /* CONFIG_ALTIVEC */
 662 };
 663
 664 #define INIT_SP         (sizeof(init_stack) + (unsigned long) &init_stack)
 665
 666 #define INIT_THREAD  { \
 667         .ksp = INIT_SP, \
 668         .fs = KERNEL_DS, \
 669         .pgdir = swapper_pg_dir, \
 670 }
 671
 672 /*
 673  * Return saved PC of a blocked thread. For now, this is the "user" PC
 674  */
 675 #define thread_saved_pc(tsk)    \
 676         ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
 677
 678 unsigned long get_wchan(struct task_struct *p);
 679
 680 #define KSTK_EIP(tsk)  ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
 681 #define KSTK_ESP(tsk)  ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)
 682
 683 /* Get/set floating-point exception mode */
 684 #define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
 685 #define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))
 686
 687 extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
 688 extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);
 689
 690 static inline unsigned int __unpack_fe01(unsigned int msr_bits)
 691 {
 692         return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8);
 693 }
 694
 695 static inline unsigned int __pack_fe01(unsigned int fpmode)
 696 {
 697         return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1);
 698 }
 699
 700 /* in process.c - for early bootup debug -- Cort */
 701 int ll_printk(const char *, ...);
 702 void ll_puts(const char *);
 703
 704 /* In misc.c */
 705 void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
 706
 707 #define have_of (_machine == _MACH_chrp || _machine == _MACH_Pmac)
 708
 709 #define cpu_relax()     barrier()
 710
 711 /*
 712  * Prefetch macros.
 713  */
 714 #define ARCH_HAS_PREFETCH
 715 #define ARCH_HAS_PREFETCHW
 716 #define ARCH_HAS_SPINLOCK_PREFETCH
 717
 718 extern inline void prefetch(const void *x)
 719 {
 720          __asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
 721 }
 722
 723 extern inline void prefetchw(const void *x)
 724 {
 725          __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
 726 }
 727
 728 #define spin_lock_prefetch(x)   prefetchw(x)
 729
 730 #endif /* !__ASSEMBLY__ */
 731
 732 #endif /* __ASM_PPC_PROCESSOR_H */
 733 #endif /* __KERNEL__ */