include/asm-i386/apicdef.h

   1 #ifndef __ASM_APICDEF_H
   2 #define __ASM_APICDEF_H
   3
   4 /*
   5  * Constants for various Intel APICs. (local APIC, IOAPIC, etc.)
   6  *
   7  * Alan Cox <Alan.Cox@linux.org>, 1995.
   8  * Ingo Molnar <mingo@redhat.com>, 1999, 2000
   9  */
  10
  11 #define         APIC_DEFAULT_PHYS_BASE  0xfee00000
  12
  13 #define         APIC_ID         0x20
  14 #ifdef CONFIG_X86_SUMMIT
  15  #define                APIC_ID_MASK            (0xFF<<24)
  16  #define                GET_APIC_ID(x)          (((x)>>24)&0xFF)
  17 #else
  18  #define                APIC_ID_MASK            (0x0F<<24)
  19  #define                GET_APIC_ID(x)          (((x)>>24)&0x0F)
  20 #endif
  21 #define         APIC_LVR        0x30
  22 #define                 APIC_LVR_MASK           0xFF00FF
  23 #define                 GET_APIC_VERSION(x)     ((x)&0xFF)
  24 #define                 GET_APIC_MAXLVT(x)      (((x)>>16)&0xFF)
  25 #define                 APIC_INTEGRATED(x)      ((x)&0xF0)
  26 #define         APIC_TASKPRI    0x80
  27 #define                 APIC_TPRI_MASK          0xFF
  28 #define         APIC_ARBPRI     0x90
  29 #define                 APIC_ARBPRI_MASK        0xFF
  30 #define         APIC_PROCPRI    0xA0
  31 #define         APIC_EOI        0xB0
  32 #define                 APIC_EIO_ACK            0x0             /* Write this to the EOI register */
  33 #define         APIC_RRR        0xC0
  34 #define         APIC_LDR        0xD0
  35 #define                 APIC_LDR_MASK           (0xFF<<24)
  36 #define                 GET_APIC_LOGICAL_ID(x)  (((x)>>24)&0xFF)
  37 #define                 SET_APIC_LOGICAL_ID(x)  (((x)<<24))
  38 #define                 APIC_ALL_CPUS           0xFF
  39 #define         APIC_DFR        0xE0
  40 #define                 APIC_DFR_CLUSTER                0x0FFFFFFFul
  41 #define                 APIC_DFR_FLAT                   0xFFFFFFFFul
  42 #define         APIC_SPIV       0xF0
  43 #define                 APIC_SPIV_FOCUS_DISABLED        (1<<9)
  44 #define                 APIC_SPIV_APIC_ENABLED          (1<<8)
  45 #define         APIC_ISR        0x100
  46 #define         APIC_TMR        0x180
  47 #define         APIC_IRR        0x200
  48 #define         APIC_ESR        0x280
  49 #define                 APIC_ESR_SEND_CS        0x00001
  50 #define                 APIC_ESR_RECV_CS        0x00002
  51 #define                 APIC_ESR_SEND_ACC       0x00004
  52 #define                 APIC_ESR_RECV_ACC       0x00008
  53 #define                 APIC_ESR_SENDILL        0x00020
  54 #define                 APIC_ESR_RECVILL        0x00040
  55 #define                 APIC_ESR_ILLREGA        0x00080
  56 #define         APIC_ICR        0x300
  57 #define                 APIC_DEST_SELF          0x40000
  58 #define                 APIC_DEST_ALLINC        0x80000
  59 #define                 APIC_DEST_ALLBUT        0xC0000
  60 #define                 APIC_ICR_RR_MASK        0x30000
  61 #define                 APIC_ICR_RR_INVALID     0x00000
  62 #define                 APIC_ICR_RR_INPROG      0x10000
  63 #define                 APIC_ICR_RR_VALID       0x20000
  64 #define                 APIC_INT_LEVELTRIG      0x08000
  65 #define                 APIC_INT_ASSERT         0x04000
  66 #define                 APIC_ICR_BUSY           0x01000
  67 #define                 APIC_DEST_LOGICAL       0x00800
  68 #define                 APIC_DM_FIXED           0x00000
  69 #define                 APIC_DM_LOWEST          0x00100
  70 #define                 APIC_DM_SMI             0x00200
  71 #define                 APIC_DM_REMRD           0x00300
  72 #define                 APIC_DM_NMI             0x00400
  73 #define                 APIC_DM_INIT            0x00500
  74 #define                 APIC_DM_STARTUP         0x00600
  75 #define                 APIC_DM_EXTINT          0x00700
  76 #define                 APIC_VECTOR_MASK        0x000FF
  77 #define         APIC_ICR2       0x310
  78 #define                 GET_APIC_DEST_FIELD(x)  (((x)>>24)&0xFF)
  79 #define                 SET_APIC_DEST_FIELD(x)  ((x)<<24)
  80 #define         APIC_LVTT       0x320
  81 #define         APIC_LVTTHMR    0x330
  82 #define         APIC_LVTPC      0x340
  83 #define         APIC_LVT0       0x350
  84 #define                 APIC_LVT_TIMER_BASE_MASK        (0x3<<18)
  85 #define                 GET_APIC_TIMER_BASE(x)          (((x)>>18)&0x3)
  86 #define                 SET_APIC_TIMER_BASE(x)          (((x)<<18))
  87 #define                 APIC_TIMER_BASE_CLKIN           0x0
  88 #define                 APIC_TIMER_BASE_TMBASE          0x1
  89 #define                 APIC_TIMER_BASE_DIV             0x2
  90 #define                 APIC_LVT_TIMER_PERIODIC         (1<<17)
  91 #define                 APIC_LVT_MASKED                 (1<<16)
  92 #define                 APIC_LVT_LEVEL_TRIGGER          (1<<15)
  93 #define                 APIC_LVT_REMOTE_IRR             (1<<14)
  94 #define                 APIC_INPUT_POLARITY             (1<<13)
  95 #define                 APIC_SEND_PENDING               (1<<12)
  96 #define                 GET_APIC_DELIVERY_MODE(x)       (((x)>>8)&0x7)
  97 #define                 SET_APIC_DELIVERY_MODE(x,y)     (((x)&~0x700)|((y)<<8))
  98 #define                         APIC_MODE_FIXED         0x0
  99 #define                         APIC_MODE_NMI           0x4
 100 #define                         APIC_MODE_EXINT         0x7
 101 #define         APIC_LVT1       0x360
 102 #define         APIC_LVTERR     0x370
 103 #define         APIC_TMICT      0x380
 104 #define         APIC_TMCCT      0x390
 105 #define         APIC_TDCR       0x3E0
 106 #define                 APIC_TDR_DIV_TMBASE     (1<<2)
 107 #define                 APIC_TDR_DIV_1          0xB
 108 #define                 APIC_TDR_DIV_2          0x0
 109 #define                 APIC_TDR_DIV_4          0x1
 110 #define                 APIC_TDR_DIV_8          0x2
 111 #define                 APIC_TDR_DIV_16         0x3
 112 #define                 APIC_TDR_DIV_32         0x8
 113 #define                 APIC_TDR_DIV_64         0x9
 114 #define                 APIC_TDR_DIV_128        0xA
 115
 116 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
 117
 118 #ifdef CONFIG_X86_NUMA
 119  #define MAX_IO_APICS 32
 120 #else
 121  #define MAX_IO_APICS 8
 122 #endif
 123
 124 /*
 125  * the local APIC register structure, memory mapped. Not terribly well
 126  * tested, but we might eventually use this one in the future - the
 127  * problem why we cannot use it right now is the P5 APIC, it has an
 128  * errata which cannot take 8-bit reads and writes, only 32-bit ones ...
 129  */
 130 #define u32 unsigned int
 131
 132 #define lapic ((volatile struct local_apic *)APIC_BASE)
 133
 134 struct local_apic {
 135
 136 /*000*/ struct { u32 __reserved[4]; } __reserved_01;
 137
 138 /*010*/ struct { u32 __reserved[4]; } __reserved_02;
 139
 140 /*020*/ struct { /* APIC ID Register */
 141                 u32   __reserved_1      : 24,
 142                         phys_apic_id    :  4,
 143                         __reserved_2    :  4;
 144                 u32 __reserved[3];
 145         } id;
 146
 147 /*030*/ const
 148         struct { /* APIC Version Register */
 149                 u32   version           :  8,
 150                         __reserved_1    :  8,
 151                         max_lvt         :  8,
 152                         __reserved_2    :  8;
 153                 u32 __reserved[3];
 154         } version;
 155
 156 /*040*/ struct { u32 __reserved[4]; } __reserved_03;
 157
 158 /*050*/ struct { u32 __reserved[4]; } __reserved_04;
 159
 160 /*060*/ struct { u32 __reserved[4]; } __reserved_05;
 161
 162 /*070*/ struct { u32 __reserved[4]; } __reserved_06;
 163
 164 /*080*/ struct { /* Task Priority Register */
 165                 u32   priority  :  8,
 166                         __reserved_1    : 24;
 167                 u32 __reserved_2[3];
 168         } tpr;
 169
 170 /*090*/ const
 171         struct { /* Arbitration Priority Register */
 172                 u32   priority  :  8,
 173                         __reserved_1    : 24;
 174                 u32 __reserved_2[3];
 175         } apr;
 176
 177 /*0A0*/ const
 178         struct { /* Processor Priority Register */
 179                 u32   priority  :  8,
 180                         __reserved_1    : 24;
 181                 u32 __reserved_2[3];
 182         } ppr;
 183
 184 /*0B0*/ struct { /* End Of Interrupt Register */
 185                 u32   eoi;
 186                 u32 __reserved[3];
 187         } eoi;
 188
 189 /*0C0*/ struct { u32 __reserved[4]; } __reserved_07;
 190
 191 /*0D0*/ struct { /* Logical Destination Register */
 192                 u32   __reserved_1      : 24,
 193                         logical_dest    :  8;
 194                 u32 __reserved_2[3];
 195         } ldr;
 196
 197 /*0E0*/ struct { /* Destination Format Register */
 198                 u32   __reserved_1      : 28,
 199                         model           :  4;
 200                 u32 __reserved_2[3];
 201         } dfr;
 202
 203 /*0F0*/ struct { /* Spurious Interrupt Vector Register */
 204                 u32     spurious_vector :  8,
 205                         apic_enabled    :  1,
 206                         focus_cpu       :  1,
 207                         __reserved_2    : 22;
 208                 u32 __reserved_3[3];
 209         } svr;
 210
 211 /*100*/ struct { /* In Service Register */
 212 /*170*/         u32 bitfield;
 213                 u32 __reserved[3];
 214         } isr [8];
 215
 216 /*180*/ struct { /* Trigger Mode Register */
 217 /*1F0*/         u32 bitfield;
 218                 u32 __reserved[3];
 219         } tmr [8];
 220
 221 /*200*/ struct { /* Interrupt Request Register */
 222 /*270*/         u32 bitfield;
 223                 u32 __reserved[3];
 224         } irr [8];
 225
 226 /*280*/ union { /* Error Status Register */
 227                 struct {
 228                         u32   send_cs_error                     :  1,
 229                                 receive_cs_error                :  1,
 230                                 send_accept_error               :  1,
 231                                 receive_accept_error            :  1,
 232                                 __reserved_1                    :  1,
 233                                 send_illegal_vector             :  1,
 234                                 receive_illegal_vector          :  1,
 235                                 illegal_register_address        :  1,
 236                                 __reserved_2                    : 24;
 237                         u32 __reserved_3[3];
 238                 } error_bits;
 239                 struct {
 240                         u32 errors;
 241                         u32 __reserved_3[3];
 242                 } all_errors;
 243         } esr;
 244
 245 /*290*/ struct { u32 __reserved[4]; } __reserved_08;
 246
 247 /*2A0*/ struct { u32 __reserved[4]; } __reserved_09;
 248
 249 /*2B0*/ struct { u32 __reserved[4]; } __reserved_10;
 250
 251 /*2C0*/ struct { u32 __reserved[4]; } __reserved_11;
 252
 253 /*2D0*/ struct { u32 __reserved[4]; } __reserved_12;
 254
 255 /*2E0*/ struct { u32 __reserved[4]; } __reserved_13;
 256
 257 /*2F0*/ struct { u32 __reserved[4]; } __reserved_14;
 258
 259 /*300*/ struct { /* Interrupt Command Register 1 */
 260                 u32   vector                    :  8,
 261                         delivery_mode           :  3,
 262                         destination_mode        :  1,
 263                         delivery_status         :  1,
 264                         __reserved_1            :  1,
 265                         level                   :  1,
 266                         trigger                 :  1,
 267                         __reserved_2            :  2,
 268                         shorthand               :  2,
 269                         __reserved_3            :  12;
 270                 u32 __reserved_4[3];
 271         } icr1;
 272
 273 /*310*/ struct { /* Interrupt Command Register 2 */
 274                 union {
 275                         u32   __reserved_1      : 24,
 276                                 phys_dest       :  4,
 277                                 __reserved_2    :  4;
 278                         u32   __reserved_3      : 24,
 279                                 logical_dest    :  8;
 280                 } dest;
 281                 u32 __reserved_4[3];
 282         } icr2;
 283
 284 /*320*/ struct { /* LVT - Timer */
 285                 u32   vector            :  8,
 286                         __reserved_1    :  4,
 287                         delivery_status :  1,
 288                         __reserved_2    :  3,
 289                         mask            :  1,
 290                         timer_mode      :  1,
 291                         __reserved_3    : 14;
 292                 u32 __reserved_4[3];
 293         } lvt_timer;
 294
 295 /*330*/ struct { /* LVT - Thermal Sensor */
 296                 u32  vector             :  8,
 297                         delivery_mode   :  3,
 298                         __reserved_1    :  1,
 299                         delivery_status :  1,
 300                         __reserved_2    :  3,
 301                         mask            :  1,
 302                         __reserved_3    : 15;
 303                 u32 __reserved_4[3];
 304         } lvt_thermal;
 305
 306 /*340*/ struct { /* LVT - Performance Counter */
 307                 u32   vector            :  8,
 308                         delivery_mode   :  3,
 309                         __reserved_1    :  1,
 310                         delivery_status :  1,
 311                         __reserved_2    :  3,
 312                         mask            :  1,
 313                         __reserved_3    : 15;
 314                 u32 __reserved_4[3];
 315         } lvt_pc;
 316
 317 /*350*/ struct { /* LVT - LINT0 */
 318                 u32   vector            :  8,
 319                         delivery_mode   :  3,
 320                         __reserved_1    :  1,
 321                         delivery_status :  1,
 322                         polarity        :  1,
 323                         remote_irr      :  1,
 324                         trigger         :  1,
 325                         mask            :  1,
 326                         __reserved_2    : 15;
 327                 u32 __reserved_3[3];
 328         } lvt_lint0;
 329
 330 /*360*/ struct { /* LVT - LINT1 */
 331                 u32   vector            :  8,
 332                         delivery_mode   :  3,
 333                         __reserved_1    :  1,
 334                         delivery_status :  1,
 335                         polarity        :  1,
 336                         remote_irr      :  1,
 337                         trigger         :  1,
 338                         mask            :  1,
 339                         __reserved_2    : 15;
 340                 u32 __reserved_3[3];
 341         } lvt_lint1;
 342
 343 /*370*/ struct { /* LVT - Error */
 344                 u32   vector            :  8,
 345                         __reserved_1    :  4,
 346                         delivery_status :  1,
 347                         __reserved_2    :  3,
 348                         mask            :  1,
 349                         __reserved_3    : 15;
 350                 u32 __reserved_4[3];
 351         } lvt_error;
 352
 353 /*380*/ struct { /* Timer Initial Count Register */
 354                 u32   initial_count;
 355                 u32 __reserved_2[3];
 356         } timer_icr;
 357
 358 /*390*/ const
 359         struct { /* Timer Current Count Register */
 360                 u32   curr_count;
 361                 u32 __reserved_2[3];
 362         } timer_ccr;
 363
 364 /*3A0*/ struct { u32 __reserved[4]; } __reserved_16;
 365
 366 /*3B0*/ struct { u32 __reserved[4]; } __reserved_17;
 367
 368 /*3C0*/ struct { u32 __reserved[4]; } __reserved_18;
 369
 370 /*3D0*/ struct { u32 __reserved[4]; } __reserved_19;
 371
 372 /*3E0*/ struct { /* Timer Divide Configuration Register */
 373                 u32   divisor           :  4,
 374                         __reserved_1    : 28;
 375                 u32 __reserved_2[3];
 376         } timer_dcr;
 377
 378 /*3F0*/ struct { u32 __reserved[4]; } __reserved_20;
 379
 380 } __attribute__ ((packed));
 381
 382 #undef u32
 383
 384 #endif