2 * linux/drivers/video/i810.h -- Intel 810 General Definitions/Declarations
4 * Copyright (C) 2001 Antonino Daplas<adaplas@pol.net>
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file COPYING in the main directory of this archive for
16 #include <linux/list.h>
17 #include <linux/agp_backend.h>
19 #include <video/vga.h>
22 #define TILEWALK_X (0 << 12)
23 #define TILEWALK_Y (1 << 12)
26 #define COLOR_COPY_ROP 0xF0
27 #define PAT_COPY_ROP 0xCC
28 #define CLEAR_ROP 0x00
29 #define WHITE_ROP 0xFF
30 #define INVERT_ROP 0x55
33 /* 2D Engine definitions */
34 #define SOLIDPATTERN 0x80000000
35 #define NONSOLID 0x00000000
36 #define BPP8 (0 << 24)
37 #define BPP16 (1 << 24)
38 #define BPP24 (2 << 24)
40 #define PIXCONF8 (2 << 16)
41 #define PIXCONF15 (4 << 16)
42 #define PIXCONF16 (5 << 16)
43 #define PIXCONF24 (6 << 16)
44 #define PIXCONF32 (7 << 16)
46 #define DYN_COLOR_EN (1 << 26)
47 #define DYN_COLOR_DIS (0 << 26)
48 #define INCREMENT 0x00000000
49 #define DECREMENT (0x01 << 30)
50 #define ARB_ON 0x00000001
51 #define ARB_OFF 0x00000000
52 #define SYNC_FLIP 0x00000000
53 #define ASYNC_FLIP 0x00000040
54 #define OPTYPE_MASK 0xE0000000
55 #define PARSER_MASK 0x001F8000
56 #define D2_MASK 0x001FC000 /* 2D mask */
58 /* Instruction type */
59 /* There are more but pertains to 3D */
60 #define PARSER 0x00000000
61 #define BLIT (0x02 << 29)
62 #define RENDER (0x03 << 29)
65 #define NOP 0x00 /* No operation, padding */
66 #define BP_INT (0x01 << 23) /* Breakpoint interrupt */
67 #define USR_INT (0x02 << 23) /* User interrupt */
68 #define WAIT_FOR_EVNT (0x03 << 23) /* Wait for event */
69 #define FLUSH (0x04 << 23)
70 #define CONTEXT_SEL (0x05 << 23)
71 #define REPORT_HEAD (0x07 << 23)
72 #define ARB_ON_OFF (0x08 << 23)
73 #define OVERLAY_FLIP (0x11 << 23)
74 #define LOAD_SCAN_INC (0x12 << 23)
75 #define LOAD_SCAN_EX (0x13 << 23)
76 #define FRONT_BUFFER (0x14 << 23)
77 #define DEST_BUFFER (0x15 << 23)
78 #define Z_BUFFER (0x16 << 23)
80 #define STORE_DWORD_IMM (0x20 << 23)
81 #define STORE_DWORD_IDX (0x21 << 23)
82 #define BATCH_BUFFER (0x30 << 23)
85 #define SETUP_BLIT 0x00
86 #define SETUP_MONO_PATTERN_SL_BLT (0x10 << 22)
87 #define PIXEL_BLT (0x20 << 22)
88 #define SCANLINE_BLT (0x21 << 22)
89 #define TEXT_BLT (0x22 << 22)
90 #define TEXT_IMM_BLT (0x30 << 22)
91 #define COLOR_BLT (0x40 << 22)
92 #define MONO_PAT_BLIT (0x42 << 22)
93 #define SOURCE_COPY_BLIT (0x43 << 22)
94 #define MONO_SOURCE_COPY_BLIT (0x44 << 22)
95 #define SOURCE_COPY_IMMEDIATE (0x60 << 22)
96 #define MONO_SOURCE_COPY_IMMEDIATE (0x61 << 22)
98 #define VERSION_MAJOR 0
99 #define VERSION_MINOR 9
100 #define VERSION_TEENIE 0
101 #define BRANCH_VERSION ""
104 /* mvo: intel i815 */
105 #ifndef PCI_DEVICE_ID_INTEL_82815_100
106 #define PCI_DEVICE_ID_INTEL_82815_100 0x1102
108 #ifndef PCI_DEVICE_ID_INTEL_82815_NOAGP
109 #define PCI_DEVICE_ID_INTEL_82815_NOAGP 0x1112
111 #ifndef PCI_DEVICE_ID_INTEL_82815_FULL_CTRL
112 #define PCI_DEVICE_ID_INTEL_82815_FULL_CTRL 0x1130
115 /* General Defines */
116 #define I810_PAGESIZE 4096
117 #define MAX_DMA_SIZE (1024 * 4096)
118 #define SAREA_SIZE 4096
119 #define PCI_I810_MISCC 0x72
120 #define MMIO_SIZE (512*1024)
121 #define GTT_SIZE (16*1024)
122 #define RINGBUFFER_SIZE (64*1024)
123 #define PIXMAP_SIZE (4 * 4096)
124 #define CURSOR_SIZE 4096
128 #define WAIT_COUNT 10000000
130 #define FONTDATAMAX 8192
131 /* Masks (AND ops) and OR's */
132 #define FB_START_MASK (0x3f << (32 - 6))
133 #define MMIO_ADDR_MASK (0x1FFF << (32 - 13))
134 #define FREQ_MASK 0x1EF
137 #define DRAM_OFF 0xE7
138 #define PG_ENABLE_MASK 0x01
139 #define RING_SIZE_MASK (RINGBUFFER_SIZE - 1);
141 /* defines for restoring registers partially */
142 #define ADDR_MAP_MASK (0x07 << 5)
144 #define PIXCONF_0 (0x64 << 8)
145 #define PIXCONF_2 (0xF3 << 24)
146 #define PIXCONF_1 (0xF0 << 16)
147 #define MN_MASK 0x3FF03FF
148 #define P_OR (0x7 << 4)
149 #define DAC_BIT (1 << 16)
150 #define INTERLACE_BIT (1 << 7)
151 #define IER_MASK (3 << 13)
152 #define IMR_MASK (3 << 13)
154 /* Power Management */
155 #define DPMS_MASK 0xF0000
156 #define POWERON 0x00000
157 #define STANDBY 0x20000
158 #define SUSPEND 0x80000
159 #define POWERDOWN 0xA0000
160 #define EMR_MASK ~0x3F
161 #define FW_BLC_MASK ~(0x3F|(7 << 8)|(0x3F << 12)|(7 << 20))
164 #define RBUFFER_START_MASK 0xFFFFF000
165 #define RBUFFER_SIZE_MASK 0x001FF000
166 #define RBUFFER_HEAD_MASK 0x001FFFFC
167 #define RBUFFER_TAIL_MASK 0x001FFFF8
170 #define REF_FREQ 24000000
171 #define TARGET_N_MAX 30
174 #define V_FRONTPORCH 1
176 #define H_SCALEFACTOR 20
177 #define H_BLANKSCALE 128
178 #define H_GRADIENT 600
180 #define MAX_PIXELCLOCK 230000000
181 #define MIN_PIXELCLOCK 15000000
188 #define CURSOR_ENABLE_MASK 0x1000
189 #define CURSOR_MODE_64_TRANS 4
190 #define CURSOR_MODE_64_XOR 5
191 #define CURSOR_MODE_64_3C 6
192 #define COORD_INACTIVE 0
193 #define COORD_ACTIVE (1 << 4)
194 #define EXTENDED_PALETTE 1
196 /* AGP Memory Types*/
197 #define AGP_NORMAL_MEMORY 0
198 #define AGP_DCACHE_MEMORY 1
199 #define AGP_PHYSICAL_MEMORY 2
201 /* Allocated resource Flags */
202 #define FRAMEBUFFER_REQ 1
204 #define PCI_DEVICE_ENABLED 4
205 #define HAS_FONTCACHE 8
209 #define HAS_ACCELERATION 2
210 #define ALWAYS_SYNC 4
214 agp_memory
*i810_fb_memory
;
215 agp_memory
*i810_cursor_memory
;
218 struct mode_registers
{
219 u32 pixclock
, M
, N
, P
;
220 u8 cr00
, cr01
, cr02
, cr03
;
221 u8 cr04
, cr05
, cr06
, cr07
;
222 u8 cr09
, cr10
, cr11
, cr12
;
223 u8 cr13
, cr15
, cr16
, cr30
;
224 u8 cr31
, cr32
, cr33
, cr35
, cr39
;
225 u32 bpp8_100
, bpp16_100
;
226 u32 bpp24_100
, bpp8_133
;
227 u32 bpp16_133
, bpp24_133
;
232 unsigned long physical
;
238 struct state_registers
{
239 u32 dclk_1d
, dclk_2d
, dclk_0ds
;
240 u32 pixconf
, fw_blc
, pgtbl_ctl
;
241 u32 fence0
, hws_pga
, dplystas
;
242 u16 bltcntl
, hwstam
, ier
, iir
, imr
;
243 u8 cr00
, cr01
, cr02
, cr03
, cr04
;
244 u8 cr05
, cr06
, cr07
, cr08
, cr09
;
245 u8 cr10
, cr11
, cr12
, cr13
, cr14
;
246 u8 cr15
, cr16
, cr17
, cr80
, gr10
;
247 u8 cr30
, cr31
, cr32
, cr33
, cr35
;
248 u8 cr39
, cr41
, cr70
, sr01
, msr
;
252 struct mode_registers regs
;
253 struct state_registers hw_state
;
254 struct gtt_data i810_gtt
;
255 struct fb_ops i810fb_ops
;
257 struct heap_data aperture
;
259 struct heap_data iring
;
260 struct heap_data cursor_heap
;
261 struct heap_data pixmap
;
262 struct vgastate state
;
265 u32 pseudo_palette
[17];
266 unsigned long mmio_start_phys
;
267 u8
*mmio_start_virtual
;
291 #define i810_readb(where, mmio) readb(mmio + where)
292 #define i810_readw(where, mmio) readw(mmio + where)
293 #define i810_readl(where, mmio) readl(mmio + where)
294 #define i810_writeb(where, mmio, val) writeb(val, mmio + where)
295 #define i810_writew(where, mmio, val) writew(val, mmio + where)
296 #define i810_writel(where, mmio, val) writel(val, mmio + where)
298 #endif /* __I810_H__ */