arch/ppc/platforms/zx4500.h

   1 /* * arch/ppc/platforms/zx4500.h
   2  *
   3  * Board setup routines for Znyx ZX4500 cPCI board.
   4  *
   5  * Author: Mark A. Greer
   6  *         mgreer@mvista.com
   7  *
   8  * 2000-2001 (c) MontaVista, Software, Inc.  This file is licensed under
   9  * the terms of the GNU General Public License version 2.1.  This program
  10  * is licensed "as is" without any warranty of any kind, whether express
  11  * or implied.
  12  */
  13 #ifndef __PPC_PLATFORMS_ZX4500_H_
  14 #define __PPC_PLATFORMS_ZX4500_H_
  15
  16 /*
  17  * Define the addresses of CPLD registers in CLPD area.
  18  */
  19 #define ZX4500_CPLD_BOARD_ID            0xff800001
  20 #define ZX4500_CPLD_REV                 0xff800002
  21 #define ZX4500_CPLD_RESET               0xff800011
  22 #define ZX4500_CPLD_PHY1                0xff800014
  23 #define ZX4500_CPLD_PHY2                0xff800015
  24 #define ZX4500_CPLD_PHY3                0xff800016
  25 #define ZX4500_CPLD_SYSCTL              0xff800017
  26 #define ZX4500_CPLD_EXT_FLASH           0xff800018
  27 #define ZX4500_CPLD_DUAL1               0xff800019
  28 #define ZX4500_CPLD_DUAL2               0xff80001A
  29 #define ZX4500_CPLD_STATUS              0xff800030
  30 #define ZX4500_CPLD_STREAM              0xff800032
  31 #define ZX4500_CPLD_PHY1_LED            0xff800034
  32 #define ZX4500_CPLD_PHY2_LED            0xff800035
  33 #define ZX4500_CPLD_PHY3_LED            0xff800036
  34 #define ZX4500_CPLD_PHY1_LNK            0xff80003C
  35 #define ZX4500_CPLD_PHY2_LNK            0xff80003D
  36 #define ZX4500_CPLD_PHY3_LNK            0xff80003E
  37
  38 #define ZX4500_CPLD_RESET_SOFT          0x01    /* Soft Reset */
  39 #define ZX4500_CPLD_RESET_XBUS          0x40    /* Reset entire board */
  40
  41 #define ZX4500_CPLD_SYSCTL_PMC          0x01    /* Enable INTA/B/C/D from PMC */
  42 #define ZX4500_CPLD_SYSCTL_BCM          0x04    /* Enable INTA from BCM */
  43 #define ZX4500_CPLD_SYSCTL_SINTA        0x08    /* Enable SINTA from 21554 */
  44 #define ZX4500_CPLD_SYSCTL_WD           0x20    /* Enable Watchdog Timer */
  45 #define ZX4500_CPLD_SYSCTL_PMC_TRI      0x80    /* Tri-state PMC EREADY */
  46
  47 #define ZX4500_CPLD_DUAL2_LED_PULL      0x01    /* Pull LED */
  48 #define ZX4500_CPLD_DUAL2_LED_EXT_FAULT 0x02    /* External Fault LED */
  49 #define ZX4500_CPLD_DUAL2_LED_INT_FAULT 0x04    /* Internal Fault LED */
  50 #define ZX4500_CPLD_DUAL2_LED_OK        0x08    /* OK LED */
  51 #define ZX4500_CPLD_DUAL2_LED_CLK       0x10    /* CLK LED */
  52
  53 /*
  54  * Defines related to boot string stored in flash.
  55  */
  56 #define ZX4500_BOOT_STRING_ADDR         0xfff7f000
  57 #define ZX4500_BOOT_STRING_LEN          80
  58
  59 /*
  60  * Define the IDSEL that the PCI bus side of the 8240 is connected to.
  61  * This IDSEL must not be selected from the 8240 processor side.
  62  */
  63 #define ZX4500_HOST_BRIDGE_IDSEL        20
  64
  65
  66 void zx4500_find_bridges(void);
  67
  68 #endif  /* __PPC_PLATFORMS_ZX4500_H_ */