arch/ppc/platforms/4xx/ibmnp405l.h

   1 /*
   2  * arch/ppc/platforms/4xx/ibmnp405l.h
   3  *
   4  * Author: Armin Kuster <akuster@mvista.com>
   5  *
   6  * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
   7  * the terms of the GNU General Public License version 2.1.  This program
   8  * is licensed "as is" without any warranty of any kind, whether express
   9  * or implied.
  10  */
  11
  12 #ifdef __KERNEL__
  13 #ifndef __ASM_IBMNP405L_H__
  14 #define __ASM_IBMNP405L_H__
  15
  16 #include <linux/config.h>
  17
  18 /* serial port defines */
  19 #define RS_TABLE_SIZE   2
  20
  21 #define UART0_INT       0
  22 #define UART1_INT       1
  23
  24 #define UART0_IO_BASE   0xEF600300
  25 #define UART1_IO_BASE   0xEF600400
  26 #define IIC0_BASE       0xEF600500
  27 #define OPB0_BASE       0xEF600600
  28 #define GPIO0_BASE      0xEF600700
  29 #define EMAC0_BASE      0xEF600800
  30 #define EMAC1_BASE      0xEF600900
  31 #define ZMII0_BASE      0xEF600C10
  32 #define BL_MAC_WOL      41      /* WOL */
  33 #define BL_MAL_SERR     45      /* MAL SERR */
  34 #define BL_MAL_TXDE     46      /* MAL TXDE */
  35 #define BL_MAL_RXDE     47      /* MAL RXDE */
  36 #define BL_MAL_TXEOB    17      /* MAL TX EOB */
  37 #define BL_MAL_RXEOB    18      /* MAL RX EOB */
  38 #define BL_MAC_ETH0     37      /* MAC */
  39 #define BL_MAC_ETH1     38      /* MAC */
  40
  41 #define EMAC_NUMS       2
  42
  43 #define IIC0_IRQ        2
  44
  45 #undef NR_UICS
  46 #define NR_UICS 2
  47 #define UIC_CASCADE_MASK 0x0003 /* bits 30 & 31 */
  48
  49 #define BD_EMAC_ADDR(e,i) bi_enetaddr[e][i]
  50
  51 #define STD_UART_OP(num)                                        \
  52         { 0, BASE_BAUD, 0, UART##num##_INT,                     \
  53                 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST),        \
  54                 iomem_base:(u8 *) UART##num##_IO_BASE,          \
  55                 io_type: SERIAL_IO_MEM},
  56
  57 #if defined(CONFIG_UART0_TTYS0)
  58 #define SERIAL_DEBUG_IO_BASE    UART0_IO_BASE
  59 #define SERIAL_PORT_DFNS        \
  60         STD_UART_OP(0)          \
  61         STD_UART_OP(1)
  62 #endif
  63
  64 #if defined(CONFIG_UART0_TTYS1)
  65 #define SERIAL_DEBUG_IO_BASE    UART1_IO_BASE
  66 #define SERIAL_PORT_DFNS        \
  67         STD_UART_OP(1)          \
  68         STD_UART_OP(0)
  69 #endif
  70
  71 /* DCR defines */
  72 /* ------------------------------------------------------------------------- */
  73
  74 #define DCRN_CHCR_BASE  0x0F1
  75 #define DCRN_CHPSR_BASE 0x0B4
  76 #define DCRN_CPMSR_BASE 0x0BA
  77 #define DCRN_CPMFR_BASE 0x0B9
  78 #define DCRN_CPMER_BASE 0x0B8
  79
  80 #define IBM_CPM_EMAC0   0x00800000      /* on-chip ethernet MM unit */
  81 #define IBM_CPM_EMAC1   0x00100000      /* EMAC 1 MII */
  82 #define IBM_CPM_UIC1    0x00020000      /* Universal Interrupt Controller */
  83 #define IBM_CPM_UIC0    0x00010000      /* Universal Interrupt Controller */
  84 #define IBM_CPM_CPU     0x00008000      /* processor core */
  85 #define IBM_CPM_EBC     0x00004000      /* ROM/SRAM peripheral controller */
  86 #define IBM_CPM_SDRAM0  0x00002000      /* SDRAM memory controller */
  87 #define IBM_CPM_GPIO0   0x00001000      /* General Purpose IO (??) */
  88 #define IBM_CPM_HDLC    0x00000800      /* HDCL */
  89 #define IBM_CPM_TMRCLK  0x00000400      /* CPU timers */
  90 #define IBM_CPM_PLB     0x00000100      /* PLB bus arbiter */
  91 #define IBM_CPM_OPB     0x00000080      /* PLB to OPB bridge */
  92 #define IBM_CPM_DMA     0x00000040      /* DMA controller */
  93 #define IBM_CPM_IIC0    0x00000010      /* IIC interface */
  94 #define IBM_CPM_UART0   0x00000002      /* serial port 0 */
  95 #define IBM_CPM_UART1   0x00000001      /* serial port 1 */
  96 #define DFLT_IBM4xx_PM  ~(IBM_CPM_UIC0 | IBM_CPM_UIC1 | IBM_CPM_CPU     \
  97                         | IBM_CPM_EBC | IBM_CPM_SDRAM0 | IBM_CPM_PLB    \
  98                         | IBM_CPM_OPB | IBM_CPM_TMRCLK | IBM_CPM_DMA    \
  99                         | IBM_CPM_EMAC0 | IBM_CPM_EMAC1)
 100
 101 #define DCRN_DMA0_BASE  0x100
 102 #define DCRN_DMA1_BASE  0x108
 103 #define DCRN_DMA2_BASE  0x110
 104 #define DCRN_DMA3_BASE  0x118
 105 #define DCRNCAP_DMA_SG  1       /* have DMA scatter/gather capability */
 106 #define DCRN_DMASR_BASE 0x120
 107 #define DCRN_EBC_BASE   0x012
 108 #define DCRN_DCP0_BASE  0x014
 109 #define DCRN_MAL_BASE   0x180
 110 #define DCRN_MAL1_BASE  0x200
 111 #define DCRN_OCM0_BASE  0x018
 112 #define DCRN_PLB0_BASE  0x084
 113 #define DCRN_PLLMR_BASE 0x0F0
 114 #define DCRN_POB0_BASE  0x0A0
 115 #define DCRN_SDRAM0_BASE 0x010
 116 #define DCRN_UIC0_BASE  0x0C0
 117 #define DCRN_UIC1_BASE  0x0D0
 118 #define DCRN_CPC0_EPRCSR 0x0F3
 119
 120 #define UIC0_UIC1NC      30     /* UIC1 non-critical interrupt */
 121 #define UIC0_UIC1CR      31     /* UIC1 critical interrupt */
 122
 123 #define CHR1_CETE       0x00000004      /* CPU external timer enable */
 124 #define UIC0    DCRN_UIC0_BASE
 125 #define UIC1    DCRN_UIC1_BASE
 126
 127 #define SDRAM_CFG       0x20
 128 #define SDRAM0_ECCCFG   0x94
 129 #define SDRAM_NO_ECC    0x10000000
 130 #include <asm/ibm405.h>
 131
 132 #endif                          /* __ASM_IBMNP405L_H__ */
 133 #endif                          /* __KERNEL__ */