2 * arch/ppc/platforms/4xx/ash.c
4 * Support for the IBM NP405H ash eval board
6 * Author: Armin Kuster <akuster@mvista.com>
8 * 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2.1. This program
10 * is licensed "as is" without any warranty of any kind, whether express
13 #include <linux/config.h>
14 #include <linux/init.h>
15 #include <linux/pagemap.h>
16 #include <linux/pci.h>
18 #include <asm/machdep.h>
19 #include <asm/pci-bridge.h>
24 #define DBG(x...) printk(x)
31 /* Some IRQs unique to Walnut.
32 * Used by the generic 405 PCI setup functions in ppc4xx_pci.c
35 ppc405_map_irq(struct pci_dev
*dev
, unsigned char idsel
, unsigned char pin
)
37 static char pci_irq_table
[][4] =
39 * PCI IDSEL/INTPIN->INTLINE
43 {24, 24, 24, 24}, /* IDSEL 1 - PCI slot 1 */
44 {25, 25, 25, 25}, /* IDSEL 2 - PCI slot 2 */
45 {26, 26, 26, 26}, /* IDSEL 3 - PCI slot 3 */
46 {27, 27, 27, 27}, /* IDSEL 4 - PCI slot 4 */
49 const long min_idsel
= 1, max_idsel
= 4, irqs_per_slot
= 4;
50 return PCI_IRQ_TABLE_LOOKUP
;
60 #ifdef CONFIG_DEBUG_BRINGUP
63 printk("machine\t: %s\n", PPC4xx_MACHINE_NAME
);
65 printk("bi_s_version\t %s\n", bip
->bi_s_version
);
66 printk("bi_r_version\t %s\n", bip
->bi_r_version
);
67 printk("bi_memsize\t 0x%8.8x\t %dMBytes\n", bip
->bi_memsize
,
68 bip
->bi_memsize
/ (1024 * 1000));
69 for (i
= 0; i
< EMAC_NUMS
; i
++) {
70 printk("bi_enetaddr %d\t %2.2x%2.2x%2.2x-%2.2x%2.2x%2.2x\n", i
,
71 bip
->bi_enetaddr
[i
][0], bip
->bi_enetaddr
[i
][1],
72 bip
->bi_enetaddr
[i
][2], bip
->bi_enetaddr
[i
][3],
73 bip
->bi_enetaddr
[i
][4], bip
->bi_enetaddr
[i
][5]);
75 printk("bi_pci_enetaddr %d\t %2.2x%2.2x%2.2x-%2.2x%2.2x%2.2x\n", 0,
76 bip
->bi_pci_enetaddr
[0], bip
->bi_pci_enetaddr
[1],
77 bip
->bi_pci_enetaddr
[2], bip
->bi_pci_enetaddr
[3],
78 bip
->bi_pci_enetaddr
[4], bip
->bi_pci_enetaddr
[5]);
80 printk("bi_intfreq\t 0x%8.8x\t clock:\t %dMhz\n",
81 bip
->bi_intfreq
, bip
->bi_intfreq
/ 1000000);
83 printk("bi_busfreq\t 0x%8.8x\t plb bus clock:\t %dMHz\n",
84 bip
->bi_busfreq
, bip
->bi_busfreq
/ 1000000);
85 printk("bi_pci_busfreq\t 0x%8.8x\t pci bus clock:\t %dMHz\n",
86 bip
->bi_pci_busfreq
, bip
->bi_pci_busfreq
/ 1000000);
90 /* RTC step for ash */
91 ash_rtc_base
= (void *) ASH_RTC_VADDR
;
92 TODC_INIT(TODC_TYPE_DS1743
, ash_rtc_base
, ash_rtc_base
, ash_rtc_base
,
97 bios_fixup(struct pci_controller
*hose
, struct pcil0_regs
*pcip
)
100 unsigned int bar_response
, bar
;
102 * Expected PCI mapping:
104 * PLB addr PCI memory addr
105 * --------------------- ---------------------
106 * 0000'0000 - 7fff'ffff <--- 0000'0000 - 7fff'ffff
107 * 8000'0000 - Bfff'ffff ---> 8000'0000 - Bfff'ffff
109 * PLB addr PCI io addr
110 * --------------------- ---------------------
111 * e800'0000 - e800'ffff ---> 0000'0000 - 0001'0000
113 * The following code is simplified by assuming that the bootrom
114 * has been well behaved in following this mapping.
120 printk("ioremap PCLIO_BASE = 0x%x\n", pcip
);
121 printk("PCI bridge regs before fixup \n");
122 for (i
= 0; i
<= 2; i
++) {
123 printk(" pmm%dma\t0x%x\n", i
, in_le32(&(pcip
->pmm
[i
].ma
)));
124 printk(" pmm%dla\t0x%x\n", i
, in_le32(&(pcip
->pmm
[i
].la
)));
125 printk(" pmm%dpcila\t0x%x\n", i
,
126 in_le32(&(pcip
->pmm
[i
].pcila
)));
127 printk(" pmm%dpciha\t0x%x\n", i
,
128 in_le32(&(pcip
->pmm
[i
].pciha
)));
130 printk(" ptm1ms\t0x%x\n", in_le32(&(pcip
->ptm1ms
)));
131 printk(" ptm1la\t0x%x\n", in_le32(&(pcip
->ptm1la
)));
132 printk(" ptm2ms\t0x%x\n", in_le32(&(pcip
->ptm2ms
)));
133 printk(" ptm2la\t0x%x\n", in_le32(&(pcip
->ptm2la
)));
134 for (bar
= PCI_BASE_ADDRESS_1
; bar
<= PCI_BASE_ADDRESS_2
; bar
+= 4) {
135 early_read_config_dword(hose
, hose
->first_busno
,
136 PCI_FUNC(hose
->first_busno
), bar
,
138 DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
139 hose
->first_busno
, PCI_SLOT(hose
->first_busno
),
140 PCI_FUNC(hose
->first_busno
), bar
, bar_response
);
145 ppc_md
.progress("bios_fixup(): enter", 0x800);
147 /* added for IBM boot rom version 1.15 bios bar changes -AK */
149 /* Disable region first */
150 out_le32((void *) &(pcip
->pmm
[0].ma
), 0x00000000);
151 /* PLB starting addr, PCI: 0x80000000 */
152 out_le32((void *) &(pcip
->pmm
[0].la
), 0x80000000);
153 /* PCI start addr, 0x80000000 */
154 out_le32((void *) &(pcip
->pmm
[0].pcila
), PPC405_PCI_MEM_BASE
);
155 /* 512MB range of PLB to PCI */
156 out_le32((void *) &(pcip
->pmm
[0].pciha
), 0x00000000);
157 /* Enable no pre-fetch, enable region */
158 out_le32((void *) &(pcip
->pmm
[0].ma
), ((0xffffffff -
159 (PPC405_PCI_UPPER_MEM
-
160 PPC405_PCI_MEM_BASE
)) | 0x01));
162 /* Disable region one */
163 out_le32((void *) &(pcip
->pmm
[1].ma
), 0x00000000);
164 out_le32((void *) &(pcip
->pmm
[1].la
), 0x00000000);
165 out_le32((void *) &(pcip
->pmm
[1].pcila
), 0x00000000);
166 out_le32((void *) &(pcip
->pmm
[1].pciha
), 0x00000000);
167 out_le32((void *) &(pcip
->pmm
[1].ma
), 0x00000000);
169 /* Disable region two */
170 out_le32((void *) &(pcip
->pmm
[2].ma
), 0x00000000);
171 out_le32((void *) &(pcip
->pmm
[2].la
), 0x00000000);
172 out_le32((void *) &(pcip
->pmm
[2].pcila
), 0x00000000);
173 out_le32((void *) &(pcip
->pmm
[2].pciha
), 0x00000000);
174 out_le32((void *) &(pcip
->pmm
[2].ma
), 0x00000000);
176 /* Enable PTM1 and PTM2, mapped to PLB address 0. */
178 out_le32((void *) &(pcip
->ptm1la
), 0x00000000);
179 out_le32((void *) &(pcip
->ptm1ms
), 0x00000001);
180 out_le32((void *) &(pcip
->ptm2la
), 0x00000000);
181 out_le32((void *) &(pcip
->ptm2ms
), 0x00000001);
183 /* Write zero to PTM1 BAR. */
185 early_write_config_dword(hose
, hose
->first_busno
,
186 PCI_FUNC(hose
->first_busno
),
190 /* Disable PTM2 (unused) */
192 out_le32((void *) &(pcip
->ptm2la
), 0x00000000);
193 out_le32((void *) &(pcip
->ptm2ms
), 0x00000000);
195 /* end work arround */
197 ppc_md
.progress("bios_fixup(): done", 0x800);
200 printk("PCI bridge regs after fixup \n");
201 for (i
= 0; i
<= 2; i
++) {
202 printk(" pmm%dma\t0x%x\n", i
, in_le32(&(pcip
->pmm
[i
].ma
)));
203 printk(" pmm%dla\t0x%x\n", i
, in_le32(&(pcip
->pmm
[i
].la
)));
204 printk(" pmm%dpcila\t0x%x\n", i
,
205 in_le32(&(pcip
->pmm
[i
].pcila
)));
206 printk(" pmm%dpciha\t0x%x\n", i
,
207 in_le32(&(pcip
->pmm
[i
].pciha
)));
209 printk(" ptm1ms\t0x%x\n", in_le32(&(pcip
->ptm1ms
)));
210 printk(" ptm1la\t0x%x\n", in_le32(&(pcip
->ptm1la
)));
211 printk(" ptm2ms\t0x%x\n", in_le32(&(pcip
->ptm2ms
)));
212 printk(" ptm2la\t0x%x\n", in_le32(&(pcip
->ptm2la
)));
214 for (bar
= PCI_BASE_ADDRESS_1
; bar
<= PCI_BASE_ADDRESS_2
; bar
+= 4) {
215 early_read_config_dword(hose
, hose
->first_busno
,
216 PCI_FUNC(hose
->first_busno
), bar
,
218 DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
219 hose
->first_busno
, PCI_SLOT(hose
->first_busno
),
220 PCI_FUNC(hose
->first_busno
), bar
, bar_response
);
231 io_block_mapping(ASH_RTC_VADDR
, ASH_RTC_PADDR
, ASH_RTC_SIZE
, _PAGE_IO
);
235 platform_init(unsigned long r3
, unsigned long r4
, unsigned long r5
,
236 unsigned long r6
, unsigned long r7
)
238 ppc4xx_init(r3
, r4
, r5
, r6
, r7
);
240 ppc_md
.setup_arch
= ash_setup_arch
;
241 ppc_md
.setup_io_mappings
= ash_map_io
;
243 #ifdef CONFIG_PPC_RTC
244 ppc_md
.time_init
= todc_time_init
;
245 ppc_md
.set_rtc_time
= todc_set_rtc_time
;
246 ppc_md
.get_rtc_time
= todc_get_rtc_time
;
247 ppc_md
.nvram_read_val
= todc_direct_read_val
;
248 ppc_md
.nvram_write_val
= todc_direct_write_val
;