arch/ppc/boot/simple/gt64260_tty.c

   1 /*
   2  * arch/ppc/boot/simple/gt64260_tty.c
   3  *
   4  * Bootloader version of the embedded MPSC/UART driver for the GT64260[A].
   5  * Note: Due to 64260A errata, DMA will be used for UART input (via SDMA).
   6  *
   7  * Author: Mark A. Greer <mgreer@mvista.com>
   8  *
   9  * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
  10  * the terms of the GNU General Public License version 2.1.  This program
  11  * is licensed "as is" without any warranty of any kind, whether express
  12  * or implied.
  13  */
  14
  15 /* This code assumes that the data cache has been disabled (L1, L2, L3). */
  16
  17 #include <linux/config.h>
  18 #include <linux/serialP.h>
  19 #include <linux/serial_reg.h>
  20 #include <asm/serial.h>
  21 #include <asm/gt64260_defs.h>
  22
  23 extern void udelay(long);
  24 static void stop_dma(int chan);
  25
  26 static u32      gt64260_base = EV64260_BRIDGE_REG_BASE; /* base addr of 64260 */
  27
  28 inline unsigned
  29 gt64260_in_le32(volatile unsigned *addr)
  30 {
  31         unsigned ret;
  32
  33         __asm__ __volatile__("lwbrx %0,0,%1; eieio" : "=r" (ret) :
  34                                      "r" (addr), "m" (*addr));
  35         return ret;
  36 }
  37
  38 inline void
  39 gt64260_out_le32(volatile unsigned *addr, int val)
  40 {
  41         __asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) :
  42                                      "r" (val), "r" (addr));
  43 }
  44
  45 #define GT64260_REG_READ(offs)                                          \
  46         (gt64260_in_le32((volatile uint *)(gt64260_base + (offs))))
  47 #define GT64260_REG_WRITE(offs, d)                                      \
  48         (gt64260_out_le32((volatile uint *)(gt64260_base + (offs)), (int)(d)))
  49
  50
  51 static struct {
  52         u32     sdc;
  53         u32     sdcm;
  54         u32     rx_desc;
  55         u32     rx_buf_ptr;
  56         u32     scrdp;
  57         u32     tx_desc;
  58         u32     sctdp;
  59         u32     sftdp;
  60 } sdma_regs;
  61
  62 #define SDMA_REGS_INIT(chan) {                                          \
  63         sdma_regs.sdc        = GT64260_SDMA_##chan##_SDC;               \
  64         sdma_regs.sdcm       = GT64260_SDMA_##chan##_SDCM;              \
  65         sdma_regs.rx_desc    = GT64260_SDMA_##chan##_RX_DESC;           \
  66         sdma_regs.rx_buf_ptr = GT64260_SDMA_##chan##_RX_BUF_PTR;        \
  67         sdma_regs.scrdp      = GT64260_SDMA_##chan##_SCRDP;             \
  68         sdma_regs.tx_desc    = GT64260_SDMA_##chan##_TX_DESC;           \
  69         sdma_regs.sctdp      = GT64260_SDMA_##chan##_SCTDP;             \
  70         sdma_regs.sftdp      = GT64260_SDMA_##chan##_SFTDP;             \
  71 }
  72
  73 typedef struct {
  74         volatile u16 bufsize;
  75         volatile u16 bytecnt;
  76         volatile u32 cmd_stat;
  77         volatile u32 next_desc_ptr;
  78         volatile u32 buffer;
  79 } gt64260_rx_desc_t;
  80
  81 typedef struct {
  82         volatile u16 bytecnt;
  83         volatile u16 shadow;
  84         volatile u32 cmd_stat;
  85         volatile u32 next_desc_ptr;
  86         volatile u32 buffer;
  87 } gt64260_tx_desc_t;
  88
  89 #define MAX_RESET_WAIT  10000
  90 #define MAX_TX_WAIT     10000
  91
  92 #define RX_NUM_DESC     2
  93 #define TX_NUM_DESC     2
  94
  95 #define RX_BUF_SIZE     16
  96 #define TX_BUF_SIZE     16
  97
  98 static gt64260_rx_desc_t rd[RX_NUM_DESC] __attribute__ ((aligned(32)));
  99 static gt64260_tx_desc_t td[TX_NUM_DESC] __attribute__ ((aligned(32)));
 100
 101 static char rx_buf[RX_NUM_DESC * RX_BUF_SIZE] __attribute__ ((aligned(32)));
 102 static char tx_buf[TX_NUM_DESC * TX_BUF_SIZE] __attribute__ ((aligned(32)));
 103
 104 static int cur_rd = 0;
 105 static int cur_td = 0;
 106
 107
 108 #define RX_INIT_RDP(rdp) {                                              \
 109         (rdp)->bufsize = 2;                                             \
 110         (rdp)->bytecnt = 0;                                             \
 111         (rdp)->cmd_stat = GT64260_SDMA_DESC_CMDSTAT_L |                 \
 112                           GT64260_SDMA_DESC_CMDSTAT_F |                 \
 113                           GT64260_SDMA_DESC_CMDSTAT_O;                  \
 114 }
 115
 116 unsigned long
 117 serial_init(int chan, void *ignored)
 118 {
 119         u32     mpsc_adjust, sdma_adjust, brg_bcr;
 120         int     i;
 121
 122         stop_dma(0);
 123         stop_dma(1);
 124
 125         if (chan != 1) {
 126                 chan = 0;  /* default to chan 0 if anything but 1 */
 127                 mpsc_adjust = 0;
 128                 sdma_adjust = 0;
 129                 brg_bcr = GT64260_BRG_0_BCR;
 130                 SDMA_REGS_INIT(0);
 131         }
 132         else {
 133                 mpsc_adjust = 0x1000;
 134                 sdma_adjust = 0x2000;
 135                 brg_bcr = GT64260_BRG_1_BCR;
 136                 SDMA_REGS_INIT(1);
 137         }
 138
 139         /* Set up ring buffers */
 140         for (i=0; i<RX_NUM_DESC; i++) {
 141                 RX_INIT_RDP(&rd[i]);
 142                 rd[i].buffer = (u32)&rx_buf[i * RX_BUF_SIZE];
 143                 rd[i].next_desc_ptr = (u32)&rd[i+1];
 144         }
 145         rd[RX_NUM_DESC - 1].next_desc_ptr = (u32)&rd[0];
 146
 147         for (i=0; i<TX_NUM_DESC; i++) {
 148                 td[i].bytecnt = 0;
 149                 td[i].shadow = 0;
 150                 td[i].buffer = (u32)&tx_buf[i * TX_BUF_SIZE];
 151                 td[i].cmd_stat = GT64260_SDMA_DESC_CMDSTAT_F |
 152                                  GT64260_SDMA_DESC_CMDSTAT_L;
 153                 td[i].next_desc_ptr = (u32)&td[i+1];
 154         }
 155         td[TX_NUM_DESC - 1].next_desc_ptr = (u32)&td[0];
 156
 157         /* Set MPSC Routing */
 158         GT64260_REG_WRITE(GT64260_MPSC_MRR, 0x3ffffe38);
 159         GT64260_REG_WRITE(GT64260_MPP_SERIAL_PORTS_MULTIPLEX, 0x00001102);
 160
 161         /* MPSC 0/1 Rx & Tx get clocks BRG0/1 */
 162         GT64260_REG_WRITE(GT64260_MPSC_RCRR, 0x00000100);
 163         GT64260_REG_WRITE(GT64260_MPSC_TCRR, 0x00000100);
 164
 165         /* clear pending interrupts */
 166         GT64260_REG_WRITE(GT64260_SDMA_INTR_MASK, 0);
 167
 168         GT64260_REG_WRITE(GT64260_SDMA_0_SCRDP + sdma_adjust, &rd[0]);
 169         GT64260_REG_WRITE(GT64260_SDMA_0_SCTDP + sdma_adjust,
 170                 &td[TX_NUM_DESC - 1]);
 171         GT64260_REG_WRITE(GT64260_SDMA_0_SFTDP + sdma_adjust,
 172                 &td[TX_NUM_DESC - 1]);
 173
 174         GT64260_REG_WRITE(GT64260_SDMA_0_SDC + sdma_adjust,
 175                           GT64260_SDMA_SDC_RFT | GT64260_SDMA_SDC_SFM |
 176                           GT64260_SDMA_SDC_BLMR | GT64260_SDMA_SDC_BLMT |
 177                           (3 << 12));
 178
 179         /* Set BRG to generate proper baud rate */
 180         GT64260_REG_WRITE(brg_bcr, ((8 << 18) | (1 << 16) | 36));
 181
 182         /* Put MPSC into UART mode, no null modem, 16x clock mode */
 183         GT64260_REG_WRITE(GT64260_MPSC_0_MMCRL + mpsc_adjust, 0x000004c4);
 184         GT64260_REG_WRITE(GT64260_MPSC_0_MMCRH + mpsc_adjust, 0x04400400);
 185
 186         GT64260_REG_WRITE(GT64260_MPSC_0_CHR_1 + mpsc_adjust, 0);
 187         GT64260_REG_WRITE(GT64260_MPSC_0_CHR_9 + mpsc_adjust, 0);
 188         GT64260_REG_WRITE(GT64260_MPSC_0_CHR_10 + mpsc_adjust, 0);
 189         GT64260_REG_WRITE(GT64260_MPSC_0_CHR_3 + mpsc_adjust, 4);
 190         GT64260_REG_WRITE(GT64260_MPSC_0_CHR_4 + mpsc_adjust, 0);
 191         GT64260_REG_WRITE(GT64260_MPSC_0_CHR_5 + mpsc_adjust, 0);
 192         GT64260_REG_WRITE(GT64260_MPSC_0_CHR_6 + mpsc_adjust, 0);
 193         GT64260_REG_WRITE(GT64260_MPSC_0_CHR_7 + mpsc_adjust, 0);
 194         GT64260_REG_WRITE(GT64260_MPSC_0_CHR_8 + mpsc_adjust, 0);
 195
 196         /* 8 data bits, 1 stop bit */
 197         GT64260_REG_WRITE(GT64260_MPSC_0_MPCR + mpsc_adjust, (3 << 12));
 198
 199         GT64260_REG_WRITE(GT64260_SDMA_0_SDCM + sdma_adjust,
 200                 GT64260_SDMA_SDCM_ERD);
 201
 202         GT64260_REG_WRITE(GT64260_MPSC_0_CHR_2 + sdma_adjust,
 203                 GT64260_MPSC_UART_CR_EH);
 204
 205         udelay(100);
 206
 207         return (ulong)chan;
 208 }
 209
 210 static void
 211 stop_dma(int chan)
 212 {
 213         u32     sdma_sdcm = GT64260_SDMA_0_SDCM;
 214         int     i;
 215
 216         if (chan == 1) {
 217                 sdma_sdcm = GT64260_SDMA_1_SDCM;
 218         }
 219
 220         /* Abort SDMA Rx, Tx */
 221         GT64260_REG_WRITE(sdma_sdcm,
 222                 GT64260_SDMA_SDCM_AR | GT64260_SDMA_SDCM_STD);
 223
 224         for (i=0; i<MAX_RESET_WAIT; i++) {
 225                 if ((GT64260_REG_READ(sdma_sdcm) & (GT64260_SDMA_SDCM_AR |
 226                                         GT64260_SDMA_SDCM_AT)) == 0) break;
 227                 udelay(100);
 228         }
 229
 230         return;
 231 }
 232
 233 static int
 234 wait_for_ownership(void)
 235 {
 236         int     i;
 237
 238         for (i=0; i<MAX_TX_WAIT; i++) {
 239                 if ((GT64260_REG_READ(sdma_regs.sdcm) &
 240                                         GT64260_SDMA_SDCM_TXD) == 0) break;
 241                 udelay(1000);
 242         }
 243
 244         return (i < MAX_TX_WAIT);
 245 }
 246
 247 void
 248 serial_putc(unsigned long com_port, unsigned char c)
 249 {
 250         gt64260_tx_desc_t       *tdp;
 251
 252         if (wait_for_ownership() == 0) return;
 253
 254         tdp = &td[cur_td];
 255         if (++cur_td >= TX_NUM_DESC) cur_td = 0;
 256
 257         *(unchar *)(tdp->buffer ^ 7) = c;
 258         tdp->bytecnt = 1;
 259         tdp->shadow = 1;
 260         tdp->cmd_stat = GT64260_SDMA_DESC_CMDSTAT_L |
 261                 GT64260_SDMA_DESC_CMDSTAT_F | GT64260_SDMA_DESC_CMDSTAT_O;
 262
 263         GT64260_REG_WRITE(sdma_regs.sctdp, tdp);
 264         GT64260_REG_WRITE(sdma_regs.sftdp, tdp);
 265         GT64260_REG_WRITE(sdma_regs.sdcm,
 266                 GT64260_REG_READ(sdma_regs.sdcm) | GT64260_SDMA_SDCM_TXD);
 267
 268         return;
 269 }
 270
 271 unsigned char
 272 serial_getc(unsigned long com_port)
 273 {
 274         gt64260_rx_desc_t       *rdp;
 275         unchar                  c = '\0';
 276
 277         rdp = &rd[cur_rd];
 278
 279         if ((rdp->cmd_stat & (GT64260_SDMA_DESC_CMDSTAT_O |
 280                               GT64260_SDMA_DESC_CMDSTAT_ES)) == 0) {
 281                 c = *(unchar *)(rdp->buffer ^ 7);
 282                 RX_INIT_RDP(rdp);
 283                 if (++cur_rd >= RX_NUM_DESC) cur_rd = 0;
 284         }
 285
 286         return c;
 287 }
 288
 289 int
 290 serial_tstc(unsigned long com_port)
 291 {
 292         gt64260_rx_desc_t       *rdp;
 293         int                     loop_count = 0;
 294         int                     rc = 0;
 295
 296         rdp = &rd[cur_rd];
 297
 298         /* Go thru rcv desc's until empty looking for one with data (no error)*/
 299         while (((rdp->cmd_stat & GT64260_SDMA_DESC_CMDSTAT_O) == 0) &&
 300                (loop_count++ < RX_NUM_DESC)) {
 301
 302                 /* If there was an error, reinit the desc & continue */
 303                 if ((rdp->cmd_stat & GT64260_SDMA_DESC_CMDSTAT_ES) != 0) {
 304                         RX_INIT_RDP(rdp);
 305                         if (++cur_rd >= RX_NUM_DESC) cur_rd = 0;
 306                         rdp = (gt64260_rx_desc_t *)rdp->next_desc_ptr;
 307                 }
 308                 else {
 309                         rc = 1;
 310                         break;
 311                 }
 312         }
 313
 314         return rc;
 315 }
 316
 317 void
 318 serial_close(unsigned long com_port)
 319 {
 320         stop_dma(com_port);
 321         return;
 322 }