2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/irq.h>
25 #include <linux/interrupt.h>
26 #include <linux/init.h>
27 #include <linux/delay.h>
28 #include <linux/sched.h>
29 #include <linux/config.h>
30 #include <linux/smp_lock.h>
31 #include <linux/mc146818rtc.h>
32 #include <linux/compiler.h>
33 #include <linux/acpi.h>
39 #include <mach_apic.h>
41 #undef APIC_LOCKUP_DEBUG
43 #define APIC_LOCKUP_DEBUG
45 static spinlock_t ioapic_lock
= SPIN_LOCK_UNLOCKED
;
48 * Is the SiS APIC rmw bug present ?
49 * -1 = dont know, 0 = no, 1 = yes
51 int sis_apic_bug
= -1;
54 * # of IRQ routing registers
56 int nr_ioapic_registers
[MAX_IO_APICS
];
59 * Rough estimation of how many shared IRQs there are, can
62 #define MAX_PLUS_SHARED_IRQS NR_IRQS
63 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
66 * This is performance-critical, we want to do it O(1)
68 * the indexing order of this array favors 1:1 mappings
69 * between pins and IRQs.
72 static struct irq_pin_list
{
74 } irq_2_pin
[PIN_MAP_SIZE
];
77 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
78 * shared ISA-space IRQs, so we have to support them. We are super
79 * fast in the common case, and fast for shared ISA-space IRQs.
81 static void __init
add_pin_to_irq(unsigned int irq
, int apic
, int pin
)
83 static int first_free_entry
= NR_IRQS
;
84 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
87 entry
= irq_2_pin
+ entry
->next
;
89 if (entry
->pin
!= -1) {
90 entry
->next
= first_free_entry
;
91 entry
= irq_2_pin
+ entry
->next
;
92 if (++first_free_entry
>= PIN_MAP_SIZE
)
93 panic("io_apic.c: whoops");
100 * Reroute an IRQ to a different pin.
102 static void __init
replace_pin_at_irq(unsigned int irq
,
103 int oldapic
, int oldpin
,
104 int newapic
, int newpin
)
106 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
109 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
110 entry
->apic
= newapic
;
115 entry
= irq_2_pin
+ entry
->next
;
119 #define __DO_ACTION(R, ACTION, FINAL) \
123 struct irq_pin_list *entry = irq_2_pin + irq; \
130 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
132 io_apic_modify(entry->apic, 0x10 + R + pin*2, reg); \
135 entry = irq_2_pin + entry->next; \
140 #define DO_ACTION(name,R,ACTION, FINAL) \
142 static void name##_IO_APIC_irq (unsigned int irq) \
143 __DO_ACTION(R, ACTION, FINAL)
145 DO_ACTION( __mask
, 0, |= 0x00010000, io_apic_sync(entry
->apic
) )
147 DO_ACTION( __unmask
, 0, &= 0xfffeffff, )
149 DO_ACTION( __mask_and_edge
, 0, = (reg
& 0xffff7fff) | 0x00010000, )
150 /* mask = 1, trigger = 0 */
151 DO_ACTION( __unmask_and_level
, 0, = (reg
& 0xfffeffff) | 0x00008000, )
152 /* mask = 0, trigger = 1 */
154 static void mask_IO_APIC_irq (unsigned int irq
)
158 spin_lock_irqsave(&ioapic_lock
, flags
);
159 __mask_IO_APIC_irq(irq
);
160 spin_unlock_irqrestore(&ioapic_lock
, flags
);
163 static void unmask_IO_APIC_irq (unsigned int irq
)
167 spin_lock_irqsave(&ioapic_lock
, flags
);
168 __unmask_IO_APIC_irq(irq
);
169 spin_unlock_irqrestore(&ioapic_lock
, flags
);
172 void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
174 struct IO_APIC_route_entry entry
;
178 * Disable it in the IO-APIC irq-routing table:
180 memset(&entry
, 0, sizeof(entry
));
182 spin_lock_irqsave(&ioapic_lock
, flags
);
183 io_apic_write(apic
, 0x10 + 2 * pin
, *(((int *)&entry
) + 0));
184 io_apic_write(apic
, 0x11 + 2 * pin
, *(((int *)&entry
) + 1));
185 spin_unlock_irqrestore(&ioapic_lock
, flags
);
188 static void clear_IO_APIC (void)
192 for (apic
= 0; apic
< nr_ioapics
; apic
++)
193 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
194 clear_IO_APIC_pin(apic
, pin
);
197 static void set_ioapic_affinity (unsigned int irq
, unsigned long mask
)
202 * Only the first 8 bits are valid.
205 spin_lock_irqsave(&ioapic_lock
, flags
);
206 __DO_ACTION(1, = mask
, )
207 spin_unlock_irqrestore(&ioapic_lock
, flags
);
214 unsigned long timestamp
;
215 } ____cacheline_aligned irq_balance_t
;
217 static irq_balance_t irq_balance
[NR_IRQS
] __cacheline_aligned
218 = { [ 0 ... NR_IRQS
-1 ] = { 0, 0 } };
220 extern unsigned long irq_affinity
[NR_IRQS
];
224 #define IDLE_ENOUGH(cpu,now) \
225 (idle_cpu(cpu) && ((now) - irq_stat[(cpu)].idle_timestamp > 1))
227 #define IRQ_ALLOWED(cpu,allowed_mask) \
228 ((1 << cpu) & (allowed_mask))
232 #define IRQ_BALANCE_INTERVAL (HZ/50)
234 static unsigned long move(int curr_cpu
, unsigned long allowed_mask
, unsigned long now
, int direction
)
242 if (unlikely(cpu
== curr_cpu
))
245 if (direction
== 1) {
254 } while (!cpu_online(cpu
) || !IRQ_ALLOWED(cpu
,allowed_mask
) ||
255 (search_idle
&& !IDLE_ENOUGH(cpu
,now
)));
260 static inline void balance_irq(int irq
)
262 irq_balance_t
*entry
= irq_balance
+ irq
;
263 unsigned long now
= jiffies
;
268 if (unlikely(time_after(now
, entry
->timestamp
+ IRQ_BALANCE_INTERVAL
))) {
269 unsigned long allowed_mask
;
270 unsigned int new_cpu
;
273 rdtscl(random_number
);
276 allowed_mask
= cpu_online_map
& irq_affinity
[irq
];
277 entry
->timestamp
= now
;
278 new_cpu
= move(entry
->cpu
, allowed_mask
, now
, random_number
);
279 if (entry
->cpu
!= new_cpu
) {
280 entry
->cpu
= new_cpu
;
281 set_ioapic_affinity(irq
, cpu_to_logical_apicid(new_cpu
));
286 static inline void balance_irq(int irq
) { }
290 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
291 * specific CPU-side IRQs.
295 int pirq_entries
[MAX_PIRQS
];
297 int skip_ioapic_setup
;
299 static int __init
ioapic_setup(char *str
)
301 skip_ioapic_setup
= 1;
305 __setup("noapic", ioapic_setup
);
307 static int __init
ioapic_pirq_setup(char *str
)
310 int ints
[MAX_PIRQS
+1];
312 get_options(str
, ARRAY_SIZE(ints
), ints
);
314 for (i
= 0; i
< MAX_PIRQS
; i
++)
315 pirq_entries
[i
] = -1;
318 printk(KERN_INFO
"PIRQ redirection, working around broken MP-BIOS.\n");
320 if (ints
[0] < MAX_PIRQS
)
323 for (i
= 0; i
< max
; i
++) {
324 printk(KERN_DEBUG
"... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
326 * PIRQs are mapped upside down, usually.
328 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
333 __setup("pirq=", ioapic_pirq_setup
);
336 * Find the IRQ entry number of a certain pin.
338 static int __init
find_irq_entry(int apic
, int pin
, int type
)
342 for (i
= 0; i
< mp_irq_entries
; i
++)
343 if (mp_irqs
[i
].mpc_irqtype
== type
&&
344 (mp_irqs
[i
].mpc_dstapic
== mp_ioapics
[apic
].mpc_apicid
||
345 mp_irqs
[i
].mpc_dstapic
== MP_APIC_ALL
) &&
346 mp_irqs
[i
].mpc_dstirq
== pin
)
353 * Find the pin to which IRQ[irq] (ISA) is connected
355 static int __init
find_isa_irq_pin(int irq
, int type
)
359 for (i
= 0; i
< mp_irq_entries
; i
++) {
360 int lbus
= mp_irqs
[i
].mpc_srcbus
;
362 if ((mp_bus_id_to_type
[lbus
] == MP_BUS_ISA
||
363 mp_bus_id_to_type
[lbus
] == MP_BUS_EISA
||
364 mp_bus_id_to_type
[lbus
] == MP_BUS_MCA
) &&
365 (mp_irqs
[i
].mpc_irqtype
== type
) &&
366 (mp_irqs
[i
].mpc_srcbusirq
== irq
))
368 return mp_irqs
[i
].mpc_dstirq
;
374 * Find a specific PCI IRQ entry.
375 * Not an __init, possibly needed by modules
377 static int pin_2_irq(int idx
, int apic
, int pin
);
379 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
381 int apic
, i
, best_guess
= -1;
383 Dprintk("querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
385 if (mp_bus_id_to_pci_bus
[bus
] == -1) {
386 printk(KERN_WARNING
"PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
389 for (i
= 0; i
< mp_irq_entries
; i
++) {
390 int lbus
= mp_irqs
[i
].mpc_srcbus
;
392 for (apic
= 0; apic
< nr_ioapics
; apic
++)
393 if (mp_ioapics
[apic
].mpc_apicid
== mp_irqs
[i
].mpc_dstapic
||
394 mp_irqs
[i
].mpc_dstapic
== MP_APIC_ALL
)
397 if ((mp_bus_id_to_type
[lbus
] == MP_BUS_PCI
) &&
398 !mp_irqs
[i
].mpc_irqtype
&&
400 (slot
== ((mp_irqs
[i
].mpc_srcbusirq
>> 2) & 0x1f))) {
401 int irq
= pin_2_irq(i
,apic
,mp_irqs
[i
].mpc_dstirq
);
403 if (!(apic
|| IO_APIC_IRQ(irq
)))
406 if (pin
== (mp_irqs
[i
].mpc_srcbusirq
& 3))
409 * Use the first all-but-pin matching entry as a
410 * best-guess fuzzy result for broken mptables.
420 * EISA Edge/Level control register, ELCR
422 static int __init
EISA_ELCR(unsigned int irq
)
425 unsigned int port
= 0x4d0 + (irq
>> 3);
426 return (inb(port
) >> (irq
& 7)) & 1;
428 printk(KERN_INFO
"Broken MPtable reports ISA irq %d\n", irq
);
432 /* EISA interrupts are always polarity zero and can be edge or level
433 * trigger depending on the ELCR value. If an interrupt is listed as
434 * EISA conforming in the MP table, that means its trigger type must
435 * be read in from the ELCR */
437 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
438 #define default_EISA_polarity(idx) (0)
440 /* ISA interrupts are always polarity zero edge triggered,
441 * when listed as conforming in the MP table. */
443 #define default_ISA_trigger(idx) (0)
444 #define default_ISA_polarity(idx) (0)
446 /* PCI interrupts are always polarity one level triggered,
447 * when listed as conforming in the MP table. */
449 #define default_PCI_trigger(idx) (1)
450 #define default_PCI_polarity(idx) (1)
452 /* MCA interrupts are always polarity zero level triggered,
453 * when listed as conforming in the MP table. */
455 #define default_MCA_trigger(idx) (1)
456 #define default_MCA_polarity(idx) (0)
458 static int __init
MPBIOS_polarity(int idx
)
460 int bus
= mp_irqs
[idx
].mpc_srcbus
;
464 * Determine IRQ line polarity (high active or low active):
466 switch (mp_irqs
[idx
].mpc_irqflag
& 3)
468 case 0: /* conforms, ie. bus-type dependent polarity */
470 switch (mp_bus_id_to_type
[bus
])
472 case MP_BUS_ISA
: /* ISA pin */
474 polarity
= default_ISA_polarity(idx
);
477 case MP_BUS_EISA
: /* EISA pin */
479 polarity
= default_EISA_polarity(idx
);
482 case MP_BUS_PCI
: /* PCI pin */
484 polarity
= default_PCI_polarity(idx
);
487 case MP_BUS_MCA
: /* MCA pin */
489 polarity
= default_MCA_polarity(idx
);
494 printk(KERN_WARNING
"broken BIOS!!\n");
501 case 1: /* high active */
506 case 2: /* reserved */
508 printk(KERN_WARNING
"broken BIOS!!\n");
512 case 3: /* low active */
517 default: /* invalid */
519 printk(KERN_WARNING
"broken BIOS!!\n");
527 static int __init
MPBIOS_trigger(int idx
)
529 int bus
= mp_irqs
[idx
].mpc_srcbus
;
533 * Determine IRQ trigger mode (edge or level sensitive):
535 switch ((mp_irqs
[idx
].mpc_irqflag
>>2) & 3)
537 case 0: /* conforms, ie. bus-type dependent */
539 switch (mp_bus_id_to_type
[bus
])
541 case MP_BUS_ISA
: /* ISA pin */
543 trigger
= default_ISA_trigger(idx
);
546 case MP_BUS_EISA
: /* EISA pin */
548 trigger
= default_EISA_trigger(idx
);
551 case MP_BUS_PCI
: /* PCI pin */
553 trigger
= default_PCI_trigger(idx
);
556 case MP_BUS_MCA
: /* MCA pin */
558 trigger
= default_MCA_trigger(idx
);
563 printk(KERN_WARNING
"broken BIOS!!\n");
575 case 2: /* reserved */
577 printk(KERN_WARNING
"broken BIOS!!\n");
586 default: /* invalid */
588 printk(KERN_WARNING
"broken BIOS!!\n");
596 static inline int irq_polarity(int idx
)
598 return MPBIOS_polarity(idx
);
601 static inline int irq_trigger(int idx
)
603 return MPBIOS_trigger(idx
);
606 static int pin_2_irq(int idx
, int apic
, int pin
)
609 int bus
= mp_irqs
[idx
].mpc_srcbus
;
612 * Debugging check, we are in big trouble if this message pops up!
614 if (mp_irqs
[idx
].mpc_dstirq
!= pin
)
615 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
617 switch (mp_bus_id_to_type
[bus
])
619 case MP_BUS_ISA
: /* ISA pin */
623 irq
= mp_irqs
[idx
].mpc_srcbusirq
;
626 case MP_BUS_PCI
: /* PCI pin */
629 * PCI IRQs are mapped in order
633 irq
+= nr_ioapic_registers
[i
++];
639 printk(KERN_ERR
"unknown bus type %d.\n",bus
);
646 * PCI IRQ command line redirection. Yes, limits are hardcoded.
648 if ((pin
>= 16) && (pin
<= 23)) {
649 if (pirq_entries
[pin
-16] != -1) {
650 if (!pirq_entries
[pin
-16]) {
651 printk(KERN_DEBUG
"disabling PIRQ%d\n", pin
-16);
653 irq
= pirq_entries
[pin
-16];
654 printk(KERN_DEBUG
"using PIRQ%d -> IRQ %d\n",
662 static inline int IO_APIC_irq_trigger(int irq
)
666 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
667 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
668 idx
= find_irq_entry(apic
,pin
,mp_INT
);
669 if ((idx
!= -1) && (irq
== pin_2_irq(idx
,apic
,pin
)))
670 return irq_trigger(idx
);
674 * nonexistent IRQs are edge default
679 int irq_vector
[NR_IRQS
] = { FIRST_DEVICE_VECTOR
, 0 };
681 static int __init
assign_irq_vector(int irq
)
683 static int current_vector
= FIRST_DEVICE_VECTOR
, offset
= 0;
684 if (IO_APIC_VECTOR(irq
) > 0)
685 return IO_APIC_VECTOR(irq
);
688 if (current_vector
== SYSCALL_VECTOR
)
691 if (current_vector
> FIRST_SYSTEM_VECTOR
) {
693 current_vector
= FIRST_DEVICE_VECTOR
+ offset
;
696 if (current_vector
== FIRST_SYSTEM_VECTOR
)
697 panic("ran out of interrupt sources!");
699 IO_APIC_VECTOR(irq
) = current_vector
;
700 return current_vector
;
703 static struct hw_interrupt_type ioapic_level_irq_type
;
704 static struct hw_interrupt_type ioapic_edge_irq_type
;
706 void __init
setup_IO_APIC_irqs(void)
708 struct IO_APIC_route_entry entry
;
709 int apic
, pin
, idx
, irq
, first_notcon
= 1, vector
;
712 printk(KERN_DEBUG
"init IO_APIC IRQs\n");
714 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
715 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
718 * add it to the IO-APIC irq-routing table:
720 memset(&entry
,0,sizeof(entry
));
722 entry
.delivery_mode
= INT_DELIVERY_MODE
;
723 entry
.dest_mode
= INT_DEST_MODE
;
724 entry
.mask
= 0; /* enable IRQ */
725 entry
.dest
.logical
.logical_dest
= TARGET_CPUS
;
727 idx
= find_irq_entry(apic
,pin
,mp_INT
);
730 printk(KERN_DEBUG
" IO-APIC (apicid-pin) %d-%d", mp_ioapics
[apic
].mpc_apicid
, pin
);
733 printk(", %d-%d", mp_ioapics
[apic
].mpc_apicid
, pin
);
737 entry
.trigger
= irq_trigger(idx
);
738 entry
.polarity
= irq_polarity(idx
);
740 if (irq_trigger(idx
)) {
745 irq
= pin_2_irq(idx
, apic
, pin
);
747 * skip adding the timer int on secondary nodes, which causes
748 * a small but painful rift in the time-space continuum
750 if (multi_timer_check(apic
, irq
))
753 add_pin_to_irq(irq
, apic
, pin
);
755 if (!apic
&& !IO_APIC_IRQ(irq
))
758 if (IO_APIC_IRQ(irq
)) {
759 vector
= assign_irq_vector(irq
);
760 entry
.vector
= vector
;
762 if (IO_APIC_irq_trigger(irq
))
763 irq_desc
[irq
].handler
= &ioapic_level_irq_type
;
765 irq_desc
[irq
].handler
= &ioapic_edge_irq_type
;
767 set_intr_gate(vector
, interrupt
[irq
]);
769 if (!apic
&& (irq
< 16))
770 disable_8259A_irq(irq
);
772 spin_lock_irqsave(&ioapic_lock
, flags
);
773 io_apic_write(apic
, 0x11+2*pin
, *(((int *)&entry
)+1));
774 io_apic_write(apic
, 0x10+2*pin
, *(((int *)&entry
)+0));
775 spin_unlock_irqrestore(&ioapic_lock
, flags
);
780 printk(" not connected.\n");
784 * Set up the 8259A-master output pin:
786 void __init
setup_ExtINT_IRQ0_pin(unsigned int pin
, int vector
)
788 struct IO_APIC_route_entry entry
;
791 memset(&entry
,0,sizeof(entry
));
793 disable_8259A_irq(0);
796 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
799 * We use logical delivery to get the timer IRQ
802 entry
.dest_mode
= INT_DEST_MODE
;
803 entry
.mask
= 0; /* unmask IRQ now */
804 entry
.dest
.logical
.logical_dest
= TARGET_CPUS
;
805 entry
.delivery_mode
= INT_DELIVERY_MODE
;
808 entry
.vector
= vector
;
811 * The timer IRQ doesn't have to know that behind the
812 * scene we have a 8259A-master in AEOI mode ...
814 irq_desc
[0].handler
= &ioapic_edge_irq_type
;
817 * Add it to the IO-APIC irq-routing table:
819 spin_lock_irqsave(&ioapic_lock
, flags
);
820 io_apic_write(0, 0x11+2*pin
, *(((int *)&entry
)+1));
821 io_apic_write(0, 0x10+2*pin
, *(((int *)&entry
)+0));
822 spin_unlock_irqrestore(&ioapic_lock
, flags
);
827 void __init
UNEXPECTED_IO_APIC(void)
829 printk(KERN_WARNING
" WARNING: unexpected IO-APIC, please mail\n");
830 printk(KERN_WARNING
" to linux-smp@vger.kernel.org\n");
833 void __init
print_IO_APIC(void)
836 struct IO_APIC_reg_00 reg_00
;
837 struct IO_APIC_reg_01 reg_01
;
838 struct IO_APIC_reg_02 reg_02
;
841 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
842 for (i
= 0; i
< nr_ioapics
; i
++)
843 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
844 mp_ioapics
[i
].mpc_apicid
, nr_ioapic_registers
[i
]);
847 * We are a bit conservative about what we expect. We have to
848 * know about every hardware change ASAP.
850 printk(KERN_INFO
"testing the IO APIC.......................\n");
852 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
854 spin_lock_irqsave(&ioapic_lock
, flags
);
855 *(int *)®_00
= io_apic_read(apic
, 0);
856 *(int *)®_01
= io_apic_read(apic
, 1);
857 if (reg_01
.version
>= 0x10)
858 *(int *)®_02
= io_apic_read(apic
, 2);
859 spin_unlock_irqrestore(&ioapic_lock
, flags
);
862 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].mpc_apicid
);
863 printk(KERN_DEBUG
".... register #00: %08X\n", *(int *)®_00
);
864 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.ID
);
865 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.delivery_type
);
866 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.LTS
);
867 if (reg_00
.__reserved_0
|| reg_00
.__reserved_1
|| reg_00
.__reserved_2
)
868 UNEXPECTED_IO_APIC();
870 printk(KERN_DEBUG
".... register #01: %08X\n", *(int *)®_01
);
871 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.entries
);
872 if ( (reg_01
.entries
!= 0x0f) && /* older (Neptune) boards */
873 (reg_01
.entries
!= 0x17) && /* typical ISA+PCI boards */
874 (reg_01
.entries
!= 0x1b) && /* Compaq Proliant boards */
875 (reg_01
.entries
!= 0x1f) && /* dual Xeon boards */
876 (reg_01
.entries
!= 0x22) && /* bigger Xeon boards */
877 (reg_01
.entries
!= 0x2E) &&
878 (reg_01
.entries
!= 0x3F)
880 UNEXPECTED_IO_APIC();
882 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.PRQ
);
883 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.version
);
884 if ( (reg_01
.version
!= 0x01) && /* 82489DX IO-APICs */
885 (reg_01
.version
!= 0x10) && /* oldest IO-APICs */
886 (reg_01
.version
!= 0x11) && /* Pentium/Pro IO-APICs */
887 (reg_01
.version
!= 0x13) && /* Xeon IO-APICs */
888 (reg_01
.version
!= 0x20) /* Intel P64H (82806 AA) */
890 UNEXPECTED_IO_APIC();
891 if (reg_01
.__reserved_1
|| reg_01
.__reserved_2
)
892 UNEXPECTED_IO_APIC();
894 if (reg_01
.version
>= 0x10) {
895 printk(KERN_DEBUG
".... register #02: %08X\n", *(int *)®_02
);
896 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.arbitration
);
897 if (reg_02
.__reserved_1
|| reg_02
.__reserved_2
)
898 UNEXPECTED_IO_APIC();
901 printk(KERN_DEBUG
".... IRQ redirection table:\n");
903 printk(KERN_DEBUG
" NR Log Phy Mask Trig IRR Pol"
904 " Stat Dest Deli Vect: \n");
906 for (i
= 0; i
<= reg_01
.entries
; i
++) {
907 struct IO_APIC_route_entry entry
;
909 spin_lock_irqsave(&ioapic_lock
, flags
);
910 *(((int *)&entry
)+0) = io_apic_read(apic
, 0x10+i
*2);
911 *(((int *)&entry
)+1) = io_apic_read(apic
, 0x11+i
*2);
912 spin_unlock_irqrestore(&ioapic_lock
, flags
);
914 printk(KERN_DEBUG
" %02x %03X %02X ",
916 entry
.dest
.logical
.logical_dest
,
917 entry
.dest
.physical
.physical_dest
920 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
925 entry
.delivery_status
,
932 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
933 for (i
= 0; i
< NR_IRQS
; i
++) {
934 struct irq_pin_list
*entry
= irq_2_pin
+ i
;
937 printk(KERN_DEBUG
"IRQ%d ", i
);
939 printk("-> %d:%d", entry
->apic
, entry
->pin
);
942 entry
= irq_2_pin
+ entry
->next
;
947 printk(KERN_INFO
".................................... done.\n");
952 static void print_APIC_bitfield (int base
)
957 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
958 for (i
= 0; i
< 8; i
++) {
959 v
= apic_read(base
+ i
*0x10);
960 for (j
= 0; j
< 32; j
++) {
970 void /*__init*/ print_local_APIC(void * dummy
)
972 unsigned int v
, ver
, maxlvt
;
974 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
975 smp_processor_id(), hard_smp_processor_id());
976 v
= apic_read(APIC_ID
);
977 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, GET_APIC_ID(v
));
978 v
= apic_read(APIC_LVR
);
979 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
980 ver
= GET_APIC_VERSION(v
);
981 maxlvt
= get_maxlvt();
983 v
= apic_read(APIC_TASKPRI
);
984 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
986 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
987 v
= apic_read(APIC_ARBPRI
);
988 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
989 v
& APIC_ARBPRI_MASK
);
990 v
= apic_read(APIC_PROCPRI
);
991 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
994 v
= apic_read(APIC_EOI
);
995 printk(KERN_DEBUG
"... APIC EOI: %08x\n", v
);
996 v
= apic_read(APIC_RRR
);
997 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
998 v
= apic_read(APIC_LDR
);
999 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1000 v
= apic_read(APIC_DFR
);
1001 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1002 v
= apic_read(APIC_SPIV
);
1003 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1005 printk(KERN_DEBUG
"... APIC ISR field:\n");
1006 print_APIC_bitfield(APIC_ISR
);
1007 printk(KERN_DEBUG
"... APIC TMR field:\n");
1008 print_APIC_bitfield(APIC_TMR
);
1009 printk(KERN_DEBUG
"... APIC IRR field:\n");
1010 print_APIC_bitfield(APIC_IRR
);
1012 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1013 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1014 apic_write(APIC_ESR
, 0);
1015 v
= apic_read(APIC_ESR
);
1016 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1019 v
= apic_read(APIC_ICR
);
1020 printk(KERN_DEBUG
"... APIC ICR: %08x\n", v
);
1021 v
= apic_read(APIC_ICR2
);
1022 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", v
);
1024 v
= apic_read(APIC_LVTT
);
1025 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1027 if (maxlvt
> 3) { /* PC is LVT#4. */
1028 v
= apic_read(APIC_LVTPC
);
1029 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1031 v
= apic_read(APIC_LVT0
);
1032 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1033 v
= apic_read(APIC_LVT1
);
1034 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1036 if (maxlvt
> 2) { /* ERR is LVT#3. */
1037 v
= apic_read(APIC_LVTERR
);
1038 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1041 v
= apic_read(APIC_TMICT
);
1042 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1043 v
= apic_read(APIC_TMCCT
);
1044 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1045 v
= apic_read(APIC_TDCR
);
1046 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1050 void print_all_local_APICs (void)
1052 smp_call_function(print_local_APIC
, NULL
, 1, 1);
1053 print_local_APIC(NULL
);
1056 void /*__init*/ print_PIC(void)
1058 extern spinlock_t i8259A_lock
;
1059 unsigned int v
, flags
;
1061 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1063 spin_lock_irqsave(&i8259A_lock
, flags
);
1065 v
= inb(0xa1) << 8 | inb(0x21);
1066 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1068 v
= inb(0xa0) << 8 | inb(0x20);
1069 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1073 v
= inb(0xa0) << 8 | inb(0x20);
1077 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1079 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1081 v
= inb(0x4d1) << 8 | inb(0x4d0);
1082 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1085 static void __init
enable_IO_APIC(void)
1087 struct IO_APIC_reg_01 reg_01
;
1089 unsigned long flags
;
1091 for (i
= 0; i
< PIN_MAP_SIZE
; i
++) {
1092 irq_2_pin
[i
].pin
= -1;
1093 irq_2_pin
[i
].next
= 0;
1096 for (i
= 0; i
< MAX_PIRQS
; i
++)
1097 pirq_entries
[i
] = -1;
1100 * The number of IO-APIC IRQ registers (== #pins):
1102 for (i
= 0; i
< nr_ioapics
; i
++) {
1103 spin_lock_irqsave(&ioapic_lock
, flags
);
1104 *(int *)®_01
= io_apic_read(i
, 1);
1105 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1106 nr_ioapic_registers
[i
] = reg_01
.entries
+1;
1110 * Do not trust the IO-APIC being empty at bootup
1116 * Not an __init, needed by the reboot code
1118 void disable_IO_APIC(void)
1121 * Clear the IO-APIC before rebooting:
1125 disconnect_bsp_APIC();
1129 * function to set the IO-APIC physical IDs based on the
1130 * values stored in the MPC table.
1132 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1135 static void __init
setup_ioapic_ids_from_mpc (void)
1137 struct IO_APIC_reg_00 reg_00
;
1138 unsigned long phys_id_present_map
;
1141 unsigned char old_id
;
1142 unsigned long flags
;
1145 /* This gets done during IOAPIC enumeration for ACPI. */
1148 phys_id_present_map
= ioapic_phys_id_map(phys_cpu_present_map
);
1151 * Set the IOAPIC ID to the value stored in the MPC table.
1153 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1155 /* Read the register 0 value */
1156 spin_lock_irqsave(&ioapic_lock
, flags
);
1157 *(int *)®_00
= io_apic_read(apic
, 0);
1158 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1160 old_id
= mp_ioapics
[apic
].mpc_apicid
;
1162 if (mp_ioapics
[apic
].mpc_apicid
>= APIC_BROADCAST_ID
) {
1163 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1164 apic
, mp_ioapics
[apic
].mpc_apicid
);
1165 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1167 mp_ioapics
[apic
].mpc_apicid
= reg_00
.ID
;
1171 * Sanity check, is the ID really free? Every APIC in a
1172 * system must have a unique ID or we get lots of nice
1173 * 'stuck on smp_invalidate_needed IPI wait' messages.
1175 if (check_apicid_used(phys_id_present_map
,
1176 mp_ioapics
[apic
].mpc_apicid
)) {
1177 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1178 apic
, mp_ioapics
[apic
].mpc_apicid
);
1179 for (i
= 0; i
< 0xf; i
++)
1180 if (!(phys_id_present_map
& (1 << i
)))
1183 panic("Max APIC ID exceeded!\n");
1184 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1186 phys_id_present_map
|= 1 << i
;
1187 mp_ioapics
[apic
].mpc_apicid
= i
;
1189 printk("Setting %d in the phys_id_present_map\n", mp_ioapics
[apic
].mpc_apicid
);
1190 phys_id_present_map
|= 1 << mp_ioapics
[apic
].mpc_apicid
;
1195 * We need to adjust the IRQ routing table
1196 * if the ID changed.
1198 if (old_id
!= mp_ioapics
[apic
].mpc_apicid
)
1199 for (i
= 0; i
< mp_irq_entries
; i
++)
1200 if (mp_irqs
[i
].mpc_dstapic
== old_id
)
1201 mp_irqs
[i
].mpc_dstapic
1202 = mp_ioapics
[apic
].mpc_apicid
;
1205 * Read the right value from the MPC table and
1206 * write it into the ID register.
1208 printk(KERN_INFO
"...changing IO-APIC physical APIC ID to %d ...",
1209 mp_ioapics
[apic
].mpc_apicid
);
1211 reg_00
.ID
= mp_ioapics
[apic
].mpc_apicid
;
1212 spin_lock_irqsave(&ioapic_lock
, flags
);
1213 io_apic_write(apic
, 0, *(int *)®_00
);
1214 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1219 spin_lock_irqsave(&ioapic_lock
, flags
);
1220 *(int *)®_00
= io_apic_read(apic
, 0);
1221 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1222 if (reg_00
.ID
!= mp_ioapics
[apic
].mpc_apicid
)
1223 panic("could not set ID!\n");
1230 * There is a nasty bug in some older SMP boards, their mptable lies
1231 * about the timer IRQ. We do the following to work around the situation:
1233 * - timer IRQ defaults to IO-APIC IRQ
1234 * - if this function detects that timer IRQs are defunct, then we fall
1235 * back to ISA timer IRQs
1237 static int __init
timer_irq_works(void)
1239 unsigned int t1
= jiffies
;
1242 /* Let ten ticks pass... */
1243 mdelay((10 * 1000) / HZ
);
1246 * Expect a few ticks at least, to be sure some possible
1247 * glue logic does not lock up after one or two first
1248 * ticks in a non-ExtINT mode. Also the local APIC
1249 * might have cached one ExtINT interrupt. Finally, at
1250 * least one tick may be lost due to delays.
1252 if (jiffies
- t1
> 4)
1259 * In the SMP+IOAPIC case it might happen that there are an unspecified
1260 * number of pending IRQ events unhandled. These cases are very rare,
1261 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1262 * better to do it this way as thus we do not have to be aware of
1263 * 'pending' interrupts in the IRQ path, except at this point.
1266 * Edge triggered needs to resend any interrupt
1267 * that was delayed but this is now handled in the device
1270 #define enable_edge_ioapic_irq unmask_IO_APIC_irq
1272 static void disable_edge_ioapic_irq (unsigned int irq
) { /* nothing */ }
1275 * Starting up a edge-triggered IO-APIC interrupt is
1276 * nasty - we need to make sure that we get the edge.
1277 * If it is already asserted for some reason, we need
1278 * return 1 to indicate that is was pending.
1280 * This is not complete - we should be able to fake
1281 * an edge even if it isn't on the 8259A...
1284 static unsigned int startup_edge_ioapic_irq(unsigned int irq
)
1286 int was_pending
= 0;
1287 unsigned long flags
;
1289 spin_lock_irqsave(&ioapic_lock
, flags
);
1291 disable_8259A_irq(irq
);
1292 if (i8259A_irq_pending(irq
))
1295 __unmask_IO_APIC_irq(irq
);
1296 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1301 #define shutdown_edge_ioapic_irq disable_edge_ioapic_irq
1304 * Once we have recorded IRQ_PENDING already, we can mask the
1305 * interrupt for real. This prevents IRQ storms from unhandled
1308 static void ack_edge_ioapic_irq(unsigned int irq
)
1311 if ((irq_desc
[irq
].status
& (IRQ_PENDING
| IRQ_DISABLED
))
1312 == (IRQ_PENDING
| IRQ_DISABLED
))
1313 mask_IO_APIC_irq(irq
);
1317 static void end_edge_ioapic_irq (unsigned int i
) { /* nothing */ }
1321 * Level triggered interrupts can just be masked,
1322 * and shutting down and starting up the interrupt
1323 * is the same as enabling and disabling them -- except
1324 * with a startup need to return a "was pending" value.
1326 * Level triggered interrupts are special because we
1327 * do not touch any IO-APIC register while handling
1328 * them. We ack the APIC in the end-IRQ handler, not
1329 * in the start-IRQ-handler. Protection against reentrance
1330 * from the same interrupt is still provided, both by the
1331 * generic IRQ layer and by the fact that an unacked local
1332 * APIC does not accept IRQs.
1334 static unsigned int startup_level_ioapic_irq (unsigned int irq
)
1336 unmask_IO_APIC_irq(irq
);
1338 return 0; /* don't check for pending */
1341 #define shutdown_level_ioapic_irq mask_IO_APIC_irq
1342 #define enable_level_ioapic_irq unmask_IO_APIC_irq
1343 #define disable_level_ioapic_irq mask_IO_APIC_irq
1345 static void end_level_ioapic_irq (unsigned int irq
)
1352 * It appears there is an erratum which affects at least version 0x11
1353 * of I/O APIC (that's the 82093AA and cores integrated into various
1354 * chipsets). Under certain conditions a level-triggered interrupt is
1355 * erroneously delivered as edge-triggered one but the respective IRR
1356 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1357 * message but it will never arrive and further interrupts are blocked
1358 * from the source. The exact reason is so far unknown, but the
1359 * phenomenon was observed when two consecutive interrupt requests
1360 * from a given source get delivered to the same CPU and the source is
1361 * temporarily disabled in between.
1363 * A workaround is to simulate an EOI message manually. We achieve it
1364 * by setting the trigger mode to edge and then to level when the edge
1365 * trigger mode gets detected in the TMR of a local APIC for a
1366 * level-triggered interrupt. We mask the source for the time of the
1367 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1368 * The idea is from Manfred Spraul. --macro
1370 i
= IO_APIC_VECTOR(irq
);
1371 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
1375 if (!(v
& (1 << (i
& 0x1f)))) {
1376 #ifdef APIC_LOCKUP_DEBUG
1377 struct irq_pin_list
*entry
;
1380 #ifdef APIC_MISMATCH_DEBUG
1381 atomic_inc(&irq_mis_count
);
1383 spin_lock(&ioapic_lock
);
1384 __mask_and_edge_IO_APIC_irq(irq
);
1385 #ifdef APIC_LOCKUP_DEBUG
1386 for (entry
= irq_2_pin
+ irq
;;) {
1389 if (entry
->pin
== -1)
1391 reg
= io_apic_read(entry
->apic
, 0x10 + entry
->pin
* 2);
1392 if (reg
& 0x00004000)
1393 printk(KERN_CRIT
"Aieee!!! Remote IRR"
1394 " still set after unlock!\n");
1397 entry
= irq_2_pin
+ entry
->next
;
1400 __unmask_and_level_IO_APIC_irq(irq
);
1401 spin_unlock(&ioapic_lock
);
1405 static void mask_and_ack_level_ioapic_irq (unsigned int irq
) { /* nothing */ }
1408 * Level and edge triggered IO-APIC interrupts need different handling,
1409 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1410 * handled with the level-triggered descriptor, but that one has slightly
1411 * more overhead. Level-triggered interrupts cannot be handled with the
1412 * edge-triggered handler, without risking IRQ storms and other ugly
1416 static struct hw_interrupt_type ioapic_edge_irq_type
= {
1418 startup_edge_ioapic_irq
,
1419 shutdown_edge_ioapic_irq
,
1420 enable_edge_ioapic_irq
,
1421 disable_edge_ioapic_irq
,
1422 ack_edge_ioapic_irq
,
1423 end_edge_ioapic_irq
,
1424 set_ioapic_affinity
,
1427 static struct hw_interrupt_type ioapic_level_irq_type
= {
1429 startup_level_ioapic_irq
,
1430 shutdown_level_ioapic_irq
,
1431 enable_level_ioapic_irq
,
1432 disable_level_ioapic_irq
,
1433 mask_and_ack_level_ioapic_irq
,
1434 end_level_ioapic_irq
,
1435 set_ioapic_affinity
,
1438 static inline void init_IO_APIC_traps(void)
1443 * NOTE! The local APIC isn't very good at handling
1444 * multiple interrupts at the same interrupt level.
1445 * As the interrupt level is determined by taking the
1446 * vector number and shifting that right by 4, we
1447 * want to spread these out a bit so that they don't
1448 * all fall in the same interrupt level.
1450 * Also, we've got to be careful not to trash gate
1451 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1453 for (irq
= 0; irq
< NR_IRQS
; irq
++) {
1454 if (IO_APIC_IRQ(irq
) && !IO_APIC_VECTOR(irq
)) {
1456 * Hmm.. We don't have an entry for this,
1457 * so default to an old-fashioned 8259
1458 * interrupt if we can..
1461 make_8259A_irq(irq
);
1463 /* Strange. Oh, well.. */
1464 irq_desc
[irq
].handler
= &no_irq_type
;
1469 static void enable_lapic_irq (unsigned int irq
)
1473 v
= apic_read(APIC_LVT0
);
1474 apic_write_around(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
1477 static void disable_lapic_irq (unsigned int irq
)
1481 v
= apic_read(APIC_LVT0
);
1482 apic_write_around(APIC_LVT0
, v
| APIC_LVT_MASKED
);
1485 static void ack_lapic_irq (unsigned int irq
)
1490 static void end_lapic_irq (unsigned int i
) { /* nothing */ }
1492 static struct hw_interrupt_type lapic_irq_type
= {
1494 NULL
, /* startup_irq() not used for IRQ0 */
1495 NULL
, /* shutdown_irq() not used for IRQ0 */
1502 void enable_NMI_through_LVT0 (void * dummy
)
1504 unsigned int v
, ver
;
1506 ver
= apic_read(APIC_LVR
);
1507 ver
= GET_APIC_VERSION(ver
);
1508 v
= APIC_DM_NMI
; /* unmask and set to NMI */
1509 if (!APIC_INTEGRATED(ver
)) /* 82489DX */
1510 v
|= APIC_LVT_LEVEL_TRIGGER
;
1511 apic_write_around(APIC_LVT0
, v
);
1514 static void setup_nmi (void)
1517 * Dirty trick to enable the NMI watchdog ...
1518 * We put the 8259A master into AEOI mode and
1519 * unmask on all local APICs LVT0 as NMI.
1521 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1522 * is from Maciej W. Rozycki - so we do not have to EOI from
1523 * the NMI handler or the timer interrupt.
1525 printk(KERN_INFO
"activating NMI Watchdog ...");
1527 smp_call_function(enable_NMI_through_LVT0
, NULL
, 1, 1);
1528 enable_NMI_through_LVT0(NULL
);
1534 * This looks a bit hackish but it's about the only one way of sending
1535 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1536 * not support the ExtINT mode, unfortunately. We need to send these
1537 * cycles as some i82489DX-based boards have glue logic that keeps the
1538 * 8259A interrupt line asserted until INTA. --macro
1540 static inline void unlock_ExtINT_logic(void)
1543 struct IO_APIC_route_entry entry0
, entry1
;
1544 unsigned char save_control
, save_freq_select
;
1545 unsigned long flags
;
1547 pin
= find_isa_irq_pin(8, mp_INT
);
1551 spin_lock_irqsave(&ioapic_lock
, flags
);
1552 *(((int *)&entry0
) + 1) = io_apic_read(0, 0x11 + 2 * pin
);
1553 *(((int *)&entry0
) + 0) = io_apic_read(0, 0x10 + 2 * pin
);
1554 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1555 clear_IO_APIC_pin(0, pin
);
1557 memset(&entry1
, 0, sizeof(entry1
));
1559 entry1
.dest_mode
= 0; /* physical delivery */
1560 entry1
.mask
= 0; /* unmask IRQ now */
1561 entry1
.dest
.physical
.physical_dest
= hard_smp_processor_id();
1562 entry1
.delivery_mode
= dest_ExtINT
;
1563 entry1
.polarity
= entry0
.polarity
;
1567 spin_lock_irqsave(&ioapic_lock
, flags
);
1568 io_apic_write(0, 0x11 + 2 * pin
, *(((int *)&entry1
) + 1));
1569 io_apic_write(0, 0x10 + 2 * pin
, *(((int *)&entry1
) + 0));
1570 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1572 save_control
= CMOS_READ(RTC_CONTROL
);
1573 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
1574 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
1576 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
1581 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
1585 CMOS_WRITE(save_control
, RTC_CONTROL
);
1586 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
1587 clear_IO_APIC_pin(0, pin
);
1589 spin_lock_irqsave(&ioapic_lock
, flags
);
1590 io_apic_write(0, 0x11 + 2 * pin
, *(((int *)&entry0
) + 1));
1591 io_apic_write(0, 0x10 + 2 * pin
, *(((int *)&entry0
) + 0));
1592 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1596 * This code may look a bit paranoid, but it's supposed to cooperate with
1597 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1598 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1599 * fanatically on his truly buggy board.
1601 static inline void check_timer(void)
1603 extern int timer_ack
;
1608 * get/set the timer IRQ vector:
1610 disable_8259A_irq(0);
1611 vector
= assign_irq_vector(0);
1612 set_intr_gate(vector
, interrupt
[0]);
1615 * Subtle, code in do_timer_interrupt() expects an AEOI
1616 * mode for the 8259A whenever interrupts are routed
1617 * through I/O APICs. Also IRQ0 has to be enabled in
1618 * the 8259A which implies the virtual wire has to be
1619 * disabled in the local APIC.
1621 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
1624 enable_8259A_irq(0);
1626 pin1
= find_isa_irq_pin(0, mp_INT
);
1627 pin2
= find_isa_irq_pin(0, mp_ExtINT
);
1629 printk(KERN_INFO
"..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector
, pin1
, pin2
);
1633 * Ok, does IRQ0 through the IOAPIC work?
1635 unmask_IO_APIC_irq(0);
1636 if (timer_irq_works()) {
1637 if (nmi_watchdog
== NMI_IO_APIC
) {
1638 disable_8259A_irq(0);
1640 enable_8259A_irq(0);
1641 check_nmi_watchdog();
1645 clear_IO_APIC_pin(0, pin1
);
1646 printk(KERN_ERR
"..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
1649 printk(KERN_INFO
"...trying to set up timer (IRQ0) through the 8259A ... ");
1651 printk("\n..... (found pin %d) ...", pin2
);
1653 * legacy devices should be connected to IO APIC #0
1655 setup_ExtINT_IRQ0_pin(pin2
, vector
);
1656 if (timer_irq_works()) {
1659 replace_pin_at_irq(0, 0, pin1
, 0, pin2
);
1661 add_pin_to_irq(0, 0, pin2
);
1662 if (nmi_watchdog
== NMI_IO_APIC
) {
1664 check_nmi_watchdog();
1669 * Cleanup, just in case ...
1671 clear_IO_APIC_pin(0, pin2
);
1673 printk(" failed.\n");
1676 printk(KERN_WARNING
"timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1680 printk(KERN_INFO
"...trying to set up timer as Virtual Wire IRQ...");
1682 disable_8259A_irq(0);
1683 irq_desc
[0].handler
= &lapic_irq_type
;
1684 apic_write_around(APIC_LVT0
, APIC_DM_FIXED
| vector
); /* Fixed mode */
1685 enable_8259A_irq(0);
1687 if (timer_irq_works()) {
1688 printk(" works.\n");
1691 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| vector
);
1692 printk(" failed.\n");
1694 printk(KERN_INFO
"...trying to set up timer as ExtINT IRQ...");
1699 apic_write_around(APIC_LVT0
, APIC_DM_EXTINT
);
1701 unlock_ExtINT_logic();
1703 if (timer_irq_works()) {
1704 printk(" works.\n");
1707 printk(" failed :(.\n");
1708 panic("IO-APIC + timer doesn't work! pester mingo@redhat.com");
1713 * IRQ's that are handled by the old PIC in all cases:
1714 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1715 * Linux doesn't really care, as it's not actually used
1716 * for any interrupt handling anyway.
1717 * - There used to be IRQ13 here as well, but all
1718 * MPS-compliant must not use it for FPU coupling and we
1719 * want to use exception 16 anyway. And there are
1720 * systems who connect it to an I/O APIC for other uses.
1721 * Thus we don't mark it special any longer.
1723 * Additionally, something is definitely wrong with irq9
1726 #define PIC_IRQS (1<<2)
1728 void __init
setup_IO_APIC(void)
1732 io_apic_irqs
= ~PIC_IRQS
;
1733 printk("ENABLING IO-APIC IRQs\n");
1736 * Set up IO-APIC IRQ routing.
1738 setup_ioapic_ids_from_mpc();
1740 setup_IO_APIC_irqs();
1741 init_IO_APIC_traps();
1747 * Called after all the initialization is done. If we didnt find any
1748 * APIC bugs then we can allow the modify fast path
1751 static int __init
io_apic_bug_finalize(void)
1753 if(sis_apic_bug
== -1)
1758 late_initcall(io_apic_bug_finalize
);
1760 /* --------------------------------------------------------------------------
1761 ACPI-based IOAPIC Configuration
1762 -------------------------------------------------------------------------- */
1764 #ifdef CONFIG_ACPI_BOOT
1766 #define IO_APIC_MAX_ID APIC_BROADCAST_ID
1768 int __init
io_apic_get_unique_id (int ioapic
, int apic_id
)
1770 struct IO_APIC_reg_00 reg_00
;
1771 static unsigned long apic_id_map
= 0;
1772 unsigned long flags
;
1776 * The P4 platform supports up to 256 APIC IDs on two separate APIC
1777 * buses (one for LAPICs, one for IOAPICs), where predecessors only
1778 * supports up to 16 on one shared APIC bus.
1780 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
1781 * advantage of new APIC bus architecture.
1785 apic_id_map
= phys_cpu_present_map
;
1787 spin_lock_irqsave(&ioapic_lock
, flags
);
1788 *(int *)®_00
= io_apic_read(ioapic
, 0);
1789 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1791 if (apic_id
>= IO_APIC_MAX_ID
) {
1792 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
1793 "%d\n", ioapic
, apic_id
, reg_00
.ID
);
1794 apic_id
= reg_00
.ID
;
1798 * Every APIC in a system must have a unique ID or we get lots of nice
1799 * 'stuck on smp_invalidate_needed IPI wait' messages.
1801 if (apic_id_map
& (1 << apic_id
)) {
1803 for (i
= 0; i
< IO_APIC_MAX_ID
; i
++) {
1804 if (!(apic_id_map
& (1 << i
)))
1808 if (i
== IO_APIC_MAX_ID
)
1809 panic("Max apic_id exceeded!\n");
1811 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
1812 "trying %d\n", ioapic
, apic_id
, i
);
1817 apic_id_map
|= (1 << apic_id
);
1819 if (reg_00
.ID
!= apic_id
) {
1820 reg_00
.ID
= apic_id
;
1822 spin_lock_irqsave(&ioapic_lock
, flags
);
1823 io_apic_write(ioapic
, 0, *(int *)®_00
);
1824 *(int *)®_00
= io_apic_read(ioapic
, 0);
1825 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1828 if (reg_00
.ID
!= apic_id
)
1829 panic("IOAPIC[%d]: Unable change apic_id!\n", ioapic
);
1832 printk(KERN_INFO
"IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
1838 int __init
io_apic_get_version (int ioapic
)
1840 struct IO_APIC_reg_01 reg_01
;
1841 unsigned long flags
;
1843 spin_lock_irqsave(&ioapic_lock
, flags
);
1844 *(int *)®_01
= io_apic_read(ioapic
, 1);
1845 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1847 return reg_01
.version
;
1851 int __init
io_apic_get_redir_entries (int ioapic
)
1853 struct IO_APIC_reg_01 reg_01
;
1854 unsigned long flags
;
1856 spin_lock_irqsave(&ioapic_lock
, flags
);
1857 *(int *)®_01
= io_apic_read(ioapic
, 1);
1858 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1860 return reg_01
.entries
;
1864 int io_apic_set_pci_routing (int ioapic
, int pin
, int irq
)
1866 struct IO_APIC_route_entry entry
;
1867 unsigned long flags
;
1869 if (!IO_APIC_IRQ(irq
)) {
1870 printk(KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0/n",
1876 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
1877 * Note that we mask (disable) IRQs now -- these get enabled when the
1878 * corresponding device driver registers for this IRQ.
1881 memset(&entry
,0,sizeof(entry
));
1883 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1884 entry
.dest_mode
= INT_DEST_MODE
;
1885 entry
.dest
.logical
.logical_dest
= TARGET_CPUS
;
1886 entry
.mask
= 1; /* Disabled (masked) */
1887 entry
.trigger
= 1; /* Level sensitive */
1888 entry
.polarity
= 1; /* Low active */
1890 add_pin_to_irq(irq
, ioapic
, pin
);
1892 entry
.vector
= assign_irq_vector(irq
);
1894 printk(KERN_DEBUG
"IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
1895 "IRQ %d)\n", ioapic
,
1896 mp_ioapics
[ioapic
].mpc_apicid
, pin
, entry
.vector
, irq
);
1898 irq_desc
[irq
].handler
= &ioapic_level_irq_type
;
1900 set_intr_gate(entry
.vector
, interrupt
[irq
]);
1902 if (!ioapic
&& (irq
< 16))
1903 disable_8259A_irq(irq
);
1905 spin_lock_irqsave(&ioapic_lock
, flags
);
1906 io_apic_write(ioapic
, 0x11+2*pin
, *(((int *)&entry
)+1));
1907 io_apic_write(ioapic
, 0x10+2*pin
, *(((int *)&entry
)+0));
1908 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1913 #endif /*CONFIG_ACPI_BOOT*/