2 * linux/arch/alpha/kernel/time.c
4 * Copyright (C) 1991, 1992, 1995, 1999, 2000 Linus Torvalds
6 * This file contains the PC-specific time handling details:
7 * reading the RTC at bootup, etc..
8 * 1994-07-02 Alan Modra
9 * fixed set_rtc_mmss, fixed time.year for >= 2000, new mktime
10 * 1995-03-26 Markus Kuhn
11 * fixed 500 ms bug at call to set_rtc_mmss, fixed DS12887
12 * precision CMOS clock update
13 * 1997-09-10 Updated NTP code according to technical memorandum Jan '96
14 * "A Kernel Model for Precision Timekeeping" by Dave Mills
15 * 1997-01-09 Adrian Sun
16 * use interval timer if CONFIG_RTC=y
17 * 1997-10-29 John Bowman (bowman@math.ualberta.ca)
18 * fixed tick loss calculation in timer_interrupt
19 * (round system clock to nearest tick instead of truncating)
20 * fixed algorithm in time_init for getting time from CMOS clock
21 * 1999-04-16 Thorsten Kranzkowski (dl8bcu@gmx.net)
22 * fixed algorithm in do_gettimeofday() for calculating the precise time
23 * from processor cycle counter (now taking lost_ticks into account)
24 * 2000-08-13 Jan-Benedict Glaw <jbglaw@lug-owl.de>
25 * Fixed time_init to be aware of epoches != 1900. This prevents
26 * booting up in 2048 for me;) Code is stolen from rtc.c.
28 #include <linux/config.h>
29 #include <linux/errno.h>
30 #include <linux/sched.h>
31 #include <linux/kernel.h>
32 #include <linux/param.h>
33 #include <linux/string.h>
35 #include <linux/delay.h>
36 #include <linux/ioport.h>
37 #include <linux/irq.h>
38 #include <linux/interrupt.h>
39 #include <linux/init.h>
40 #include <linux/bcd.h>
42 #include <asm/uaccess.h>
44 #include <asm/hwrpb.h>
46 #include <linux/mc146818rtc.h>
47 #include <linux/timex.h>
54 extern rwlock_t xtime_lock
;
55 extern unsigned long wall_jiffies
; /* kernel/timer.c */
57 static int set_rtc_mmss(unsigned long);
59 spinlock_t rtc_lock
= SPIN_LOCK_UNLOCKED
;
61 #define TICK_SIZE (tick_nsec / 1000)
64 * Shift amount by which scaled_ticks_per_cycle is scaled. Shifting
65 * by 48 gives us 16 bits for HZ while keeping the accuracy good even
66 * for large CPU clock rates.
70 /* lump static variables together for more efficient access: */
72 /* cycle counter last time it got invoked */
74 /* ticks/cycle * 2^48 */
75 unsigned long scaled_ticks_per_cycle
;
76 /* last time the CMOS clock got updated */
77 time_t last_rtc_update
;
78 /* partial unused tick */
79 unsigned long partial_tick
;
82 unsigned long est_cycle_freq
;
85 static inline __u32
rpcc(void)
88 asm volatile ("rpcc %0" : "=r"(result
));
94 * timer_interrupt() needs to keep up the real-time clock,
95 * as well as call the "do_timer()" routine every clocktick
97 void timer_interrupt(int irq
, void *dev
, struct pt_regs
* regs
)
104 /* Not SMP, do kernel PC profiling here. */
105 if (!user_mode(regs
))
106 alpha_do_profile(regs
->pc
);
109 write_lock(&xtime_lock
);
112 * Calculate how many ticks have passed since the last update,
113 * including any previous partial leftover. Save any resulting
114 * fraction for the next pass.
117 delta
= now
- state
.last_time
;
118 state
.last_time
= now
;
119 delta
= delta
* state
.scaled_ticks_per_cycle
+ state
.partial_tick
;
120 state
.partial_tick
= delta
& ((1UL << FIX_SHIFT
) - 1);
121 nticks
= delta
>> FIX_SHIFT
;
129 * If we have an externally synchronized Linux clock, then update
130 * CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
131 * called as close as possible to 500 ms before the new second starts.
133 if ((time_status
& STA_UNSYNC
) == 0
134 && xtime
.tv_sec
> state
.last_rtc_update
+ 660
135 && xtime
.tv_nsec
>= 500000 - ((unsigned) TICK_SIZE
) / 2
136 && xtime
.tv_nsec
<= 500000 + ((unsigned) TICK_SIZE
) / 2) {
137 int tmp
= set_rtc_mmss(xtime
.tv_sec
);
138 state
.last_rtc_update
= xtime
.tv_sec
- (tmp
? 600 : 0);
141 write_unlock(&xtime_lock
);
145 common_init_rtc(void)
149 /* Reset periodic interrupt frequency. */
150 x
= CMOS_READ(RTC_FREQ_SELECT
) & 0x3f;
151 if (x
!= 0x26 && x
!= 0x19 && x
!= 0x06) {
152 printk("Setting RTC_FREQ to 1024 Hz (%x)\n", x
);
153 CMOS_WRITE(0x26, RTC_FREQ_SELECT
);
156 /* Turn on periodic interrupts. */
157 x
= CMOS_READ(RTC_CONTROL
);
158 if (!(x
& RTC_PIE
)) {
159 printk("Turning on RTC interrupts.\n");
161 x
&= ~(RTC_AIE
| RTC_UIE
);
162 CMOS_WRITE(x
, RTC_CONTROL
);
164 (void) CMOS_READ(RTC_INTR_FLAGS
);
166 outb(0x36, 0x43); /* pit counter 0: system timer */
170 outb(0xb6, 0x43); /* pit counter 2: speaker */
178 /* Validate a computed cycle counter result against the known bounds for
179 the given processor core. There's too much brokenness in the way of
180 timing hardware for any one method to work everywhere. :-(
182 Return 0 if the result cannot be trusted, otherwise return the argument. */
184 static unsigned long __init
185 validate_cc_value(unsigned long cc
)
187 static struct bounds
{
188 unsigned int min
, max
;
189 } cpu_hz
[] __initdata
= {
190 [EV3_CPU
] = { 50000000, 200000000 }, /* guess */
191 [EV4_CPU
] = { 100000000, 300000000 },
192 [LCA4_CPU
] = { 100000000, 300000000 }, /* guess */
193 [EV45_CPU
] = { 200000000, 300000000 },
194 [EV5_CPU
] = { 250000000, 433000000 },
195 [EV56_CPU
] = { 333000000, 667000000 },
196 [PCA56_CPU
] = { 400000000, 600000000 }, /* guess */
197 [PCA57_CPU
] = { 500000000, 600000000 }, /* guess */
198 [EV6_CPU
] = { 466000000, 600000000 },
199 [EV67_CPU
] = { 600000000, 750000000 },
200 [EV68AL_CPU
] = { 750000000, 940000000 },
201 [EV68CB_CPU
] = { 1000000000, 1333333333 },
202 /* None of the following are shipping as of 2001-11-01. */
203 [EV68CX_CPU
] = { 1000000000, 1700000000 }, /* guess */
204 [EV69_CPU
] = { 1000000000, 1700000000 }, /* guess */
205 [EV7_CPU
] = { 800000000, 1400000000 }, /* guess */
206 [EV79_CPU
] = { 1000000000, 2000000000 }, /* guess */
209 /* Allow for some drift in the crystal. 10MHz is more than enough. */
210 const unsigned int deviation
= 10000000;
212 struct percpu_struct
*cpu
;
215 cpu
= (struct percpu_struct
*)((char*)hwrpb
+ hwrpb
->processor_offset
);
216 index
= cpu
->type
& 0xffffffff;
218 /* If index out of bounds, no way to validate. */
219 if (index
>= sizeof(cpu_hz
)/sizeof(cpu_hz
[0]))
222 /* If index contains no data, no way to validate. */
223 if (cpu_hz
[index
].max
== 0)
226 if (cc
< cpu_hz
[index
].min
- deviation
227 || cc
> cpu_hz
[index
].max
+ deviation
)
235 * Calibrate CPU clock using legacy 8254 timer/counter. Stolen from
239 #define CALIBRATE_LATCH (52 * LATCH)
240 #define CALIBRATE_TIME (52 * 1000020 / HZ)
242 static unsigned long __init
243 calibrate_cc_with_pic(void)
247 /* Set the Gate high, disable speaker */
248 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
251 * Now let's take care of CTC channel 2
253 * Set the Gate high, program CTC channel 2 for mode 0,
254 * (interrupt on terminal count mode), binary count,
255 * load 5 * LATCH count, (LSB and MSB) to begin countdown.
257 outb(0xb0, 0x43); /* binary, mode 0, LSB/MSB, Ch 2 */
258 outb(CALIBRATE_LATCH
& 0xff, 0x42); /* LSB of count */
259 outb(CALIBRATE_LATCH
>> 8, 0x42); /* MSB of count */
263 count
+=100; /* by 1 takes too long to timeout from 0 */
264 } while ((inb(0x61) & 0x20) == 0 && count
> 0);
267 /* Error: ECTCNEVERSET or ECPUTOOFAST. */
271 /* Error: ECPUTOOSLOW. */
272 if (cc
<= CALIBRATE_TIME
)
275 return (cc
* 1000000UL) / CALIBRATE_TIME
;
278 /* The Linux interpretation of the CMOS clock register contents:
279 When the Update-In-Progress (UIP) flag goes from 1 to 0, the
280 RTC registers show the second which has precisely just started.
281 Let's hope other operating systems interpret the RTC the same way. */
283 static unsigned long __init
284 rpcc_after_update_in_progress(void)
286 do { } while (!(CMOS_READ(RTC_FREQ_SELECT
) & RTC_UIP
));
287 do { } while (CMOS_READ(RTC_FREQ_SELECT
) & RTC_UIP
);
295 unsigned int year
, mon
, day
, hour
, min
, sec
, cc1
, cc2
, epoch
;
296 unsigned long cycle_freq
, one_percent
;
299 /* Calibrate CPU clock -- attempt #1. */
301 est_cycle_freq
= validate_cc_value(calibrate_cc_with_pic());
303 cc1
= rpcc_after_update_in_progress();
305 /* Calibrate CPU clock -- attempt #2. */
306 if (!est_cycle_freq
) {
307 cc2
= rpcc_after_update_in_progress();
308 est_cycle_freq
= validate_cc_value(cc2
- cc1
);
312 cycle_freq
= hwrpb
->cycle_freq
;
313 if (est_cycle_freq
) {
314 /* If the given value is within 1% of what we calculated,
315 accept it. Otherwise, use what we found. */
316 one_percent
= cycle_freq
/ 100;
317 diff
= cycle_freq
- est_cycle_freq
;
320 if ((unsigned long)diff
> one_percent
) {
321 cycle_freq
= est_cycle_freq
;
322 printk("HWRPB cycle frequency bogus. "
323 "Estimated %lu Hz\n", cycle_freq
);
327 } else if (! validate_cc_value (cycle_freq
)) {
328 printk("HWRPB cycle frequency bogus, "
329 "and unable to estimate a proper value!\n");
332 /* From John Bowman <bowman@math.ualberta.ca>: allow the values
333 to settle, as the Update-In-Progress bit going low isn't good
334 enough on some hardware. 2ms is our guess; we havn't found
335 bogomips yet, but this is close on a 500Mhz box. */
338 sec
= CMOS_READ(RTC_SECONDS
);
339 min
= CMOS_READ(RTC_MINUTES
);
340 hour
= CMOS_READ(RTC_HOURS
);
341 day
= CMOS_READ(RTC_DAY_OF_MONTH
);
342 mon
= CMOS_READ(RTC_MONTH
);
343 year
= CMOS_READ(RTC_YEAR
);
345 if (!(CMOS_READ(RTC_CONTROL
) & RTC_DM_BINARY
) || RTC_ALWAYS_BCD
) {
354 /* PC-like is standard; used for year < 20 || year >= 70 */
358 else if (year
>= 20 && year
< 48)
361 else if (year
>= 48 && year
< 70)
362 /* Digital UNIX epoch */
365 printk(KERN_INFO
"Using epoch = %d\n", epoch
);
367 if ((year
+= epoch
) < 1970)
370 xtime
.tv_sec
= mktime(year
, mon
, day
, hour
, min
, sec
);
374 extern void __you_loose (void);
378 state
.last_time
= cc1
;
379 state
.scaled_ticks_per_cycle
380 = ((unsigned long) HZ
<< FIX_SHIFT
) / cycle_freq
;
381 state
.last_rtc_update
= 0;
382 state
.partial_tick
= 0L;
384 /* Startup the timer source. */
388 * If we had wanted SRM console printk echoing early, undo it now.
390 * "srmcons" specified in the boot command arguments allows us to
391 * see kernel messages during the period of time before the true
392 * console device is "registered" during console_init(). As of this
393 * version (2.4.10), time_init() is the last Alpha-specific code
394 * called before console_init(), so we put this "unregister" code
395 * here to prevent schizophrenic console behavior later... ;-}
397 if (alpha_using_srm
&& srmcons_output
) {
398 unregister_srm_console();
404 * Use the cycle counter to estimate an displacement from the last time
405 * tick. Unfortunately the Alpha designers made only the low 32-bits of
406 * the cycle counter active, so we overflow on 8.2 seconds on a 500MHz
407 * part. So we can't do the "find absolute time in terms of cycles" thing
408 * that the other ports do.
411 do_gettimeofday(struct timeval
*tv
)
413 unsigned long sec
, usec
, lost
, flags
;
414 unsigned long delta_cycles
, delta_usec
, partial_tick
;
416 read_lock_irqsave(&xtime_lock
, flags
);
418 delta_cycles
= rpcc() - state
.last_time
;
420 usec
= (xtime
.tv_nsec
/ 1000);
421 partial_tick
= state
.partial_tick
;
422 lost
= jiffies
- wall_jiffies
;
424 read_unlock_irqrestore(&xtime_lock
, flags
);
427 /* Until and unless we figure out how to get cpu cycle counters
428 in sync and keep them there, we can't use the rpcc tricks. */
429 delta_usec
= lost
* (1000000 / HZ
);
432 * usec = cycles * ticks_per_cycle * 2**48 * 1e6 / (2**48 * ticks)
433 * = cycles * (s_t_p_c) * 1e6 / (2**48 * ticks)
434 * = cycles * (s_t_p_c) * 15625 / (2**42 * ticks)
436 * which, given a 600MHz cycle and a 1024Hz tick, has a
437 * dynamic range of about 1.7e17, which is less than the
438 * 1.8e19 in an unsigned long, so we are safe from overflow.
440 * Round, but with .5 up always, since .5 to even is harder
441 * with no clear gain.
444 delta_usec
= (delta_cycles
* state
.scaled_ticks_per_cycle
446 + (lost
<< FIX_SHIFT
)) * 15625;
447 delta_usec
= ((delta_usec
/ ((1UL << (FIX_SHIFT
-6-1)) * HZ
)) + 1) / 2;
451 if (usec
>= 1000000) {
461 do_settimeofday(struct timeval
*tv
)
463 unsigned long delta_usec
;
466 write_lock_irq(&xtime_lock
);
468 /* The offset that is added into time in do_gettimeofday above
469 must be subtracted out here to keep a coherent view of the
470 time. Without this, a full-tick error is possible. */
473 delta_usec
= (jiffies
- wall_jiffies
) * (1000000 / HZ
);
475 delta_usec
= rpcc() - state
.last_time
;
476 delta_usec
= (delta_usec
* state
.scaled_ticks_per_cycle
478 + ((jiffies
- wall_jiffies
) << FIX_SHIFT
)) * 15625;
479 delta_usec
= ((delta_usec
/ ((1UL << (FIX_SHIFT
-6-1)) * HZ
)) + 1) / 2;
491 xtime
.tv_nsec
= (usec
/ 1000);
492 time_adjust
= 0; /* stop active adjtime() */
493 time_status
|= STA_UNSYNC
;
494 time_maxerror
= NTP_PHASE_LIMIT
;
495 time_esterror
= NTP_PHASE_LIMIT
;
497 write_unlock_irq(&xtime_lock
);
502 * In order to set the CMOS clock precisely, set_rtc_mmss has to be
503 * called 500 ms after the second nowtime has started, because when
504 * nowtime is written into the registers of the CMOS clock, it will
505 * jump to the next second precisely 500 ms later. Check the Motorola
506 * MC146818A or Dallas DS12887 data sheet for details.
508 * BUG: This routine does not handle hour overflow properly; it just
509 * sets the minutes. Usually you won't notice until after reboot!
515 set_rtc_mmss(unsigned long nowtime
)
518 int real_seconds
, real_minutes
, cmos_minutes
;
519 unsigned char save_control
, save_freq_select
;
521 /* irq are locally disabled here */
522 spin_lock(&rtc_lock
);
523 /* Tell the clock it's being set */
524 save_control
= CMOS_READ(RTC_CONTROL
);
525 CMOS_WRITE((save_control
|RTC_SET
), RTC_CONTROL
);
527 /* Stop and reset prescaler */
528 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
529 CMOS_WRITE((save_freq_select
|RTC_DIV_RESET2
), RTC_FREQ_SELECT
);
531 cmos_minutes
= CMOS_READ(RTC_MINUTES
);
532 if (!(save_control
& RTC_DM_BINARY
) || RTC_ALWAYS_BCD
)
533 BCD_TO_BIN(cmos_minutes
);
536 * since we're only adjusting minutes and seconds,
537 * don't interfere with hour overflow. This avoids
538 * messing with unknown time zones but requires your
539 * RTC not to be off by more than 15 minutes
541 real_seconds
= nowtime
% 60;
542 real_minutes
= nowtime
/ 60;
543 if (((abs(real_minutes
- cmos_minutes
) + 15)/30) & 1) {
544 /* correct for half hour time zone */
549 if (abs(real_minutes
- cmos_minutes
) < 30) {
550 if (!(save_control
& RTC_DM_BINARY
) || RTC_ALWAYS_BCD
) {
551 BIN_TO_BCD(real_seconds
);
552 BIN_TO_BCD(real_minutes
);
554 CMOS_WRITE(real_seconds
,RTC_SECONDS
);
555 CMOS_WRITE(real_minutes
,RTC_MINUTES
);
558 "set_rtc_mmss: can't update from %d to %d\n",
559 cmos_minutes
, real_minutes
);
563 /* The following flags have to be released exactly in this order,
564 * otherwise the DS12887 (popular MC146818A clone with integrated
565 * battery and quartz) will not reset the oscillator and will not
566 * update precisely 500 ms later. You won't find this mentioned in
567 * the Dallas Semiconductor data sheets, but who believes data
568 * sheets anyway ... -- Markus Kuhn
570 CMOS_WRITE(save_control
, RTC_CONTROL
);
571 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
572 spin_unlock(&rtc_lock
);