arch/alpha/kernel/sys_ruffian.c

   1 /*
   2  *      linux/arch/alpha/kernel/sys_ruffian.c
   3  *
   4  *      Copyright (C) 1995 David A Rusling
   5  *      Copyright (C) 1996 Jay A Estabrook
   6  *      Copyright (C) 1998, 1999, 2000 Richard Henderson
   7  *
   8  * Code supporting the RUFFIAN.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/types.h>
  13 #include <linux/mm.h>
  14 #include <linux/sched.h>
  15 #include <linux/pci.h>
  16 #include <linux/ioport.h>
  17 #include <linux/init.h>
  18
  19 #include <asm/ptrace.h>
  20 #include <asm/system.h>
  21 #include <asm/dma.h>
  22 #include <asm/irq.h>
  23 #include <asm/mmu_context.h>
  24 #include <asm/io.h>
  25 #include <asm/pgtable.h>
  26 #include <asm/core_cia.h>
  27 #include <asm/tlbflush.h>
  28
  29 #include "proto.h"
  30 #include "irq_impl.h"
  31 #include "pci_impl.h"
  32 #include "machvec_impl.h"
  33
  34
  35 static void __init
  36 ruffian_init_irq(void)
  37 {
  38         /* Invert 6&7 for i82371 */
  39         *(vulp)PYXIS_INT_HILO  = 0x000000c0UL; mb();
  40         *(vulp)PYXIS_INT_CNFG  = 0x00002064UL; mb();     /* all clear */
  41
  42         outb(0x11,0xA0);
  43         outb(0x08,0xA1);
  44         outb(0x02,0xA1);
  45         outb(0x01,0xA1);
  46         outb(0xFF,0xA1);
  47
  48         outb(0x11,0x20);
  49         outb(0x00,0x21);
  50         outb(0x04,0x21);
  51         outb(0x01,0x21);
  52         outb(0xFF,0x21);
  53
  54         /* Finish writing the 82C59A PIC Operation Control Words */
  55         outb(0x20,0xA0);
  56         outb(0x20,0x20);
  57
  58         init_i8259a_irqs();
  59
  60         /* Not interested in the bogus interrupts (0,3,6),
  61            NMI (1), HALT (2), flash (5), or 21142 (8).  */
  62         init_pyxis_irqs(0x16f0000);
  63
  64         common_init_isa_dma();
  65 }
  66
  67 static void __init
  68 ruffian_init_rtc(void)
  69 {
  70         /* Ruffian does not have the RTC connected to the CPU timer
  71            interrupt.  Instead, it uses the PIT connected to IRQ 0.  */
  72
  73         /* Setup interval timer.  */
  74         outb(0x34, 0x43);               /* binary, mode 2, LSB/MSB, ch 0 */
  75         outb(LATCH & 0xff, 0x40);       /* LSB */
  76         outb(LATCH >> 8, 0x40);         /* MSB */
  77
  78         outb(0xb6, 0x43);               /* pit counter 2: speaker */
  79         outb(0x31, 0x42);
  80         outb(0x13, 0x42);
  81
  82         setup_irq(0, &timer_irqaction);
  83 }
  84
  85 static void
  86 ruffian_kill_arch (int mode)
  87 {
  88         cia_kill_arch(mode);
  89 #if 0
  90         /* This only causes re-entry to ARCSBIOS */
  91         /* Perhaps this works for other PYXIS as well?  */
  92         *(vuip) PYXIS_RESET = 0x0000dead;
  93         mb();
  94 #endif
  95 }
  96
  97 /*
  98  *  Interrupt routing:
  99  *
 100  *              Primary bus
 101  *        IdSel         INTA    INTB    INTC    INTD
 102  * 21052   13             -       -       -       -
 103  * SIO     14            23       -       -       -
 104  * 21143   15            44       -       -       -
 105  * Slot 0  17            43      42      41      40
 106  *
 107  *              Secondary bus
 108  *        IdSel         INTA    INTB    INTC    INTD
 109  * Slot 0   8 (18)       19      18      17      16
 110  * Slot 1   9 (19)       31      30      29      28
 111  * Slot 2  10 (20)       27      26      25      24
 112  * Slot 3  11 (21)       39      38      37      36
 113  * Slot 4  12 (22)       35      34      33      32
 114  * 53c875  13 (23)       20       -       -       -
 115  *
 116  */
 117
 118 static int __init
 119 ruffian_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 120 {
 121         static char irq_tab[11][5] __initdata = {
 122               /*INT  INTA INTB INTC INTD */
 123                 {-1,  -1,  -1,  -1,  -1},  /* IdSel 13,  21052       */
 124                 {-1,  -1,  -1,  -1,  -1},  /* IdSel 14,  SIO         */
 125                 {44,  44,  44,  44,  44},  /* IdSel 15,  21143       */
 126                 {-1,  -1,  -1,  -1,  -1},  /* IdSel 16,  none        */
 127                 {43,  43,  42,  41,  40},  /* IdSel 17,  64-bit slot */
 128                 /* the next 6 are actually on PCI bus 1, across the bridge */
 129                 {19,  19,  18,  17,  16},  /* IdSel  8,  slot 0      */
 130                 {31,  31,  30,  29,  28},  /* IdSel  9,  slot 1      */
 131                 {27,  27,  26,  25,  24},  /* IdSel 10,  slot 2      */
 132                 {39,  39,  38,  37,  36},  /* IdSel 11,  slot 3      */
 133                 {35,  35,  34,  33,  32},  /* IdSel 12,  slot 4      */
 134                 {20,  20,  20,  20,  20},  /* IdSel 13,  53c875      */
 135         };
 136         const long min_idsel = 13, max_idsel = 23, irqs_per_slot = 5;
 137         return COMMON_TABLE_LOOKUP;
 138 }
 139
 140 static u8 __init
 141 ruffian_swizzle(struct pci_dev *dev, u8 *pinp)
 142 {
 143         int slot, pin = *pinp;
 144
 145         if (dev->bus->number == 0) {
 146                 slot = PCI_SLOT(dev->devfn);
 147         }
 148         /* Check for the built-in bridge.  */
 149         else if (PCI_SLOT(dev->bus->self->devfn) == 13) {
 150                 slot = PCI_SLOT(dev->devfn) + 10;
 151         }
 152         else
 153         {
 154                 /* Must be a card-based bridge.  */
 155                 do {
 156                         if (PCI_SLOT(dev->bus->self->devfn) == 13) {
 157                                 slot = PCI_SLOT(dev->devfn) + 10;
 158                                 break;
 159                         }
 160                         pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
 161
 162                         /* Move up the chain of bridges.  */
 163                         dev = dev->bus->self;
 164                         /* Slot of the next bridge.  */
 165                         slot = PCI_SLOT(dev->devfn);
 166                 } while (dev->bus->self);
 167         }
 168         *pinp = pin;
 169         return slot;
 170 }
 171
 172 #ifdef BUILDING_FOR_MILO
 173 /*
 174  * The DeskStation Ruffian motherboard firmware does not place
 175  * the memory size in the PALimpure area.  Therefore, we use
 176  * the Bank Configuration Registers in PYXIS to obtain the size.
 177  */
 178 static unsigned long __init
 179 ruffian_get_bank_size(unsigned long offset)
 180 {
 181         unsigned long bank_addr, bank, ret = 0;
 182
 183         /* Valid offsets are: 0x800, 0x840 and 0x880
 184            since Ruffian only uses three banks.  */
 185         bank_addr = (unsigned long)PYXIS_MCR + offset;
 186         bank = *(vulp)bank_addr;
 187
 188         /* Check BANK_ENABLE */
 189         if (bank & 0x01) {
 190                 static unsigned long size[] __initdata = {
 191                         0x40000000UL, /* 0x00,   1G */
 192                         0x20000000UL, /* 0x02, 512M */
 193                         0x10000000UL, /* 0x04, 256M */
 194                         0x08000000UL, /* 0x06, 128M */
 195                         0x04000000UL, /* 0x08,  64M */
 196                         0x02000000UL, /* 0x0a,  32M */
 197                         0x01000000UL, /* 0x0c,  16M */
 198                         0x00800000UL, /* 0x0e,   8M */
 199                         0x80000000UL, /* 0x10,   2G */
 200                 };
 201
 202                 bank = (bank & 0x1e) >> 1;
 203                 if (bank < sizeof(size)/sizeof(*size))
 204                         ret = size[bank];
 205         }
 206
 207         return ret;
 208 }
 209 #endif /* BUILDING_FOR_MILO */
 210
 211 /*
 212  * The System Vector
 213  */
 214
 215 struct alpha_machine_vector ruffian_mv __initmv = {
 216         .vector_name            = "Ruffian",
 217         DO_EV5_MMU,
 218         DO_DEFAULT_RTC,
 219         DO_PYXIS_IO,
 220         DO_CIA_BUS,
 221         .machine_check          = cia_machine_check,
 222         .max_isa_dma_address    = ALPHA_RUFFIAN_MAX_ISA_DMA_ADDRESS,
 223         .min_io_address         = DEFAULT_IO_BASE,
 224         .min_mem_address        = DEFAULT_MEM_BASE,
 225         .pci_dac_offset         = PYXIS_DAC_OFFSET,
 226
 227         .nr_irqs                = 48,
 228         .device_interrupt       = pyxis_device_interrupt,
 229
 230         .init_arch              = pyxis_init_arch,
 231         .init_irq               = ruffian_init_irq,
 232         .init_rtc               = ruffian_init_rtc,
 233         .init_pci               = cia_init_pci,
 234         .kill_arch              = ruffian_kill_arch,
 235         .pci_map_irq            = ruffian_map_irq,
 236         .pci_swizzle            = ruffian_swizzle,
 237 };
 238 ALIAS_MV(ruffian)