arch/mips/kernel/cpu-probe.c

   1 #include <linux/init.h>
   2 #include <linux/kernel.h>
   3 #include <linux/stddef.h>
   4 #include <asm/bugs.h>
   5 #include <asm/cpu.h>
   6 #include <asm/fpu.h>
   7 #include <asm/mipsregs.h>
   8
   9 /*
  10  * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
  11  * the implementation of the "wait" feature differs between CPU families. This
  12  * points to the function that implements CPU specific wait.
  13  * The wait instruction stops the pipeline and reduces the power consumption of
  14  * the CPU very much.
  15  */
  16 void (*cpu_wait)(void) = NULL;
  17
  18 static void r3081_wait(void)
  19 {
  20         unsigned long cfg = read_c0_conf();
  21         write_c0_conf(cfg | R30XX_CONF_HALT);
  22 }
  23
  24 static void r39xx_wait(void)
  25 {
  26         unsigned long cfg = read_c0_conf();
  27         write_c0_conf(cfg | TX39_CONF_HALT);
  28 }
  29
  30 static void r4k_wait(void)
  31 {
  32         __asm__(".set\tmips3\n\t"
  33                 "wait\n\t"
  34                 ".set\tmips0");
  35 }
  36
  37 void au1k_wait(void)
  38 {
  39 #ifdef CONFIG_PM
  40         /* using the wait instruction makes CP0 counter unusable */
  41         __asm__(".set\tmips3\n\t"
  42                 "wait\n\t"
  43                 "nop\n\t"
  44                 "nop\n\t"
  45                 "nop\n\t"
  46                 "nop\n\t"
  47                 ".set\tmips0");
  48 #else
  49         __asm__("nop\n\t"
  50                 "nop");
  51 #endif
  52 }
  53
  54 static inline void check_wait(void)
  55 {
  56         struct cpuinfo_mips *c = &current_cpu_data;
  57
  58         printk("Checking for 'wait' instruction... ");
  59         switch (c->cputype) {
  60         case CPU_R3081:
  61         case CPU_R3081E:
  62                 cpu_wait = r3081_wait;
  63                 printk(" available.\n");
  64                 break;
  65         case CPU_TX3927:
  66                 cpu_wait = r39xx_wait;
  67                 printk(" available.\n");
  68                 break;
  69         case CPU_R4200:
  70 /*      case CPU_R4300: */
  71         case CPU_R4600:
  72         case CPU_R4640:
  73         case CPU_R4650:
  74         case CPU_R4700:
  75         case CPU_R5000:
  76         case CPU_NEVADA:
  77         case CPU_RM7000:
  78         case CPU_TX49XX:
  79         case CPU_4KC:
  80         case CPU_4KEC:
  81         case CPU_4KSC:
  82         case CPU_5KC:
  83 /*      case CPU_20KC:*/
  84                 cpu_wait = r4k_wait;
  85                 printk(" available.\n");
  86                 break;
  87         case CPU_AU1000:
  88         case CPU_AU1100:
  89         case CPU_AU1500:
  90                 cpu_wait = au1k_wait;
  91                 printk(" available.\n");
  92                 break;
  93         default:
  94                 printk(" unavailable.\n");
  95                 break;
  96         }
  97 }
  98
  99 void __init check_bugs(void)
 100 {
 101         check_wait();
 102 }
 103
 104 /*
 105  * Probe whether cpu has config register by trying to play with
 106  * alternate cache bit and see whether it matters.
 107  * It's used by cpu_probe to distinguish between R3000A and R3081.
 108  */
 109 static inline int cpu_has_confreg(void)
 110 {
 111 #ifdef CONFIG_CPU_R3000
 112         extern unsigned long r3k_cache_size(unsigned long);
 113         unsigned long size1, size2;
 114         unsigned long cfg = read_c0_conf();
 115
 116         size1 = r3k_cache_size(ST0_ISC);
 117         write_c0_conf(cfg ^ R30XX_CONF_AC);
 118         size2 = r3k_cache_size(ST0_ISC);
 119         write_c0_conf(cfg);
 120         return size1 != size2;
 121 #else
 122         return 0;
 123 #endif
 124 }
 125
 126 /*
 127  * Get the FPU Implementation/Revision.
 128  */
 129 static inline unsigned long cpu_get_fpu_id(void)
 130 {
 131         unsigned long tmp, fpu_id;
 132
 133         tmp = read_c0_status();
 134         __enable_fpu();
 135         fpu_id = read_32bit_cp1_register(CP1_REVISION);
 136         write_c0_status(tmp);
 137         return fpu_id;
 138 }
 139
 140 /*
 141  * Check the CPU has an FPU the official way.
 142  */
 143 static inline int __cpu_has_fpu(void)
 144 {
 145         return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
 146 }
 147
 148 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4KTLB \
 149                 | MIPS_CPU_COUNTER | MIPS_CPU_CACHE_CDEX)
 150
 151 __init void cpu_probe(void)
 152 {
 153         struct cpuinfo_mips *c = &current_cpu_data;
 154         unsigned long config0 = read_c0_config();
 155         unsigned long config1;
 156
 157         c->processor_id = PRID_IMP_UNKNOWN;
 158         c->fpu_id       = FPIR_IMP_NONE;
 159         c->cputype      = CPU_UNKNOWN;
 160
 161         if (config0 & (1 << 31)) {
 162                 /* MIPS32 or MIPS64 compliant CPU. Read Config 1 register. */
 163                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 164                         MIPS_CPU_4KTLB | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
 165                         MIPS_CPU_LLSC;
 166                 config1 = read_c0_config1();
 167                 if (config1 & (1 << 3))
 168                         c->options |= MIPS_CPU_WATCH;
 169                 if (config1 & (1 << 2))
 170                         c->options |= MIPS_CPU_MIPS16;
 171                 if (config1 & (1 << 1))
 172                         c->options |= MIPS_CPU_EJTAG;
 173                 if (config1 & 1) {
 174                         c->options |= MIPS_CPU_FPU;
 175                         c->options |= MIPS_CPU_32FPR;
 176                 }
 177                 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
 178
 179                 c->tlbsize = ((config1 >> 25) & 0x3f) + 1;
 180         }
 181
 182         c->processor_id = read_c0_prid();
 183         switch (c->processor_id & 0xff0000) {
 184         case PRID_COMP_LEGACY:
 185                 switch (c->processor_id & 0xff00) {
 186                 case PRID_IMP_R2000:
 187                         c->cputype = CPU_R2000;
 188                         c->isa_level = MIPS_CPU_ISA_I;
 189                         c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX |
 190                                      MIPS_CPU_LLSC;
 191                         if (__cpu_has_fpu())
 192                                 c->options |= MIPS_CPU_FPU;
 193                         c->tlbsize = 64;
 194                         break;
 195                 case PRID_IMP_R3000:
 196                         if ((c->processor_id & 0xff) == PRID_REV_R3000A)
 197                                 if (cpu_has_confreg())
 198                                         c->cputype = CPU_R3081E;
 199                                 else
 200                                         c->cputype = CPU_R3000A;
 201                         else
 202                                 c->cputype = CPU_R3000;
 203                         c->isa_level = MIPS_CPU_ISA_I;
 204                         c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX |
 205                                      MIPS_CPU_LLSC;
 206                         if (__cpu_has_fpu())
 207                                 c->options |= MIPS_CPU_FPU;
 208                         c->tlbsize = 64;
 209                         break;
 210                 case PRID_IMP_R4000:
 211                         if ((c->processor_id & 0xff) >= PRID_REV_R4400)
 212                                 c->cputype = CPU_R4400SC;
 213                         else
 214                                 c->cputype = CPU_R4000SC;
 215                         c->isa_level = MIPS_CPU_ISA_III;
 216                         c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 217                                      MIPS_CPU_WATCH | MIPS_CPU_VCE |
 218                                      MIPS_CPU_LLSC;
 219                         c->tlbsize = 48;
 220                         break;
 221                 case PRID_IMP_VR41XX:
 222                         switch (c->processor_id & 0xf0) {
 223 #ifndef CONFIG_VR4181
 224                         case PRID_REV_VR4111:
 225                                 c->cputype = CPU_VR4111;
 226                                 break;
 227 #else
 228                         case PRID_REV_VR4181:
 229                                 c->cputype = CPU_VR4181;
 230                                 break;
 231 #endif
 232                         case PRID_REV_VR4121:
 233                                 c->cputype = CPU_VR4121;
 234                                 break;
 235                         case PRID_REV_VR4122:
 236                                 if ((c->processor_id & 0xf) < 0x3)
 237                                         c->cputype = CPU_VR4122;
 238                                 else
 239                                         c->cputype = CPU_VR4181A;
 240                                 break;
 241                         case PRID_REV_VR4131:
 242                                 c->cputype = CPU_VR4131;
 243                                 break;
 244                         default:
 245                                 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
 246                                 c->cputype = CPU_VR41XX;
 247                                 break;
 248                         }
 249                         c->isa_level = MIPS_CPU_ISA_III;
 250                         c->options = R4K_OPTS;
 251                         c->tlbsize = 32;
 252                         break;
 253                 case PRID_IMP_R4300:
 254                         c->cputype = CPU_R4300;
 255                         c->isa_level = MIPS_CPU_ISA_III;
 256                         c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 257                                      MIPS_CPU_LLSC;
 258                         c->tlbsize = 32;
 259                         break;
 260                 case PRID_IMP_R4600:
 261                         c->cputype = CPU_R4600;
 262                         c->isa_level = MIPS_CPU_ISA_III;
 263                         c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
 264                         c->tlbsize = 48;
 265                         break;
 266                 #if 0
 267                 case PRID_IMP_R4650:
 268                         /*
 269                          * This processor doesn't have an MMU, so it's not
 270                          * "real easy" to run Linux on it. It is left purely
 271                          * for documentation.  Commented out because it shares
 272                          * it's c0_prid id number with the TX3900.
 273                          */
 274                         c->cputype = CPU_R4650;
 275                         c->isa_level = MIPS_CPU_ISA_III;
 276                         c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
 277                         c->tlbsize = 48;
 278                         break;
 279                 #endif
 280                 case PRID_IMP_TX39:
 281                         c->isa_level = MIPS_CPU_ISA_I;
 282                         c->options = MIPS_CPU_TLB;
 283
 284                         if ((c->processor_id & 0xf0) ==
 285                             (PRID_REV_TX3927 & 0xf0)) {
 286                                 c->cputype = CPU_TX3927;
 287                                 c->tlbsize = 64;
 288                         } else {
 289                                 switch (c->processor_id & 0xff) {
 290                                 case PRID_REV_TX3912:
 291                                         c->cputype = CPU_TX3912;
 292                                         c->tlbsize = 32;
 293                                         break;
 294                                 case PRID_REV_TX3922:
 295                                         c->cputype = CPU_TX3922;
 296                                         c->tlbsize = 64;
 297                                         break;
 298                                 default:
 299                                         c->cputype = CPU_UNKNOWN;
 300                                         break;
 301                                 }
 302                         }
 303                         break;
 304                 case PRID_IMP_R4700:
 305                         c->cputype = CPU_R4700;
 306                         c->isa_level = MIPS_CPU_ISA_III;
 307                         c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 308                                      MIPS_CPU_LLSC;
 309                         c->tlbsize = 48;
 310                         break;
 311                 case PRID_IMP_TX49:
 312                         c->cputype = CPU_TX49XX;
 313                         c->isa_level = MIPS_CPU_ISA_III;
 314                         c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 315                                      MIPS_CPU_LLSC;
 316                         c->tlbsize = 48;
 317                         break;
 318                 case PRID_IMP_R5000:
 319                         c->cputype = CPU_R5000;
 320                         c->isa_level = MIPS_CPU_ISA_IV;
 321                         c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 322                                      MIPS_CPU_LLSC;
 323                         c->tlbsize = 48;
 324                         break;
 325                 case PRID_IMP_R5432:
 326                         c->cputype = CPU_R5432;
 327                         c->isa_level = MIPS_CPU_ISA_IV;
 328                         c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 329                                      MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 330                         c->tlbsize = 48;
 331                         break;
 332                 case PRID_IMP_R5500:
 333                         c->cputype = CPU_R5500;
 334                         c->isa_level = MIPS_CPU_ISA_IV;
 335                         c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 336                                      MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 337                         c->tlbsize = 48;
 338                         break;
 339                 case PRID_IMP_NEVADA:
 340                         c->cputype = CPU_NEVADA;
 341                         c->isa_level = MIPS_CPU_ISA_IV;
 342                         c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 343                                      MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
 344                         c->tlbsize = 48;
 345                         break;
 346                 case PRID_IMP_R6000:
 347                         c->cputype = CPU_R6000;
 348                         c->isa_level = MIPS_CPU_ISA_II;
 349                         c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 350                                      MIPS_CPU_LLSC;
 351                         c->tlbsize = 32;
 352                         break;
 353                 case PRID_IMP_R6000A:
 354                         c->cputype = CPU_R6000A;
 355                         c->isa_level = MIPS_CPU_ISA_II;
 356                         c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 357                                      MIPS_CPU_LLSC;
 358                         c->tlbsize = 32;
 359                         break;
 360                 case PRID_IMP_RM7000:
 361                         c->cputype = CPU_RM7000;
 362                         c->isa_level = MIPS_CPU_ISA_IV;
 363                         c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 364                                      MIPS_CPU_LLSC;
 365                         /*
 366                          * Undocumented RM7000:  Bit 29 in the info register of
 367                          * the RM7000 v2.0 indicates if the TLB has 48 or 64
 368                          * entries.
 369                          *
 370                          * 29      1 =>    64 entry JTLB
 371                          *         0 =>    48 entry JTLB
 372                          */
 373                         c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 374                         break;
 375                 case PRID_IMP_R8000:
 376                         c->cputype = CPU_R8000;
 377                         c->isa_level = MIPS_CPU_ISA_IV;
 378                         c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 379                                      MIPS_CPU_FPU | MIPS_CPU_32FPR |
 380                                      MIPS_CPU_LLSC;
 381                         c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
 382                         break;
 383                 case PRID_IMP_R10000:
 384                         c->cputype = CPU_R10000;
 385                         c->isa_level = MIPS_CPU_ISA_IV;
 386                         c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 387                                      MIPS_CPU_FPU | MIPS_CPU_32FPR |
 388                                      MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 389                                      MIPS_CPU_LLSC;
 390                         c->tlbsize = 64;
 391                         break;
 392                 case PRID_IMP_R12000:
 393                         c->cputype = CPU_R12000;
 394                         c->isa_level = MIPS_CPU_ISA_IV;
 395                         c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 396                                      MIPS_CPU_FPU | MIPS_CPU_32FPR |
 397                                      MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 398                                      MIPS_CPU_LLSC;
 399                         c->tlbsize = 64;
 400                         break;
 401                 default:
 402                         c->cputype = CPU_UNKNOWN;
 403                         break;
 404                 }
 405                 break;
 406         case PRID_COMP_MIPS:
 407                 switch (c->processor_id & 0xff00) {
 408                 case PRID_IMP_4KC:
 409                         c->cputype = CPU_4KC;
 410                         c->isa_level = MIPS_CPU_ISA_M32;
 411                         break;
 412                 case PRID_IMP_4KEC:
 413                         c->cputype = CPU_4KEC;
 414                         c->isa_level = MIPS_CPU_ISA_M32;
 415                         break;
 416                 case PRID_IMP_4KSC:
 417                         c->cputype = CPU_4KSC;
 418                         c->isa_level = MIPS_CPU_ISA_M32;
 419                         break;
 420                 case PRID_IMP_5KC:
 421                         c->cputype = CPU_5KC;
 422                         c->isa_level = MIPS_CPU_ISA_M64;
 423                         break;
 424                 case PRID_IMP_20KC:
 425                         c->cputype = CPU_20KC;
 426                         c->isa_level = MIPS_CPU_ISA_M64;
 427                         break;
 428                 default:
 429                         c->cputype = CPU_UNKNOWN;
 430                         break;
 431                 }
 432                 break;
 433         case PRID_COMP_ALCHEMY:
 434                 switch (c->processor_id & 0xff00) {
 435                 case PRID_IMP_AU1_REV1:
 436                 case PRID_IMP_AU1_REV2:
 437                         switch ((c->processor_id >> 24) & 0xff) {
 438                         case 0:
 439                                 c->cputype = CPU_AU1000;
 440                                 break;
 441                         case 1:
 442                                 c->cputype = CPU_AU1500;
 443                                 break;
 444                         case 2:
 445                                 c->cputype = CPU_AU1100;
 446                                 break;
 447                         default:
 448                                 panic("Unknown Au Core!");
 449                                 break;
 450                         }
 451                         c->isa_level = MIPS_CPU_ISA_M32;
 452                         break;
 453                 default:
 454                         c->cputype = CPU_UNKNOWN;
 455                         break;
 456                 }
 457                 break;
 458         case PRID_COMP_SIBYTE:
 459                 switch (c->processor_id & 0xff00) {
 460                 case PRID_IMP_SB1:
 461                         c->cputype = CPU_SB1;
 462                         c->isa_level = MIPS_CPU_ISA_M64;
 463                         c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 464                                      MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
 465                                      MIPS_CPU_MCHECK | MIPS_CPU_EJTAG |
 466                                      MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 467 #ifndef CONFIG_SB1_PASS_1_WORKAROUNDS
 468                         /* FPU in pass1 is known to have issues. */
 469                         c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
 470 #endif
 471                         break;
 472                 default:
 473                         c->cputype = CPU_UNKNOWN;
 474                         break;
 475                 }
 476                 break;
 477
 478         case PRID_COMP_SANDCRAFT:
 479                 switch (c->processor_id & 0xff00) {
 480                 case PRID_IMP_SR71000:
 481                         c->cputype = CPU_SR71000;
 482                         c->isa_level = MIPS_CPU_ISA_M64;
 483                         c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 484                                      MIPS_CPU_4KTLB | MIPS_CPU_FPU |
 485                                      MIPS_CPU_COUNTER | MIPS_CPU_MCHECK;
 486                         c->scache.ways = 8;
 487                         c->tlbsize = 64;
 488                         break;
 489                 default:
 490                         c->cputype = CPU_UNKNOWN;
 491                         break;
 492                 }
 493                 break;
 494         default:
 495                 c->cputype = CPU_UNKNOWN;
 496         }
 497         if (c->options & MIPS_CPU_FPU)
 498                 c->fpu_id = cpu_get_fpu_id();
 499 }
 500
 501 __init void cpu_report(void)
 502 {
 503         struct cpuinfo_mips *c = &current_cpu_data;
 504
 505         printk("CPU revision is: %08x\n", c->processor_id);
 506         if (c->options & MIPS_CPU_FPU)
 507                 printk("FPU revision is: %08x\n", c->fpu_id);
 508 }