include/asm-mips/cpu.h

   1 /*
   2  * cpu.h: Values of the PRId register used to match up
   3  *        various MIPS cpu types.
   4  *
   5  * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
   6  */
   7 #ifndef _ASM_CPU_H
   8 #define _ASM_CPU_H
   9
  10 #include <asm/cache.h>
  11
  12 /* Assigned Company values for bits 23:16 of the PRId Register
  13    (CP0 register 15, select 0).  As of the MIPS32 and MIPS64 specs from
  14    MTI, the PRId register is defined in this (backwards compatible)
  15    way:
  16
  17   +----------------+----------------+----------------+----------------+
  18   | Company Options| Company ID     | Processor ID   | Revision       |
  19   +----------------+----------------+----------------+----------------+
  20    31            24 23            16 15             8 7
  21
  22    I don't have docs for all the previous processors, but my impression is
  23    that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
  24    spec.
  25 */
  26
  27 #define PRID_COMP_LEGACY       0x000000
  28 #define PRID_COMP_MIPS         0x010000
  29 #define PRID_COMP_BROADCOM     0x020000
  30 #define PRID_COMP_ALCHEMY      0x030000
  31 #define PRID_COMP_SIBYTE       0x040000
  32
  33 /*
  34  * Assigned values for the product ID register.  In order to detect a
  35  * certain CPU type exactly eventually additional registers may need to
  36  * be examined.  These are valid when 23:16 == PRID_COMP_LEGACY
  37  */
  38 #define PRID_IMP_R2000          0x0100
  39 #define PRID_IMP_AU1_REV1       0x0100
  40 #define PRID_IMP_AU1_REV2       0x0200
  41 #define PRID_IMP_R3000          0x0200          /* Same as R2000A  */
  42 #define PRID_IMP_R6000          0x0300          /* Same as R3000A  */
  43 #define PRID_IMP_R4000          0x0400
  44 #define PRID_IMP_R6000A         0x0600
  45 #define PRID_IMP_R10000         0x0900
  46 #define PRID_IMP_R4300          0x0b00
  47 #define PRID_IMP_VR41XX         0x0c00
  48 #define PRID_IMP_R12000         0x0e00
  49 #define PRID_IMP_R8000          0x1000
  50 #define PRID_IMP_R4600          0x2000
  51 #define PRID_IMP_R4700          0x2100
  52 #define PRID_IMP_TX39           0x2200
  53 #define PRID_IMP_R4640          0x2200
  54 #define PRID_IMP_R4650          0x2200          /* Same as R4640 */
  55 #define PRID_IMP_R5000          0x2300
  56 #define PRID_IMP_TX49           0x2d00
  57 #define PRID_IMP_SONIC          0x2400
  58 #define PRID_IMP_MAGIC          0x2500
  59 #define PRID_IMP_RM7000         0x2700
  60 #define PRID_IMP_NEVADA         0x2800          /* RM5260 ??? */
  61 #define PRID_IMP_R5432          0x5400
  62 #define PRID_IMP_R5500          0x5500
  63 #define PRID_IMP_4KC            0x8000
  64 #define PRID_IMP_5KC            0x8100
  65 #define PRID_IMP_20KC           0x8200
  66 #define PRID_IMP_4KEC           0x8400
  67 #define PRID_IMP_4KSC           0x8600
  68
  69
  70 #define PRID_IMP_UNKNOWN        0xff00
  71
  72 /*
  73  * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
  74  */
  75
  76 #define PRID_IMP_SB1            0x0100
  77
  78 /*
  79  * Definitions for 7:0 on legacy processors
  80  */
  81
  82
  83 #define PRID_REV_R4400          0x0040
  84 #define PRID_REV_R3000A         0x0030
  85 #define PRID_REV_R3000          0x0020
  86 #define PRID_REV_R2000A         0x0010
  87 #define PRID_REV_TX3912         0x0010
  88 #define PRID_REV_TX3922         0x0030
  89 #define PRID_REV_TX3927         0x0040
  90 #define PRID_REV_VR4111         0x0050
  91 #define PRID_REV_VR4181         0x0050  /* Same as VR4111 */
  92 #define PRID_REV_VR4121         0x0060
  93 #define PRID_REV_VR4122         0x0070
  94 #define PRID_REV_VR4181A        0x0070  /* Same as VR4122 */
  95 #define PRID_REV_VR4131         0x0080
  96
  97 /*
  98  * FPU implementation/revision register (CP1 control register 0).
  99  *
 100  * +---------------------------------+----------------+----------------+
 101  * | 0                               | Implementation | Revision       |
 102  * +---------------------------------+----------------+----------------+
 103  *  31                             16 15             8 7              0
 104  */
 105
 106 #define FPIR_IMP_NONE           0x0000
 107
 108 #ifndef __ASSEMBLY__
 109
 110 extern void cpu_probe(void);
 111 extern void cpu_report(void);
 112
 113 enum cputype {
 114         CPU_UNKNOWN,
 115         CPU_R2000, CPU_R3000, CPU_R3000A, CPU_R3041, CPU_R3051, CPU_R3052,
 116         CPU_R3081, CPU_R3081E, CPU_R4000PC, CPU_R4000SC, CPU_R4000MC,
 117         CPU_R4200, CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600,
 118         CPU_R6000, CPU_R6000A, CPU_R8000, CPU_R10000, CPU_R12000, CPU_R4300,
 119         CPU_R4650, CPU_R4700, CPU_R5000, CPU_R5000A, CPU_R4640, CPU_NEVADA,
 120         CPU_RM7000, CPU_R5432, CPU_4KC, CPU_5KC, CPU_R4310, CPU_SB1,
 121         CPU_TX3912, CPU_TX3922, CPU_TX3927, CPU_AU1000, CPU_4KEC, CPU_4KSC,
 122         CPU_VR41XX, CPU_R5500, CPU_TX49XX, CPU_TX39XX, CPU_AU1500, CPU_20KC,
 123         CPU_VR4111, CPU_VR4121, CPU_VR4122, CPU_VR4131, CPU_VR4181, CPU_VR4181A,
 124         CPU_AU1100, CPU_LAST
 125 };
 126
 127 #endif /* !__ASSEMBLY__ */
 128
 129 /*
 130  * ISA Level encodings
 131  */
 132 #define MIPS_CPU_ISA_I          0x00000001
 133 #define MIPS_CPU_ISA_II         0x00000002
 134 #define MIPS_CPU_ISA_III        0x00000003
 135 #define MIPS_CPU_ISA_IV         0x00000004
 136 #define MIPS_CPU_ISA_V          0x00000005
 137 #define MIPS_CPU_ISA_M32        0x00000020
 138 #define MIPS_CPU_ISA_M64        0x00000040
 139
 140 /*
 141  * CPU Option encodings
 142  */
 143 #define MIPS_CPU_TLB            0x00000001 /* CPU has TLB */
 144 /* Leave a spare bit for variant MMU types... */
 145 #define MIPS_CPU_4KEX           0x00000004 /* "R4K" exception model */
 146 #define MIPS_CPU_4KTLB          0x00000008 /* "R4K" TLB handler */
 147 #define MIPS_CPU_FPU            0x00000010 /* CPU has FPU */
 148 #define MIPS_CPU_32FPR          0x00000020 /* 32 dbl. prec. FP registers */
 149 #define MIPS_CPU_COUNTER        0x00000040 /* Cycle count/compare */
 150 #define MIPS_CPU_WATCH          0x00000080 /* watchpoint registers */
 151 #define MIPS_CPU_MIPS16         0x00000100 /* code compression */
 152 #define MIPS_CPU_DIVEC          0x00000200 /* dedicated interrupt vector */
 153 #define MIPS_CPU_VCE            0x00000400 /* virt. coherence conflict possible */
 154 #define MIPS_CPU_CACHE_CDEX     0x00000800 /* Create_Dirty_Exclusive CACHE op */
 155 #define MIPS_CPU_MCHECK         0x00001000 /* Machine check exception */
 156 #define MIPS_CPU_EJTAG          0x00002000 /* EJTAG exception */
 157 #define MIPS_CPU_NOFPUEX        0x00004000 /* no FPU exception */
 158
 159 #endif /* _ASM_CPU_H */