arch/mips/ddb5xxx/ddb5477/setup.c

   1 /*
   2  *
   3  * Copyright 2001 MontaVista Software Inc.
   4  * Author: jsun@mvista.com or jsun@junsun.net
   5  *
   6  * arch/mips/ddb5xxx/ddb5477/setup.c
   7  *     Setup file for DDB5477.
   8  *
   9  * This program is free software; you can redistribute  it and/or modify it
  10  * under  the terms of  the GNU General  Public License as published by the
  11  * Free Software Foundation;  either version 2 of the  License, or (at your
  12  * option) any later version.
  13  */
  14 #include <linux/config.h>
  15 #include <linux/init.h>
  16 #include <linux/kernel.h>
  17 #include <linux/types.h>
  18 #include <linux/console.h>
  19 #include <linux/sched.h>
  20 #include <linux/pci.h>
  21 #include <linux/ide.h>
  22 #include <linux/fs.h>
  23 #include <linux/ioport.h>
  24 #include <linux/param.h>        /* for HZ */
  25 #include <linux/major.h>
  26 #include <linux/kdev_t.h>
  27 #include <linux/root_dev.h>
  28
  29 #include <asm/cpu.h>
  30 #include <asm/bootinfo.h>
  31 #include <asm/addrspace.h>
  32 #include <asm/time.h>
  33 #include <asm/bcache.h>
  34 #include <asm/irq.h>
  35 #include <asm/reboot.h>
  36 #include <asm/gdb-stub.h>
  37 #include <asm/traps.h>
  38 #include <asm/debug.h>
  39 #ifdef CONFIG_PC_KEYB
  40 #include <asm/keyboard.h>
  41 #endif
  42
  43 #include <asm/ddb5xxx/ddb5xxx.h>
  44
  45 #include "lcd44780.h"
  46
  47
  48 // #define      USE_CPU_COUNTER_TIMER   /* whether we use cpu counter */
  49
  50 #define SP_TIMER_BASE                   DDB_SPT1CTRL_L
  51 #define SP_TIMER_IRQ                    VRC5477_IRQ_SPT1
  52
  53 static int bus_frequency = CONFIG_DDB5477_BUS_FREQUENCY*1000;
  54
  55 static void ddb_machine_restart(char *command)
  56 {
  57         static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000;
  58
  59         u32 t;
  60
  61         /* PCI cold reset */
  62         ddb_pci_reset_bus();
  63
  64         /* CPU cold reset */
  65         t = ddb_in32(DDB_CPUSTAT);
  66         db_assert((t&1));
  67         ddb_out32(DDB_CPUSTAT, t);
  68
  69         /* Call the PROM */
  70         back_to_prom();
  71 }
  72
  73 static void ddb_machine_halt(void)
  74 {
  75         printk("DDB Vrc-5477 halted.\n");
  76         while (1);
  77 }
  78
  79 static void ddb_machine_power_off(void)
  80 {
  81         printk("DDB Vrc-5477 halted. Please turn off the power.\n");
  82         while (1);
  83 }
  84
  85 extern void rtc_ds1386_init(unsigned long base);
  86
  87 static unsigned int __init detect_bus_frequency(unsigned long rtc_base)
  88 {
  89         unsigned int freq;
  90         unsigned char c;
  91         unsigned int t1, t2;
  92         unsigned i;
  93
  94         ddb_out32(SP_TIMER_BASE, 0xffffffff);
  95         ddb_out32(SP_TIMER_BASE+4, 0x1);
  96         ddb_out32(SP_TIMER_BASE+8, 0xffffffff);
  97
  98         /* check if rtc is running */
  99         c= *(volatile unsigned char*)rtc_base;
 100         for(i=0; (c == *(volatile unsigned char*)rtc_base) && (i<100000000); i++);
 101         if (c == *(volatile unsigned char*)rtc_base) {
 102                 printk("Failed to detect bus frequency.  Use default 83.3MHz.\n");
 103                 return 83333000;
 104         }
 105
 106         c= *(volatile unsigned char*)rtc_base;
 107         while (c == *(volatile unsigned char*)rtc_base);
 108         /* we are now at the turn of 1/100th second, if no error. */
 109         t1 = ddb_in32(SP_TIMER_BASE+8);
 110
 111         for (i=0; i< 10; i++) {
 112                 c= *(volatile unsigned char*)rtc_base;
 113                 while (c == *(volatile unsigned char*)rtc_base);
 114                 /* we are now at the turn of another 1/100th second */
 115                 t2 = ddb_in32(SP_TIMER_BASE+8);
 116         }
 117
 118         ddb_out32(SP_TIMER_BASE+4, 0x0);        /* disable it again */
 119
 120         freq = (t1 - t2)*10;
 121         printk("DDB bus frequency detection : %u \n", freq);
 122         return freq;
 123 }
 124
 125 static void __init ddb_time_init(void)
 126 {
 127         unsigned long rtc_base;
 128         unsigned int i;
 129
 130         /* we have ds1396 RTC chip */
 131         if (mips_machtype == MACH_NEC_ROCKHOPPER
 132                 ||  mips_machtype == MACH_NEC_ROCKHOPPERII) {
 133                 rtc_base = KSEG1ADDR(DDB_LCS2_BASE);
 134         } else {
 135                 rtc_base = KSEG1ADDR(DDB_LCS1_BASE);
 136         }
 137         rtc_ds1386_init(rtc_base);
 138
 139         /* do we need to do run-time detection of bus speed? */
 140         if (bus_frequency == 0) {
 141                 bus_frequency = detect_bus_frequency(rtc_base);
 142         }
 143
 144         /* mips_counter_frequency is 1/2 of the cpu core freq */
 145         i =  (read_32bit_cp0_register(CP0_CONFIG) >> 28 ) & 7;
 146         if ((current_cpu_data.cputype == CPU_R5432) && (i == 3))
 147                 i = 4;
 148         mips_counter_frequency = bus_frequency*(i+4)/4;
 149 }
 150
 151 extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
 152
 153 static void __init ddb_timer_setup(struct irqaction *irq)
 154 {
 155 #if defined(USE_CPU_COUNTER_TIMER)
 156         unsigned int count;
 157
 158         /* we are using the cpu counter for timer interrupts */
 159         setup_irq(CPU_IRQ_BASE + 7, irq);
 160
 161         /* to generate the first timer interrupt */
 162         count = read_c0_count();
 163         write_c0_compare(count + 1000);
 164
 165 #else
 166
 167         /* if we use Special purpose timer 1 */
 168         ddb_out32(SP_TIMER_BASE, bus_frequency/HZ);
 169         ddb_out32(SP_TIMER_BASE+4, 0x1);
 170         setup_irq(SP_TIMER_IRQ, irq);
 171
 172 #endif
 173 }
 174
 175 static void ddb5477_board_init(void);
 176 extern void ddb5477_irq_setup(void);
 177
 178 #if defined(CONFIG_BLK_DEV_INITRD)
 179 extern unsigned long __rd_start, __rd_end, initrd_start, initrd_end;
 180 #endif
 181
 182 void __init ddb_setup(void)
 183 {
 184         extern int panic_timeout;
 185 #ifdef CONFIG_BLK_DEV_IDE
 186         extern struct ide_ops std_ide_ops;
 187 #endif
 188
 189         /* initialize board - we don't trust the loader */
 190         ddb5477_board_init();
 191
 192         irq_setup = ddb5477_irq_setup;
 193         set_io_port_base(KSEG1ADDR(DDB_PCI_IO_BASE));
 194
 195         board_time_init = ddb_time_init;
 196         board_timer_setup = ddb_timer_setup;
 197
 198         _machine_restart = ddb_machine_restart;
 199         _machine_halt = ddb_machine_halt;
 200         _machine_power_off = ddb_machine_power_off;
 201
 202         /* setup resource limits */
 203         ioport_resource.end = DDB_PCI0_IO_SIZE + DDB_PCI1_IO_SIZE - 1;
 204         iomem_resource.end = 0xffffffff;
 205
 206         /* Reboot on panic */
 207         panic_timeout = 180;
 208
 209 #ifdef CONFIG_BLK_DEV_IDE
 210         ide_ops = &std_ide_ops;
 211 #endif
 212
 213
 214 #ifdef CONFIG_FB
 215         conswitchp = &dummy_con;
 216 #endif
 217
 218 #if defined(CONFIG_BLK_DEV_INITRD)
 219         ROOT_DEV = Root_RAM0;
 220         initrd_start = (unsigned long)&__rd_start;
 221         initrd_end = (unsigned long)&__rd_end;
 222 #endif
 223 }
 224
 225 void __init bus_error_init(void)
 226 {
 227 }
 228
 229 static void __init ddb5477_board_init(void)
 230 {
 231 #ifdef CONFIG_PC_KEYB
 232         extern struct kbd_ops std_kbd_ops;
 233 #endif
 234         /* ----------- setup PDARs ------------ */
 235
 236         /* SDRAM should have been set */
 237         db_assert(ddb_in32(DDB_SDRAM0) ==
 238                     ddb_calc_pdar(DDB_SDRAM_BASE, board_ram_size, 32, 0, 1));
 239
 240         /* SDRAM1 should be turned off.  What is this for anyway ? */
 241         db_assert( (ddb_in32(DDB_SDRAM1) & 0xf) == 0);
 242
 243         /* Setup local bus. */
 244
 245         /* Flash U12 PDAR and timing. */
 246         ddb_set_pdar(DDB_LCS0, DDB_LCS0_BASE, DDB_LCS0_SIZE, 16, 0, 0);
 247         ddb_out32(DDB_LCST0, 0x00090842);
 248
 249         /* We need to setup LCS1 and LCS2 differently based on the
 250            board_version */
 251         if (mips_machtype == MACH_NEC_ROCKHOPPER) {
 252                 /* Flash U13 PDAR and timing. */
 253                 ddb_set_pdar(DDB_LCS1, DDB_LCS1_BASE, DDB_LCS1_SIZE, 16, 0, 0);
 254                 ddb_out32(DDB_LCST1, 0x00090842);
 255
 256                 /* EPLD (NVRAM, switch, LCD, and mezzanie). */
 257                 ddb_set_pdar(DDB_LCS2, DDB_LCS2_BASE, DDB_LCS2_SIZE, 8, 0, 0);
 258         } else {
 259                 /* misc */
 260                 ddb_set_pdar(DDB_LCS1, DDB_LCS1_BASE, DDB_LCS1_SIZE, 8, 0, 0);
 261                 /* mezzanie (?) */
 262                 ddb_set_pdar(DDB_LCS2, DDB_LCS2_BASE, DDB_LCS2_SIZE, 16, 0, 0);
 263         }
 264
 265         /* verify VRC5477 base addr */
 266         db_assert(ddb_in32(DDB_VRC5477) ==
 267                   ddb_calc_pdar(DDB_VRC5477_BASE, DDB_VRC5477_SIZE, 32, 0, 1));
 268
 269         /* verify BOOT ROM addr */
 270         db_assert(ddb_in32(DDB_BOOTCS) ==
 271                   ddb_calc_pdar(DDB_BOOTCS_BASE, DDB_BOOTCS_SIZE, 8, 0, 0));
 272
 273         /* setup PCI windows - window0 for MEM/config, window1 for IO */
 274         ddb_set_pdar(DDB_PCIW0, DDB_PCI0_MEM_BASE, DDB_PCI0_MEM_SIZE, 32, 0, 1);
 275         ddb_set_pdar(DDB_PCIW1, DDB_PCI0_IO_BASE, DDB_PCI0_IO_SIZE, 32, 0, 1);
 276         ddb_set_pdar(DDB_IOPCIW0, DDB_PCI1_MEM_BASE, DDB_PCI1_MEM_SIZE, 32, 0, 1);
 277         ddb_set_pdar(DDB_IOPCIW1, DDB_PCI1_IO_BASE, DDB_PCI1_IO_SIZE, 32, 0, 1);
 278
 279         /* ------------ reset PCI bus and BARs ----------------- */
 280         ddb_pci_reset_bus();
 281
 282         ddb_out32(DDB_BARM010, 0x00000008);
 283         ddb_out32(DDB_BARM011, 0x00000008);
 284
 285         ddb_out32(DDB_BARC0, 0xffffffff);
 286         ddb_out32(DDB_BARM230, 0xffffffff);
 287         ddb_out32(DDB_BAR00, 0xffffffff);
 288         ddb_out32(DDB_BAR10, 0xffffffff);
 289         ddb_out32(DDB_BAR20, 0xffffffff);
 290         ddb_out32(DDB_BAR30, 0xffffffff);
 291         ddb_out32(DDB_BAR40, 0xffffffff);
 292         ddb_out32(DDB_BAR50, 0xffffffff);
 293         ddb_out32(DDB_BARB0, 0xffffffff);
 294
 295         ddb_out32(DDB_BARC1, 0xffffffff);
 296         ddb_out32(DDB_BARM231, 0xffffffff);
 297         ddb_out32(DDB_BAR01, 0xffffffff);
 298         ddb_out32(DDB_BAR11, 0xffffffff);
 299         ddb_out32(DDB_BAR21, 0xffffffff);
 300         ddb_out32(DDB_BAR31, 0xffffffff);
 301         ddb_out32(DDB_BAR41, 0xffffffff);
 302         ddb_out32(DDB_BAR51, 0xffffffff);
 303         ddb_out32(DDB_BARB1, 0xffffffff);
 304
 305         /*
 306          * We use pci master register 0  for memory space / config space
 307          * And we use register 1 for IO space.
 308          * Note that for memory space, we bump up the pci base address
 309          * so that we have 1:1 mapping between PCI memory and cpu physical.
 310          * For PCI IO space, it starts from 0 in PCI IO space but with
 311          * DDB_xx_IO_BASE in CPU physical address space.
 312          */
 313         ddb_set_pmr(DDB_PCIINIT00, DDB_PCICMD_MEM, DDB_PCI0_MEM_BASE,
 314                     DDB_PCI_ACCESS_32);
 315         ddb_set_pmr(DDB_PCIINIT10, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);
 316
 317         ddb_set_pmr(DDB_PCIINIT01, DDB_PCICMD_MEM, DDB_PCI1_MEM_BASE,
 318                     DDB_PCI_ACCESS_32);
 319         ddb_set_pmr(DDB_PCIINIT11, DDB_PCICMD_IO, DDB_PCI0_IO_SIZE,
 320                     DDB_PCI_ACCESS_32);
 321
 322
 323         /* PCI cross window should be set properly */
 324         ddb_set_pdar(DDB_BARP00, DDB_PCI1_MEM_BASE, DDB_PCI1_MEM_SIZE, 32, 0, 1);
 325         ddb_set_pdar(DDB_BARP10, DDB_PCI1_IO_BASE, DDB_PCI1_IO_SIZE, 32, 0, 1);
 326         ddb_set_pdar(DDB_BARP01, DDB_PCI0_MEM_BASE, DDB_PCI0_MEM_SIZE, 32, 0, 1);
 327         ddb_set_pdar(DDB_BARP11, DDB_PCI0_IO_BASE, DDB_PCI0_IO_SIZE, 32, 0, 1);
 328
 329         if (mips_machtype == MACH_NEC_ROCKHOPPER
 330            ||  mips_machtype == MACH_NEC_ROCKHOPPERII) {
 331                 /* Disable bus diagnostics. */
 332                 ddb_out32(DDB_PCICTL0_L, 0);
 333                 ddb_out32(DDB_PCICTL0_H, 0);
 334                 ddb_out32(DDB_PCICTL1_L, 0);
 335                 ddb_out32(DDB_PCICTL1_H, 0);
 336         }
 337
 338         if (mips_machtype == MACH_NEC_ROCKHOPPER) {
 339                 u16                     vid;
 340                 struct pci_bus          bus;
 341                 struct pci_dev          dev_m1533;
 342                 extern struct pci_ops   ddb5477_ext_pci_ops;
 343
 344                 bus.parent      = NULL;    /* we scan the top level only */
 345                 bus.ops         = &ddb5477_ext_pci_ops;
 346                 dev_m1533.bus         = &bus;
 347                 dev_m1533.sysdata     = NULL;
 348                 dev_m1533.devfn       = 7*8;     // slot 7: M1533 SouthBridge.
 349                 pci_read_config_word(&dev_m1533, 0, &vid);
 350                 if (vid == PCI_VENDOR_ID_AL) {
 351                         printk("Changing mips_machtype to MACH_NEC_ROCKHOPPERII\n");
 352                         mips_machtype = MACH_NEC_ROCKHOPPERII;
 353                 }
 354         }
 355
 356         /* enable USB input buffers */
 357         ddb_out32(DDB_PIBMISC, 0x00000007);
 358
 359         /* For dual-function pins, make them all non-GPIO */
 360         ddb_out32(DDB_GIUFUNSEL, 0x0);
 361         // ddb_out32(DDB_GIUFUNSEL, 0xfe0fcfff);  /* NEC recommanded value */
 362
 363         if (mips_machtype == MACH_NEC_ROCKHOPPERII) {
 364 #ifdef CONFIG_PC_KEYB
 365         printk("kdb_ops is std\n");
 366         kbd_ops = &std_kbd_ops;
 367 #endif
 368         }
 369
 370         if (mips_machtype == MACH_NEC_ROCKHOPPERII) {
 371
 372                 /* enable IDE controller on Ali chip (south bridge) */
 373                 u8                      temp8;
 374                 struct pci_bus          bus;
 375                 struct pci_dev          dev_m1533;
 376                 struct pci_dev          dev_m5229;
 377                 extern struct pci_ops   ddb5477_ext_pci_ops;
 378
 379                 /* Setup M1535 registers */
 380                 bus.parent      = NULL;    /* we scan the top level only */
 381                 bus.ops         = &ddb5477_ext_pci_ops;
 382                 dev_m1533.bus         = &bus;
 383                 dev_m1533.sysdata     = NULL;
 384                 dev_m1533.devfn       = 7*8;     // slot 7: M1533 SouthBridge.
 385
 386                 /* setup IDE controller
 387                  * enable IDE controller (bit 6 - 1)
 388                  * IDE IDSEL to be addr:A15 (bit 4:5 - 11)
 389                  * disable IDE ATA Secondary Bus Signal Pad Control (bit 3 - 0)
 390                  * enable IDE ATA Primary Bus Signal Pad Control (bit 2 - 1)
 391                  */
 392                 pci_write_config_byte(&dev_m1533, 0x58, 0x74);
 393
 394                 /*
 395                  * positive decode (bit6 -0)
 396                  * enable IDE controler interrupt (bit 4 -1)
 397                  * setup SIRQ to point to IRQ 14 (bit 3:0 - 1101)
 398                  */
 399                 pci_write_config_byte(&dev_m1533, 0x44, 0x1d);
 400
 401                 /* Setup M5229 registers */
 402                 dev_m5229.bus = &bus;
 403                 dev_m5229.sysdata = NULL;
 404                 dev_m5229.devfn = 4*8;          // slot 4 (AD15): M5229 IDE
 405
 406                 /*
 407                  * enable IDE in the M5229 config register 0x50 (bit 0 - 1)
 408                  * M5229 IDSEL is addr:15; see above setting
 409                  */
 410                 pci_read_config_byte(&dev_m5229, 0x50, &temp8);
 411                 pci_write_config_byte(&dev_m5229, 0x50, temp8 | 0x1);
 412
 413                 /*
 414                  * enable bus master (bit 2)  and IO decoding  (bit 0)
 415                  */
 416                 pci_read_config_byte(&dev_m5229, 0x04, &temp8);
 417                 pci_write_config_byte(&dev_m5229, 0x04, temp8 | 0x5);
 418
 419                 /*
 420                  * enable native, copied from arch/ppc/k2boot/head.S
 421                  * TODO - need volatile, need to be portable
 422                  */
 423                 pci_write_config_byte(&dev_m5229, 0x09, 0xef);
 424
 425                 /* Set Primary Channel Command Block Timing */
 426                 pci_write_config_byte(&dev_m5229, 0x59, 0x31);
 427
 428                 /*
 429                  * Enable primary channel 40-pin cable
 430                  * M5229 register 0x4a (bit 0)
 431                  */
 432                 pci_read_config_byte(&dev_m5229, 0x4a, &temp8);
 433                 pci_write_config_byte(&dev_m5229, 0x4a, temp8 | 0x1);
 434         }
 435
 436         if (mips_machtype == MACH_NEC_ROCKHOPPER
 437            ||  mips_machtype == MACH_NEC_ROCKHOPPERII) {
 438                 printk("lcd44780: initializing\n");
 439                 lcd44780_init();
 440                 lcd44780_puts("MontaVista Linux");
 441         }
 442 }