include/asm-i386/mmu_context.h

   1 #ifndef __I386_SCHED_H
   2 #define __I386_SCHED_H
   3
   4 #include <linux/config.h>
   5 #include <asm/desc.h>
   6 #include <asm/atomic.h>
   7 #include <asm/pgalloc.h>
   8 #include <asm/tlbflush.h>
   9
  10 /*
  11  * Used for LDT copy/destruction.
  12  */
  13 int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
  14 void destroy_context(struct mm_struct *mm);
  15
  16 #ifdef CONFIG_SMP
  17
  18 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk, unsigned cpu)
  19 {
  20         if (cpu_tlbstate[cpu].state == TLBSTATE_OK)
  21                 cpu_tlbstate[cpu].state = TLBSTATE_LAZY;
  22 }
  23 #else
  24 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk, unsigned cpu)
  25 {
  26 }
  27 #endif
  28
  29 static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, struct task_struct *tsk, unsigned cpu)
  30 {
  31         if (likely(prev != next)) {
  32                 /* stop flush ipis for the previous mm */
  33                 clear_bit(cpu, &prev->cpu_vm_mask);
  34 #ifdef CONFIG_SMP
  35                 cpu_tlbstate[cpu].state = TLBSTATE_OK;
  36                 cpu_tlbstate[cpu].active_mm = next;
  37 #endif
  38                 set_bit(cpu, &next->cpu_vm_mask);
  39
  40                 /* Re-load page tables */
  41                 load_cr3(next->pgd);
  42
  43                 /*
  44                  * load the LDT, if the LDT is different:
  45                  */
  46                 if (unlikely(prev->context.ldt != next->context.ldt))
  47                         load_LDT_nolock(&next->context, cpu);
  48         }
  49 #ifdef CONFIG_SMP
  50         else {
  51                 cpu_tlbstate[cpu].state = TLBSTATE_OK;
  52                 if (cpu_tlbstate[cpu].active_mm != next)
  53                         BUG();
  54                 if (!test_and_set_bit(cpu, &next->cpu_vm_mask)) {
  55                         /* We were in lazy tlb mode and leave_mm disabled
  56                          * tlb flush IPI delivery. We must reload %cr3.
  57                          */
  58                         load_cr3(next->pgd);
  59                         load_LDT_nolock(&next->context, cpu);
  60                 }
  61         }
  62 #endif
  63 }
  64
  65 #define deactivate_mm(tsk, mm) \
  66         asm("movl %0,%%fs ; movl %0,%%gs": :"r" (0))
  67
  68 #define activate_mm(prev, next) \
  69         switch_mm((prev),(next),NULL,smp_processor_id())
  70
  71 #endif