include/asm-mips/processor.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994 Waldorf GMBH
   7  * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
   8  * Copyright (C) 1996 Paul M. Antoine
   9  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
  10  */
  11 #ifndef _ASM_PROCESSOR_H
  12 #define _ASM_PROCESSOR_H
  13
  14 #include <linux/config.h>
  15
  16 /*
  17  * Return current * instruction pointer ("program counter").
  18  */
  19 #define current_text_addr() ({ __label__ _l; _l: &&_l;})
  20
  21 #ifndef __ASSEMBLY__
  22 #include <linux/cache.h>
  23 #include <linux/threads.h>
  24
  25 #include <asm/cachectl.h>
  26 #include <asm/mipsregs.h>
  27 #include <asm/system.h>
  28
  29 #if defined(CONFIG_SGI_IP27)
  30 #include <asm/sn/types.h>
  31 #include <asm/sn/intr_public.h>
  32 #endif
  33
  34 /*
  35  * Descriptor for a cache
  36  */
  37 struct cache_desc {
  38         unsigned short linesz;  /* Size of line in bytes */
  39         unsigned short ways;    /* Number of ways */
  40         unsigned short sets;    /* Number of lines per set */
  41         unsigned int waysize;   /* Bytes per way */
  42         unsigned int waybit;    /* Bits to select in a cache set */
  43         unsigned int flags;     /* Flags describing cache properties */
  44 };
  45
  46 /*
  47  * Flag definitions
  48  */
  49 #define MIPS_CACHE_NOT_PRESENT  0x00000001
  50 #define MIPS_CACHE_VTAG         0x00000002      /* Virtually tagged cache */
  51 #define MIPS_CACHE_ALIASES      0x00000004      /* Cache could have aliases */
  52 #define MIPS_CACHE_IC_F_DC      0x00000008      /* Ic can refill from D-cache */
  53
  54 struct cpuinfo_mips {
  55         unsigned long           udelay_val;
  56         unsigned long           asid_cache;
  57 #if defined(CONFIG_SGI_IP27)
  58         cpuid_t         p_cpuid;        /* PROM assigned cpuid */
  59         cnodeid_t       p_nodeid;       /* my node ID in compact-id-space */
  60         nasid_t         p_nasid;        /* my node ID in numa-as-id-space */
  61         unsigned char   p_slice;        /* Physical position on node board */
  62         hub_intmasks_t  p_intmasks;     /* SN0 per-CPU interrupt masks */
  63 #endif
  64 #if 0
  65         unsigned long           loops_per_sec;
  66         unsigned long           ipi_count;
  67         unsigned long           irq_attempt[NR_IRQS];
  68         unsigned long           smp_local_irq_count;
  69         unsigned long           prof_multiplier;
  70         unsigned long           prof_counter;
  71 #endif
  72
  73         /*
  74          * Capability and feature descriptor structure for MIPS CPU
  75          */
  76         unsigned long           options;
  77         unsigned int            processor_id;
  78         unsigned int            fpu_id;
  79         unsigned int            cputype;
  80         int                     isa_level;
  81         int                     tlbsize;
  82         struct cache_desc       icache; /* Primary I-cache */
  83         struct cache_desc       dcache; /* Primary D or combined I/D cache */
  84         struct cache_desc       scache; /* Secondary cache */
  85         struct cache_desc       tcache; /* Tertiary/split secondary cache */
  86 } __attribute__((aligned(SMP_CACHE_BYTES)));
  87
  88 /*
  89  * Assumption: Options of CPU 0 are a superset of all processors.
  90  * This is true for all known MIPS systems.
  91  */
  92 #define cpu_has_tlb             (cpu_data[0].options & MIPS_CPU_TLB)
  93 #define cpu_has_4kex            (cpu_data[0].options & MIPS_CPU_4KEX)
  94 #define cpu_has_4ktlb           (cpu_data[0].options & MIPS_CPU_4KTLB)
  95 #define cpu_has_fpu             (cpu_data[0].options & MIPS_CPU_FPU)
  96 #define cpu_has_32fpr           (cpu_data[0].options & MIPS_CPU_32FPR)
  97 #define cpu_has_counter         (cpu_data[0].options & MIPS_CPU_COUNTER)
  98 #define cpu_has_watch           (cpu_data[0].options & MIPS_CPU_WATCH)
  99 #define cpu_has_mips16          (cpu_data[0].options & MIPS_CPU_MIPS16)
 100 #define cpu_has_divec           (cpu_data[0].options & MIPS_CPU_DIVEC)
 101 #define cpu_has_vce             (cpu_data[0].options & MIPS_CPU_VCE)
 102 #define cpu_has_cache_cdex      (cpu_data[0].options & MIPS_CPU_CACHE_CDEX)
 103 #define cpu_has_mcheck          (cpu_data[0].options & MIPS_CPU_MCHECK)
 104 #define cpu_has_ejtag           (cpu_data[0].options & MIPS_CPU_EJTAG)
 105 /* no FPU exception; never set on 64-bit */
 106 #ifdef CONFIG_MIPS64
 107 #define cpu_has_nofpuex         0
 108 #else
 109 #define cpu_has_nofpuex         (cpu_data[0].options & MIPS_CPU_NOFPUEX)
 110 #endif
 111 #define cpu_has_llsc            (cpu_data[0].options & MIPS_CPU_LLSC)
 112 #define cpu_has_vtag_icache     (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
 113 #define cpu_has_dc_aliases      (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
 114 #define cpu_has_ic_fills_f_dc   (cpu_data[0].dcache.flags & MIPS_CACHE_IC_F_DC)
 115 #ifdef CONFIG_MIPS64
 116 #define cpu_has_64bits          1
 117 #else
 118 #define cpu_has_64bits          (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
 119 #endif
 120 #define cpu_has_subset_pcaches  (cpu_data[0].options & MIPS_CPU_SUBSET_CACHES)
 121
 122 extern struct cpuinfo_mips cpu_data[];
 123 #define current_cpu_data cpu_data[smp_processor_id()]
 124
 125 extern void cpu_probe(void);
 126 extern void cpu_report(void);
 127
 128 /*
 129  * System setup and hardware flags..
 130  */
 131 extern void (*cpu_wait)(void);
 132
 133 extern unsigned int vced_count, vcei_count;
 134
 135 /*
 136  * Bus types (default is ISA, but people can check others with these..)
 137  */
 138 #ifdef CONFIG_EISA
 139 extern int EISA_bus;
 140 #else
 141 #define EISA_bus (0)
 142 #endif
 143
 144 #define MCA_bus 0
 145 #define MCA_bus__is_a_macro /* for versions in ksyms.c */
 146
 147 #ifdef CONFIG_MIPS32
 148 /*
 149  * User space process size: 2GB. This is hardcoded into a few places,
 150  * so don't change it unless you know what you are doing.
 151  */
 152 #define TASK_SIZE       0x7fff8000UL
 153
 154 /*
 155  * This decides where the kernel will search for a free chunk of vm
 156  * space during mmap's.
 157  */
 158 #define TASK_UNMAPPED_BASE      (PAGE_ALIGN(TASK_SIZE / 3))
 159 #endif
 160
 161 #ifdef CONFIG_MIPS64
 162 /*
 163  * User space process size: 1TB. This is hardcoded into a few places,
 164  * so don't change it unless you know what you are doing.  TASK_SIZE
 165  * is limited to 1TB by the R4000 architecture; R10000 and better can
 166  * support 16TB; the architectural reserve for future expansion is
 167  * 8192EB ...
 168  */
 169 #define TASK_SIZE32     0x7fff8000UL
 170 #define TASK_SIZE       0x10000000000UL
 171
 172 /*
 173  * This decides where the kernel will search for a free chunk of vm
 174  * space during mmap's.
 175  */
 176 #define TASK_UNMAPPED_BASE      ((current->thread.mflags & MF_32BIT_ADDR) ? \
 177         PAGE_ALIGN(TASK_SIZE32 / 3) : PAGE_ALIGN(TASK_SIZE / 3))
 178 #endif
 179
 180 /*
 181  * Size of io_bitmap in longwords: 32 is ports 0-0x3ff.
 182  */
 183 #define IO_BITMAP_SIZE  32
 184
 185 #define NUM_FPU_REGS    32
 186
 187 typedef u64 fpureg_t;
 188
 189 struct mips_fpu_hard_struct {
 190         fpureg_t        fpr[NUM_FPU_REGS];
 191         unsigned int    fcr31;
 192 };
 193
 194 /*
 195  * It would be nice to add some more fields for emulator statistics, but there
 196  * are a number of fixed offsets in offset.h and elsewhere that would have to
 197  * be recalculated by hand.  So the additional information will be private to
 198  * the FPU emulator for now.  See asm-mips/fpu_emulator.h.
 199  */
 200
 201 struct mips_fpu_soft_struct {
 202         fpureg_t        fpr[NUM_FPU_REGS];
 203         unsigned int    fcr31;
 204 };
 205
 206 union mips_fpu_union {
 207         struct mips_fpu_hard_struct hard;
 208         struct mips_fpu_soft_struct soft;
 209 };
 210
 211 #define INIT_FPU { \
 212         {{0,},} \
 213 }
 214
 215 typedef struct {
 216         unsigned long seg;
 217 } mm_segment_t;
 218
 219 /*
 220  * If you change thread_struct remember to change the #defines below too!
 221  */
 222 struct thread_struct {
 223         /* Saved main processor registers. */
 224         unsigned long reg16;
 225         unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23;
 226         unsigned long reg29, reg30, reg31;
 227
 228         /* Saved cp0 stuff. */
 229         unsigned long cp0_status;
 230
 231         /* Saved fpu/fpu emulator stuff. */
 232         union mips_fpu_union fpu;
 233
 234         /* Other stuff associated with the thread. */
 235         unsigned long cp0_badvaddr;     /* Last user fault */
 236         unsigned long cp0_baduaddr;     /* Last kernel fault accessing USEG */
 237         unsigned long error_code;
 238         unsigned long trap_no;
 239 #define MF_FIXADE       1               /* Fix address errors in software */
 240 #define MF_LOGADE       2               /* Log address errors to syslog */
 241 #define MF_32BIT_REGS   4               /* also implies 16/32 fprs */
 242 #define MF_32BIT_ADDR   8               /* 32-bit address space (o32/n32) */
 243         unsigned long mflags;
 244         unsigned long irix_trampoline;  /* Wheee... */
 245         unsigned long irix_oldctx;
 246 };
 247
 248 #define MF_ABI_MASK     (MF_32BIT_REGS | MF_32BIT_ADDR)
 249 #define MF_O32          (MF_32BIT_REGS | MF_32BIT_ADDR)
 250 #define MF_N32          MF_32BIT_ADDR
 251 #define MF_N64          0
 252
 253 #endif /* !__ASSEMBLY__ */
 254
 255 #define INIT_THREAD  { \
 256         /* \
 257          * saved main processor registers \
 258          */ \
 259         0, 0, 0, 0, 0, 0, 0, 0, \
 260                        0, 0, 0, \
 261         /* \
 262          * saved cp0 stuff \
 263          */ \
 264         0, \
 265         /* \
 266          * saved fpu/fpu emulator stuff \
 267          */ \
 268         INIT_FPU, \
 269         /* \
 270          * Other stuff associated with the process \
 271          */ \
 272         0, 0, 0, 0, \
 273         /* \
 274          * For now the default is to fix address errors \
 275          */ \
 276         MF_FIXADE, 0, 0 \
 277 }
 278
 279 #ifdef __KERNEL__
 280 #ifndef __ASSEMBLY__
 281
 282 struct task_struct;
 283
 284 /* Free all resources held by a thread. */
 285 #define release_thread(thread) do { } while(0)
 286
 287 /* Prepare to copy thread state - unlazy all lazy status */
 288 #define prepare_to_copy(tsk)    do { } while (0)
 289
 290 extern long kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
 291
 292 extern unsigned long thread_saved_pc(struct task_struct *tsk);
 293
 294 /*
 295  * Do necessary setup to start up a newly executed thread.
 296  */
 297 extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp);
 298
 299 unsigned long get_wchan(struct task_struct *p);
 300
 301 #define __PT_REG(reg) ((long)&((struct pt_regs *)0)->reg - sizeof(struct pt_regs))
 302 #define __KSTK_TOS(tsk) ((unsigned long)(tsk->thread_info) + THREAD_SIZE - 32)
 303 #define KSTK_EIP(tsk) (*(unsigned long *)(__KSTK_TOS(tsk) + __PT_REG(cp0_epc)))
 304 #define KSTK_ESP(tsk) (*(unsigned long *)(__KSTK_TOS(tsk) + __PT_REG(regs[29])))
 305 #define KSTK_STATUS(tsk) (*(unsigned long *)(__KSTK_TOS(tsk) + __PT_REG(cp0_status)))
 306
 307 #define cpu_relax()     barrier()
 308
 309 #endif /* !__ASSEMBLY__ */
 310 #endif /* __KERNEL__ */
 311
 312 /*
 313  * Return_address is a replacement for __builtin_return_address(count)
 314  * which on certain architectures cannot reasonably be implemented in GCC
 315  * (MIPS, Alpha) or is unuseable with -fomit-frame-pointer (i386).
 316  * Note that __builtin_return_address(x>=1) is forbidden because GCC
 317  * aborts compilation on some CPUs.  It's simply not possible to unwind
 318  * some CPU's stackframes.
 319  *
 320  * __builtin_return_address works only for non-leaf functions.  We avoid the
 321  * overhead of a function call by forcing the compiler to save the return
 322  * address register on the stack.
 323  */
 324 #define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
 325
 326 #endif /* _ASM_PROCESSOR_H */